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33534526ec
Use a more extensive FPGA feature reporting style in the gdsys ioep-fpga driver. Signed-off-by: Mario Six <mario.six@gdsys.cc>
590 lines
14 KiB
C
590 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*/
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#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
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#include <common.h>
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#include <gdsys_fpga.h>
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enum pcb_video_type {
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PCB_DVI_SL,
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PCB_DP_165MPIX,
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PCB_DP_300MPIX,
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PCB_HDMI,
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PCB_DP_1_2,
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PCB_HDMI_2_0,
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};
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enum pcb_transmission_type {
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PCB_CAT_1G,
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PCB_FIBER_3G,
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PCB_CAT_10G,
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PCB_FIBER_10G,
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};
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enum carrier_speed {
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CARRIER_SPEED_1G,
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CARRIER_SPEED_3G,
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CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
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CARRIER_SPEED_10G,
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};
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enum ram_config {
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RAM_DDR2_32BIT_295MBPS,
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RAM_DDR3_32BIT_590MBPS,
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RAM_DDR3_48BIT_590MBPS,
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RAM_DDR3_64BIT_1800MBPS,
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RAM_DDR3_48BIT_1800MBPS,
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};
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enum sysclock {
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SYSCLK_147456,
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};
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struct fpga_versions {
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bool video_channel;
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bool con_side;
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enum pcb_video_type pcb_video_type;
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enum pcb_transmission_type pcb_transmission_type;
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unsigned int hw_version;
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};
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struct fpga_features {
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u8 video_channels;
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u8 carriers;
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enum carrier_speed carrier_speed;
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enum ram_config ram_config;
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enum sysclock sysclock;
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bool pcm_tx;
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bool pcm_rx;
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bool spdif_tx;
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bool spdif_rx;
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bool usb2;
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bool rs232;
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bool compression_type1;
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bool compression_type2;
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bool compression_type3;
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bool interlace;
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bool osd;
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bool compression_pipes;
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};
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#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
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static int get_versions(unsigned int fpga, struct fpga_versions *versions)
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{
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enum {
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VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
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VERSIONS_FPGA_CON_SIDE = BIT(13),
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VERSIONS_FPGA_SC = BIT(14),
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VERSIONS_PCB_CON = BIT(9),
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VERSIONS_PCB_SC = BIT(8),
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VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
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VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
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VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
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VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
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VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
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VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
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VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
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VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
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VERSIONS_HW_VER_MASK = 0xf << 0,
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};
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u16 raw_versions;
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memset(versions, 0, sizeof(struct fpga_versions));
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FPGA_GET_REG(fpga, versions, &raw_versions);
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versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
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versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
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switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
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case VERSIONS_PCB_VIDEO_DP_1_2:
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versions->pcb_video_type = PCB_DP_1_2;
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break;
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case VERSIONS_PCB_VIDEO_HDMI_2_0:
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versions->pcb_video_type = PCB_HDMI_2_0;
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break;
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}
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switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
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case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
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versions->pcb_transmission_type = PCB_FIBER_10G;
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break;
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case VERSIONS_PCB_TRANSMISSION_CAT_10G:
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versions->pcb_transmission_type = PCB_CAT_10G;
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break;
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case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
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versions->pcb_transmission_type = PCB_FIBER_3G;
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break;
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case VERSIONS_PCB_TRANSMISSION_CAT_1G:
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versions->pcb_transmission_type = PCB_CAT_1G;
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break;
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}
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versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
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return 0;
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}
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static int get_features(unsigned int fpga, struct fpga_features *features)
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{
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enum {
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FEATURE_SPDIF_RX = BIT(15),
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FEATURE_SPDIF_TX = BIT(14),
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FEATURE_PCM_RX = BIT(13),
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FEATURE_PCM_TX = BIT(12),
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FEATURE_RAM_MASK = GENMASK(11, 8),
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FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
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FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
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FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
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FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
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FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
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FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
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FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
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FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
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FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
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FEATURE_CARRIERS_MASK = GENMASK(5, 4),
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FEATURE_CARRIERS_0 = 0x0 << 4,
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FEATURE_CARRIERS_1 = 0x1 << 4,
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FEATURE_CARRIERS_2 = 0x2 << 4,
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FEATURE_CARRIERS_4 = 0x3 << 4,
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FEATURE_USB2 = BIT(3),
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FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
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FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
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FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
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FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
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FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
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};
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enum {
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EXT_FEATURE_OSD = BIT(15),
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EXT_FEATURE_ETHERNET = BIT(9),
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EXT_FEATURE_INTERLACE = BIT(8),
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EXT_FEATURE_RS232 = BIT(7),
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EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
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EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
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EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
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EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
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EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
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EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
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EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
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};
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u16 raw_features;
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u16 raw_extended_features;
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memset(features, 0, sizeof(struct fpga_features));
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FPGA_GET_REG(fpga, fpga_features, &raw_features);
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FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
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switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
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case FEATURE_VIDEOCHANNELS_0:
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features->video_channels = 0;
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break;
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case FEATURE_VIDEOCHANNELS_1:
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features->video_channels = 1;
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break;
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case FEATURE_VIDEOCHANNELS_1_1:
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case FEATURE_VIDEOCHANNELS_2:
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features->video_channels = 2;
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break;
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};
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switch (raw_features & FEATURE_CARRIERS_MASK) {
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case FEATURE_CARRIERS_0:
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features->carriers = 0;
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break;
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case FEATURE_CARRIERS_1:
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features->carriers = 1;
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break;
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case FEATURE_CARRIERS_2:
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features->carriers = 2;
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break;
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case FEATURE_CARRIERS_4:
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features->carriers = 4;
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break;
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}
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switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
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case FEATURE_CARRIER_SPEED_1G:
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features->carrier_speed = CARRIER_SPEED_1G;
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break;
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case FEATURE_CARRIER_SPEED_2_5G:
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features->carrier_speed = CARRIER_SPEED_2_5G;
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break;
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case FEATURE_CARRIER_SPEED_10G:
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features->carrier_speed = CARRIER_SPEED_10G;
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break;
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}
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switch (raw_features & FEATURE_RAM_MASK) {
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case FEATURE_RAM_DDR2_32BIT_295MBPS:
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features->ram_config = RAM_DDR2_32BIT_295MBPS;
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break;
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case FEATURE_RAM_DDR3_32BIT_590MBPS:
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features->ram_config = RAM_DDR3_32BIT_590MBPS;
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break;
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case FEATURE_RAM_DDR3_48BIT_590MBPS:
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features->ram_config = RAM_DDR3_48BIT_590MBPS;
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break;
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case FEATURE_RAM_DDR3_64BIT_1800MBPS:
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features->ram_config = RAM_DDR3_64BIT_1800MBPS;
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break;
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case FEATURE_RAM_DDR3_48BIT_1800MBPS:
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features->ram_config = RAM_DDR3_48BIT_1800MBPS;
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break;
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}
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features->pcm_tx = raw_features & FEATURE_PCM_TX;
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features->pcm_rx = raw_features & FEATURE_PCM_RX;
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features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
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features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
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features->usb2 = raw_features & FEATURE_USB2;
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features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
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features->compression_type1 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE1;
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features->compression_type2 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE2;
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features->compression_type3 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE3;
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features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
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features->osd = raw_extended_features & EXT_FEATURE_OSD;
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features->compression_pipes = raw_extended_features & EXT_FEATURE_COMPRESSION_PERF_MASK;
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return 0;
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}
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#else
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static int get_versions(unsigned int fpga, struct fpga_versions *versions)
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{
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enum {
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/* HW version encoding is a mess, leave it for the moment */
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VERSIONS_HW_VER_MASK = 0xf << 0,
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VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
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VERSIONS_SFP = BIT(5),
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VERSIONS_VIDEO_MASK = 0x7 << 6,
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VERSIONS_VIDEO_DVI = 0x0 << 6,
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VERSIONS_VIDEO_DP_165 = 0x1 << 6,
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VERSIONS_VIDEO_DP_300 = 0x2 << 6,
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VERSIONS_VIDEO_HDMI = 0x3 << 6,
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VERSIONS_UT_MASK = 0xf << 12,
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VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
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VERSIONS_UT_MAIN_USER = 0x1 << 12,
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VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
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VERSIONS_UT_VIDEO_USER = 0x3 << 12,
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};
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u16 raw_versions;
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memset(versions, 0, sizeof(struct fpga_versions));
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FPGA_GET_REG(fpga, versions, &raw_versions);
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switch (raw_versions & VERSIONS_UT_MASK) {
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case VERSIONS_UT_MAIN_SERVER:
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versions->video_channel = false;
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versions->con_side = false;
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break;
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case VERSIONS_UT_MAIN_USER:
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versions->video_channel = false;
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versions->con_side = true;
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break;
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case VERSIONS_UT_VIDEO_SERVER:
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versions->video_channel = true;
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versions->con_side = false;
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break;
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case VERSIONS_UT_VIDEO_USER:
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versions->video_channel = true;
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versions->con_side = true;
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break;
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}
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switch (raw_versions & VERSIONS_VIDEO_MASK) {
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case VERSIONS_VIDEO_DVI:
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versions->pcb_video_type = PCB_DVI_SL;
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break;
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case VERSIONS_VIDEO_DP_165:
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versions->pcb_video_type = PCB_DP_165MPIX;
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break;
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case VERSIONS_VIDEO_DP_300:
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versions->pcb_video_type = PCB_DP_300MPIX;
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break;
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case VERSIONS_VIDEO_HDMI:
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versions->pcb_video_type = PCB_HDMI;
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break;
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}
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versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
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if (raw_versions & VERSIONS_SFP)
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versions->pcb_transmission_type = PCB_FIBER_3G;
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else
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versions->pcb_transmission_type = PCB_CAT_1G;
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return 0;
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}
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static int get_features(unsigned int fpga, struct fpga_features *features)
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{
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enum {
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FEATURE_CARRIER_SPEED_2_5 = BIT(4),
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FEATURE_RAM_MASK = 0x7 << 5,
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FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
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FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
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FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
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FEATURE_PCM_AUDIO_TX = BIT(9),
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FEATURE_PCM_AUDIO_RX = BIT(10),
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FEATURE_OSD = BIT(11),
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FEATURE_USB20 = BIT(12),
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FEATURE_COMPRESSION_MASK = 7 << 13,
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FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
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FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
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FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
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};
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enum {
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EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
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EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
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EXTENDED_FEATURE_RS232 = BIT(2),
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EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
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EXTENDED_FEATURE_INTERLACE = BIT(4),
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};
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u16 raw_features;
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#ifdef GDSYS_LEGACY_DRIVERS
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u16 raw_extended_features;
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#endif
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memset(features, 0, sizeof(struct fpga_features));
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FPGA_GET_REG(fpga, fpga_features, &raw_features);
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#ifdef GDSYS_LEGACY_DRIVERS
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FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
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#endif
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features->video_channels = raw_features & 0x3;
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features->carriers = (raw_features >> 2) & 0x3;
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features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
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? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
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switch (raw_features & FEATURE_RAM_MASK) {
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case FEATURE_RAM_DDR2_32BIT:
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features->ram_config = RAM_DDR2_32BIT_295MBPS;
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break;
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case FEATURE_RAM_DDR3_32BIT:
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features->ram_config = RAM_DDR3_32BIT_590MBPS;
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break;
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case FEATURE_RAM_DDR3_48BIT:
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features->ram_config = RAM_DDR3_48BIT_590MBPS;
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break;
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}
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features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
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features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
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#ifdef GDSYS_LEGACY_DRIVERS
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features->spdif_tx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_TX;
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features->spdif_rx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_RX;
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#endif
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features->usb2 = raw_features & FEATURE_USB20;
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#ifdef GDSYS_LEGACY_DRIVERS
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features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
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#endif
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features->compression_type1 = false;
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features->compression_type2 = false;
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features->compression_type3 = false;
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switch (raw_features & FEATURE_COMPRESSION_MASK) {
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case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
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features->compression_type3 = true;
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case FEATURE_COMPRESSION_TYPE1_TYPE2:
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features->compression_type2 = true;
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case FEATURE_COMPRESSION_TYPE1:
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features->compression_type1 = true;
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break;
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}
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#ifdef GDSYS_LEGACY_DRIVERS
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features->interlace = raw_extended_features & EXTENDED_FEATURE_INTERLACE;
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#endif
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features->osd = raw_features & FEATURE_OSD;
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#ifdef GDSYS_LEGACY_DRIVERS
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features->compression_pipes = raw_extended_features & EXTENDED_FEATURE_COMPRESSION_PIPES;
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#endif
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return 0;
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}
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#endif
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bool ioep_fpga_has_osd(unsigned int fpga)
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{
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struct fpga_features features;
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get_features(fpga, &features);
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return features.osd;
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}
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void ioep_fpga_print_info(unsigned int fpga)
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{
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u16 fpga_version;
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struct fpga_versions versions;
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struct fpga_features features;
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FPGA_GET_REG(fpga, fpga_version, &fpga_version);
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get_versions(fpga, &versions);
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get_features(fpga, &features);
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if (versions.video_channel)
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printf("Videochannel");
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else
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printf("Mainchannel");
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if (versions.con_side)
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printf(" User");
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else
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printf(" Server");
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// FIXME
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#if 0
|
|
if (versions & (1<<4))
|
|
printf(" UC");
|
|
#endif
|
|
|
|
switch(versions.pcb_transmission_type) {
|
|
case PCB_CAT_1G:
|
|
case PCB_CAT_10G:
|
|
printf(" CAT");
|
|
break;
|
|
case PCB_FIBER_3G:
|
|
case PCB_FIBER_10G:
|
|
printf(" Fiber");
|
|
break;
|
|
};
|
|
|
|
switch (versions.pcb_video_type) {
|
|
case PCB_DVI_SL:
|
|
printf(" DVI,");
|
|
break;
|
|
case PCB_DP_165MPIX:
|
|
printf(" DP 165MPix/s,");
|
|
break;
|
|
case PCB_DP_300MPIX:
|
|
printf(" DP 300MPix/s,");
|
|
break;
|
|
case PCB_HDMI:
|
|
printf(" HDMI,");
|
|
break;
|
|
case PCB_DP_1_2:
|
|
printf(" DP 1.2,");
|
|
break;
|
|
case PCB_HDMI_2_0:
|
|
printf(" HDMI 2.0,");
|
|
break;
|
|
}
|
|
|
|
printf(" FPGA V %d.%02d\n features: ",
|
|
fpga_version / 100, fpga_version % 100);
|
|
|
|
if (!features.compression_type1 &&
|
|
!features.compression_type2 &&
|
|
!features.compression_type3)
|
|
printf("no compression, ");
|
|
|
|
if (features.compression_type1)
|
|
printf("type1, ");
|
|
|
|
if (features.compression_type2)
|
|
printf("type2, ");
|
|
|
|
if (features.compression_type3)
|
|
printf("type3, ");
|
|
|
|
printf("%sosd", features.osd ? "" : "no ");
|
|
|
|
if (features.pcm_rx && features.pcm_tx)
|
|
printf(", pcm rx+tx");
|
|
else if(features.pcm_rx)
|
|
printf(", pcm rx");
|
|
else if(features.pcm_tx)
|
|
printf(", pcm tx");
|
|
|
|
if (features.spdif_rx && features.spdif_tx)
|
|
printf(", spdif rx+tx");
|
|
else if(features.spdif_rx)
|
|
printf(", spdif rx");
|
|
else if(features.spdif_tx)
|
|
printf(", spdif tx");
|
|
|
|
puts(",\n ");
|
|
|
|
switch (features.sysclock) {
|
|
case SYSCLK_147456:
|
|
printf("clock 147.456 MHz");
|
|
break;
|
|
}
|
|
|
|
switch (features.ram_config) {
|
|
case RAM_DDR2_32BIT_295MBPS:
|
|
printf(", RAM 32 bit DDR2");
|
|
break;
|
|
case RAM_DDR3_32BIT_590MBPS:
|
|
printf(", RAM 32 bit DDR3");
|
|
break;
|
|
case RAM_DDR3_48BIT_590MBPS:
|
|
case RAM_DDR3_48BIT_1800MBPS:
|
|
printf(", RAM 48 bit DDR3");
|
|
break;
|
|
case RAM_DDR3_64BIT_1800MBPS:
|
|
printf(", RAM 64 bit DDR3");
|
|
break;
|
|
}
|
|
|
|
printf(", %d carrier(s)", features.carriers);
|
|
|
|
switch(features.carrier_speed) {
|
|
case CARRIER_SPEED_1G:
|
|
printf(", 1Gbit/s");
|
|
break;
|
|
case CARRIER_SPEED_3G:
|
|
printf(", 3Gbit/s");
|
|
break;
|
|
case CARRIER_SPEED_10G:
|
|
printf(", 10Gbit/s");
|
|
break;
|
|
}
|
|
|
|
printf(", %d video channel(s)\n", features.video_channels);
|
|
}
|
|
|
|
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
|