Tien Fong Chee ee06c5390f ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS ...

Bit[7-4] for both register seq2core and core2seq handshake in HPS are not
required for triggering DDR re-calibration or resetting EMIF. So, ignoring
these bits just for playing it safe.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

2022-06-16 16:10:44 +08:00

..

altera

ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS

2022-06-16 16:10:44 +08:00

fsl

ddr: fsl: Allow to compile it without env support

2022-04-26 17:18:39 +05:30

imx

imx8m: fix reading of DDR4 MR registers

2022-05-20 09:30:28 +02:00

marvell

db-mv784mp-gp: Rename CONFIG_DB_784MP_GP to CONFIG_TARGET_DB_MV784MP_GP

2022-04-01 10:28:47 -04:00

microchip

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07 09:34:12 -04:00

Kconfig

nxp: Migrate CONFIG_DDR_CLK_FREQ to Kconfig

2021-08-31 17:46:37 -04:00