mirror of
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379 lines
12 KiB
C
379 lines
12 KiB
C
/*
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* MCF5329 Internal Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __IMMAP_5235__
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#define __IMMAP_5235__
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#define MMAP_SCM (CFG_MBAR + 0x00000000)
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#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
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#define MMAP_FBCS (CFG_MBAR + 0x00000080)
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#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
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#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
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#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
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#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
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#define MMAP_UART0 (CFG_MBAR + 0x00000200)
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#define MMAP_UART1 (CFG_MBAR + 0x00000240)
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#define MMAP_UART2 (CFG_MBAR + 0x00000280)
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#define MMAP_I2C (CFG_MBAR + 0x00000300)
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#define MMAP_QSPI (CFG_MBAR + 0x00000340)
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#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
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#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
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#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
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#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
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#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
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#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
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#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
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#define MMAP_FEC (CFG_MBAR + 0x00001000)
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#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
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#define MMAP_GPIO (CFG_MBAR + 0x00100000)
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#define MMAP_CCM (CFG_MBAR + 0x00110000)
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#define MMAP_PLL (CFG_MBAR + 0x00120000)
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#define MMAP_EPORT (CFG_MBAR + 0x00130000)
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#define MMAP_WDOG (CFG_MBAR + 0x00140000)
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#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
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#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
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#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
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#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
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#define MMAP_MDHA (CFG_MBAR + 0x00190000)
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#define MMAP_RNG (CFG_MBAR + 0x001A0000)
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#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
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#define MMAP_CAN1 (CFG_MBAR + 0x001C0000)
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#define MMAP_ETPU (CFG_MBAR + 0x001D0000)
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#define MMAP_CAN2 (CFG_MBAR + 0x001F0000)
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/* System Control Module register */
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typedef struct scm_ctrl {
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u32 ipsbar; /* 0x00 - MBAR */
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u32 res1; /* 0x04 */
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u32 rambar; /* 0x08 - RAMBAR */
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u32 res2; /* 0x0C */
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u8 crsr; /* 0x10 Core Reset Status Register */
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u8 cwcr; /* 0x11 Core Watchdog Control Register */
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u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */
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u8 cwsr; /* 0x13 Core Watchdog Service Register */
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u32 dmareqc; /* 0x14 */
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u32 res3; /* 0x18 */
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u32 mpark; /* 0x1C */
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u8 mpr; /* 0x20 */
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u8 res4[3]; /* 0x21 - 0x23 */
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u8 pacr0; /* 0x24 */
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u8 pacr1; /* 0x25 */
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u8 pacr2; /* 0x26 */
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u8 pacr3; /* 0x27 */
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u8 pacr4; /* 0x28 */
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u32 res5; /* 0x29 */
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u8 pacr5; /* 0x2a */
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u8 pacr6; /* 0x2b */
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u8 pacr7; /* 0x2c */
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u32 res6; /* 0x2d */
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u8 pacr8; /* 0x2e */
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u32 res7; /* 0x2f */
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u8 gpacr; /* 0x30 */
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u8 res8[3]; /* 0x31 - 0x33 */
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} scm_t;
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/* SDRAM controller registers */
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typedef struct sdram_ctrl {
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u16 dcr; /* 0x00 Control register */
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u16 res1[3]; /* 0x02 - 0x07 */
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u32 dacr0; /* 0x08 address and control register 0 */
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u32 dmr0; /* 0x0C mask register block 0 */
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u32 dacr1; /* 0x10 address and control register 1 */
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u32 dmr1; /* 0x14 mask register block 1 */
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} sdram_t;
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/* Flexbus module Chip select registers */
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typedef struct fbcs_ctrl {
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u16 csar0; /* 0x00 Chip-Select Address Register 0 */
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u16 res0;
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u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
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u16 res1; /* 0x08 */
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u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
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u16 csar1; /* 0x0C Chip-Select Address Register 1 */
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u16 res2;
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u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
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u16 res3; /* 0x14 */
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u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
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u16 csar2; /* 0x18 Chip-Select Address Register 2 */
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u16 res4;
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u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
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u16 res5; /* 0x20 */
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u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
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u16 csar3; /* 0x24 Chip-Select Address Register 3 */
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u16 res6;
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u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
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u16 res7; /* 0x2C */
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u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
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u16 csar4; /* 0x30 Chip-Select Address Register 4 */
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u16 res8;
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u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
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u16 res9; /* 0x38 */
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u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
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u16 csar5; /* 0x3C Chip-Select Address Register 5 */
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u16 res10;
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u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
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u16 res11; /* 0x44 */
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u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
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u16 csar6; /* 0x48 Chip-Select Address Register 5 */
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u16 res12;
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u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
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u16 res13; /* 0x50 */
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u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
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u16 csar7; /* 0x54 Chip-Select Address Register 5 */
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u16 res14;
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u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
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u16 res15; /* 0x5C */
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u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
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} fbcs_t;
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/* QSPI module registers */
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typedef struct qspi_ctrl {
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u16 qmr; /* Mode register */
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u16 res1;
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u16 qdlyr; /* Delay register */
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u16 res2;
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u16 qwr; /* Wrap register */
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u16 res3;
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u16 qir; /* Interrupt register */
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u16 res4;
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u16 qar; /* Address register */
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u16 res5;
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u16 qdr; /* Data register */
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u16 res6;
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} qspi_t;
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/* Interrupt module registers */
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typedef struct int0_ctrl {
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/* Interrupt Controller 0 */
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u32 iprh0; /* 0x00 Pending Register High */
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u32 iprl0; /* 0x04 Pending Register Low */
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u32 imrh0; /* 0x08 Mask Register High */
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u32 imrl0; /* 0x0C Mask Register Low */
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u32 frch0; /* 0x10 Force Register High */
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u32 frcl0; /* 0x14 Force Register Low */
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u8 irlr; /* 0x18 */
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u8 iacklpr; /* 0x19 */
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u16 res1[19]; /* 0x1a - 0x3c */
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u8 icr0[64]; /* 0x40 - 0x7F Control registers */
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u32 res3[24]; /* 0x80 - 0xDF */
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u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
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u8 res4[3]; /* 0xE1 - 0xE3 */
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u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
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u8 res5[3]; /* 0xE5 - 0xE7 */
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u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
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u8 res6[3]; /* 0xE9 - 0xEB */
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u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
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u8 res7[3]; /* 0xED - 0xEF */
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u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
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u8 res8[3]; /* 0xF1 - 0xF3 */
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u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
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u8 res9[3]; /* 0xF5 - 0xF7 */
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u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
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u8 resa[3]; /* 0xF9 - 0xFB */
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u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
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u8 resb[3]; /* 0xFD - 0xFF */
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} int0_t;
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typedef struct int1_ctrl {
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/* Interrupt Controller 1 */
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u32 iprh1; /* 0x00 Pending Register High */
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u32 iprl1; /* 0x04 Pending Register Low */
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u32 imrh1; /* 0x08 Mask Register High */
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u32 imrl1; /* 0x0C Mask Register Low */
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u32 frch1; /* 0x10 Force Register High */
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u32 frcl1; /* 0x14 Force Register Low */
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u8 irlr; /* 0x18 */
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u8 iacklpr; /* 0x19 */
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u16 res1[19]; /* 0x1a - 0x3c */
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u8 icr1[64]; /* 0x40 - 0x7F */
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u32 res4[24]; /* 0x80 - 0xDF */
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u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
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u8 res5[3]; /* 0xE1 - 0xE3 */
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u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
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u8 res6[3]; /* 0xE5 - 0xE7 */
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u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
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u8 res7[3]; /* 0xE9 - 0xEB */
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u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
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u8 res8[3]; /* 0xED - 0xEF */
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u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
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u8 res9[3]; /* 0xF1 - 0xF3 */
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u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
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u8 resa[3]; /* 0xF5 - 0xF7 */
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u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
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u8 resb[3]; /* 0xF9 - 0xFB */
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u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
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u8 resc[3]; /* 0xFD - 0xFF */
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} int1_t;
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typedef struct intgack_ctrl1 {
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/* Global IACK Registers */
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u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
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u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
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} intgack_t;
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/* GPIO port registers */
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typedef struct gpio_ctrl {
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/* Port Output Data Registers */
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u8 podr_addr; /* 0x00 */
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u8 podr_datah; /* 0x01 */
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u8 podr_datal; /* 0x02 */
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u8 podr_busctl; /* 0x03 */
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u8 podr_bs; /* 0x04 */
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u8 podr_cs; /* 0x05 */
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u8 podr_sdram; /* 0x06 */
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u8 podr_feci2c; /* 0x07 */
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u8 podr_uarth; /* 0x08 */
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u8 podr_uartl; /* 0x09 */
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u8 podr_qspi; /* 0x0A */
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u8 podr_timer; /* 0x0B */
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u8 podr_etpu; /* 0x0C */
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u8 res1[3]; /* 0x0D - 0x0F */
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/* Port Data Direction Registers */
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u8 pddr_addr; /* 0x10 */
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u8 pddr_datah; /* 0x11 */
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u8 pddr_datal; /* 0x12 */
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u8 pddr_busctl; /* 0x13 */
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u8 pddr_bs; /* 0x14 */
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u8 pddr_cs; /* 0x15 */
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u8 pddr_sdram; /* 0x16 */
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u8 pddr_feci2c; /* 0x17 */
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u8 pddr_uarth; /* 0x18 */
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u8 pddr_uartl; /* 0x19 */
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u8 pddr_qspi; /* 0x1A */
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u8 pddr_timer; /* 0x1B */
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u8 pddr_etpu; /* 0x1C */
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u8 res2[3]; /* 0x1D - 0x1F */
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/* Port Data Direction Registers */
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u8 ppdsdr_addr; /* 0x20 */
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u8 ppdsdr_datah; /* 0x21 */
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u8 ppdsdr_datal; /* 0x22 */
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u8 ppdsdr_busctl; /* 0x23 */
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u8 ppdsdr_bs; /* 0x24 */
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u8 ppdsdr_cs; /* 0x25 */
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u8 ppdsdr_sdram; /* 0x26 */
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u8 ppdsdr_feci2c; /* 0x27 */
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u8 ppdsdr_uarth; /* 0x28 */
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u8 ppdsdr_uartl; /* 0x29 */
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u8 ppdsdr_qspi; /* 0x2A */
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u8 ppdsdr_timer; /* 0x2B */
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u8 ppdsdr_etpu; /* 0x2C */
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u8 res3[3]; /* 0x2D - 0x2F */
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/* Port Clear Output Data Registers */
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u8 pclrr_addr; /* 0x30 */
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u8 pclrr_datah; /* 0x31 */
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u8 pclrr_datal; /* 0x32 */
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u8 pclrr_busctl; /* 0x33 */
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u8 pclrr_bs; /* 0x34 */
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u8 pclrr_cs; /* 0x35 */
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u8 pclrr_sdram; /* 0x36 */
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u8 pclrr_feci2c; /* 0x37 */
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u8 pclrr_uarth; /* 0x38 */
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u8 pclrr_uartl; /* 0x39 */
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u8 pclrr_qspi; /* 0x3A */
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u8 pclrr_timer; /* 0x3B */
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u8 pclrr_etpu; /* 0x3C */
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u8 res4[3]; /* 0x3D - 0x3F */
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/* Pin Assignment Registers */
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u8 par_ad; /* 0x40 */
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u8 res5; /* 0x41 */
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u16 par_busctl; /* 0x42 */
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u8 par_bs; /* 0x44 */
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u8 par_cs; /* 0x45 */
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u8 par_sdram; /* 0x46 */
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u8 par_feci2c; /* 0x47 */
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u16 par_uart; /* 0x48 */
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u8 par_qspi; /* 0x4A */
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u8 res6; /* 0x4B */
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u16 par_timer; /* 0x4C */
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u8 par_etpu; /* 0x4E */
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u8 res7; /* 0x4F */
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/* Drive Strength Control Registers */
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u8 dscr_eim; /* 0x50 */
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u8 dscr_etpu; /* 0x51 */
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u8 dscr_feci2c; /* 0x52 */
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u8 dscr_uart; /* 0x53 */
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u8 dscr_qspi; /* 0x54 */
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u8 dscr_timer; /* 0x55 */
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u16 res8; /* 0x56 */
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} gpio_t;
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/*Chip configuration module registers */
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typedef struct ccm_ctrl {
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u8 rcr; /* 0x01 */
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u8 rsr; /* 0x02 */
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u16 res1; /* 0x03 */
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u16 ccr; /* 0x04 Chip configuration register */
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u16 lpcr; /* 0x06 Low-power Control register */
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u16 rcon; /* 0x08 Rreset configuration register */
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u16 cir; /* 0x0a Chip identification register */
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} ccm_t;
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/* Clock Module registers */
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typedef struct pll_ctrl {
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u32 syncr; /* 0x00 synthesizer control register */
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u32 synsr; /* 0x04 synthesizer status register */
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} pll_t;
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/* Watchdog registers */
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typedef struct wdog_ctrl {
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u16 cr; /* 0x00 Control register */
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u16 mr; /* 0x02 Modulus register */
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u16 cntr; /* 0x04 Count register */
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u16 sr; /* 0x06 Service register */
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} wdog_t;
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/* FlexCan module registers */
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typedef struct can_ctrl {
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u32 mcr; /* 0x00 Module Configuration register */
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u32 ctrl; /* 0x04 Control register */
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u32 timer; /* 0x08 Free Running Timer */
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u32 res1; /* 0x0C */
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u32 rxgmask; /* 0x10 Rx Global Mask */
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u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
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u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
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u32 errcnt; /* 0x1C Error Counter Register */
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u32 errstat; /* 0x20 Error and status Register */
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u32 res2; /* 0x24 */
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u32 imask; /* 0x28 Interrupt Mask Register */
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u32 res3; /* 0x2C */
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u32 iflag; /* 0x30 Interrupt Flag Register */
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u32 res4[19]; /* 0x34 - 0x7F */
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u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
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} can_t;
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#endif /* __IMMAP_5235__ */
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