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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
159 lines
2.8 KiB
C
159 lines
2.8 KiB
C
/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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* Keith Outwater, keith_outwater@mvis.com.
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*
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* (C) Copyright 2011
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* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ACEX1K.h>
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#include <command.h>
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#include "mergerbox.h"
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#include "fpga.h"
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Altera_CYC2_Passive_Serial_fns altera_fns = {
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fpga_null_fn,
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fpga_config_fn,
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fpga_status_fn,
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fpga_done_fn,
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fpga_wr_fn,
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fpga_null_fn,
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fpga_null_fn,
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};
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Altera_desc cyclone2 = {
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Altera_CYC2,
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passive_serial,
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Altera_EP2C20_SIZE,
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(void *) &altera_fns,
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NULL,
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0
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};
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DECLARE_GLOBAL_DATA_PTR;
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int mergerbox_init_fpga(void)
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{
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debug("Initialize FPGA interface\n");
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fpga_init();
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fpga_add(fpga_altera, &cyclone2);
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return 1;
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}
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int fpga_null_fn(int cookie)
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{
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return 0;
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}
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int fpga_config_fn(int assert, int flush, int cookie)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
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u32 dvo = gpio->dat;
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dvo &= ~FPGA_CONFIG;
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gpio->dat = dvo;
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udelay(5);
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dvo |= FPGA_CONFIG;
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gpio->dat = dvo;
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return assert;
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}
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int fpga_done_fn(int cookie)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
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int result = 0;
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udelay(10);
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debug("CONF_DONE check ... ");
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if (gpio->dat & FPGA_CONF_DONE) {
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debug("high\n");
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result = 1;
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} else
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debug("low\n");
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return result;
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}
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int fpga_status_fn(int cookie)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
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int result = 0;
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debug("STATUS check ... ");
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if (gpio->dat & FPGA_STATUS) {
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debug("high\n");
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result = 1;
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} else
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debug("low\n");
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return result;
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}
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int fpga_clk_fn(int assert_clk, int flush, int cookie)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
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u32 dvo = gpio->dat;
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debug("CLOCK %s\n", assert_clk ? "high" : "low");
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if (assert_clk)
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dvo |= FPGA_CCLK;
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else
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dvo &= ~FPGA_CCLK;
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if (flush)
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gpio->dat = dvo;
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return assert_clk;
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}
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static inline int _write_fpga(u8 val, int dump)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
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int i;
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u32 dvo = gpio->dat;
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if (dump)
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debug(" %02x -> ", val);
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for (i = 0; i < 8; i++) {
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dvo &= ~FPGA_CCLK;
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gpio->dat = dvo;
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dvo &= ~FPGA_DIN;
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if (dump)
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debug("%d ", val&1);
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if (val & 1)
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dvo |= FPGA_DIN;
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gpio->dat = dvo;
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dvo |= FPGA_CCLK;
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gpio->dat = dvo;
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val >>= 1;
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}
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if (dump)
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debug("\n");
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return 0;
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}
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int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
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{
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unsigned char *data = (unsigned char *) buf;
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int i;
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debug("fpga_wr: buf %p / size %d\n", buf, len);
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for (i = 0; i < len; i++)
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_write_fpga(data[i], 0);
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debug("\n");
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return FPGA_SUCCESS;
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}
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