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91172baf46
Provides initial support for TI OMAP-L1x/DA8xx SoC devices. See http://www.ti.com Provides: Low level initialisation. System clock API. Timer control. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
192 lines
4.5 KiB
C
192 lines
4.5 KiB
C
/*
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* Copyright (C) 2004 Texas Instruments.
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* Copyright (C) 2009 David Brownell
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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/* offsets from PLL controller base */
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#define PLLC_PLLCTL 0x100
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#define PLLC_PLLM 0x110
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#define PLLC_PREDIV 0x114
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#define PLLC_PLLDIV1 0x118
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#define PLLC_PLLDIV2 0x11c
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#define PLLC_PLLDIV3 0x120
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#define PLLC_POSTDIV 0x128
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#define PLLC_BPDIV 0x12c
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#define PLLC_PLLDIV4 0x160
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#define PLLC_PLLDIV5 0x164
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#define PLLC_PLLDIV6 0x168
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#define PLLC_PLLDIV8 0x170
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#define PLLC_PLLDIV9 0x174
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#define BIT(x) (1 << (x))
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/* SOC-specific pll info */
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#ifdef CONFIG_SOC_DM355
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#define ARM_PLLDIV PLLC_PLLDIV1
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#define DDR_PLLDIV PLLC_PLLDIV1
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#endif
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#ifdef CONFIG_SOC_DM644X
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#define ARM_PLLDIV PLLC_PLLDIV2
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#define DSP_PLLDIV PLLC_PLLDIV1
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#define DDR_PLLDIV PLLC_PLLDIV2
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#endif
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#ifdef CONFIG_SOC_DM6447
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#define ARM_PLLDIV PLLC_PLLDIV2
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#define DSP_PLLDIV PLLC_PLLDIV1
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#define DDR_PLLDIV PLLC_PLLDIV1
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#endif
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#ifdef CONFIG_SOC_DA8XX
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const dv_reg * const sysdiv[7] = {
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&davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
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&davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4,
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&davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6,
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&davinci_pllc_regs->plldiv7
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};
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int clk_get(enum davinci_clk_ids id)
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{
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int pre_div;
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int pllm;
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int post_div;
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int pll_out;
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pll_out = CONFIG_SYS_OSCIN_FREQ;
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if (id == DAVINCI_AUXCLK_CLKID)
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goto out;
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/*
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* Lets keep this simple. Combining operations can result in
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* unexpected approximations
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*/
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pre_div = (readl(&davinci_pllc_regs->prediv) &
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DAVINCI_PLLC_DIV_MASK) + 1;
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pllm = readl(&davinci_pllc_regs->pllm) + 1;
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pll_out /= pre_div;
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pll_out *= pllm;
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if (id == DAVINCI_PLLM_CLKID)
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goto out;
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post_div = (readl(&davinci_pllc_regs->postdiv) &
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DAVINCI_PLLC_DIV_MASK) + 1;
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pll_out /= post_div;
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if (id == DAVINCI_PLLC_CLKID)
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goto out;
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pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1;
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out:
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return pll_out;
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}
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#endif /* CONFIG_SOC_DA8XX */
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#ifdef CONFIG_DISPLAY_CPUINFO
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static unsigned pll_div(volatile void *pllbase, unsigned offset)
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{
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u32 div;
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div = REG(pllbase + offset);
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return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
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}
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static inline unsigned pll_prediv(volatile void *pllbase)
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{
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#ifdef CONFIG_SOC_DM355
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/* this register read seems to fail on pll0 */
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if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
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return 8;
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else
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return pll_div(pllbase, PLLC_PREDIV);
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#endif
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return 1;
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}
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static inline unsigned pll_postdiv(volatile void *pllbase)
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{
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#ifdef CONFIG_SOC_DM355
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return pll_div(pllbase, PLLC_POSTDIV);
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#elif defined(CONFIG_SOC_DM6446)
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if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
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return pll_div(pllbase, PLLC_POSTDIV);
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#endif
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return 1;
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}
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static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
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{
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volatile void *pllbase = (volatile void *) pll_addr;
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unsigned base = CONFIG_SYS_HZ_CLOCK / 1000;
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/* the PLL might be bypassed */
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if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
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base /= pll_prediv(pllbase);
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base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
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base /= pll_postdiv(pllbase);
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}
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return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
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}
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int print_cpuinfo(void)
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{
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/* REVISIT fetch and display CPU ID and revision information
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* too ... that will matter as more revisions appear.
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*/
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printf("Cores: ARM %d MHz",
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pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
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#ifdef DSP_PLLDIV
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printf(", DSP %d MHz",
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pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
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#endif
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printf("\nDDR: %d MHz\n",
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/* DDR PHY uses an x2 input clock */
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pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
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/ 2);
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return 0;
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}
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#endif
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int cpu_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_DRIVER_TI_EMAC)
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davinci_emac_initialize();
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#endif
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return 0;
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}
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