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3eb90bad65
According to the PPC reference implementation the udelay() function is responsible for resetting the watchdog timer as frequently as needed. Most other architectures do not meet that requirement, so long-running operations might result in a watchdog reset. This patch adds a generic udelay() function which takes care of resetting the watchdog before calling an architecture-specific __udelay(). Signed-off-by: Ingo van Lil <inguin@gmx.de>
85 lines
2.2 KiB
C
85 lines
2.2 KiB
C
/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* stuff specific for the sc520, but independent of implementation */
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#include <common.h>
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#include <asm/interrupt.h>
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#include <asm/ic/sc520.h>
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void sc520_timer_isr(void)
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{
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/* Ack the GP Timer Interrupt */
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sc520_mmcr->gptmrsta = 0x02;
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}
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int timer_init(void)
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{
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/* Register the SC520 specific timer interrupt handler */
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register_timer_isr (sc520_timer_isr);
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/* Install interrupt handler for GP Timer 1 */
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irq_install_handler (0, timer_isr, NULL);
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/* Map GP Timer 1 to Master PIC IR0 */
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sc520_mmcr->gp_tmr_int_map[1] = 0x01;
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/* Disable GP Timers 1 & 2 - Allow configuration writes */
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sc520_mmcr->gptmr1ctl = 0x4000;
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sc520_mmcr->gptmr2ctl = 0x4000;
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/* Reset GP Timers 1 & 2 */
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sc520_mmcr->gptmr1cnt = 0x0000;
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sc520_mmcr->gptmr2cnt = 0x0000;
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/* Setup GP Timer 2 as a 100kHz (10us) prescaler */
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sc520_mmcr->gptmr2maxcmpa = 83;
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sc520_mmcr->gptmr2ctl = 0xc001;
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/* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
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sc520_mmcr->gptmr1maxcmpa = 100;
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sc520_mmcr->gptmr1ctl = 0xe009;
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unmask_irq (0);
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/* Clear the GP Timer 1 status register to get the show rolling*/
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sc520_mmcr->gptmrsta = 0x02;
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return 0;
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}
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void __udelay(unsigned long usec)
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{
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int m = 0;
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long u;
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long temp;
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temp = sc520_mmcr->swtmrmilli;
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temp = sc520_mmcr->swtmrmicro;
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do {
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m += sc520_mmcr->swtmrmilli;
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u = sc520_mmcr->swtmrmicro + (m * 1000);
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} while (u < usec);
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}
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