Chin Liang See 89a54abf1b ddr: altera: Configuring SDRAM extra cycles timing parameters ...

To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

2016-10-27 08:03:07 +02:00

..

Makefile

driver/ddr/altera: Add the sdram calibration portion

2015-08-08 14:14:05 +02:00

sdram.c

ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-10-27 08:03:07 +02:00

sequencer.c

ddr: altera: Repair DQ window centering code

2016-04-20 11:28:45 +02:00

sequencer.h

ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL

2015-08-08 14:14:29 +02:00