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dd4fdc0b14
This patch adds support for MediaTek MT7620 SoC. All files are dedicated for u-boot. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
114 lines
3.4 KiB
C
114 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <asm/addrspace.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/sizes.h>
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#include <linux/io.h>
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#include <mach/ddr.h>
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#include <mach/mc.h>
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#include "mt7620.h"
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/* SDR parameters */
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#define SDR_CFG0_VAL 0x51B283B3
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#define SDR_CFG1_VAL 0xC00003A9
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/* DDR2 DQ_DLY */
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#define DDR2_DQ_DLY 0x88888888
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/* DDR2 DQS_DLY */
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#define DDR2_DQS_DLY 0x88888888
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static const struct mc_ddr_cfg ddr1_cfgs_200mhz[] = {
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[DRAM_8MB] = { 0x34A1EB94, 0x20262324, 0x28000033, 0x00000002, 0x00000000 },
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[DRAM_16MB] = { 0x34A1EB94, 0x202A2324, 0x28000033, 0x00000002, 0x00000000 },
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[DRAM_32MB] = { 0x34A1E5CA, 0x202E2324, 0x28000033, 0x00000002, 0x00000000 },
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[DRAM_64MB] = { 0x3421E5CA, 0x20322324, 0x28000033, 0x00000002, 0x00000000 },
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[DRAM_128MB] = { 0x241B05CA, 0x20362334, 0x28000033, 0x00000002, 0x00000000 },
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};
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static const struct mc_ddr_cfg ddr1_cfgs_160mhz[] = {
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[DRAM_8MB] = { 0x239964A1, 0x20262323, 0x00000033, 0x00000002, 0x00000000 },
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[DRAM_16MB] = { 0x239964A1, 0x202A2323, 0x00000033, 0x00000002, 0x00000000 },
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[DRAM_32MB] = { 0x239964A1, 0x202E2323, 0x00000033, 0x00000002, 0x00000000 },
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[DRAM_64MB] = { 0x239984A1, 0x20322323, 0x00000033, 0x00000002, 0x00000000 },
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[DRAM_128MB] = { 0x239AB4A1, 0x20362333, 0x00000033, 0x00000002, 0x00000000 },
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};
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static const struct mc_ddr_cfg ddr2_cfgs_200mhz[] = {
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[DRAM_32MB] = { 0x2519E2E5, 0x222E2323, 0x68000C43, 0x00000416, 0x0000000A },
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[DRAM_64MB] = { 0x249AA2E5, 0x22322323, 0x68000C43, 0x00000416, 0x0000000A },
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[DRAM_128MB] = { 0x249B42E5, 0x22362323, 0x68000C43, 0x00000416, 0x0000000A },
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[DRAM_256MB] = { 0x249CE2E5, 0x223A2323, 0x68000C43, 0x00000416, 0x0000000A },
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};
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static const struct mc_ddr_cfg ddr2_cfgs_160mhz[] = {
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[DRAM_32MB] = { 0x23918250, 0x222E2322, 0x40000A43, 0x00000416, 0x00000006 },
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[DRAM_64MB] = { 0x239A2250, 0x22322322, 0x40000A43, 0x00000416, 0x00000008 },
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[DRAM_128MB] = { 0x2392A250, 0x22362322, 0x40000A43, 0x00000416, 0x00000008 },
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[DRAM_256MB] = { 0x24140250, 0x223A2322, 0x40000A43, 0x00000416, 0x00000008 },
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};
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static void mt7620_memc_reset(int assert)
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{
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void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
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if (assert)
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setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST);
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else
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clrbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST);
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}
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void mt7620_dram_init(void)
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{
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void __iomem *sysc;
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bool lspd = false;
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int ddr_type, aux;
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struct mc_ddr_init_param param;
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sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
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ddr_type = (readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE_M)
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>> DRAM_TYPE_S;
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aux = readl(sysc + SYSCTL_CPLL_CFG1_REG) &
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(CPU_CLK_AUX1 | CPU_CLK_AUX0);
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if (aux == CPU_CLK_AUX1 || aux == CPU_CLK_AUX0)
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lspd = true;
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mt7620_memc_reset(1);
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__udelay(200);
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param.memc = ioremap_nocache(MEMCTL_BASE, MEMCTL_SIZE);
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param.dq_dly = DDR2_DQ_DLY;
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param.dqs_dly = DDR2_DQS_DLY;
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param.mc_reset = mt7620_memc_reset;
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param.memsize = 0;
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param.bus_width = 0;
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if (ddr_type == DRAM_DDR1) {
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if (lspd)
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param.cfgs = ddr1_cfgs_160mhz;
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else
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param.cfgs = ddr1_cfgs_200mhz;
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ddr1_init(¶m);
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} else if (ddr_type == DRAM_DDR2) {
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if (lspd)
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param.cfgs = ddr2_cfgs_160mhz;
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else
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param.cfgs = ddr2_cfgs_200mhz;
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ddr2_init(¶m);
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} else {
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param.sdr_cfg0 = SDR_CFG0_VAL;
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param.sdr_cfg1 = SDR_CFG1_VAL;
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sdr_init(¶m);
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}
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}
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