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d9434a17e5
Add common x86 ASL files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
81 lines
1.7 KiB
Plaintext
81 lines
1.7 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2018 Intel Corporation.
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*/
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#include <intelblocks/pcr.h>
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/*
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* Calculate PCR register base at specified PID
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* Arg0 - PCR Port ID
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*/
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Method (PCRB, 1, NotSerialized)
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{
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Return (Add (IOMAP_P2SB_BAR,
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ShiftLeft (Arg0, PCR_PORTID_SHIFT)))
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}
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/*
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* Read a PCR register at specified PID and offset
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* Arg0 - PCR Port ID
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* Arg1 - Register Offset
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*/
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Method (PCRR, 2, Serialized)
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{
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OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
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Field (PCRD, DWordAcc, NoLock, Preserve)
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{
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DATA, 32
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}
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Return (DATA)
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}
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/*
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* AND a value with PCR register at specified PID and offset
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* Arg0 - PCR Port ID
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* Arg1 - Register Offset
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* Arg2 - Value to AND
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*/
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Method (PCRA, 3, Serialized)
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{
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OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
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Field (PCRD, DWordAcc, NoLock, Preserve)
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{
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DATA, 32
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}
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And (DATA, Arg2, DATA)
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/*
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* After every write one needs to read an innocuous register
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* to ensure the writes are completed for certain ports. This is done
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* for all ports so that the callers don't need the per-port knowledge
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* for each transaction.
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*/
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PCRR (Arg0, Arg1)
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}
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/*
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* OR a value with PCR register at specified PID and offset
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* Arg0 - PCR Port ID
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* Arg1 - Register Offset
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* Arg2 - Value to OR
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*/
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Method (PCRO, 3, Serialized)
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{
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OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
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Field (PCRD, DWordAcc, NoLock, Preserve)
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{
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DATA, 32
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}
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Or (DATA, Arg2, DATA)
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/*
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* After every write one needs to read an innocuous register
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* to ensure the writes are completed for certain ports. This is done
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* for all ports so that the callers don't need the per-port knowledge
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* for each transaction.
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*/
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PCRR (Arg0, Arg1)
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}
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