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1be82afa80
Use proper project name in comments, Kconfig, readmes. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Qu Wenruo <wqu@suse.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com
194 lines
6.7 KiB
ReStructuredText
194 lines
6.7 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0+
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LS1046ARDB
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==========
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The LS1046A Reference Design Board (RDB) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS1046A
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LayerScape Architecture processor. The LS1046ARDB provides SW development
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platform for the Freescale LS1046A processor series, with a complete
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debugging environment. The LS1046A RDB is lead-free and RoHS-compliant.
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LS1046A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
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SoC overview.
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LS1046ARDB board Overview
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-------------------------
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- SERDES1 Connections, 4 lanes supporting:
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- Lane0: 10GBase-R with x1 RJ45 connector
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- Lane1: 10GBase-R Cage
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- Lane2: SGMII.5
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- Lane3: SGMII.6
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- SERDES2 Connections, 4 lanes supporting:
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- Lane0: PCIe1 with miniPCIe slot
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- Lane1: PCIe2 with PCIe x2 slot
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- Lane2: PCIe3 with PCIe x4 slot
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- Lane3: SATA
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- DDR Controller
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- 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
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- IFC/Local Bus
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- One 512 MB NAND flash with ECC support
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- CPLD connection
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- USB 3.0
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- one Type A port, one Micro-AB port
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- SDHC: connects directly to a full SD/MMC slot
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- DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz)
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- 4 I2C controllers
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- UART
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- Two 4-pin serial ports at up to 115.2 Kbit/s
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- Two DB9 D-Type connectors supporting one Serial port each
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- ARM JTAG support
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Memory map from core's view
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----------------------------
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================== ================== ================ =====
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Start Address End Address Description Size
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================== ================== ================ =====
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``0x00_0000_0000`` ``0x00_000F_FFFF`` Secure Boot ROM 1M
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``0x00_0100_0000`` ``0x00_0FFF_FFFF`` CCSRBAR 240M
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``0x00_1000_0000`` ``0x00_1000_FFFF`` OCRAM0 64K
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``0x00_1001_0000`` ``0x00_1001_FFFF`` OCRAM1 64K
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``0x00_2000_0000`` ``0x00_20FF_FFFF`` DCSR 16M
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``0x00_7E80_0000`` ``0x00_7E80_FFFF`` IFC - NAND Flash 64K
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``0x00_7FB0_0000`` ``0x00_7FB0_0FFF`` IFC - CPLD 4K
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``0x00_8000_0000`` ``0x00_FFFF_FFFF`` DRAM1 2G
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``0x05_0000_0000`` ``0x05_07FF_FFFF`` QMAN S/W Portal 128M
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``0x05_0800_0000`` ``0x05_0FFF_FFFF`` BMAN S/W Portal 128M
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``0x08_8000_0000`` ``0x09_FFFF_FFFF`` DRAM2 6G
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``0x40_0000_0000`` ``0x47_FFFF_FFFF`` PCI Express1 32G
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``0x48_0000_0000`` ``0x4F_FFFF_FFFF`` PCI Express2 32G
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``0x50_0000_0000`` ``0x57_FFFF_FFFF`` PCI Express3 32G
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================== ================== ================ =====
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QSPI flash map
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--------------
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================== ================== ================== =====
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Start Address End Address Description Size
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================== ================== ================== =====
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``0x00_4000_0000`` ``0x00_400F_FFFF`` RCW + PBI 1M
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``0x00_4010_0000`` ``0x00_402F_FFFF`` U-Boot 2M
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``0x00_4030_0000`` ``0x00_403F_FFFF`` U-Boot Env 1M
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``0x00_4040_0000`` ``0x00_405F_FFFF`` PPA 2M
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``0x00_4060_0000`` ``0x00_408F_FFFF`` Secure boot header 3M
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+ bootscript
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``0x00_4090_0000`` ``0x00_4093_FFFF`` FMan ucode 256K
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``0x00_4094_0000`` ``0x00_4097_FFFF`` QE/uQE firmware 256K
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``0x00_4098_0000`` ``0x00_40FF_FFFF`` Reserved 6M
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``0x00_4100_0000`` ``0x00_43FF_FFFF`` FIT Image 48M
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================== ================== ================== =====
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Booting Options
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---------------
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NB: The reference manual documents the RCW source with the *least-significant
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bit first*.
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QSPI boot
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^^^^^^^^^
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This is the default. ``{ SW5[0:8], SW4[0] }`` should be ``0010_0010_0``.
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SD boot and eMMC boot
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^^^^^^^^^^^^^^^^^^^^^
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``{ SW5[0:8], SW4[0] }`` should be ``0010_0000_0``. eMMC is selected only if
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there is no SD card in the slot.
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.. _ls1046ardb_jtag:
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JTAG boot
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^^^^^^^^^
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To recover a bricked board, or to perform initial programming, the ls1046
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supports using two hard-coded Reset Configuration Words (RCWs). Unfortunately,
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this configuration disables most functionality, including the uarts and ethernet.
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However, the SD/MMC and flash controllers are still functional. To get around
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the lack of a serial console, we will use ARM semihosting instead. When
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enabled, OpenOCD will interpret certain instructions as calls to the host
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operating system. This allows U-Boot to use the console, read/write files, or
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run arbitrary commands (!).
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When configuring U-Boot, ensure that ``CONFIG_SEMIHOSTING``,
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``CONFIG_SPL_SEMIHOSTING``, and ``CONFIG_SEMIHOSTING_SERIAL`` are enabled.
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``{ SW5[0:8], SW4[0] }`` should be ``0100_1111_0``. Additionally, ``SW4[7]``
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should be set to ``0``. Connect to the "console" USB connector on the front of
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the enclosure.
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Create a new file called ``u-boot.tcl`` (or whatever you choose) with the
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following contents::
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# Load the configuration for the LS1046ARDB
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source [find board/nxp_rdb-ls1046a.cfg]
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# Initialize the scan chain
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init
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# Stop the processor
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halt
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# Enable semihosting
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arm semihosting enable
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# Load U-Boot SPL
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load_image spl/u-boot-spl 0 elf
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# Start executing SPL at the beginning of OCRAM
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resume 0x10000000
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Then, launch openocd like::
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openocd -f u-boot.tcl
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You should see the U-Boot SPL banner followed by the banner for U-Boot proper
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in the output of openocd. The CMSIS-DAP adapter is slow, so this can take a
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long time. If you don't see it, something has gone wrong. After a while, you
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should see the prompt. You can load an image using semihosting by running::
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=> load hostfs - $loadaddr <name of file>
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Note that openocd's terminal is "cooked," so commands will only be sent to
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U-Boot when you press enter, and all commands will be echoed twice.
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Additionally, openocd will block when waiting for input, ignoring gdb, JTAG
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events, and Ctrl-Cs. To make openocd process these events, just hit enter.
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Using an external JTAG adapter
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""""""""""""""""""""""""""""""
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The CMSIS-DAP adapter can be rather slow. To speed up booting, use an external
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JTAG adapter. The following examples assume you are using a J-Link, though any
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adapter supported by OpenOCD will do. Ensure that ``SW4[7]`` is ``1``. Attach
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your jtag adapter to J22. Modify ``u-boot.tcl`` and replace the first two lines
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with the following::
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# Load the J-Link configuration (or whatever your adapter is)
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source [find interface/jlink.cfg]
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# Use JTAG, since the J-Link also supports SWD
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transport select jtag
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# The reset pin resets the whole CPU
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reset_config srst_only
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# Load the LS1046A config
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source [find target/ls1046a.cfg]
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You can proceed as normal through the rest of the steps above. I got a speedup
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of around 100x by using a J-Link.
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Debug UART
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----------
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To enable the debug UART, enable the following config options::
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CONFIG_DEBUG_UART_NS16550=y
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CONFIG_DEBUG_UART_BASE=0x21c0500
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CONFIG_DEBUG_UART_CLOCK=300000000
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