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273d11eae5
1. Add linkage.h support from blackfin to common include, which is a reduced version from Linux. 2. Add architecture part support of linkage.h into blackfin 3. Fix include path of in blackfin related to linkage.h due to header file movement. Signed-off-by: Macpaul Lin <macpaul@andestech.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
88 lines
2.0 KiB
ArmAsm
88 lines
2.0 KiB
ArmAsm
/*
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* Blackfin cache control code
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*
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* Copyright 2003-2008 Analog Devices Inc.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/blackfin.h>
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.text
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/* Since all L1 caches work the same way, we use the same method for flushing
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* them. Only the actual flush instruction differs. We write this in asm as
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* GCC can be hard to coax into writing nice hardware loops.
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*
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* Also, we assume the following register setup:
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* R0 = start address
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* R1 = end address
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*/
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.macro do_flush flushins:req optflushins optnopins label
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R2 = -L1_CACHE_BYTES;
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/* start = (start & -L1_CACHE_BYTES) */
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R0 = R0 & R2;
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/* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
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R1 += -1;
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R1 = R1 & R2;
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R1 += L1_CACHE_BYTES;
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/* count = (end - start) >> L1_CACHE_SHIFT */
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R2 = R1 - R0;
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R2 >>= L1_CACHE_SHIFT;
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P1 = R2;
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.ifnb \label
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\label :
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.endif
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P0 = R0;
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LSETUP (1f, 2f) LC1 = P1;
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1:
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.ifnb \optflushins
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\optflushins [P0];
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.endif
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#if ANOMALY_05000443
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.ifb \optnopins
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2:
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.endif
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\flushins [P0++];
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.ifnb \optnopins
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2: \optnopins;
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.endif
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#else
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2: \flushins [P0++];
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#endif
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RTS;
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.endm
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/* Invalidate all instruction cache lines assocoiated with this memory area */
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ENTRY(_blackfin_icache_flush_range)
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do_flush IFLUSH, , nop
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ENDPROC(_blackfin_icache_flush_range)
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/* Flush all cache lines assocoiated with this area of memory. */
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ENTRY(_blackfin_icache_dcache_flush_range)
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do_flush FLUSH, IFLUSH
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ENDPROC(_blackfin_icache_dcache_flush_range)
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/* Throw away all D-cached data in specified region without any obligation to
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* write them back. Since the Blackfin ISA does not have an "invalidate"
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* instruction, we use flush/invalidate. Perhaps as a speed optimization we
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* could bang on the DTEST MMRs ...
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*/
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ENTRY(_blackfin_dcache_flush_invalidate_range)
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do_flush FLUSHINV
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ENDPROC(_blackfin_dcache_flush_invalidate_range)
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/* Flush all data cache lines assocoiated with this memory area */
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ENTRY(_blackfin_dcache_flush_range)
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do_flush FLUSH, , , .Ldfr
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ENDPROC(_blackfin_dcache_flush_range)
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