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0c12a1592c
T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
37 lines
701 B
C
37 lines
701 B
C
/*
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* Copyright 2003 Motorola,Inc.
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* Xianghua Xiao(x.xiao@motorola.com)
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*/
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#ifndef __E500_H__
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#define __E500_H__
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#ifndef __ASSEMBLY__
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typedef struct
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{
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unsigned long freq_processor[CONFIG_MAX_CPUS];
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unsigned long freq_systembus;
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unsigned long freq_ddrbus;
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unsigned long freq_localbus;
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unsigned long freq_qe;
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#ifdef CONFIG_SYS_DPAA_FMAN
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unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
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#endif
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#ifdef CONFIG_SYS_DPAA_QBMAN
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unsigned long freq_qman;
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#endif
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#ifdef CONFIG_SYS_DPAA_PME
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unsigned long freq_pme;
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#endif
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#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
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unsigned char diff_sysclk;
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#endif
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} MPC85xx_SYS_INFO;
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#endif /* _ASMLANGUAGE */
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#define RESET_VECTOR 0xfffffffc
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#endif /* __E500_H__ */
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