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	SH4 and SH4A are compatible. But some instructions are different from these. In Linux kernel, It is treated as a separate CPU, but for now, I think that there is no need to divide especially in the U-Boot. This removes CONFIG_SH4A definition from source code, SH4A is treated as SH4. And this fix white space. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
		
			
				
	
	
		
			78 lines
		
	
	
		
			970 B
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			78 lines
		
	
	
		
			970 B
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * (C) Copyright 2007
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|  * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #include <common.h>
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| #include <command.h>
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| #include <netdev.h>
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| #include <asm/processor.h>
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| #include <asm/cache.h>
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| 
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| int checkcpu(void)
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| {
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| 	puts("CPU: SH4\n");
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| 	return 0;
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| }
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| 
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| int cpu_init (void)
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| {
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| 	return 0;
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| }
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| 
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| int cleanup_before_linux (void)
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| {
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| 	disable_interrupts();
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| 	return 0;
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| }
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| 
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| int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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| {
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| 	disable_interrupts();
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| 	reset_cpu (0);
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| 	return 0;
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| }
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| 
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| void flush_cache (unsigned long addr, unsigned long size)
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| {
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| 	invalidate_dcache_range(addr , addr + size);
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| }
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| 
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| void icache_enable (void)
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| {
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| 	cache_control(0);
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| }
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| 
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| void icache_disable (void)
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| {
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| 	cache_control(1);
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| }
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| 
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| int icache_status (void)
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| {
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| 	return 0;
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| }
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| 
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| void dcache_enable (void)
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| {
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| }
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| 
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| void dcache_disable (void)
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| {
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| }
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| 
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| int dcache_status (void)
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| {
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| 	return 0;
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| }
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| 
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| int cpu_eth_init(bd_t *bis)
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| {
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| #ifdef CONFIG_SH_ETHER
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| 	sh_eth_initialize(bis);
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| #endif
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| 	return 0;
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| }
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