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a821c4af79
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
118 lines
2.6 KiB
C
118 lines
2.6 KiB
C
/*
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* Andestech ATCPIT100 timer driver
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*
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* (C) Copyright 2016
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* Rick Chen, NDS32 Software Engineering, rick@andestech.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <timer.h>
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#include <linux/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define REG32_TMR(x) (*(unsigned long *) ((plat->regs) + (x>>2)))
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/*
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* Definition of register offsets
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*/
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/* ID and Revision Register */
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#define ID_REV 0x0
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/* Configuration Register */
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#define CFG 0x10
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/* Interrupt Enable Register */
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#define INT_EN 0x14
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#define CH_INT_EN(c , i) ((1<<i)<<(4*c))
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/* Interrupt Status Register */
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#define INT_STA 0x18
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#define CH_INT_STA(c , i) ((1<<i)<<(4*c))
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/* Channel Enable Register */
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#define CH_EN 0x1C
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#define CH_TMR_EN(c , t) ((1<<t)<<(4*c))
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/* Ch n Control REgister */
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#define CH_CTL(n) (0x20+0x10*n)
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/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
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#define APB_CLK (1<<3)
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/* Channel mode , bit 0~2 */
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#define TMR_32 1
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#define TMR_16 2
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#define TMR_8 3
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#define PWM 4
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#define CH_REL(n) (0x24+0x10*n)
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#define CH_CNT(n) (0x28+0x10*n)
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struct atctmr_timer_regs {
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u32 id_rev; /* 0x00 */
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u32 reservd[3]; /* 0x04 ~ 0x0c */
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u32 cfg; /* 0x10 */
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u32 int_en; /* 0x14 */
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u32 int_st; /* 0x18 */
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u32 ch_en; /* 0x1c */
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u32 ch0_ctrl; /* 0x20 */
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u32 ch0_reload; /* 0x24 */
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u32 ch0_cntr; /* 0x28 */
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u32 reservd1; /* 0x2c */
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u32 ch1_ctrl; /* 0x30 */
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u32 ch1_reload; /* 0x34 */
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u32 int_mask; /* 0x38 */
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};
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struct atftmr_timer_platdata {
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unsigned long *regs;
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};
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static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
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{
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struct atftmr_timer_platdata *plat = dev->platdata;
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u32 val;
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val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
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*count = timer_conv_64(val);
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return 0;
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}
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static int atctmr_timer_probe(struct udevice *dev)
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{
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struct atftmr_timer_platdata *plat = dev->platdata;
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REG32_TMR(CH_REL(1)) = 0xffffffff;
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REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
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REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
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return 0;
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}
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static int atctme_timer_ofdata_to_platdata(struct udevice *dev)
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{
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struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
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plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE);
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return 0;
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}
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static const struct timer_ops ag101p_timer_ops = {
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.get_count = atftmr_timer_get_count,
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};
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static const struct udevice_id ag101p_timer_ids[] = {
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{ .compatible = "andestech,atcpit100" },
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{}
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};
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U_BOOT_DRIVER(altera_timer) = {
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.name = "ae3xx_timer",
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.id = UCLASS_TIMER,
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.of_match = ag101p_timer_ids,
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.ofdata_to_platdata = atctme_timer_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
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.probe = atctmr_timer_probe,
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.ops = &ag101p_timer_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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