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https://github.com/smaeul/u-boot.git
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69ef98b209
Device tree alignment with Linux kernel v5.19-rc1 - ARM: dts: stm32: Add alternate pinmux for ethernet0 pins - ARM: dts: stm32: Add alternate pinmux for mco2 pins - ARM: dts: stm32: fix pinctrl node name warnings (MPU soc) - ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group - dt-bindings: clock: add IDs for SCMI clocks on stm32mp15 - dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15 - dt-bindings: clock: stm32mp15: rename CK_SCMI define - dt-bindings: reset: stm32mp15: rename RST_SCMI define - dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15 - dt-bindings: clk: cleanup comments - ARM: dts: align SPI NOR node name with dtschema - ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP15 - ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1) - ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15 + patch from stm32-dt-for-v5.19-fixes-2 - ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15 - ARM: dts: stm32: fix pwr regulators references to use scmi - ARM: dts: stm32: use the correct clock source for CEC on stm32mp151 - ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 board - ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMI - ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
64 lines
1.3 KiB
C
64 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* stm32fx-clock.h
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*
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* Copyright (C) 2016 STMicroelectronics
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* Author: Gabriel Fernandez for STMicroelectronics.
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*/
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/*
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* List of clocks which are not derived from system clock (SYSCLOCK)
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*
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* The index of these clocks is the secondary index of DT bindings
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* (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt)
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*
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* e.g:
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<assigned-clocks = <&rcc 1 CLK_LSE>;
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*/
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#ifndef _DT_BINDINGS_CLK_STMFX_H
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#define _DT_BINDINGS_CLK_STMFX_H
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#define SYSTICK 0
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#define FCLK 1
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#define CLK_LSI 2
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#define CLK_LSE 3
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#define CLK_HSE_RTC 4
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#define CLK_RTC 5
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#define PLL_VCO_I2S 6
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#define PLL_VCO_SAI 7
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#define CLK_LCD 8
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#define CLK_I2S 9
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#define CLK_SAI1 10
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#define CLK_SAI2 11
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#define CLK_I2SQ_PDIV 12
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#define CLK_SAIQ_PDIV 13
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#define CLK_HSI 14
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#define CLK_SYSCLK 15
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#define CLK_F469_DSI 16
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#define END_PRIMARY_CLK 17
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#define CLK_HDMI_CEC 16
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#define CLK_SPDIF 17
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#define CLK_USART1 18
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#define CLK_USART2 19
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#define CLK_USART3 20
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#define CLK_UART4 21
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#define CLK_UART5 22
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#define CLK_USART6 23
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#define CLK_UART7 24
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#define CLK_UART8 25
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#define CLK_I2C1 26
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#define CLK_I2C2 27
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#define CLK_I2C3 28
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#define CLK_I2C4 29
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#define CLK_LPTIMER 30
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#define CLK_PLL_SRC 31
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#define CLK_DFSDM1 32
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#define CLK_ADFSDM1 33
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#define CLK_F769_DSI 34
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#define END_PRIMARY_CLK_F7 35
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#endif
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