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https://github.com/smaeul/u-boot.git
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5cae28c3b1
Pull common.c into common subdirectory of the board file, since this code can be reused by other Data Modul SBCs. Drop the include of lpddr4_timing.h, which is unneeded. Signed-off-by: Marek Vasut <marex@denx.de>
99 lines
2.2 KiB
C
99 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <hang.h>
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#include <image.h>
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#include <init.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8mm_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/ddr.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <dm/uclass.h>
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#include <dm/device.h>
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#include <dm/uclass-internal.h>
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#include <dm/device-internal.h>
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#include <power/pmic.h>
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#include <power/bd71837.h>
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#include "lpddr4_timing.h"
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#include "../common/common.h"
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DECLARE_GLOBAL_DATA_PTR;
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int data_modul_imx_edm_sbc_board_power_init(void)
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{
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struct udevice *dev;
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int ret;
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ret = pmic_get("pmic@4b", &dev);
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if (ret == -ENODEV) {
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puts("Failed to get PMIC\n");
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return 0;
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}
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if (ret != 0)
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return ret;
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/* Unlock the PMIC regs */
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pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
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/* Increase VDD_SOC to typical value 0.85V before first DRAM access */
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pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
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/* Increase VDD_DRAM to 0.975V for 3GHz DDR */
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pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
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/* Lock the PMIC regs */
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pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
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return 0;
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}
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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if (boot_dev_spl == MMC3_BOOT)
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return BOOT_DEVICE_MMC2; /* eMMC */
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else
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return BOOT_DEVICE_MMC1; /* SD */
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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int boot_device = spl_boot_device();
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spl_boot_list[0] = boot_device; /* 1:SD 2:eMMC */
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if (boot_device == BOOT_DEVICE_MMC1)
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spl_boot_list[1] = BOOT_DEVICE_MMC2; /* eMMC */
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else
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spl_boot_list[1] = BOOT_DEVICE_MMC1; /* SD */
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spl_boot_list[2] = BOOT_DEVICE_UART; /* YModem */
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spl_boot_list[3] = BOOT_DEVICE_NONE;
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}
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static struct dram_timing_info *dram_timing_info[8] = {
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&dmo_imx8mm_sbc_dram_timing_32_32, /* 32 Gbit x32 */
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NULL, /* 32 Gbit x16 */
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&dmo_imx8mm_sbc_dram_timing_16_32, /* 16 Gbit x32 */
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NULL, /* 16 Gbit x16 */
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NULL, /* 8 Gbit x32 */
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NULL, /* 8 Gbit x16 */
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NULL, /* INVALID */
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NULL, /* INVALID */
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};
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void board_init_f(ulong dummy)
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{
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dmo_board_init_f(IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B, dram_timing_info);
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}
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