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35b65dd8ef
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
56 lines
972 B
C
56 lines
972 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Renesas Electronics
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* Copyright (C) Chris Brandt
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#define RZA1_WDT_BASE 0xfcfe0000
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#define WTCSR 0x00
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#define WTCNT 0x02
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#define WRCSR 0x04
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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void reset_cpu(void)
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{
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/* Dummy read (must read WRCSR:WOVF at least once before clearing) */
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readb(RZA1_WDT_BASE + WRCSR);
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writew(0xa500, RZA1_WDT_BASE + WRCSR);
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writew(0x5a5f, RZA1_WDT_BASE + WRCSR);
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writew(0x5a00, RZA1_WDT_BASE + WTCNT);
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writew(0xa578, RZA1_WDT_BASE + WTCSR);
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for (;;)
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asm volatile("wfi");
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}
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