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25a9f9747a
Add a driver for the Xilinx LogiCORE DisplayPort IP core, which is a pure DP transmitter core for Xiling FPGA (no display capabilities). Signed-off-by: Mario Six <mario.six@gdsys.cc>
55 lines
1.8 KiB
C
55 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* logicore_dp_tx.h
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*
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* Driver for XILINX LogiCore DisplayPort v6.1 TX (Source)
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*
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* (C) Copyright 2016
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*/
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#ifndef __GDSYS_LOGICORE_DP_TX_H__
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#define __GDSYS_LOGICORE_DP_TX_H__
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/*
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* struct logicore_dp_tx_msa - Main Stream Attributes (MSA)
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* @pixel_clock_hz: The pixel clock of the stream (in Hz)
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* @bits_per_color: Number of bits per color component
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* @h_active: Horizontal active resolution (pixels)
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* @h_start: Horizontal blank start (in pixels)
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* @h_sync_polarity: Horizontal sync polarity
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* (0 = negative | 1 = positive)
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* @h_sync_width: Horizontal sync width (pixels)
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* @h_total: Horizontal total (pixels)
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* @v_active: Vertical active resolution (lines)
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* @v_start: Vertical blank start (in lines).
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* @v_sync_polarity: Vertical sync polarity
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* (0 = negative | 1 = positive)
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* @v_sync_width: Vertical sync width (lines)
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* @v_total: Vertical total (lines)
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* @override_user_pixel_width: If true, the value stored for user_pixel_width
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* will be used as the pixel width.
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* @user_pixel_width: The width of the user data input port.
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*
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* This is a stripped down version of struct main_stream_attributes that
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* contains only the parameters that are not set by cfg_msa_recalculate()
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*/
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struct logicore_dp_tx_msa {
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u32 pixel_clock_hz;
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u32 bits_per_color;
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u16 h_active;
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u32 h_start;
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bool h_sync_polarity;
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u16 h_sync_width;
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u16 h_total;
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u16 v_active;
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u32 v_start;
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bool v_sync_polarity;
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u16 v_sync_width;
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u16 v_total;
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bool override_user_pixel_width;
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u32 user_pixel_width;
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};
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#endif /* __GDSYS_LOGICORE_DP_TX_H__ */
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