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5818198e6a
Commit 5bb2c550b11e ("arm: mvebu: Move internal registers in
arch_very_early_init() function") moved code from file cpu.c to lowlevel.c,
which moves Marvell internal registers from address INTREG_BASE_ADDR_REG to
SOC_REGS_PHY_BASE.
But the steps describing how to do it correctly were documented only in
older U-Boot versions and commit cefd764222ee ("arm: mvebu: Fix internal
register config on A38x") probably unintentionally removed important
details about MMU from code comments around.
Commit 5bb2c550b11e ("arm: mvebu: Move internal registers in
arch_very_early_init() function") implemented code movement according to
(now incomplete) comments which resulted in semi-broken code.
The result is that I-cache is currently disabled for all Armada 38x boards
and maybe there are some other (unreported / undetected) issues.
Reimplement it correctly. First flush all caches, then disable MMU and L2
cache and then move Marvell internal registers. There is no need to
explicitly disable I-cache.
After this change lzmadec command with lzma image of 0x7000000 bytes is
doing decompression just 5 seconds. Before this change it was 30 seconds.
To make lowlevel.S code more readable, extend asm/pl310.h header file to be
compatible with assembler and use macros from this file.
Fixes: 5bb2c550b11e ("arm: mvebu: Move internal registers in arch_very_early_init() function")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
95 lines
2.2 KiB
C
95 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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* Aneesh V <aneesh@ti.com>
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*/
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#ifndef _PL310_H_
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#define _PL310_H_
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/* Register bit fields */
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#define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16)
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#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1)
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#define L2X0_STNDBY_MODE_EN (1 << 0)
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#define L2X0_CTRL_EN 1
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#define L2X0_CTRL_OFF 0x100
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#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22)
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#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28)
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#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29)
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#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
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#define L310_LATENCY_CTRL_RD(n) ((n) << 4)
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#define L310_LATENCY_CTRL_WR(n) ((n) << 8)
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#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
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#define L2X0_CACHE_ID_PART_L310 (3 << 6)
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#define L2X0_CACHE_ID_RTL_MASK 0x3f
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#define L2X0_CACHE_ID_RTL_R3P2 0x8
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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struct pl310_regs {
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u32 pl310_cache_id;
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u32 pl310_cache_type;
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u32 pad1[62];
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u32 pl310_ctrl;
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u32 pl310_aux_ctrl;
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u32 pl310_tag_latency_ctrl;
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u32 pl310_data_latency_ctrl;
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u32 pad2[60];
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u32 pl310_event_cnt_ctrl;
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u32 pl310_event_cnt1_cfg;
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u32 pl310_event_cnt0_cfg;
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u32 pl310_event_cnt1_val;
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u32 pl310_event_cnt0_val;
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u32 pl310_intr_mask;
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u32 pl310_masked_intr_stat;
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u32 pl310_raw_intr_stat;
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u32 pl310_intr_clear;
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u32 pad3[323];
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u32 pl310_cache_sync;
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u32 pad4[15];
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u32 pl310_inv_line_pa;
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u32 pad5[2];
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u32 pl310_inv_way;
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u32 pad6[12];
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u32 pl310_clean_line_pa;
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u32 pad7[1];
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u32 pl310_clean_line_idx;
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u32 pl310_clean_way;
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u32 pad8[12];
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u32 pl310_clean_inv_line_pa;
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u32 pad9[1];
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u32 pl310_clean_inv_line_idx;
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u32 pl310_clean_inv_way;
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u32 pad10[64];
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u32 pl310_lockdown_dbase;
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u32 pl310_lockdown_ibase;
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u32 pad11[190];
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u32 pl310_addr_filter_start;
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u32 pl310_addr_filter_end;
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u32 pad12[190];
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u32 pl310_test_operation;
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u32 pad13[3];
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u32 pl310_line_data;
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u32 pad14[7];
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u32 pl310_line_tag;
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u32 pad15[3];
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u32 pl310_debug_ctrl;
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u32 pad16[7];
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u32 pl310_prefetch_ctrl;
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u32 pad17[7];
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u32 pl310_power_ctrl;
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};
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void pl310_inval_all(void);
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void pl310_clean_inval_all(void);
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void pl310_inval_range(u32 start, u32 end);
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void pl310_clean_inval_range(u32 start, u32 end);
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#endif
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#endif
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