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Add STM32MP257F-EV1 board -----BEGIN PGP SIGNATURE----- iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmVR87YcHHBhdHJpY2Uu Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/ph+cD/0YFWkURt5TASxw49MB EE8PHjuWFPRVhR/lBX0vUxJRfltbmbJOKeGSZZeRW7LGApDVKVxKdrk2gGeLekJk L4i5KHBCDts35v3xfFhfxBYMYgXN7KiCo5Cv49b6ibxNeAUt/zKM1+CmLQWW+O8J 60LhATQduTHE9/QYiZYJusO4ma+HOSlCgbE+4jwj19Y3DaridBZ0/P+yVarjB6Mo j/cpGkQ9YQekx0gD6OJjd13kU8LJ5/qaKpMhLhU5HwnxvSuosy1JX8r9gNA2x5yt EqscRJBnQE2pKCIekzETX347Es/vhcYM6YFIGyY40bDT83on2cgxFm4xKAZ4RdNb uT4G24AueIiyT3Rpd4vGv9cWuSksSiSxcAa4ouMGAxnNyDwJaJ7HYGqnQ4yA8doR VbtwK1bT6LutgMn7ymFAiDEYaeplhF4ybxvXZJT9/qjeMXfwhBGF9UYqQNDUCDah 8ljbA0jIIV1SIVgYL4jPCwby9D53GGVtQ06SVXiJRhHgVJnkQaojByYU7xS8xrqS 1j1Ccy9rmpixS4pt589Q1dKoPGiUVgh9Z58PpR9yrCWzIokIL0WTMttG0PkSUJYJ VpNuQbsKK3LZ01xbhVpZWauOoKTfK2Fe6XsF04WCP+cK8rM+uV6DeE+bqhnadj/M CHJscGOKvhIR3jkF10F5mMJ1RA== =E2zX -----END PGP SIGNATURE----- Merge tag 'u-boot-stm32-20231113' of https://source.denx.de/u-boot/custodians/u-boot-stm into next Introduce STM32MP2 SoCs family support Add STM32MP257F-EV1 board [trini: Adjust some includes] Signed-off-by: Tom Rini <trini@konsulko.com>
69 lines
1.8 KiB
C
69 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
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*/
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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#include <mach/stm32.h>
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#define MP2_MEM_MAP_MAX 10
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#if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \
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(CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE))
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#error "invalid CONFIG_TEXT_BASE value"
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#endif
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struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = {
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{
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/* PCIe */
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.virt = 0x10000000UL,
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.phys = 0x10000000UL,
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.size = 0x10000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */
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.virt = 0x20000000UL,
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.phys = 0x20000000UL,
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.size = 0x00200000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* Peripherals: alias1 */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x10000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* OSPI and FMC: memory-map area */
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.virt = 0x60000000UL,
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.phys = 0x60000000UL,
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.size = 0x20000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/*
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* DDR = STM32_DDR_BASE / STM32_DDR_SIZE
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* the beginning of DDR (before CONFIG_TEXT_BASE) is not
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* mapped, protected by RIF and reserved for other firmware
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* (OP-TEE / TF-M / Cube M33)
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*/
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.virt = CONFIG_TEXT_BASE,
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.phys = CONFIG_TEXT_BASE,
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.size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE),
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = stm32mp2_mem_map;
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