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b195134984
All flush_cache() calls in microblaze code are supposed to flush the entire instruction and data caches, so introduce flush_cache_all() helper to handle this. Also, provide implementations for flush_dcache_all() and invalidate_icache_all() so that icache and dcache u-boot commands can work. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-9-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
27 lines
677 B
C
27 lines
677 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*/
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#ifndef __MICROBLAZE_CACHE_H__
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#define __MICROBLAZE_CACHE_H__
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/*
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* The microblaze can have either a 4 or 16 byte cacheline depending on whether
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* you are using OPB(4) or CacheLink(16). If the board config has not specified
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* a cacheline size we assume the larger value of 16 bytes for DMA buffer
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* alignment.
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*/
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#else
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#define ARCH_DMA_MINALIGN 16
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#endif
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/**
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* flush_cache_all - flush the entire instruction/data caches
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*/
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void flush_cache_all(void);
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#endif /* __MICROBLAZE_CACHE_H__ */
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