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a47a12becf
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
92 lines
2.9 KiB
C
92 lines
2.9 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor, Inc.
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* Liberty Eran (liberty@freescale.com)
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*/
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#ifndef __E300_H__
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#define __E300_H__
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#define PVR_E300C1 0x80830000
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#define PVR_E300C2 0x80840000
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#define PVR_E300C3 0x80850000
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#define PVR_E300C4 0x80860000
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/*
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* Hardware Implementation-Dependent Register 0 (HID0)
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*/
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/* #define HID0 1008 already defined in processor.h */
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#define HID0_MASK_MACHINE_CHECK 0x00000000
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#define HID0_ENABLE_MACHINE_CHECK 0x80000000
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#define HID0_DISABLE_CACHE_PARITY 0x00000000
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#define HID0_ENABLE_CACHE_PARITY 0x40000000
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#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */
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#define HID0_ENABLE_ADDRESS_PARITY 0x20000000
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#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */
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#define HID0_ENABLE_DATE_PARITY 0x10000000
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#define HID0_CORE_CLK_OUT 0x00000000
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#define HID0_CORE_CLK_OUT_DIV_2 0x08000000
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#define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */
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#define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000
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#define HID0_DISABLE_DOSE_MODE 0x00000000
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#define HID0_ENABLE_DOSE_MODE 0x00800000
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#define HID0_DISABLE_NAP_MODE 0x00000000
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#define HID0_ENABLE_NAP_MODE 0x00400000
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#define HID0_DISABLE_SLEEP_MODE 0x00000000
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#define HID0_ENABLE_SLEEP_MODE 0x00200000
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#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
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#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000
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#define HID0_SOFT_RESET 0x00010000
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#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000
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#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000
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#define HID0_DISABLE_DATA_CACHE 0x00000000
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#define HID0_ENABLE_DATA_CACHE 0x00004000
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#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000
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#define HID0_LOCK_DATA_CACHE 0x00001000
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#define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800
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#define HID0_INVALIDATE_DATA_CACHE 0x00000400
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#define HID0_DISABLE_M_BIT 0x00000000
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#define HID0_ENABLE_M_BIT 0x00000080
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#define HID0_FBIOB 0x00000010
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#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000
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#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008
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#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000
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#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
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/*
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* Hardware Implementation-Dependent Register 2 (HID2)
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*/
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#define HID2 1011
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#define HID2_LET 0x08000000
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#define HID2_HBE 0x00040000
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#define HID2_IWLCK_000 0x00000000 /* no ways locked */
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#define HID2_IWLCK_001 0x00002000 /* way 0 locked */
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#define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
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#define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
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#define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
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#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
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#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
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#endif /* __E300_H__ */
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