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This interface will be used to configure properly some pins on Merrifield that are shared with SCU. scu_ipc_raw_command() writes SPTR and DPTR registers before sending a command to SCU. This code has been ported from Linux work done by Andy Shevchenko. Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
32 lines
900 B
C
32 lines
900 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2017 Intel Corporation
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*/
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#ifndef _X86_ASM_SCU_IPC_H_
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#define _X86_ASM_SCU_IPC_H_
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/* IPC defines the following message types */
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#define IPCMSG_INDIRECT_READ 0x02
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#define IPCMSG_INDIRECT_WRITE 0x05
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#define IPCMSG_WARM_RESET 0xf0
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#define IPCMSG_COLD_RESET 0xf1
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#define IPCMSG_SOFT_RESET 0xf2
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#define IPCMSG_COLD_BOOT 0xf3
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#define IPCMSG_GET_FW_REVISION 0xf4
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#define IPCMSG_WATCHDOG_TIMER 0xf8 /* Set Kernel Watchdog Threshold */
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struct ipc_ifwi_version {
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u16 minor;
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u8 major;
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u8 hardware_id;
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u32 reserved[3];
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};
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/* Issue commands to the SCU with or without data */
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int scu_ipc_simple_command(u32 cmd, u32 sub);
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int scu_ipc_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out, int outlen);
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int scu_ipc_raw_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out,
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int outlen, u32 dptr, u32 sptr);
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#endif /* _X86_ASM_SCU_IPC_H_ */
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