mirror of
https://github.com/easytarget/MQ-Pro-IO.git
synced 2026-01-22 10:53:12 +00:00
cleanup
This commit is contained in:
Ubuntu
Binary file not shown.
@@ -1,32 +0,0 @@
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# 0 "sun20i-common-regulators.dtsi"
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# 0 "<built-in>"
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# 0 "<command-line>"
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# 1 "sun20i-common-regulators.dtsi"
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||||
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||||
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||||
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||||
/ {
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reg_vcc: vcc {
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compatible = "regulator-fixed";
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regulator-name = "vcc";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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reg_vcc_3v3: vcc-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vcc-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <®_vcc>;
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};
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};
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&pio {
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vcc-pb-supply = <®_vcc_3v3>;
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vcc-pc-supply = <®_vcc_3v3>;
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vcc-pd-supply = <®_vcc_3v3>;
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vcc-pe-supply = <®_vcc_3v3>;
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vcc-pf-supply = <®_vcc_3v3>;
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vcc-pg-supply = <®_vcc_3v3>;
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};
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Load Diff
@@ -1,19 +0,0 @@
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# 0 "sunxi-d1-t113.dtsi"
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# 0 "<built-in>"
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||||
# 0 "<command-line>"
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# 1 "sunxi-d1-t113.dtsi"
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||||
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||||
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||||
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/ {
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soc {
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dsp_wdt: watchdog@1700400 {
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compatible = "allwinner,sun20i-d1-wdt";
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reg = <0x1700400 0x20>;
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interrupts = <SOC_PERIPHERAL_IRQ(122) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dcxo>, <&rtc CLK_OSC32K>;
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clock-names = "hosc", "losc";
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status = "reserved";
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};
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};
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};
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@@ -1,940 +0,0 @@
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# 0 "sunxi-d1s-t113.dtsi"
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# 0 "<built-in>"
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# 0 "<command-line>"
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# 1 "sunxi-d1s-t113.dtsi"
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# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun6i-rtc.h" 1
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# 5 "sunxi-d1s-t113.dtsi" 2
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# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun8i-de2.h" 1
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# 6 "sunxi-d1s-t113.dtsi" 2
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# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun8i-tcon-top.h" 1
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# 7 "sunxi-d1s-t113.dtsi" 2
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# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun20i-d1-ccu.h" 1
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# 8 "sunxi-d1s-t113.dtsi" 2
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# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/clock/sun20i-d1-r-ccu.h" 1
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# 9 "sunxi-d1s-t113.dtsi" 2
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# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/interrupt-controller/irq.h" 1
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# 10 "sunxi-d1s-t113.dtsi" 2
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# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun8i-de2.h" 1
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# 11 "sunxi-d1s-t113.dtsi" 2
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# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun20i-d1-ccu.h" 1
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# 12 "sunxi-d1s-t113.dtsi" 2
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# 1 "/usr/src/linux-headers-6.8.0-31-generic/include/dt-bindings/reset/sun20i-d1-r-ccu.h" 1
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# 13 "sunxi-d1s-t113.dtsi" 2
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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dcxo: dcxo-clk {
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compatible = "fixed-clock";
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clock-output-names = "dcxo";
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#clock-cells = <0>;
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};
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de: display-engine {
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compatible = "allwinner,sun20i-d1-display-engine";
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allwinner,pipelines = <&mixer0>, <&mixer1>;
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status = "disabled";
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};
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soc {
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compatible = "simple-bus";
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ranges;
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dma-noncoherent;
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#address-cells = <1>;
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#size-cells = <1>;
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pio: pinctrl@2000000 {
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compatible = "allwinner,sun20i-d1-pinctrl";
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reg = <0x2000000 0x800>;
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interrupts = <SOC_PERIPHERAL_IRQ(69) 4>,
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<SOC_PERIPHERAL_IRQ(71) 4>,
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<SOC_PERIPHERAL_IRQ(73) 4>,
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<SOC_PERIPHERAL_IRQ(75) 4>,
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<SOC_PERIPHERAL_IRQ(77) 4>,
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<SOC_PERIPHERAL_IRQ(79) 4>;
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clocks = <&ccu 24>,
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<&dcxo>,
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<&rtc 0>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#gpio-cells = <3>;
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#interrupt-cells = <3>;
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||||
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/omit-if-no-ref/
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can0_pins: can0-pins {
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pins = "PB2", "PB3";
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function = "can0";
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||||
};
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/omit-if-no-ref/
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can1_pins: can1-pins {
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pins = "PB4", "PB5";
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function = "can1";
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};
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/omit-if-no-ref/
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clk_pg11_pin: clk-pg11-pin {
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pins = "PG11";
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function = "clk";
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};
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/omit-if-no-ref/
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||||
dsi_4lane_pins: dsi-4lane-pins {
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||||
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
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"PD6", "PD7", "PD8", "PD9";
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drive-strength = <30>;
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function = "dsi";
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||||
};
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||||
/omit-if-no-ref/
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||||
lcd_rgb666_pins: lcd-rgb666-pins {
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||||
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
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"PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
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"PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
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"PD18", "PD19", "PD20", "PD21";
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||||
function = "lcd0";
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};
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||||
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||||
/omit-if-no-ref/
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
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function = "mmc0";
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};
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/omit-if-no-ref/
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mmc1_pins: mmc1-pins {
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pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
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function = "mmc1";
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};
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||||
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/omit-if-no-ref/
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mmc2_pins: mmc2-pins {
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pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
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function = "mmc2";
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};
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/omit-if-no-ref/
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rgmii_pe_pins: rgmii-pe-pins {
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pins = "PE0", "PE1", "PE2", "PE3", "PE4",
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"PE5", "PE6", "PE7", "PE8", "PE9",
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||||
"PE11", "PE12", "PE13", "PE14", "PE15";
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||||
function = "emac";
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||||
};
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/omit-if-no-ref/
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||||
rmii_pe_pins: rmii-pe-pins {
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pins = "PE0", "PE1", "PE2", "PE3", "PE4",
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"PE5", "PE6", "PE7", "PE8", "PE9";
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function = "emac";
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};
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/omit-if-no-ref/
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spi0_pins: spi0-pins {
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pins = "PC2", "PC3", "PC4", "PC5";
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function = "spi0";
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};
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/omit-if-no-ref/
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uart1_pg6_pins: uart1-pg6-pins {
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pins = "PG6", "PG7";
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function = "uart1";
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};
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/omit-if-no-ref/
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||||
uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
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||||
pins = "PG8", "PG9";
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function = "uart1";
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};
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/omit-if-no-ref/
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uart3_pb_pins: uart3-pb-pins {
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||||
pins = "PB6", "PB7";
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||||
function = "uart3";
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||||
};
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||||
};
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||||
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ccu: clock-controller@2001000 {
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compatible = "allwinner,sun20i-d1-ccu";
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reg = <0x2001000 0x1000>;
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clocks = <&dcxo>,
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<&rtc 0>,
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<&rtc 2>;
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clock-names = "hosc", "losc", "iosc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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||||
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gpadc: adc@2009000 {
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compatible = "allwinner,sun20i-d1-gpadc";
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reg = <0x2009000 0x400>;
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clocks = <&ccu 80>;
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resets = <&ccu 32>;
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interrupts = <SOC_PERIPHERAL_IRQ(57) 4>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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||||
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dmic: dmic@2031000 {
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compatible = "allwinner,sun20i-d1-dmic",
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"allwinner,sun50i-h6-dmic";
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reg = <0x2031000 0x400>;
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interrupts = <SOC_PERIPHERAL_IRQ(24) 4>;
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clocks = <&ccu 93>,
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<&ccu 92>;
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clock-names = "bus", "mod";
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resets = <&ccu 38>;
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dmas = <&dma 8>;
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dma-names = "rx";
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status = "disabled";
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#sound-dai-cells = <0>;
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};
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i2s1: i2s@2033000 {
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compatible = "allwinner,sun20i-d1-i2s",
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"allwinner,sun50i-r329-i2s";
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reg = <0x2033000 0x1000>;
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interrupts = <SOC_PERIPHERAL_IRQ(27) 4>;
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clocks = <&ccu 87>,
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<&ccu 83>;
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clock-names = "apb", "mod";
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resets = <&ccu 35>;
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dmas = <&dma 4>, <&dma 4>;
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dma-names = "rx", "tx";
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status = "disabled";
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#sound-dai-cells = <0>;
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};
|
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|
||||
i2s2: i2s@2034000 {
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||||
compatible = "allwinner,sun20i-d1-i2s",
|
||||
"allwinner,sun50i-r329-i2s";
|
||||
reg = <0x2034000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(28) 4>;
|
||||
clocks = <&ccu 88>,
|
||||
<&ccu 84>;
|
||||
clock-names = "apb", "mod";
|
||||
resets = <&ccu 36>;
|
||||
dmas = <&dma 5>, <&dma 5>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
timer: timer@2050000 {
|
||||
compatible = "allwinner,sun20i-d1-timer",
|
||||
"allwinner,sun8i-a23-timer";
|
||||
reg = <0x2050000 0xa0>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(59) 4>,
|
||||
<SOC_PERIPHERAL_IRQ(60) 4>;
|
||||
clocks = <&dcxo>;
|
||||
};
|
||||
|
||||
wdt: watchdog@20500a0 {
|
||||
compatible = "allwinner,sun20i-d1-wdt-reset",
|
||||
"allwinner,sun20i-d1-wdt";
|
||||
reg = <0x20500a0 0x20>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(63) 4>;
|
||||
clocks = <&dcxo>, <&rtc 0>;
|
||||
clock-names = "hosc", "losc";
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
uart0: serial@2500000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2500000 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(2) 4>;
|
||||
clocks = <&ccu 62>;
|
||||
resets = <&ccu 18>;
|
||||
dmas = <&dma 14>, <&dma 14>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@2500400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2500400 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(3) 4>;
|
||||
clocks = <&ccu 63>;
|
||||
resets = <&ccu 19>;
|
||||
dmas = <&dma 15>, <&dma 15>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@2500800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2500800 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(4) 4>;
|
||||
clocks = <&ccu 64>;
|
||||
resets = <&ccu 20>;
|
||||
dmas = <&dma 16>, <&dma 16>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@2500c00 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2500c00 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(5) 4>;
|
||||
clocks = <&ccu 65>;
|
||||
resets = <&ccu 21>;
|
||||
dmas = <&dma 17>, <&dma 17>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@2501000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2501000 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(6) 4>;
|
||||
clocks = <&ccu 66>;
|
||||
resets = <&ccu 22>;
|
||||
dmas = <&dma 18>, <&dma 18>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@2501400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2501400 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(7) 4>;
|
||||
clocks = <&ccu 67>;
|
||||
resets = <&ccu 23>;
|
||||
dmas = <&dma 19>, <&dma 19>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@2502000 {
|
||||
compatible = "allwinner,sun20i-d1-i2c",
|
||||
"allwinner,sun8i-v536-i2c",
|
||||
"allwinner,sun6i-a31-i2c";
|
||||
reg = <0x2502000 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(9) 4>;
|
||||
clocks = <&ccu 68>;
|
||||
resets = <&ccu 24>;
|
||||
dmas = <&dma 43>, <&dma 43>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@2502400 {
|
||||
compatible = "allwinner,sun20i-d1-i2c",
|
||||
"allwinner,sun8i-v536-i2c",
|
||||
"allwinner,sun6i-a31-i2c";
|
||||
reg = <0x2502400 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(10) 4>;
|
||||
clocks = <&ccu 69>;
|
||||
resets = <&ccu 25>;
|
||||
dmas = <&dma 44>, <&dma 44>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c2: i2c@2502800 {
|
||||
compatible = "allwinner,sun20i-d1-i2c",
|
||||
"allwinner,sun8i-v536-i2c",
|
||||
"allwinner,sun6i-a31-i2c";
|
||||
reg = <0x2502800 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(11) 4>;
|
||||
clocks = <&ccu 70>;
|
||||
resets = <&ccu 26>;
|
||||
dmas = <&dma 45>, <&dma 45>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c3: i2c@2502c00 {
|
||||
compatible = "allwinner,sun20i-d1-i2c",
|
||||
"allwinner,sun8i-v536-i2c",
|
||||
"allwinner,sun6i-a31-i2c";
|
||||
reg = <0x2502c00 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(12) 4>;
|
||||
clocks = <&ccu 71>;
|
||||
resets = <&ccu 27>;
|
||||
dmas = <&dma 46>, <&dma 46>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
can0: can@2504000 {
|
||||
compatible = "allwinner,sun20i-d1-can";
|
||||
reg = <0x02504000 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(21) 4>;
|
||||
clocks = <&ccu 145>;
|
||||
resets = <&ccu 66>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can0_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@2504400 {
|
||||
compatible = "allwinner,sun20i-d1-can";
|
||||
reg = <0x02504400 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(22) 4>;
|
||||
clocks = <&ccu 146>;
|
||||
resets = <&ccu 67>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can1_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
syscon: syscon@3000000 {
|
||||
compatible = "allwinner,sun20i-d1-system-control";
|
||||
reg = <0x3000000 0x1000>;
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
dma: dma-controller@3002000 {
|
||||
compatible = "allwinner,sun20i-d1-dma";
|
||||
reg = <0x3002000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(50) 4>;
|
||||
clocks = <&ccu 37>, <&ccu 48>;
|
||||
clock-names = "bus", "mbus";
|
||||
resets = <&ccu 6>;
|
||||
dma-channels = <16>;
|
||||
dma-requests = <48>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
sid: efuse@3006000 {
|
||||
compatible = "allwinner,sun20i-d1-sid";
|
||||
reg = <0x3006000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
crypto: crypto@3040000 {
|
||||
compatible = "allwinner,sun20i-d1-crypto";
|
||||
reg = <0x3040000 0x800>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(52) 4>;
|
||||
clocks = <&ccu 34>,
|
||||
<&ccu 33>,
|
||||
<&ccu 50>,
|
||||
<&rtc 2>;
|
||||
clock-names = "bus", "mod", "ram", "trng";
|
||||
resets = <&ccu 4>;
|
||||
};
|
||||
|
||||
mbus: dram-controller@3102000 {
|
||||
compatible = "allwinner,sun20i-d1-mbus";
|
||||
reg = <0x3102000 0x1000>,
|
||||
<0x3103000 0x1000>;
|
||||
reg-names = "mbus", "dram";
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(43) 4>;
|
||||
clocks = <&ccu 26>,
|
||||
<&ccu 47>,
|
||||
<&ccu 55>;
|
||||
clock-names = "mbus", "dram", "bus";
|
||||
dma-ranges = <0 0x40000000 0x80000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
mmc0: mmc@4020000 {
|
||||
compatible = "allwinner,sun20i-d1-mmc";
|
||||
reg = <0x4020000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(40) 4>;
|
||||
clocks = <&ccu 59>, <&ccu 56>;
|
||||
clock-names = "ahb", "mmc";
|
||||
resets = <&ccu 15>;
|
||||
reset-names = "ahb";
|
||||
cap-sd-highspeed;
|
||||
max-frequency = <150000000>;
|
||||
no-mmc;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mmc1: mmc@4021000 {
|
||||
compatible = "allwinner,sun20i-d1-mmc";
|
||||
reg = <0x4021000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(41) 4>;
|
||||
clocks = <&ccu 60>, <&ccu 57>;
|
||||
clock-names = "ahb", "mmc";
|
||||
resets = <&ccu 16>;
|
||||
reset-names = "ahb";
|
||||
cap-sd-highspeed;
|
||||
max-frequency = <150000000>;
|
||||
no-mmc;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mmc2: mmc@4022000 {
|
||||
compatible = "allwinner,sun20i-d1-emmc",
|
||||
"allwinner,sun50i-a100-emmc";
|
||||
reg = <0x4022000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(42) 4>;
|
||||
clocks = <&ccu 61>, <&ccu 58>;
|
||||
clock-names = "ahb", "mmc";
|
||||
resets = <&ccu 17>;
|
||||
reset-names = "ahb";
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <150000000>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-ddr-3_3v;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi0: spi@4025000 {
|
||||
compatible = "allwinner,sun20i-d1-spi",
|
||||
"allwinner,sun50i-r329-spi";
|
||||
reg = <0x04025000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(15) 4>;
|
||||
clocks = <&ccu 74>, <&ccu 72>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma 22>, <&dma 22>;
|
||||
dma-names = "rx", "tx";
|
||||
resets = <&ccu 28>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1: spi@4026000 {
|
||||
compatible = "allwinner,sun20i-d1-spi-dbi",
|
||||
"allwinner,sun50i-r329-spi-dbi",
|
||||
"allwinner,sun50i-r329-spi";
|
||||
reg = <0x04026000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(16) 4>;
|
||||
clocks = <&ccu 75>, <&ccu 73>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma 23>, <&dma 23>;
|
||||
dma-names = "rx", "tx";
|
||||
resets = <&ccu 29>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
usb_otg: usb@4100000 {
|
||||
compatible = "allwinner,sun20i-d1-musb",
|
||||
"allwinner,sun8i-a33-musb";
|
||||
reg = <0x4100000 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(29) 4>;
|
||||
interrupt-names = "mc";
|
||||
clocks = <&ccu 103>;
|
||||
resets = <&ccu 46>;
|
||||
extcon = <&usbphy 0>;
|
||||
phys = <&usbphy 0>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy: phy@4100400 {
|
||||
compatible = "allwinner,sun20i-d1-usb-phy";
|
||||
reg = <0x4100400 0x100>,
|
||||
<0x4101800 0x100>,
|
||||
<0x4200800 0x100>;
|
||||
reg-names = "phy_ctrl",
|
||||
"pmu0",
|
||||
"pmu1";
|
||||
clocks = <&dcxo>,
|
||||
<&dcxo>;
|
||||
clock-names = "usb0_phy",
|
||||
"usb1_phy";
|
||||
resets = <&ccu 40>,
|
||||
<&ccu 41>;
|
||||
reset-names = "usb0_reset",
|
||||
"usb1_reset";
|
||||
status = "disabled";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
ehci0: usb@4101000 {
|
||||
compatible = "allwinner,sun20i-d1-ehci",
|
||||
"generic-ehci";
|
||||
reg = <0x4101000 0x100>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(30) 4>;
|
||||
clocks = <&ccu 99>,
|
||||
<&ccu 101>,
|
||||
<&ccu 97>;
|
||||
resets = <&ccu 42>,
|
||||
<&ccu 44>;
|
||||
phys = <&usbphy 0>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@4101400 {
|
||||
compatible = "allwinner,sun20i-d1-ohci",
|
||||
"generic-ohci";
|
||||
reg = <0x4101400 0x100>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(31) 4>;
|
||||
clocks = <&ccu 99>,
|
||||
<&ccu 97>;
|
||||
resets = <&ccu 42>;
|
||||
phys = <&usbphy 0>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@4200000 {
|
||||
compatible = "allwinner,sun20i-d1-ehci",
|
||||
"generic-ehci";
|
||||
reg = <0x4200000 0x100>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(33) 4>;
|
||||
clocks = <&ccu 100>,
|
||||
<&ccu 102>,
|
||||
<&ccu 98>;
|
||||
resets = <&ccu 43>,
|
||||
<&ccu 45>;
|
||||
phys = <&usbphy 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci1: usb@4200400 {
|
||||
compatible = "allwinner,sun20i-d1-ohci",
|
||||
"generic-ohci";
|
||||
reg = <0x4200400 0x100>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(34) 4>;
|
||||
clocks = <&ccu 100>,
|
||||
<&ccu 98>;
|
||||
resets = <&ccu 43>;
|
||||
phys = <&usbphy 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
emac: ethernet@4500000 {
|
||||
compatible = "allwinner,sun20i-d1-emac",
|
||||
"allwinner,sun50i-a64-emac";
|
||||
reg = <0x4500000 0x10000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(46) 4>;
|
||||
interrupt-names = "macirq";
|
||||
clocks = <&ccu 77>;
|
||||
clock-names = "stmmaceth";
|
||||
resets = <&ccu 30>;
|
||||
reset-names = "stmmaceth";
|
||||
syscon = <&syscon>;
|
||||
status = "disabled";
|
||||
|
||||
mdio: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
display_clocks: clock-controller@5000000 {
|
||||
compatible = "allwinner,sun20i-d1-de2-clk",
|
||||
"allwinner,sun50i-h5-de2-clk";
|
||||
reg = <0x5000000 0x10000>;
|
||||
clocks = <&ccu 28>, <&ccu 27>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu 1>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
mixer0: mixer@5100000 {
|
||||
compatible = "allwinner,sun20i-d1-de2-mixer-0";
|
||||
reg = <0x5100000 0x100000>;
|
||||
clocks = <&display_clocks 0>,
|
||||
<&display_clocks 6>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&display_clocks 0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mixer0_out: port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mixer0_out_tcon_top_mixer0: endpoint {
|
||||
remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mixer1: mixer@5200000 {
|
||||
compatible = "allwinner,sun20i-d1-de2-mixer-1";
|
||||
reg = <0x5200000 0x100000>;
|
||||
clocks = <&display_clocks 1>,
|
||||
<&display_clocks 7>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&display_clocks 1>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mixer1_out: port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mixer1_out_tcon_top_mixer1: endpoint {
|
||||
remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi: dsi@5450000 {
|
||||
compatible = "allwinner,sun20i-d1-mipi-dsi",
|
||||
"allwinner,sun50i-a100-mipi-dsi";
|
||||
reg = <0x5450000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(92) 4>;
|
||||
clocks = <&ccu 111>,
|
||||
<&tcon_top 2>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu 51>;
|
||||
phys = <&dphy>;
|
||||
phy-names = "dphy";
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
dsi_in_tcon_lcd0: endpoint {
|
||||
remote-endpoint = <&tcon_lcd0_out_dsi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dphy: phy@5451000 {
|
||||
compatible = "allwinner,sun20i-d1-mipi-dphy",
|
||||
"allwinner,sun50i-a100-mipi-dphy";
|
||||
reg = <0x5451000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(92) 4>;
|
||||
clocks = <&ccu 111>,
|
||||
<&ccu 110>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu 51>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
tcon_top: tcon-top@5460000 {
|
||||
compatible = "allwinner,sun20i-d1-tcon-top";
|
||||
reg = <0x5460000 0x1000>;
|
||||
clocks = <&ccu 105>,
|
||||
<&ccu 114>,
|
||||
<&ccu 116>,
|
||||
<&ccu 112>;
|
||||
clock-names = "bus", "tcon-tv0", "tve0", "dsi";
|
||||
clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
|
||||
resets = <&ccu 48>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_top_mixer0_in: port@0 {
|
||||
reg = <0>;
|
||||
|
||||
tcon_top_mixer0_in_mixer0: endpoint {
|
||||
remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_mixer0_out: port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
|
||||
};
|
||||
|
||||
tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_mixer1_in: port@2 {
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_top_mixer1_in_mixer1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_mixer1_out: port@3 {
|
||||
reg = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
|
||||
};
|
||||
|
||||
tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_hdmi_in: port@4 {
|
||||
reg = <4>;
|
||||
|
||||
tcon_top_hdmi_in_tcon_tv0: endpoint {
|
||||
remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_hdmi_out: port@5 {
|
||||
reg = <5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tcon_lcd0: lcd-controller@5461000 {
|
||||
compatible = "allwinner,sun20i-d1-tcon-lcd";
|
||||
reg = <0x5461000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(90) 4>;
|
||||
clocks = <&ccu 113>,
|
||||
<&ccu 112>;
|
||||
clock-names = "ahb", "tcon-ch0";
|
||||
clock-output-names = "tcon-pixel-clock";
|
||||
resets = <&ccu 52>,
|
||||
<&ccu 54>;
|
||||
reset-names = "lcd", "lvds";
|
||||
#clock-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_lcd0_in: port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
|
||||
};
|
||||
|
||||
tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_lcd0_out: port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_lcd0_out_dsi: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&dsi_in_tcon_lcd0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tcon_tv0: lcd-controller@5470000 {
|
||||
compatible = "allwinner,sun20i-d1-tcon-tv";
|
||||
reg = <0x5470000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(91) 4>;
|
||||
clocks = <&ccu 115>,
|
||||
<&tcon_top 0>;
|
||||
clock-names = "ahb", "tcon-ch1";
|
||||
resets = <&ccu 53>;
|
||||
reset-names = "lcd";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_tv0_in: port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
|
||||
};
|
||||
|
||||
tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_tv0_out: port@1 {
|
||||
reg = <1>;
|
||||
|
||||
tcon_tv0_out_tcon_top_hdmi: endpoint {
|
||||
remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ppu: power-controller@7001000 {
|
||||
compatible = "allwinner,sun20i-d1-ppu";
|
||||
reg = <0x7001000 0x1000>;
|
||||
clocks = <&r_ccu 4>;
|
||||
resets = <&r_ccu 2>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
r_ccu: clock-controller@7010000 {
|
||||
compatible = "allwinner,sun20i-d1-r-ccu";
|
||||
reg = <0x7010000 0x400>;
|
||||
clocks = <&dcxo>,
|
||||
<&rtc 0>,
|
||||
<&rtc 2>,
|
||||
<&ccu 6>;
|
||||
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
rtc: rtc@7090000 {
|
||||
compatible = "allwinner,sun20i-d1-rtc",
|
||||
"allwinner,sun50i-r329-rtc";
|
||||
reg = <0x7090000 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(144) 4>;
|
||||
clocks = <&r_ccu 7>,
|
||||
<&dcxo>,
|
||||
<&r_ccu 0>;
|
||||
clock-names = "bus", "hosc", "ahb";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,117 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
|
||||
|
||||
#define SOC_PERIPHERAL_IRQ(nr) (nr + 16)
|
||||
|
||||
#include "sunxi-d1s-t113.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
timebase-frequency = <24000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "thead,c906", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
clocks = <&ccu CLK_RISCV>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <128>;
|
||||
i-cache-size = <32768>;
|
||||
mmu-type = "riscv,sv39";
|
||||
operating-points-v2 = <&opp_table_cpu>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm";
|
||||
#cooling-cells = <2>;
|
||||
|
||||
cpu0_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
opp_table_cpu: opp-table-cpu {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-408000000 {
|
||||
opp-hz = /bits/ 64 <408000000>;
|
||||
opp-microvolt = <900000 900000 1100000>;
|
||||
};
|
||||
|
||||
opp-1080000000 {
|
||||
opp-hz = /bits/ 64 <1008000000>;
|
||||
opp-microvolt = <900000 900000 1100000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
interrupt-parent = <&plic>;
|
||||
|
||||
riscv_wdt: watchdog@6011000 {
|
||||
compatible = "allwinner,sun20i-d1-wdt";
|
||||
reg = <0x6011000 0x20>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dcxo>, <&rtc CLK_OSC32K>;
|
||||
clock-names = "hosc", "losc";
|
||||
};
|
||||
|
||||
plic: interrupt-controller@10000000 {
|
||||
compatible = "allwinner,sun20i-d1-plic",
|
||||
"thead,c900-plic";
|
||||
reg = <0x10000000 0x4000000>;
|
||||
interrupts-extended = <&cpu0_intc 11>,
|
||||
<&cpu0_intc 9>;
|
||||
interrupt-controller;
|
||||
riscv,ndev = <175>;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "riscv,pmu";
|
||||
riscv,event-to-mhpmcounters =
|
||||
<0x00003 0x00003 0x00000008>,
|
||||
<0x00004 0x00004 0x00000010>,
|
||||
<0x00005 0x00005 0x00000200>,
|
||||
<0x00006 0x00006 0x00000100>,
|
||||
<0x10000 0x10000 0x00004000>,
|
||||
<0x10001 0x10001 0x00008000>,
|
||||
<0x10002 0x10002 0x00010000>,
|
||||
<0x10003 0x10003 0x00020000>,
|
||||
<0x10019 0x10019 0x00000040>,
|
||||
<0x10021 0x10021 0x00000020>;
|
||||
riscv,event-to-mhpmevent =
|
||||
<0x00003 0x00000000 0x00000001>,
|
||||
<0x00004 0x00000000 0x00000002>,
|
||||
<0x00005 0x00000000 0x00000007>,
|
||||
<0x00006 0x00000000 0x00000006>,
|
||||
<0x10000 0x00000000 0x0000000c>,
|
||||
<0x10001 0x00000000 0x0000000d>,
|
||||
<0x10002 0x00000000 0x0000000e>,
|
||||
<0x10003 0x00000000 0x0000000f>,
|
||||
<0x10019 0x00000000 0x00000004>,
|
||||
<0x10021 0x00000000 0x00000003>;
|
||||
riscv,raw-event-to-mhpmcounters =
|
||||
<0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
|
||||
<0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
|
||||
<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
|
||||
<0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
|
||||
<0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
|
||||
<0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
|
||||
<0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
|
||||
<0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
|
||||
<0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
|
||||
<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
|
||||
<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
|
||||
<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
|
||||
};
|
||||
};
|
||||
@@ -1,15 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
dsp_wdt: watchdog@1700400 {
|
||||
compatible = "allwinner,sun20i-d1-wdt";
|
||||
reg = <0x1700400 0x20>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(122) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dcxo>, <&rtc CLK_OSC32K>;
|
||||
clock-names = "hosc", "losc";
|
||||
status = "reserved";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,927 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
|
||||
|
||||
#include <dt-bindings/clock/sun6i-rtc.h>
|
||||
#include <dt-bindings/clock/sun8i-de2.h>
|
||||
#include <dt-bindings/clock/sun8i-tcon-top.h>
|
||||
#include <dt-bindings/clock/sun20i-d1-ccu.h>
|
||||
#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/reset/sun8i-de2.h>
|
||||
#include <dt-bindings/reset/sun20i-d1-ccu.h>
|
||||
#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
dcxo: dcxo-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "dcxo";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
de: display-engine {
|
||||
compatible = "allwinner,sun20i-d1-display-engine";
|
||||
allwinner,pipelines = <&mixer0>, <&mixer1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
dma-noncoherent;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
pio: pinctrl@2000000 {
|
||||
compatible = "allwinner,sun20i-d1-pinctrl";
|
||||
reg = <0x2000000 0x800>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>,
|
||||
<SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>,
|
||||
<SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>,
|
||||
<SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>,
|
||||
<SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>,
|
||||
<SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_APB0>,
|
||||
<&dcxo>,
|
||||
<&rtc CLK_OSC32K>;
|
||||
clock-names = "apb", "hosc", "losc";
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <3>;
|
||||
#interrupt-cells = <3>;
|
||||
|
||||
/omit-if-no-ref/
|
||||
can0_pins: can0-pins {
|
||||
pins = "PB2", "PB3";
|
||||
function = "can0";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
can1_pins: can1-pins {
|
||||
pins = "PB4", "PB5";
|
||||
function = "can1";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
clk_pg11_pin: clk-pg11-pin {
|
||||
pins = "PG11";
|
||||
function = "clk";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
dsi_4lane_pins: dsi-4lane-pins {
|
||||
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
|
||||
"PD6", "PD7", "PD8", "PD9";
|
||||
drive-strength = <30>;
|
||||
function = "dsi";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
lcd_rgb666_pins: lcd-rgb666-pins {
|
||||
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
|
||||
"PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
|
||||
"PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
|
||||
"PD18", "PD19", "PD20", "PD21";
|
||||
function = "lcd0";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
mmc0_pins: mmc0-pins {
|
||||
pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
|
||||
function = "mmc0";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
mmc1_pins: mmc1-pins {
|
||||
pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
|
||||
function = "mmc1";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
mmc2_pins: mmc2-pins {
|
||||
pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
|
||||
function = "mmc2";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
rgmii_pe_pins: rgmii-pe-pins {
|
||||
pins = "PE0", "PE1", "PE2", "PE3", "PE4",
|
||||
"PE5", "PE6", "PE7", "PE8", "PE9",
|
||||
"PE11", "PE12", "PE13", "PE14", "PE15";
|
||||
function = "emac";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
rmii_pe_pins: rmii-pe-pins {
|
||||
pins = "PE0", "PE1", "PE2", "PE3", "PE4",
|
||||
"PE5", "PE6", "PE7", "PE8", "PE9";
|
||||
function = "emac";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
spi0_pins: spi0-pins {
|
||||
pins = "PC2", "PC3", "PC4", "PC5";
|
||||
function = "spi0";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
uart1_pg6_pins: uart1-pg6-pins {
|
||||
pins = "PG6", "PG7";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
|
||||
pins = "PG8", "PG9";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
uart3_pb_pins: uart3-pb-pins {
|
||||
pins = "PB6", "PB7";
|
||||
function = "uart3";
|
||||
};
|
||||
};
|
||||
|
||||
ccu: clock-controller@2001000 {
|
||||
compatible = "allwinner,sun20i-d1-ccu";
|
||||
reg = <0x2001000 0x1000>;
|
||||
clocks = <&dcxo>,
|
||||
<&rtc CLK_OSC32K>,
|
||||
<&rtc CLK_IOSC>;
|
||||
clock-names = "hosc", "losc", "iosc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
gpadc: adc@2009000 {
|
||||
compatible = "allwinner,sun20i-d1-gpadc";
|
||||
reg = <0x2009000 0x400>;
|
||||
clocks = <&ccu CLK_BUS_GPADC>;
|
||||
resets = <&ccu RST_BUS_GPADC>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(57) IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
dmic: dmic@2031000 {
|
||||
compatible = "allwinner,sun20i-d1-dmic",
|
||||
"allwinner,sun50i-h6-dmic";
|
||||
reg = <0x2031000 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_DMIC>,
|
||||
<&ccu CLK_DMIC>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu RST_BUS_DMIC>;
|
||||
dmas = <&dma 8>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
i2s1: i2s@2033000 {
|
||||
compatible = "allwinner,sun20i-d1-i2s",
|
||||
"allwinner,sun50i-r329-i2s";
|
||||
reg = <0x2033000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_I2S1>,
|
||||
<&ccu CLK_I2S1>;
|
||||
clock-names = "apb", "mod";
|
||||
resets = <&ccu RST_BUS_I2S1>;
|
||||
dmas = <&dma 4>, <&dma 4>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
i2s2: i2s@2034000 {
|
||||
compatible = "allwinner,sun20i-d1-i2s",
|
||||
"allwinner,sun50i-r329-i2s";
|
||||
reg = <0x2034000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_I2S2>,
|
||||
<&ccu CLK_I2S2>;
|
||||
clock-names = "apb", "mod";
|
||||
resets = <&ccu RST_BUS_I2S2>;
|
||||
dmas = <&dma 5>, <&dma 5>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
timer: timer@2050000 {
|
||||
compatible = "allwinner,sun20i-d1-timer",
|
||||
"allwinner,sun8i-a23-timer";
|
||||
reg = <0x2050000 0xa0>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>,
|
||||
<SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dcxo>;
|
||||
};
|
||||
|
||||
wdt: watchdog@20500a0 {
|
||||
compatible = "allwinner,sun20i-d1-wdt-reset",
|
||||
"allwinner,sun20i-d1-wdt";
|
||||
reg = <0x20500a0 0x20>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dcxo>, <&rtc CLK_OSC32K>;
|
||||
clock-names = "hosc", "losc";
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
uart0: serial@2500000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2500000 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_UART0>;
|
||||
resets = <&ccu RST_BUS_UART0>;
|
||||
dmas = <&dma 14>, <&dma 14>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@2500400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2500400 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_UART1>;
|
||||
resets = <&ccu RST_BUS_UART1>;
|
||||
dmas = <&dma 15>, <&dma 15>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@2500800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2500800 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_UART2>;
|
||||
resets = <&ccu RST_BUS_UART2>;
|
||||
dmas = <&dma 16>, <&dma 16>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@2500c00 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2500c00 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_UART3>;
|
||||
resets = <&ccu RST_BUS_UART3>;
|
||||
dmas = <&dma 17>, <&dma 17>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@2501000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2501000 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_UART4>;
|
||||
resets = <&ccu RST_BUS_UART4>;
|
||||
dmas = <&dma 18>, <&dma 18>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@2501400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2501400 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_UART5>;
|
||||
resets = <&ccu RST_BUS_UART5>;
|
||||
dmas = <&dma 19>, <&dma 19>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@2502000 {
|
||||
compatible = "allwinner,sun20i-d1-i2c",
|
||||
"allwinner,sun8i-v536-i2c",
|
||||
"allwinner,sun6i-a31-i2c";
|
||||
reg = <0x2502000 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_I2C0>;
|
||||
resets = <&ccu RST_BUS_I2C0>;
|
||||
dmas = <&dma 43>, <&dma 43>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@2502400 {
|
||||
compatible = "allwinner,sun20i-d1-i2c",
|
||||
"allwinner,sun8i-v536-i2c",
|
||||
"allwinner,sun6i-a31-i2c";
|
||||
reg = <0x2502400 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_I2C1>;
|
||||
resets = <&ccu RST_BUS_I2C1>;
|
||||
dmas = <&dma 44>, <&dma 44>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c2: i2c@2502800 {
|
||||
compatible = "allwinner,sun20i-d1-i2c",
|
||||
"allwinner,sun8i-v536-i2c",
|
||||
"allwinner,sun6i-a31-i2c";
|
||||
reg = <0x2502800 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_I2C2>;
|
||||
resets = <&ccu RST_BUS_I2C2>;
|
||||
dmas = <&dma 45>, <&dma 45>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c3: i2c@2502c00 {
|
||||
compatible = "allwinner,sun20i-d1-i2c",
|
||||
"allwinner,sun8i-v536-i2c",
|
||||
"allwinner,sun6i-a31-i2c";
|
||||
reg = <0x2502c00 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_I2C3>;
|
||||
resets = <&ccu RST_BUS_I2C3>;
|
||||
dmas = <&dma 46>, <&dma 46>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
can0: can@2504000 {
|
||||
compatible = "allwinner,sun20i-d1-can";
|
||||
reg = <0x02504000 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_CAN0>;
|
||||
resets = <&ccu RST_BUS_CAN0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can0_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@2504400 {
|
||||
compatible = "allwinner,sun20i-d1-can";
|
||||
reg = <0x02504400 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_CAN1>;
|
||||
resets = <&ccu RST_BUS_CAN1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can1_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
syscon: syscon@3000000 {
|
||||
compatible = "allwinner,sun20i-d1-system-control";
|
||||
reg = <0x3000000 0x1000>;
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
dma: dma-controller@3002000 {
|
||||
compatible = "allwinner,sun20i-d1-dma";
|
||||
reg = <0x3002000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
|
||||
clock-names = "bus", "mbus";
|
||||
resets = <&ccu RST_BUS_DMA>;
|
||||
dma-channels = <16>;
|
||||
dma-requests = <48>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
sid: efuse@3006000 {
|
||||
compatible = "allwinner,sun20i-d1-sid";
|
||||
reg = <0x3006000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
crypto: crypto@3040000 {
|
||||
compatible = "allwinner,sun20i-d1-crypto";
|
||||
reg = <0x3040000 0x800>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_CE>,
|
||||
<&ccu CLK_CE>,
|
||||
<&ccu CLK_MBUS_CE>,
|
||||
<&rtc CLK_IOSC>;
|
||||
clock-names = "bus", "mod", "ram", "trng";
|
||||
resets = <&ccu RST_BUS_CE>;
|
||||
};
|
||||
|
||||
mbus: dram-controller@3102000 {
|
||||
compatible = "allwinner,sun20i-d1-mbus";
|
||||
reg = <0x3102000 0x1000>,
|
||||
<0x3103000 0x1000>;
|
||||
reg-names = "mbus", "dram";
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_MBUS>,
|
||||
<&ccu CLK_DRAM>,
|
||||
<&ccu CLK_BUS_DRAM>;
|
||||
clock-names = "mbus", "dram", "bus";
|
||||
dma-ranges = <0 0x40000000 0x80000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
mmc0: mmc@4020000 {
|
||||
compatible = "allwinner,sun20i-d1-mmc";
|
||||
reg = <0x4020000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
|
||||
clock-names = "ahb", "mmc";
|
||||
resets = <&ccu RST_BUS_MMC0>;
|
||||
reset-names = "ahb";
|
||||
cap-sd-highspeed;
|
||||
max-frequency = <150000000>;
|
||||
no-mmc;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mmc1: mmc@4021000 {
|
||||
compatible = "allwinner,sun20i-d1-mmc";
|
||||
reg = <0x4021000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
|
||||
clock-names = "ahb", "mmc";
|
||||
resets = <&ccu RST_BUS_MMC1>;
|
||||
reset-names = "ahb";
|
||||
cap-sd-highspeed;
|
||||
max-frequency = <150000000>;
|
||||
no-mmc;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mmc2: mmc@4022000 {
|
||||
compatible = "allwinner,sun20i-d1-emmc",
|
||||
"allwinner,sun50i-a100-emmc";
|
||||
reg = <0x4022000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
|
||||
clock-names = "ahb", "mmc";
|
||||
resets = <&ccu RST_BUS_MMC2>;
|
||||
reset-names = "ahb";
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <150000000>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-ddr-3_3v;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi0: spi@4025000 {
|
||||
compatible = "allwinner,sun20i-d1-spi",
|
||||
"allwinner,sun50i-r329-spi";
|
||||
reg = <0x04025000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma 22>, <&dma 22>;
|
||||
dma-names = "rx", "tx";
|
||||
resets = <&ccu RST_BUS_SPI0>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1: spi@4026000 {
|
||||
compatible = "allwinner,sun20i-d1-spi-dbi",
|
||||
"allwinner,sun50i-r329-spi-dbi",
|
||||
"allwinner,sun50i-r329-spi";
|
||||
reg = <0x04026000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(16) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma 23>, <&dma 23>;
|
||||
dma-names = "rx", "tx";
|
||||
resets = <&ccu RST_BUS_SPI1>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
usb_otg: usb@4100000 {
|
||||
compatible = "allwinner,sun20i-d1-musb",
|
||||
"allwinner,sun8i-a33-musb";
|
||||
reg = <0x4100000 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mc";
|
||||
clocks = <&ccu CLK_BUS_OTG>;
|
||||
resets = <&ccu RST_BUS_OTG>;
|
||||
extcon = <&usbphy 0>;
|
||||
phys = <&usbphy 0>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy: phy@4100400 {
|
||||
compatible = "allwinner,sun20i-d1-usb-phy";
|
||||
reg = <0x4100400 0x100>,
|
||||
<0x4101800 0x100>,
|
||||
<0x4200800 0x100>;
|
||||
reg-names = "phy_ctrl",
|
||||
"pmu0",
|
||||
"pmu1";
|
||||
clocks = <&dcxo>,
|
||||
<&dcxo>;
|
||||
clock-names = "usb0_phy",
|
||||
"usb1_phy";
|
||||
resets = <&ccu RST_USB_PHY0>,
|
||||
<&ccu RST_USB_PHY1>;
|
||||
reset-names = "usb0_reset",
|
||||
"usb1_reset";
|
||||
status = "disabled";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
ehci0: usb@4101000 {
|
||||
compatible = "allwinner,sun20i-d1-ehci",
|
||||
"generic-ehci";
|
||||
reg = <0x4101000 0x100>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_OHCI0>,
|
||||
<&ccu CLK_BUS_EHCI0>,
|
||||
<&ccu CLK_USB_OHCI0>;
|
||||
resets = <&ccu RST_BUS_OHCI0>,
|
||||
<&ccu RST_BUS_EHCI0>;
|
||||
phys = <&usbphy 0>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@4101400 {
|
||||
compatible = "allwinner,sun20i-d1-ohci",
|
||||
"generic-ohci";
|
||||
reg = <0x4101400 0x100>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_OHCI0>,
|
||||
<&ccu CLK_USB_OHCI0>;
|
||||
resets = <&ccu RST_BUS_OHCI0>;
|
||||
phys = <&usbphy 0>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@4200000 {
|
||||
compatible = "allwinner,sun20i-d1-ehci",
|
||||
"generic-ehci";
|
||||
reg = <0x4200000 0x100>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_OHCI1>,
|
||||
<&ccu CLK_BUS_EHCI1>,
|
||||
<&ccu CLK_USB_OHCI1>;
|
||||
resets = <&ccu RST_BUS_OHCI1>,
|
||||
<&ccu RST_BUS_EHCI1>;
|
||||
phys = <&usbphy 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci1: usb@4200400 {
|
||||
compatible = "allwinner,sun20i-d1-ohci",
|
||||
"generic-ohci";
|
||||
reg = <0x4200400 0x100>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_OHCI1>,
|
||||
<&ccu CLK_USB_OHCI1>;
|
||||
resets = <&ccu RST_BUS_OHCI1>;
|
||||
phys = <&usbphy 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
emac: ethernet@4500000 {
|
||||
compatible = "allwinner,sun20i-d1-emac",
|
||||
"allwinner,sun50i-a64-emac";
|
||||
reg = <0x4500000 0x10000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
clocks = <&ccu CLK_BUS_EMAC>;
|
||||
clock-names = "stmmaceth";
|
||||
resets = <&ccu RST_BUS_EMAC>;
|
||||
reset-names = "stmmaceth";
|
||||
syscon = <&syscon>;
|
||||
status = "disabled";
|
||||
|
||||
mdio: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
display_clocks: clock-controller@5000000 {
|
||||
compatible = "allwinner,sun20i-d1-de2-clk",
|
||||
"allwinner,sun50i-h5-de2-clk";
|
||||
reg = <0x5000000 0x10000>;
|
||||
clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu RST_BUS_DE>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
mixer0: mixer@5100000 {
|
||||
compatible = "allwinner,sun20i-d1-de2-mixer-0";
|
||||
reg = <0x5100000 0x100000>;
|
||||
clocks = <&display_clocks CLK_BUS_MIXER0>,
|
||||
<&display_clocks CLK_MIXER0>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&display_clocks RST_MIXER0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mixer0_out: port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mixer0_out_tcon_top_mixer0: endpoint {
|
||||
remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mixer1: mixer@5200000 {
|
||||
compatible = "allwinner,sun20i-d1-de2-mixer-1";
|
||||
reg = <0x5200000 0x100000>;
|
||||
clocks = <&display_clocks CLK_BUS_MIXER1>,
|
||||
<&display_clocks CLK_MIXER1>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&display_clocks RST_MIXER1>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mixer1_out: port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mixer1_out_tcon_top_mixer1: endpoint {
|
||||
remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi: dsi@5450000 {
|
||||
compatible = "allwinner,sun20i-d1-mipi-dsi",
|
||||
"allwinner,sun50i-a100-mipi-dsi";
|
||||
reg = <0x5450000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_MIPI_DSI>,
|
||||
<&tcon_top CLK_TCON_TOP_DSI>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu RST_BUS_MIPI_DSI>;
|
||||
phys = <&dphy>;
|
||||
phy-names = "dphy";
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
dsi_in_tcon_lcd0: endpoint {
|
||||
remote-endpoint = <&tcon_lcd0_out_dsi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dphy: phy@5451000 {
|
||||
compatible = "allwinner,sun20i-d1-mipi-dphy",
|
||||
"allwinner,sun50i-a100-mipi-dphy";
|
||||
reg = <0x5451000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_MIPI_DSI>,
|
||||
<&ccu CLK_MIPI_DSI>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu RST_BUS_MIPI_DSI>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
tcon_top: tcon-top@5460000 {
|
||||
compatible = "allwinner,sun20i-d1-tcon-top";
|
||||
reg = <0x5460000 0x1000>;
|
||||
clocks = <&ccu CLK_BUS_DPSS_TOP>,
|
||||
<&ccu CLK_TCON_TV>,
|
||||
<&ccu CLK_TVE>,
|
||||
<&ccu CLK_TCON_LCD0>;
|
||||
clock-names = "bus", "tcon-tv0", "tve0", "dsi";
|
||||
clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
|
||||
resets = <&ccu RST_BUS_DPSS_TOP>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_top_mixer0_in: port@0 {
|
||||
reg = <0>;
|
||||
|
||||
tcon_top_mixer0_in_mixer0: endpoint {
|
||||
remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_mixer0_out: port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
|
||||
};
|
||||
|
||||
tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_mixer1_in: port@2 {
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_top_mixer1_in_mixer1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_mixer1_out: port@3 {
|
||||
reg = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
|
||||
};
|
||||
|
||||
tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_hdmi_in: port@4 {
|
||||
reg = <4>;
|
||||
|
||||
tcon_top_hdmi_in_tcon_tv0: endpoint {
|
||||
remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_hdmi_out: port@5 {
|
||||
reg = <5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tcon_lcd0: lcd-controller@5461000 {
|
||||
compatible = "allwinner,sun20i-d1-tcon-lcd";
|
||||
reg = <0x5461000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_TCON_LCD0>,
|
||||
<&ccu CLK_TCON_LCD0>;
|
||||
clock-names = "ahb", "tcon-ch0";
|
||||
clock-output-names = "tcon-pixel-clock";
|
||||
resets = <&ccu RST_BUS_TCON_LCD0>,
|
||||
<&ccu RST_BUS_LVDS0>;
|
||||
reset-names = "lcd", "lvds";
|
||||
#clock-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_lcd0_in: port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
|
||||
};
|
||||
|
||||
tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_lcd0_out: port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_lcd0_out_dsi: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&dsi_in_tcon_lcd0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tcon_tv0: lcd-controller@5470000 {
|
||||
compatible = "allwinner,sun20i-d1-tcon-tv";
|
||||
reg = <0x5470000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_TCON_TV>,
|
||||
<&tcon_top CLK_TCON_TOP_TV0>;
|
||||
clock-names = "ahb", "tcon-ch1";
|
||||
resets = <&ccu RST_BUS_TCON_TV>;
|
||||
reset-names = "lcd";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_tv0_in: port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
|
||||
};
|
||||
|
||||
tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_tv0_out: port@1 {
|
||||
reg = <1>;
|
||||
|
||||
tcon_tv0_out_tcon_top_hdmi: endpoint {
|
||||
remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ppu: power-controller@7001000 {
|
||||
compatible = "allwinner,sun20i-d1-ppu";
|
||||
reg = <0x7001000 0x1000>;
|
||||
clocks = <&r_ccu CLK_BUS_R_PPU>;
|
||||
resets = <&r_ccu RST_BUS_R_PPU>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
r_ccu: clock-controller@7010000 {
|
||||
compatible = "allwinner,sun20i-d1-r-ccu";
|
||||
reg = <0x7010000 0x400>;
|
||||
clocks = <&dcxo>,
|
||||
<&rtc CLK_OSC32K>,
|
||||
<&rtc CLK_IOSC>,
|
||||
<&ccu CLK_PLL_PERIPH0_DIV3>;
|
||||
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
rtc: rtc@7090000 {
|
||||
compatible = "allwinner,sun20i-d1-rtc",
|
||||
"allwinner,sun50i-r329-rtc";
|
||||
reg = <0x7090000 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&r_ccu CLK_BUS_R_RTC>,
|
||||
<&dcxo>,
|
||||
<&r_ccu CLK_R_AHB>;
|
||||
clock-names = "bus", "hosc", "ahb";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user