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https://github.com/riscv-software-src/opensbi
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8e9966c1a7
Corrected the typos of some documents in the 'docs' folder. Signed-off-by: zhangdongdong <zhangdongdong@eswincomputing.com> Reviewed-by: Anup Patel <anup@brainfault.org>
39 lines
1.1 KiB
Markdown
39 lines
1.1 KiB
Markdown
Ariane FPGA SoC Platform
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========================
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Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit
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RISC-V instruction set. The Ariane FPGA development platform is based on FPGA
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SoC (which currently supports only Genesys 2 board) and is capable of running
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Linux.
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The FPGA SoC currently contains the following peripherals:
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- DDR3 memory controller
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- SPI controller to connect to an SDCard
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- Ethernet controller
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- JTAG port (see debugging section below)
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- Bootrom containing zero stage bootloader and device tree.
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To build platform specific library and firmwares, provide the
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*PLATFORM=fpga/ariane* parameter to the top level `make` command.
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Platform Options
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----------------
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The *Ariane FPGA* platform does not have any platform-specific options.
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Building Ariane FPGA Platform
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-----------------------------
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**Linux Kernel Payload**
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```
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make PLATFORM=fpga/ariane FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
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```
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Booting Ariane FPGA Platform
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----------------------------
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**Linux Kernel Payload**
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As Linux kernel image is embedded in the OpenSBI firmware binary, Ariane will
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directly boot into Linux directly after powered on.
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