mirror of
https://github.com/riscv-software-src/opensbi
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25 lines
1.6 KiB
Markdown
25 lines
1.6 KiB
Markdown
OpenSBI as coreboot payload
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==============================
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[coreboot](https://www.coreboot.org/) is a free/libre and open source firmware platform support multiple hardware architectures( x86, ARMv7, arm64, PowerPC64, MIPS and RISC-V) and diverse hardware models. In RISC-V world, coreboot currently support HiFive Unleashed with OpenSBI as a payload to boot GNU/Linux:
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```
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SiFive HiFive unleashed's original firmware boot process:
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+-----------+
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+------+ +------+ +------+ | BBL |
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| MSEL |--->| ZSBL |--->| FSBL |--->| +-------+
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+------+ +------+ +------+ | | linux |
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+---+-------+
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coreboot boot process:
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+---------------------------------------------------------------------+
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| coreboot |
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+------+ +------+ | +-----------+ +----------+ +----------+ +-----------------------+
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| MSEL |-->| ZSBL |-->| | bootblock |->| romstage |->| ramstage |->| payload ( OpenSBI) |
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+------+ +------+ | +-----------+ +----------+ +----------+ | +-------+ |
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| | | linux | |
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+---------------------------------------------+-------------+-------+-+
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```
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The upstreaming work is still in progress. There's a [documentation](https://github.com/hardenedlinux/embedded-iot_profile/blob/master/docs/riscv/hifiveunleashed_coreboot_notes-en.md) about how to build [out-of-tree code](https://github.com/hardenedlinux/coreboot-HiFiveUnleashed) to load OpenSBI.
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