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https://github.com/riscv-software-src/opensbi
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4035ae94be
The current DT binding description is misleading and confusing. Clarify the text and provide more examples. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
101 lines
4.5 KiB
Markdown
101 lines
4.5 KiB
Markdown
OpenSBI SBI PMU extension support
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==================================
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SBI PMU extension supports allow supervisor software to configure/start/stop
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any performance counter at anytime. Thus, an user can leverage full
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capability of performance analysis tools such as perf if SBI PMU extension is
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enabled. The OpenSBI implementation makes the following assumptions about the
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hardware platform.
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* MCOUNTINHIBIT CSR must be implemented in the hardware. Otherwise, SBI PMU
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extension will not be enabled.
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* The platform must provide information about PMU event to counter mapping
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via device tree or platform specific hooks. Otherwise, SBI PMU extension will
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not be enabled.
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* The platforms should provide information about the PMU event selector values
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that should be encoded in the expected value of MHPMEVENTx while configuring
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MHPMCOUNTERx for that specific event. This can be done via a device tree or
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platform specific hooks. The exact value to be written to he MHPMEVENTx is
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completely depends on platform. Generic platform writes the zero-extended event_idx
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as the expected value for hardware cache/generic events as suggested by the SBI
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specification.
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SBI PMU Device Tree Bindings
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----------------------------
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Platforms may choose to describe PMU event selector and event to counter mapping
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values via device tree. The following sections describes the PMU DT node
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bindings in details.
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* **compatible** (Mandatory) - The compatible string of SBI PMU device tree node.
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This DT property must have the value **riscv,pmu**.
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* **riscv,event-to-mhpmevent**(Optional) - It represents an ONE-to-ONE mapping
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between a PMU event and the event selector value that platform expects to be
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written to the MHPMEVENTx CSR for that event. The mapping is encoded in a
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table format where each row represents an event. The first column represent the
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event idx where the 2nd & 3rd column represent the event selector value that
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should be encoded in the expected value to be written in MHPMEVENTx.
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This property shouldn't encode any raw hardware event.
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* **riscv,event-to-mhpmcounters**(Optional) - It represents a MANY-to-MANY
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mapping between a range of events and all the MHPMCOUNTERx in a bitmap format
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that can be used to monitor these range of events. The information is encoded in
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a table format where each row represent a certain range of events and
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corresponding counters. The first column represents starting of the pmu event id
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and 2nd column represents the end of the pmu event id. The third column
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represent a bitmap of all the MHPMCOUNTERx. This property is mandatory if
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event-to-mhpmevent is present. Otherwise, it can be omitted. This property
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shouldn't encode any raw event.
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* **riscv,raw-event-to-mhpmcounters**(Optional) - It represents an ONE-to-MANY
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or MANY-to-MANY mapping between the raw event(s) and all the MHPMCOUNTERx in
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a bitmap format that can be used to monitor that raw event. The encoding of the
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raw events are platform specific. The information is encoded in a table format
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where each row represent the specific raw event(s). The first column is a 64bit
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match value where the invariant bits of range of events are set. The second
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column is a 64 bit mask that will have all the variant bits of the range of
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events cleared. Every other bits should be set in the mask.
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The third column is a 32bit value to represent bitmap of all MHPMCOUNTERx that
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can monitor these set of event(s).
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If a platform directly encodes each raw PMU event as a unique ID, the value of
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select_mask must be 0xffffffff_ffffffff.
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*Note:* A platform may choose to provide the mapping between event & counters
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via platform hooks rather than the device tree.
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### Example 1
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```
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pmu {
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compatible = "riscv,pmu";
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riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>,
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riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
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<0x00002 0x00002 0x00000004>,
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<0x00003 0x0000A 0x00000ff8>,
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<0x10000 0x10033 0x000ff000>,
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/* For event ID 0x0002 */
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riscv,raw-event-to-mhpmcounters = <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
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/* For event ID 0-4 */
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<0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
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/* For event ID 0xffffffff0000000f - 0xffffffff000000ff */
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<0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>,
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};
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```
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### Example 2
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```
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/*
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* For HiFive Unmatched board. The encodings can be found here
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* https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
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*/
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pmu {
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compatible = "riscv,pmu";
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riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0xc>,
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<0x0 0x1 0xffffffff 0xfff800ff 0xc>,
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<0x0 0x2 0xffffffff 0xffffe0ff 0xc>;
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};
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```
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