sunxi: Add a U-Boot port for the Allwinner D1 Nezha

Signed-off-by: Samuel Holland <samuel@sholland.org>

Kconfig

@@ -12,6 +12,8 @@ source "scripts/Kconfig.include"
 # Allow defaults in arch-specific code to override any given here
 source "arch/Kconfig"
 
+source "board/sunxi/Kconfig"
+
 menu "General setup"
 
 config BROKEN

arch/arm/mach-sunxi/Kconfig

@@ -986,8 +986,6 @@ config BLUETOOTH_DT_DEVICE_FIXUP
 	  The used address is "bdaddr" if set, and "ethaddr" with the LSB
 	  flipped elsewise.
 
-source "board/sunxi/Kconfig"
-
 endif
 
 config CHIP_DIP_SCAN

arch/riscv/Kconfig

@@ -31,6 +31,10 @@ config TARGET_SIPEED_MAIX
 	bool "Support Sipeed Maix Board"
 	select SYS_CACHE_SHIFT_6
 
+config TARGET_SUNXI
+	bool "Support Allwinner sunxi SoCs with RISC-V cores"
+	select SYS_CACHE_SHIFT_6
+
 endchoice
 
 config SYS_ICACHE_OFF

arch/riscv/dts/Makefile

@@ -7,6 +7,7 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+dtb-$(CONFIG_TARGET_SUNXI) += sun20i-d1-nezha.dtb
 
 include $(srctree)/scripts/Makefile.dts
 

arch/riscv/dts/sun20i-d1-common-regulators.dtsi

@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
+
+/ {
+	reg_vcc: vcc {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	reg_vcc_3v3: vcc-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&reg_vcc>;
+	};
+};
+
+&codec {
+	avcc-supply = <&reg_aldo>;
+	hpvcc-supply = <&reg_hpldo>;
+	vdd33-supply = <&reg_vcc_3v3>;
+};
+
+&gpio {
+	vcc-pb-supply = <&reg_vcc_3v3>;
+	vcc-pc-supply = <&reg_vcc_3v3>;
+	vcc-pd-supply = <&reg_vcc_3v3>;
+	vcc-pe-supply = <&reg_vcc_3v3>;
+	vcc-pf-supply = <&reg_vcc_3v3>;
+	vcc-pg-supply = <&reg_vcc_3v3>;
+};
+
+&hdmi {
+	hvcc-supply = <&reg_ldoa>;
+};
+
+&lradc {
+	vref-supply = <&reg_aldo>;
+};
+
+&reg_aldo {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	vdd33-supply = <&reg_vcc_3v3>;
+};
+
+&reg_hpldo {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	hpldoin-supply = <&reg_vcc_3v3>;
+};
+
+&reg_ldoa {
+	regulator-always-on;
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	ldo-in-supply = <&reg_vcc_3v3>;
+};
+
+&ths {
+	vref-supply = <&reg_aldo>;
+};

arch/riscv/dts/sun20i-d1-nezha.dts

@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+
+#include "sun20i-d1.dtsi"
+#include "sun20i-d1-common-regulators.dtsi"
+
+/ {
+	model = "Allwinner D1 Nezha";
+	compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
+
+	aliases {
+		ethernet0 = &emac;
+		mmc0 = &mmc0;
+		mmc1 = &mmc1;
+		mmc2 = &mmc2;
+		serial0 = &uart0;
+		spi0 = &spi0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	hdmi_connector: connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	reg_usbvbus: usbvbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usbvbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
+		enable-active-high;
+		vin-supply = <&reg_vcc>;
+	};
+
+	reg_vdd_cpu: vdd-cpu {
+		compatible = "pwm-regulator";
+		pwms = <&pwm 0 50000 0>;
+		pwm-supply = <&reg_vcc>;
+		regulator-name = "vdd-cpu";
+		regulator-min-microvolt = <810000>;
+		regulator-max-microvolt = <1160000>;
+	};
+
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+	};
+};
+
+&codec {
+	allwinner,routing = "Headphone Jack", "HPOUTL",
+			    "Headphone Jack", "HPOUTR",
+			    "LINEINL", "HPOUTL",
+			    "LINEINR", "HPOUTR",
+			    "MICIN3", "Headset Microphone",
+			    "Headset Microphone", "HBIAS";
+	allwinner,widgets = "Microphone", "Headset Microphone",
+			    "Headphone", "Headphone Jack";
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&reg_vdd_cpu>;
+};
+
+&de {
+	status = "okay";
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&emac {
+	pinctrl-0 = <&rgmii_pe_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&ext_rgmii_phy>;
+	phy-mode = "rgmii-id";
+	phy-supply = <&reg_vcc_3v3>;
+	status = "okay";
+};
+
+&gpio {
+	i2s2_pb_pins: i2s2-pb-pins {
+		pins = "PB5", "PB6", "PB7";
+		function = "i2s2";
+	};
+
+	i2s2_pb3_din_pin: i2s2-pb3-din-pin {
+		pins = "PB3";
+		function = "i2s2_din";
+	};
+
+	i2s2_pb4_dout_pin: i2s2-pb4-dout-pin {
+		pins = "PB4";
+		function = "i2s2_dout";
+	};
+
+	ledc_pc0_pin: ledc-pc0-pin {
+		pins = "PC0";
+		function = "ledc";
+	};
+
+	pwm0_pd16_pin: pwm0-pd16-pin {
+		pins = "PD16";
+		function = "pwm";
+	};
+
+	pwm2_pd18_pin: pwm2-pd18-pin {
+		pins = "PD18";
+		function = "pwm";
+	};
+
+	pwm7_pd22_pin: pwm7-pd22-pin {
+		pins = "PD22";
+		function = "pwm";
+	};
+
+	spdif_pd22_pin: spdif-pd22-pin {
+		pins = "PD22";
+		function = "spdif";
+	};
+};
+
+&hdmi {
+	status = "okay";
+
+	port {
+		hdmi_out_con: endpoint {
+			remote-endpoint = <&hdmi_con_in>;
+		};
+	};
+};
+
+&hdmi_phy {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-0 = <&i2c0_pb10_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_pb0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	pcf8574a: gpio@38 {
+		compatible = "nxp,pcf8574a";
+		#address-cells = <0>;
+		reg = <0x38>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts-extended = <&gpio 1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&i2s2 {
+	pinctrl-0 = <&i2s2_pb_pins>, <&i2s2_pb3_din_pin>, <&i2s2_pb4_dout_pin>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&ledc {
+	pinctrl-0 = <&ledc_pc0_pin>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	led@0 {
+		reg = <0x0>;
+		color = <LED_COLOR_ID_RGB>;
+		function = LED_FUNCTION_INDICATOR;
+	};
+};
+
+&lradc {
+	wakeup-source;
+	status = "okay";
+
+	button-160 {
+		label = "OK";
+		linux,code = <KEY_OK>;
+		channel = <0>;
+		voltage = <160000>;
+	};
+};
+
+&mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
+
+&mmc0 {
+	bus-width = <4>;
+	cd-gpios = <&gpio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+	disable-wp;
+	vmmc-supply = <&reg_vcc_3v3>;
+	vqmmc-supply = <&reg_vcc_3v3>;
+	pinctrl-0 = <&mmc0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&mmc1 {
+	bus-width = <4>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	non-removable;
+	vmmc-supply = <&reg_vcc_3v3>;
+	vqmmc-supply = <&reg_vcc_3v3>;
+	pinctrl-0 = <&mmc1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	xr829: wifi@1 {
+		reg = <1>;
+		host-wake-gpios = <&gpio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */
+	};
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&pwm {
+	pinctrl-0 = <&pwm0_pd16_pin>, <&pwm2_pd18_pin>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spdif {
+	pinctrl-0 = <&spdif_pd22_pin>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-0 = <&spi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "boot0";
+				reg = <0x00000000 0x00100000>;
+			};
+
+			partition@100000 {
+				label = "uboot";
+				reg = <0x00100000 0x00300000>;
+			};
+
+			partition@400000 {
+				label = "secure_storage";
+				reg = <0x00400000 0x00100000>;
+			};
+
+			partition@500000 {
+				label = "sys";
+				reg = <0x00500000 0x0fb00000>;
+			};
+		};
+	};
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_pd_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_pb8_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	bluetooth {
+		compatible = "xradio,xr829-bt";
+		device-wakeup-gpios = <&gpio 6 16 GPIO_ACTIVE_LOW>; /* PG16 */
+		interrupts-extended = <&gpio 6 17 IRQ_TYPE_LEVEL_LOW>; /* PG17 */
+		interrupt-names = "wakeup";
+		reset-gpios = <&gpio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
+	};
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usbphy {
+	usb0_id_det-gpios = <&gpio 3 21 GPIO_ACTIVE_LOW>; /* PD21 */
+	usb0_vbus_det-gpios = <&gpio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
+	usb0_vbus-supply = <&reg_usbvbus>;
+	usb1_vbus-supply = <&reg_vcc>;
+	status = "okay";
+};

arch/riscv/dts/sunxi-u-boot.dtsi

@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "binman.dtsi"

board/sunxi/Kconfig

@@ -1,5 +1,24 @@
+menu "Board-specific options"
+	depends on ARCH_SUNXI || TARGET_SUNXI
+
+choice
+	prompt "sunxi SoC Variant"
+
+config MACH_SUN20I
+	bool "sun20i (Allwinner D1)"
+	depends on RISCV
+	select GENERIC_RISCV
+	select SPL_DM if SPL
+	imply SYSRESET_SBI
+
+endchoice
+
+config NR_DRAM_BANKS
+	default 1
+
 choice
 	prompt "SPL Image Type"
+	depends on SPL
 	default SPL_IMAGE_TYPE_SUNXI_EGON
 
 config SPL_IMAGE_TYPE_SUNXI_EGON
@@ -22,3 +41,72 @@ config SPL_IMAGE_TYPE
 	string
 	default "sunxi_egon" if SPL_IMAGE_TYPE_SUNXI_EGON
 	default "sunxi_toc0" if SPL_IMAGE_TYPE_SUNXI_TOC0
+
+config SPL_MAX_SIZE
+	hex
+	default SUNXI_SRAM_SIZE
+
+config SPL_OPENSBI_LOAD_ADDR
+	default 0x40000000
+
+config SUNXI_SRAM_ADDRESS
+	hex
+	default 0x20000 if MACH_SUN20I
+
+config SUNXI_SRAM_SIZE
+	hex
+	default 0x28000 if MACH_SUN20I
+
+config SYS_BOARD
+	default "sunxi"
+
+config SYS_CONFIG_NAME
+	default "sun20i" if MACH_SUN20I
+
+config SYS_CPU
+	default "generic" if MACH_SUN20I
+
+config SYS_SOC
+	default "sunxi"
+
+config SYS_TEXT_BASE
+	default 0x4a000000 if MACH_SUN20I
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select CLK
+	select DM_ETH if NET
+	select DM_GPIO
+	select DM_I2C if I2C
+	select DM_SERIAL
+	select DM_SPI if SPI
+	select GPIO
+	select MMC_SUNXI_HAS_NEW_MODE if MMC_SUNXI
+	select OF_HAS_PRIOR_STAGE
+	select PHY_SUN4I_USB if USB
+	select PINCTRL
+	select SPL_CLK if SPL_DM
+	select SPL_GPIO if SPL_DM
+	select SPL_OF_CONTROL if SPL_DM
+	select SPL_PINCTRL if SPL_DM
+	select SPL_SEPARATE_BSS if SPL
+	select SUPPORT_SPL
+	imply CMD_MMC
+	imply CMD_USB
+	imply DISTRO_DEFAULTS
+	imply FIT
+	imply MMC
+	imply SPL
+	imply SPL_SPI if SPI
+	imply SPL_MMC if MMC
+	imply SUNXI_GPIO
+	imply SYS_I2C_MVTWSI
+	imply SYS_NS16550
+	imply SYSRESET
+	imply USB_EHCI_GENERIC
+	imply USB_EHCI_HCD
+	imply USB_OHCI_GENERIC
+	imply USB_OHCI_HCD
+	imply WDT
+
+endmenu

board/sunxi/Makefile

@@ -6,7 +6,8 @@
 #
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-y	+= board.o
+obj-$(CONFIG_ARCH_SUNXI)	+= board.o
+obj-$(CONFIG_TARGET_SUNXI)	+= board-riscv.o
 obj-$(CONFIG_SUN7I_GMAC)	+= gmac.o
 obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i_auto.o
 obj-$(CONFIG_MACH_SUN5I)	+= dram_sun5i_auto.o

board/sunxi/board-riscv.c

@@ -0,0 +1,23 @@
+#include <common.h>
+#include <cpu.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void *board_fdt_blob_setup(int *err)
+{
+	*err = 0;
+
+	return (void *)(ulong)gd->arch.firmware_fdt_addr;
+}
+
+int board_init(void)
+{
+	/* https://lore.kernel.org/u-boot/31587574-4cd1-02da-9761-0134ac82b94b@sholland.org/ */
+	return cpu_probe_all();
+}
+
+uint32_t spl_boot_device(void)
+{
+	return BOOT_DEVICE_MMC1;
+}

common/spl/Kconfig

@@ -175,7 +175,7 @@ config SPL_TEXT_BASE
 	hex "SPL Text Base"
 	default ISW_ENTRY_ADDR if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
 	default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
-	default 0x20060 if SUN50I_GEN_H6
+	default 0x20060 if SUN50I_GEN_H6 || MACH_SUN20I
 	default 0x00060 if ARCH_SUNXI
 	default 0xfffc0000 if ARCH_ZYNQMP
 	default 0x0
@@ -1323,7 +1323,7 @@ config SPL_OPTEE_IMAGE
 
 config SPL_OPENSBI
 	bool "Support RISC-V OpenSBI"
-	depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE
+	depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE && SPL_LOAD_FIT
 	help
 	  OpenSBI is an open-source implementation of the RISC-V Supervisor Binary
 	  Interface (SBI) specification. U-Boot supports the OpenSBI FW_DYNAMIC

configs/nezha_defconfig

@@ -0,0 +1,31 @@
+CONFIG_RISCV=y
+CONFIG_DEFAULT_DEVICE_TREE="sun20i-d1-nezha"
+CONFIG_TARGET_SUNXI=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+# CONFIG_SPL_SMP is not set
+CONFIG_SYS_LOAD_ADDR=0x4a000000
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_PHY_REALTEK=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_MASS_STORAGE=y

drivers/clk/Makefile

@@ -23,7 +23,6 @@ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
 obj-$(CONFIG_ARCH_NPCM) += nuvoton/
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_ARCH_SOCFPGA) += altera/
-obj-$(CONFIG_ARCH_SUNXI) += sunxi/
 obj-$(CONFIG_CLK_AT91) += at91/
 obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
 obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
@@ -41,6 +40,7 @@ obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
 obj-$(CONFIG_CLK_SIFIVE) += sifive/
 obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
 obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
+obj-$(CONFIG_CLK_SUNXI) += sunxi/
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
 obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
 obj-$(CONFIG_CLK_VERSAL) += clk_versal.o

drivers/clk/sunxi/Kconfig

@@ -1,6 +1,6 @@
 config CLK_SUNXI
 	bool "Clock support for Allwinner SoCs"
-	depends on CLK && ARCH_SUNXI
+	depends on CLK && (ARCH_SUNXI || TARGET_SUNXI)
 	select DM_RESET
 	select SPL_DM_RESET if SPL_CLK
 	default y
@@ -98,6 +98,7 @@ config CLK_SUN8I_H3
 
 config CLK_SUN20I_D1
 	bool "Clock driver for Allwinner D1"
+	default MACH_SUN20I
 	help
 	  This enables common clock driver support for platforms based
 	  on Allwinner D1 SoC.

drivers/net/phy/Kconfig

@@ -19,14 +19,14 @@ if PHYLIB
 
 config PHY_ADDR_ENABLE
 	bool "Limit phy address"
-	default y if ARCH_SUNXI
+	default y if (ARCH_SUNXI || TARGET_SUNXI)
 	help
 	  Select this if you want to control which phy address is used
 
 if PHY_ADDR_ENABLE
 config PHY_ADDR
 	int "PHY address"
-	default 1 if ARCH_SUNXI
+	default 1 if (ARCH_SUNXI || TARGET_SUNXI)
 	default 0
 	help
 	  The address of PHY on MII bus. Usually in range of 0 to 31.

drivers/phy/allwinner/Kconfig

@@ -3,7 +3,7 @@
 #
 config PHY_SUN4I_USB
 	bool "Allwinner Sun4I USB PHY driver"
-	depends on ARCH_SUNXI
+	depends on (ARCH_SUNXI || TARGET_SUNXI)
 	select DM_REGULATOR
 	select PHY
 	help

drivers/reset/Kconfig

@@ -137,7 +137,7 @@ config RESET_MTMIPS
 
 config RESET_SUNXI
 	bool "RESET support for Allwinner SoCs"
-	depends on DM_RESET && ARCH_SUNXI
+	depends on DM_RESET && (ARCH_SUNXI || TARGET_SUNXI)
 	default y
 	help
 	  This enables support for common reset driver for

drivers/spi/Kconfig

@@ -403,7 +403,7 @@ config SOFT_SPI
 
 config SPI_SUNXI
 	bool "Allwinner SoC SPI controllers"
-	default ARCH_SUNXI
+	default (ARCH_SUNXI || TARGET_SUNXI)
 	help
 	  Enable the Allwinner SoC SPi controller driver.
 

drivers/usb/gadget/Kconfig

@@ -40,7 +40,7 @@ if USB_GADGET
 
 config USB_GADGET_MANUFACTURER
 	string "Vendor name of the USB device"
-	default "Allwinner Technology" if ARCH_SUNXI
+	default "Allwinner Technology" if (ARCH_SUNXI || TARGET_SUNXI)
 	default "Rockchip" if ARCH_ROCKCHIP
 	default "U-Boot"
 	help
@@ -49,7 +49,7 @@ config USB_GADGET_MANUFACTURER
 
 config USB_GADGET_VENDOR_NUM
 	hex "Vendor ID of the USB device"
-	default 0x1f3a if ARCH_SUNXI
+	default 0x1f3a if (ARCH_SUNXI || TARGET_SUNXI)
 	default 0x2207 if ARCH_ROCKCHIP
 	default 0x0
 	help
@@ -59,7 +59,7 @@ config USB_GADGET_VENDOR_NUM
 
 config USB_GADGET_PRODUCT_NUM
 	hex "Product ID of the USB device"
-	default 0x1010 if ARCH_SUNXI
+	default 0x1010 if (ARCH_SUNXI || TARGET_SUNXI)
 	default 0x310a if ROCKCHIP_RK3036
 	default 0x310c if ROCKCHIP_RK3128
 	default 0x320a if ROCKCHIP_RK3229 || ROCKCHIP_RK3288

drivers/usb/musb-new/Kconfig

@@ -67,7 +67,7 @@ config USB_MUSB_PIC32
 
 config USB_MUSB_SUNXI
 	bool "Enable sunxi OTG / DRC USB controller"
-	depends on ARCH_SUNXI
+	depends on (ARCH_SUNXI || TARGET_SUNXI)
 	select USB_MUSB_PIO_ONLY
 	default y
 	---help---

drivers/watchdog/Kconfig

@@ -28,7 +28,7 @@ config WATCHDOG_TIMEOUT_MSECS
 	default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6
 	default 128000 if ARCH_MX7 || ARCH_VF610
 	default 30000 if ARCH_SOCFPGA
-	default 16000 if ARCH_SUNXI
+	default 16000 if (ARCH_SUNXI || TARGET_SUNXI)
 	default 60000
 	help
 	  Watchdog timeout in msec
@@ -306,7 +306,7 @@ config WDT_STM32MP
 
 config WDT_SUNXI
 	bool "Allwinner sunxi watchdog timer support"
-	depends on WDT && ARCH_SUNXI
+	depends on WDT && (ARCH_SUNXI || TARGET_SUNXI)
 	default y
 	help
 	  Enable support for the watchdog timer in Allwinner sunxi SoCs.

include/configs/sun20i.h

@@ -0,0 +1,68 @@
+#include <linux/stringify.h>
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/* FIXME: Need a real clock driver! */
+#define CONFIG_SYS_NS16550_CLK		24000000
+#define CONFIG_SYS_TCLK			24000000
+
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+#endif
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x4fe00000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000 /* 512 KiB */
+#define CONFIG_SPL_BSS_START_ADDR	0x4ff80000
+#define CONFIG_SPL_STACK		0x00048000
+
+#define SDRAM_OFFSET(x)			0x4##x
+#define BOOTM_SIZE			__stringify(0xa000000)
+#define KERNEL_ADDR_R			__stringify(SDRAM_OFFSET(0200000))
+#define KERNEL_COMP_ADDR_R		__stringify(SDRAM_OFFSET(4000000))
+#define KERNEL_COMP_SIZE		__stringify(0xb000000)
+#define FDT_ADDR_R			__stringify(SDRAM_OFFSET(FA00000))
+#define SCRIPT_ADDR_R			__stringify(SDRAM_OFFSET(FC00000))
+#define PXEFILE_ADDR_R			__stringify(SDRAM_OFFSET(FD00000))
+#define FDTOVERLAY_ADDR_R		__stringify(SDRAM_OFFSET(FE00000))
+#define RAMDISK_ADDR_R			__stringify(SDRAM_OFFSET(FF00000))
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=" BOOTM_SIZE "\0" \
+	"fdt_addr_r=" FDT_ADDR_R "\0" \
+	"fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \
+	"kernel_addr_r=" KERNEL_ADDR_R "\0" \
+	"kernel_comp_addr_r=" KERNEL_COMP_ADDR_R "\0" \
+	"kernel_comp_size=" KERNEL_COMP_SIZE "\0" \
+	"pxefile_addr_r=" PXEFILE_ADDR_R "\0" \
+	"ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
+	"scriptaddr=" SCRIPT_ADDR_R "\0"
+
+#ifdef CONFIG_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
+#ifdef CONFIG_CMD_DHCP
+#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
+#else
+#define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_DEVICES_MMC(func) \
+	BOOT_TARGET_DEVICES_USB(func) \
+	BOOT_TARGET_DEVICES_DHCP(func)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	MEM_LAYOUT_ENV_SETTINGS \
+	BOOTENV

include/dt-bindings/clock/sun20i-d1-r-ccu.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
+
+#define CLK_R_AHB		0
+
+#define CLK_BUS_R_TIMER		2
+#define CLK_BUS_R_TWD		3
+#define CLK_BUS_R_PPU		4
+#define CLK_R_IR_RX		5
+#define CLK_BUS_R_IR_RX		6
+#define CLK_BUS_R_RTC		7
+#define CLK_BUS_R_CPUCFG	8
+
+#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */

include/dt-bindings/clock/sun6i-rtc.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+
+#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_
+#define _DT_BINDINGS_CLK_SUN6I_RTC_H_
+
+#define CLK_OSC32K		0
+#define CLK_OSC32K_FANOUT	1
+#define CLK_IOSC		2
+
+#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */

include/dt-bindings/mailbox/sun20i-d1-msgbox.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _DT_BINDINGS_MAILBOX_SUN20I_D1_MSGBOX_H_
+#define _DT_BINDINGS_MAILBOX_SUN20I_D1_MSGBOX_H_
+
+/* First cell: channel (transmitting user) */
+#define MBOX_USER_CPUX			0
+#define MBOX_USER_DSP			1
+#define MBOX_USER_RISCV			2
+
+/* Second cell: direction (RX if phandle references local mailbox, else TX) */
+#define MBOX_RX				0
+#define MBOX_TX				1
+
+#endif /* _DT_BINDINGS_MAILBOX_SUN20I_D1_MSGBOX_H_ */

include/dt-bindings/reset/sun20i-d1-r-ccu.h

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
+
+#define RST_BUS_R_TIMER		0
+#define RST_BUS_R_TWD		1
+#define RST_BUS_R_PPU		2
+#define RST_BUS_R_IR_RX		3
+#define RST_BUS_R_RTC		4
+#define RST_BUS_R_CPUCFG	5
+
+#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */

scripts/Makefile.spl

@@ -271,6 +271,10 @@ INPUTS-y	+= $(obj)/sunxi-spl-with-ecc.bin
 endif
 endif
 
+ifdef CONFIG_TARGET_SUNXI
+INPUTS-y	+= $(obj)/sunxi-spl.bin
+endif
+
 ifeq ($(CONFIG_SYS_SOC),"at91")
 INPUTS-y	+= $(obj)/boot.bin
 endif