random-mirrors/smaeul-u-boot
1
0
Fork 0
mirror of https://github.com/smaeul/u-boot.git synced 2025-10-14 12:56:00 +01:00
Code Issues Packages Projects Releases Wiki Activity

riscv: Add BL808 register definitions

Browse Source 
Signed-off-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Samuel Holland 2022-12-01 19:50:57 -06:00
parent 425696477f
commit 30355416b3
37 changed files with 48104 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

251
include/bl808/adc_reg.h Normal file
View File

@ -0,0 +1,251 @@
/**
******************************************************************************
* @file adc_reg.h
* @version V1.0
* @date 2022-08-05
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_ADC_H__
#define __HARDWARE_ADC_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
/* gpip base */
#define GPIP_GPADC_CONFIG_OFFSET (0x0) /* gpadc_config */
#define GPIP_GPADC_DMA_RDATA_OFFSET (0x4) /* gpadc_dma_rdata */
#define GPIP_GPADC_PIR_TRAIN_OFFSET (0x20) /* gpadc_pir_train */
/* aon base */
#define AON_GPADC_REG_CMD_OFFSET (0x90C) /* gpadc_reg_cmd */
#define AON_GPADC_REG_CONFIG1_OFFSET (0x910) /* gpadc_reg_config1 */
#define AON_GPADC_REG_CONFIG2_OFFSET (0x914) /* gpadc_reg_config2 */
#define AON_GPADC_REG_SCN_POS1_OFFSET (0x918) /* adc converation sequence 1 */
#define AON_GPADC_REG_SCN_POS2_OFFSET (0x91C) /* adc converation sequence 2 */
#define AON_GPADC_REG_SCN_NEG1_OFFSET (0x920) /* adc converation sequence 3 */
#define AON_GPADC_REG_SCN_NEG2_OFFSET (0x924) /* adc converation sequence 4 */
#define AON_GPADC_REG_STATUS_OFFSET (0x928) /* gpadc_reg_status */
#define AON_GPADC_REG_ISR_OFFSET (0x92C) /* gpadc_reg_isr */
#define AON_GPADC_REG_RESULT_OFFSET (0x930) /* gpadc_reg_result */
#define AON_GPADC_REG_RAW_RESULT_OFFSET (0x934) /* gpadc_reg_raw_result */
#define AON_GPADC_REG_DEFINE_OFFSET (0x938) /* gpadc_reg_define */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : gpadc_config */
#define GPIP_GPADC_DMA_EN (1 << 0U)
#define GPIP_GPADC_FIFO_CLR (1 << 1U)
#define GPIP_GPADC_FIFO_NE (1 << 2U)
#define GPIP_GPADC_FIFO_FULL (1 << 3U)
#define GPIP_GPADC_RDY (1 << 4U)
#define GPIP_GPADC_FIFO_OVERRUN (1 << 5U)
#define GPIP_GPADC_FIFO_UNDERRUN (1 << 6U)
#define GPIP_GPADC_RDY_CLR (1 << 8U)
#define GPIP_GPADC_FIFO_OVERRUN_CLR (1 << 9U)
#define GPIP_GPADC_FIFO_UNDERRUN_CLR (1 << 10U)
#define GPIP_GPADC_RDY_MASK (1 << 12U)
#define GPIP_GPADC_FIFO_OVERRUN_MASK (1 << 13U)
#define GPIP_GPADC_FIFO_UNDERRUN_MASK (1 << 14U)
#define GPIP_GPADC_FIFO_DATA_COUNT_SHIFT (16U)
#define GPIP_GPADC_FIFO_DATA_COUNT_MASK (0x3f << GPIP_GPADC_FIFO_DATA_COUNT_SHIFT)
#define GPIP_GPADC_FIFO_THL_SHIFT (22U)
#define GPIP_GPADC_FIFO_THL_MASK (0x3 << GPIP_GPADC_FIFO_THL_SHIFT)
/* 0x4 : gpadc_dma_rdata */
#define GPIP_GPADC_DMA_RDATA_SHIFT (0U)
#define GPIP_GPADC_DMA_RDATA_MASK (0x3ffffff << GPIP_GPADC_DMA_RDATA_SHIFT)
/* 0x20 : gpadc_pir_train */
#define GPIP_PIR_EXTEND_SHIFT (0U)
#define GPIP_PIR_EXTEND_MASK (0x1f << GPIP_PIR_EXTEND_SHIFT)
#define GPIP_PIR_CNT_V_SHIFT (8U)
#define GPIP_PIR_CNT_V_MASK (0x1f << GPIP_PIR_CNT_V_SHIFT)
#define GPIP_PIR_TRAIN (1 << 16U)
#define GPIP_PIR_STOP (1 << 17U)
/* 0x90C : gpadc_reg_cmd */
#define AON_GPADC_GLOBAL_EN (1 << 0U)
#define AON_GPADC_CONV_START (1 << 1U)
#define AON_GPADC_SOFT_RST (1 << 2U)
#define AON_GPADC_NEG_SEL_SHIFT (3U)
#define AON_GPADC_NEG_SEL_MASK (0x1f << AON_GPADC_NEG_SEL_SHIFT)
#define AON_GPADC_POS_SEL_SHIFT (8U)
#define AON_GPADC_POS_SEL_MASK (0x1f << AON_GPADC_POS_SEL_SHIFT)
#define AON_GPADC_NEG_GND (1 << 13U)
#define AON_GPADC_MICBIAS_EN (1 << 14U)
#define AON_GPADC_MICPGA_EN (1 << 15U)
#define AON_GPADC_BYP_MICBOOST (1 << 16U)
#define AON_GPADC_RCAL_EN (1 << 17U)
#define AON_GPADC_DWA_EN (1 << 18U)
#define AON_GPADC_MIC2_DIFF (1 << 19U)
#define AON_GPADC_MIC1_DIFF (1 << 20U)
#define AON_GPADC_MIC_PGA2_GAIN_SHIFT (21U)
#define AON_GPADC_MIC_PGA2_GAIN_MASK (0x3 << AON_GPADC_MIC_PGA2_GAIN_SHIFT)
#define AON_GPADC_MICBOOST_32DB_EN (1 << 23U)
#define AON_GPADC_CHIP_SEN_PU (1 << 27U)
#define AON_GPADC_SEN_SEL_SHIFT (28U)
#define AON_GPADC_SEN_SEL_MASK (0x7 << AON_GPADC_SEN_SEL_SHIFT)
#define AON_GPADC_SEN_TEST_EN (1 << 31U)
/* 0x910 : gpadc_reg_config1 */
#define AON_GPADC_CAL_OS_EN (1 << 0U)
#define AON_GPADC_CONT_CONV_EN (1 << 1U)
#define AON_GPADC_RES_SEL_SHIFT (2U)
#define AON_GPADC_RES_SEL_MASK (0x7 << AON_GPADC_RES_SEL_SHIFT)
#define AON_GPADC_VCM_SEL_EN (1 << 8U)
#define AON_GPADC_VCM_HYST_SEL (1 << 9U)
#define AON_GPADC_LOWV_DET_EN (1 << 10U)
#define AON_GPADC_PWM_TRG_EN (1 << 11U)
#define AON_GPADC_CLK_ANA_DLY_SHIFT (12U)
#define AON_GPADC_CLK_ANA_DLY_MASK (0xf << AON_GPADC_CLK_ANA_DLY_SHIFT)
#define AON_GPADC_CLK_ANA_DLY_EN (1 << 16U)
#define AON_GPADC_CLK_ANA_INV (1 << 17U)
#define AON_GPADC_CLK_DIV_RATIO_SHIFT (18U)
#define AON_GPADC_CLK_DIV_RATIO_MASK (0x7 << AON_GPADC_CLK_DIV_RATIO_SHIFT)
#define AON_GPADC_SCAN_LENGTH_SHIFT (21U)
#define AON_GPADC_SCAN_LENGTH_MASK (0xf << AON_GPADC_SCAN_LENGTH_SHIFT)
#define AON_GPADC_SCAN_EN (1 << 25U)
#define AON_GPADC_DITHER_EN (1 << 26U)
#define AON_GPADC_V11_SEL_SHIFT (27U)
#define AON_GPADC_V11_SEL_MASK (0x3 << AON_GPADC_V11_SEL_SHIFT)
#define AON_GPADC_V18_SEL_SHIFT (29U)
#define AON_GPADC_V18_SEL_MASK (0x3 << AON_GPADC_V18_SEL_SHIFT)
/* 0x914 : gpadc_reg_config2 */
#define AON_GPADC_DIFF_MODE (1 << 2U)
#define AON_GPADC_VREF_SEL (1 << 3U)
#define AON_GPADC_VBAT_EN (1 << 4U)
#define AON_GPADC_TSEXT_SEL (1 << 5U)
#define AON_GPADC_TS_EN (1 << 6U)
#define AON_GPADC_PGA_VCM_SHIFT (7U)
#define AON_GPADC_PGA_VCM_MASK (0x3 << AON_GPADC_PGA_VCM_SHIFT)
#define AON_GPADC_PGA_OS_CAL_SHIFT (9U)
#define AON_GPADC_PGA_OS_CAL_MASK (0xf << AON_GPADC_PGA_OS_CAL_SHIFT)
#define AON_GPADC_PGA_EN (1 << 13U)
#define AON_GPADC_PGA_VCMI_EN (1 << 14U)
#define AON_GPADC_CHOP_MODE_SHIFT (15U)
#define AON_GPADC_CHOP_MODE_MASK (0x3 << AON_GPADC_CHOP_MODE_SHIFT)
#define AON_GPADC_BIAS_SEL (1 << 17U)
#define AON_GPADC_TEST_EN (1 << 18U)
#define AON_GPADC_TEST_SEL_SHIFT (19U)
#define AON_GPADC_TEST_SEL_MASK (0x7 << AON_GPADC_TEST_SEL_SHIFT)
#define AON_GPADC_PGA2_GAIN_SHIFT (22U)
#define AON_GPADC_PGA2_GAIN_MASK (0x7 << AON_GPADC_PGA2_GAIN_SHIFT)
#define AON_GPADC_PGA1_GAIN_SHIFT (25U)
#define AON_GPADC_PGA1_GAIN_MASK (0x7 << AON_GPADC_PGA1_GAIN_SHIFT)
#define AON_GPADC_DLY_SEL_SHIFT (28U)
#define AON_GPADC_DLY_SEL_MASK (0x7 << AON_GPADC_DLY_SEL_SHIFT)
#define AON_GPADC_TSVBE_LOW (1 << 31U)
/* 0x918 : adc converation sequence 1 */
#define AON_GPADC_SCAN_POS_0_SHIFT (0U)
#define AON_GPADC_SCAN_POS_0_MASK (0x1f << AON_GPADC_SCAN_POS_0_SHIFT)
#define AON_GPADC_SCAN_POS_1_SHIFT (5U)
#define AON_GPADC_SCAN_POS_1_MASK (0x1f << AON_GPADC_SCAN_POS_1_SHIFT)
#define AON_GPADC_SCAN_POS_2_SHIFT (10U)
#define AON_GPADC_SCAN_POS_2_MASK (0x1f << AON_GPADC_SCAN_POS_2_SHIFT)
#define AON_GPADC_SCAN_POS_3_SHIFT (15U)
#define AON_GPADC_SCAN_POS_3_MASK (0x1f << AON_GPADC_SCAN_POS_3_SHIFT)
#define AON_GPADC_SCAN_POS_4_SHIFT (20U)
#define AON_GPADC_SCAN_POS_4_MASK (0x1f << AON_GPADC_SCAN_POS_4_SHIFT)
#define AON_GPADC_SCAN_POS_5_SHIFT (25U)
#define AON_GPADC_SCAN_POS_5_MASK (0x1f << AON_GPADC_SCAN_POS_5_SHIFT)
/* 0x91C : adc converation sequence 2 */
#define AON_GPADC_SCAN_POS_6_SHIFT (0U)
#define AON_GPADC_SCAN_POS_6_MASK (0x1f << AON_GPADC_SCAN_POS_6_SHIFT)
#define AON_GPADC_SCAN_POS_7_SHIFT (5U)
#define AON_GPADC_SCAN_POS_7_MASK (0x1f << AON_GPADC_SCAN_POS_7_SHIFT)
#define AON_GPADC_SCAN_POS_8_SHIFT (10U)
#define AON_GPADC_SCAN_POS_8_MASK (0x1f << AON_GPADC_SCAN_POS_8_SHIFT)
#define AON_GPADC_SCAN_POS_9_SHIFT (15U)
#define AON_GPADC_SCAN_POS_9_MASK (0x1f << AON_GPADC_SCAN_POS_9_SHIFT)
#define AON_GPADC_SCAN_POS_10_SHIFT (20U)
#define AON_GPADC_SCAN_POS_10_MASK (0x1f << AON_GPADC_SCAN_POS_10_SHIFT)
#define AON_GPADC_SCAN_POS_11_SHIFT (25U)
#define AON_GPADC_SCAN_POS_11_MASK (0x1f << AON_GPADC_SCAN_POS_11_SHIFT)
/* 0x920 : adc converation sequence 3 */
#define AON_GPADC_SCAN_NEG_0_SHIFT (0U)
#define AON_GPADC_SCAN_NEG_0_MASK (0x1f << AON_GPADC_SCAN_NEG_0_SHIFT)
#define AON_GPADC_SCAN_NEG_1_SHIFT (5U)
#define AON_GPADC_SCAN_NEG_1_MASK (0x1f << AON_GPADC_SCAN_NEG_1_SHIFT)
#define AON_GPADC_SCAN_NEG_2_SHIFT (10U)
#define AON_GPADC_SCAN_NEG_2_MASK (0x1f << AON_GPADC_SCAN_NEG_2_SHIFT)
#define AON_GPADC_SCAN_NEG_3_SHIFT (15U)
#define AON_GPADC_SCAN_NEG_3_MASK (0x1f << AON_GPADC_SCAN_NEG_3_SHIFT)
#define AON_GPADC_SCAN_NEG_4_SHIFT (20U)
#define AON_GPADC_SCAN_NEG_4_MASK (0x1f << AON_GPADC_SCAN_NEG_4_SHIFT)
#define AON_GPADC_SCAN_NEG_5_SHIFT (25U)
#define AON_GPADC_SCAN_NEG_5_MASK (0x1f << AON_GPADC_SCAN_NEG_5_SHIFT)
/* 0x924 : adc converation sequence 4 */
#define AON_GPADC_SCAN_NEG_6_SHIFT (0U)
#define AON_GPADC_SCAN_NEG_6_MASK (0x1f << AON_GPADC_SCAN_NEG_6_SHIFT)
#define AON_GPADC_SCAN_NEG_7_SHIFT (5U)
#define AON_GPADC_SCAN_NEG_7_MASK (0x1f << AON_GPADC_SCAN_NEG_7_SHIFT)
#define AON_GPADC_SCAN_NEG_8_SHIFT (10U)
#define AON_GPADC_SCAN_NEG_8_MASK (0x1f << AON_GPADC_SCAN_NEG_8_SHIFT)
#define AON_GPADC_SCAN_NEG_9_SHIFT (15U)
#define AON_GPADC_SCAN_NEG_9_MASK (0x1f << AON_GPADC_SCAN_NEG_9_SHIFT)
#define AON_GPADC_SCAN_NEG_10_SHIFT (20U)
#define AON_GPADC_SCAN_NEG_10_MASK (0x1f << AON_GPADC_SCAN_NEG_10_SHIFT)
#define AON_GPADC_SCAN_NEG_11_SHIFT (25U)
#define AON_GPADC_SCAN_NEG_11_MASK (0x1f << AON_GPADC_SCAN_NEG_11_SHIFT)
/* 0x928 : gpadc_reg_status */
#define AON_GPADC_DATA_RDY (1 << 0U)
#define AON_GPADC_RESERVED_SHIFT (16U)
#define AON_GPADC_RESERVED_MASK (0xffff << AON_GPADC_RESERVED_SHIFT)
/* 0x92C : gpadc_reg_isr */
#define AON_GPADC_NEG_SATUR (1 << 0U)
#define AON_GPADC_POS_SATUR (1 << 1U)
#define AON_GPADC_NEG_SATUR_CLR (1 << 4U)
#define AON_GPADC_POS_SATUR_CLR (1 << 5U)
#define AON_GPADC_NEG_SATUR_MASK (1 << 8U)
#define AON_GPADC_POS_SATUR_MASK (1 << 9U)
/* 0x930 : gpadc_reg_result */
#define AON_GPADC_DATA_OUT_SHIFT (0U)
#define AON_GPADC_DATA_OUT_MASK (0x3ffffff << AON_GPADC_DATA_OUT_SHIFT)
/* 0x934 : gpadc_reg_raw_result */
#define AON_GPADC_RAW_DATA_SHIFT (0U)
#define AON_GPADC_RAW_DATA_MASK (0xfff << AON_GPADC_RAW_DATA_SHIFT)
/* 0x938 : gpadc_reg_define */
#define AON_GPADC_OS_CAL_DATA_SHIFT (0U)
#define AON_GPADC_OS_CAL_DATA_MASK (0xffff << AON_GPADC_OS_CAL_DATA_SHIFT)
#endif /* __HARDWARE_ADC_H__ */

2039
include/bl808/aon_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

1351
include/bl808/cci_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

64
include/bl808/cks_reg.h Normal file
View File

@ -0,0 +1,64 @@
/**
******************************************************************************
* @file cks_reg.h
* @version V1.0
* @date 2022-10-25
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __CKS_REG_H__
#define __CKS_REG_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define CKS_CONFIG_OFFSET (0x0)/* cks_config */
#define CKS_DATA_IN_OFFSET (0x4)/* data_in */
#define CKS_OUT_OFFSET (0x8)/* cks_out */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : cks_config */
#define CKS_CR_CKS_CLR (1<<0U)
#define CKS_CR_CKS_BYTE_SWAP (1<<1U)
/* 0x4 : data_in */
#define CKS_DATA_IN_SHIFT (0U)
#define CKS_DATA_IN_MASK (0xff<<CKS_DATA_IN_SHIFT)
/* 0x8 : cks_out */
#define CKS_OUT_SHIFT (0U)
#define CKS_OUT_MASK (0xffff<<CKS_OUT_SHIFT)
#endif /* __CKS_REG_H__ */

340
include/bl808/codec_misc_reg.h Normal file
View File

@ -0,0 +1,340 @@
/**
******************************************************************************
* @file codec_misc_reg.h
* @version V1.0
* @date 2021-05-11
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __CODEC_MISC_REG_H__
#define __CODEC_MISC_REG_H__
#include <linux/types.h>
/* 0x00 : codec_bus_ctrl */
#define CODEC_MISC_CODEC_BUS_CTRL_OFFSET (0x00)
#define CODEC_MISC_RG_PCLK_FORCE_ON CODEC_MISC_RG_PCLK_FORCE_ON
#define CODEC_MISC_RG_PCLK_FORCE_ON_POS (0U)
#define CODEC_MISC_RG_PCLK_FORCE_ON_LEN (16U)
#define CODEC_MISC_RG_PCLK_FORCE_ON_MSK (((1U << CODEC_MISC_RG_PCLK_FORCE_ON_LEN) - 1) << CODEC_MISC_RG_PCLK_FORCE_ON_POS)
#define CODEC_MISC_RG_PCLK_FORCE_ON_UMSK (~(((1U << CODEC_MISC_RG_PCLK_FORCE_ON_LEN) - 1) << CODEC_MISC_RG_PCLK_FORCE_ON_POS))
/* 0x04 : codec_qos_ctrl */
#define CODEC_MISC_CODEC_QOS_CTRL_OFFSET (0x04)
#define CODEC_MISC_REG_JENC_AWQOS CODEC_MISC_REG_JENC_AWQOS
#define CODEC_MISC_REG_JENC_AWQOS_POS (0U)
#define CODEC_MISC_REG_JENC_AWQOS_LEN (1U)
#define CODEC_MISC_REG_JENC_AWQOS_MSK (((1U << CODEC_MISC_REG_JENC_AWQOS_LEN) - 1) << CODEC_MISC_REG_JENC_AWQOS_POS)
#define CODEC_MISC_REG_JENC_AWQOS_UMSK (~(((1U << CODEC_MISC_REG_JENC_AWQOS_LEN) - 1) << CODEC_MISC_REG_JENC_AWQOS_POS))
#define CODEC_MISC_REG_JENC_ARQOS CODEC_MISC_REG_JENC_ARQOS
#define CODEC_MISC_REG_JENC_ARQOS_POS (1U)
#define CODEC_MISC_REG_JENC_ARQOS_LEN (1U)
#define CODEC_MISC_REG_JENC_ARQOS_MSK (((1U << CODEC_MISC_REG_JENC_ARQOS_LEN) - 1) << CODEC_MISC_REG_JENC_ARQOS_POS)
#define CODEC_MISC_REG_JENC_ARQOS_UMSK (~(((1U << CODEC_MISC_REG_JENC_ARQOS_LEN) - 1) << CODEC_MISC_REG_JENC_ARQOS_POS))
#define CODEC_MISC_REG_JDEC_AWQOS CODEC_MISC_REG_JDEC_AWQOS
#define CODEC_MISC_REG_JDEC_AWQOS_POS (2U)
#define CODEC_MISC_REG_JDEC_AWQOS_LEN (1U)
#define CODEC_MISC_REG_JDEC_AWQOS_MSK (((1U << CODEC_MISC_REG_JDEC_AWQOS_LEN) - 1) << CODEC_MISC_REG_JDEC_AWQOS_POS)
#define CODEC_MISC_REG_JDEC_AWQOS_UMSK (~(((1U << CODEC_MISC_REG_JDEC_AWQOS_LEN) - 1) << CODEC_MISC_REG_JDEC_AWQOS_POS))
#define CODEC_MISC_REG_JDEC_ARQOS CODEC_MISC_REG_JDEC_ARQOS
#define CODEC_MISC_REG_JDEC_ARQOS_POS (3U)
#define CODEC_MISC_REG_JDEC_ARQOS_LEN (1U)
#define CODEC_MISC_REG_JDEC_ARQOS_MSK (((1U << CODEC_MISC_REG_JDEC_ARQOS_LEN) - 1) << CODEC_MISC_REG_JDEC_ARQOS_POS)
#define CODEC_MISC_REG_JDEC_ARQOS_UMSK (~(((1U << CODEC_MISC_REG_JDEC_ARQOS_LEN) - 1) << CODEC_MISC_REG_JDEC_ARQOS_POS))
#define CODEC_MISC_REG_VDO0_AWQOS CODEC_MISC_REG_VDO0_AWQOS
#define CODEC_MISC_REG_VDO0_AWQOS_POS (4U)
#define CODEC_MISC_REG_VDO0_AWQOS_LEN (1U)
#define CODEC_MISC_REG_VDO0_AWQOS_MSK (((1U << CODEC_MISC_REG_VDO0_AWQOS_LEN) - 1) << CODEC_MISC_REG_VDO0_AWQOS_POS)
#define CODEC_MISC_REG_VDO0_AWQOS_UMSK (~(((1U << CODEC_MISC_REG_VDO0_AWQOS_LEN) - 1) << CODEC_MISC_REG_VDO0_AWQOS_POS))
#define CODEC_MISC_REG_VDO0_ARQOS CODEC_MISC_REG_VDO0_ARQOS
#define CODEC_MISC_REG_VDO0_ARQOS_POS (5U)
#define CODEC_MISC_REG_VDO0_ARQOS_LEN (1U)
#define CODEC_MISC_REG_VDO0_ARQOS_MSK (((1U << CODEC_MISC_REG_VDO0_ARQOS_LEN) - 1) << CODEC_MISC_REG_VDO0_ARQOS_POS)
#define CODEC_MISC_REG_VDO0_ARQOS_UMSK (~(((1U << CODEC_MISC_REG_VDO0_ARQOS_LEN) - 1) << CODEC_MISC_REG_VDO0_ARQOS_POS))
#define CODEC_MISC_REG_VDO1_AWQOS CODEC_MISC_REG_VDO1_AWQOS
#define CODEC_MISC_REG_VDO1_AWQOS_POS (6U)
#define CODEC_MISC_REG_VDO1_AWQOS_LEN (1U)
#define CODEC_MISC_REG_VDO1_AWQOS_MSK (((1U << CODEC_MISC_REG_VDO1_AWQOS_LEN) - 1) << CODEC_MISC_REG_VDO1_AWQOS_POS)
#define CODEC_MISC_REG_VDO1_AWQOS_UMSK (~(((1U << CODEC_MISC_REG_VDO1_AWQOS_LEN) - 1) << CODEC_MISC_REG_VDO1_AWQOS_POS))
#define CODEC_MISC_REG_VDO1_ARQOS CODEC_MISC_REG_VDO1_ARQOS
#define CODEC_MISC_REG_VDO1_ARQOS_POS (7U)
#define CODEC_MISC_REG_VDO1_ARQOS_LEN (1U)
#define CODEC_MISC_REG_VDO1_ARQOS_MSK (((1U << CODEC_MISC_REG_VDO1_ARQOS_LEN) - 1) << CODEC_MISC_REG_VDO1_ARQOS_POS)
#define CODEC_MISC_REG_VDO1_ARQOS_UMSK (~(((1U << CODEC_MISC_REG_VDO1_ARQOS_LEN) - 1) << CODEC_MISC_REG_VDO1_ARQOS_POS))
#define CODEC_MISC_REG_REF_AWQOS CODEC_MISC_REG_REF_AWQOS
#define CODEC_MISC_REG_REF_AWQOS_POS (8U)
#define CODEC_MISC_REG_REF_AWQOS_LEN (1U)
#define CODEC_MISC_REG_REF_AWQOS_MSK (((1U << CODEC_MISC_REG_REF_AWQOS_LEN) - 1) << CODEC_MISC_REG_REF_AWQOS_POS)
#define CODEC_MISC_REG_REF_AWQOS_UMSK (~(((1U << CODEC_MISC_REG_REF_AWQOS_LEN) - 1) << CODEC_MISC_REG_REF_AWQOS_POS))
#define CODEC_MISC_REG_REF_ARQOS CODEC_MISC_REG_REF_ARQOS
#define CODEC_MISC_REG_REF_ARQOS_POS (9U)
#define CODEC_MISC_REG_REF_ARQOS_LEN (1U)
#define CODEC_MISC_REG_REF_ARQOS_MSK (((1U << CODEC_MISC_REG_REF_ARQOS_LEN) - 1) << CODEC_MISC_REG_REF_ARQOS_POS)
#define CODEC_MISC_REG_REF_ARQOS_UMSK (~(((1U << CODEC_MISC_REG_REF_ARQOS_LEN) - 1) << CODEC_MISC_REG_REF_ARQOS_POS))
#define CODEC_MISC_REG_CNN_AWQOS CODEC_MISC_REG_CNN_AWQOS
#define CODEC_MISC_REG_CNN_AWQOS_POS (10U)
#define CODEC_MISC_REG_CNN_AWQOS_LEN (1U)
#define CODEC_MISC_REG_CNN_AWQOS_MSK (((1U << CODEC_MISC_REG_CNN_AWQOS_LEN) - 1) << CODEC_MISC_REG_CNN_AWQOS_POS)
#define CODEC_MISC_REG_CNN_AWQOS_UMSK (~(((1U << CODEC_MISC_REG_CNN_AWQOS_LEN) - 1) << CODEC_MISC_REG_CNN_AWQOS_POS))
#define CODEC_MISC_REG_CNN_ARQOS CODEC_MISC_REG_CNN_ARQOS
#define CODEC_MISC_REG_CNN_ARQOS_POS (11U)
#define CODEC_MISC_REG_CNN_ARQOS_LEN (1U)
#define CODEC_MISC_REG_CNN_ARQOS_MSK (((1U << CODEC_MISC_REG_CNN_ARQOS_LEN) - 1) << CODEC_MISC_REG_CNN_ARQOS_POS)
#define CODEC_MISC_REG_CNN_ARQOS_UMSK (~(((1U << CODEC_MISC_REG_CNN_ARQOS_LEN) - 1) << CODEC_MISC_REG_CNN_ARQOS_POS))
/* 0x08 : codec_bus_thre */
#define CODEC_MISC_CODEC_BUS_THRE_OFFSET (0x08)
#define CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM
#define CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_POS (0U)
#define CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_LEN (2U)
#define CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_MSK (((1U << CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_POS)
#define CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_UMSK (~(((1U << CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_BLAI2SYSRAM_POS))
#define CODEC_MISC_REG_X_WTHRE_BLAI2EXT CODEC_MISC_REG_X_WTHRE_BLAI2EXT
#define CODEC_MISC_REG_X_WTHRE_BLAI2EXT_POS (2U)
#define CODEC_MISC_REG_X_WTHRE_BLAI2EXT_LEN (2U)
#define CODEC_MISC_REG_X_WTHRE_BLAI2EXT_MSK (((1U << CODEC_MISC_REG_X_WTHRE_BLAI2EXT_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_BLAI2EXT_POS)
#define CODEC_MISC_REG_X_WTHRE_BLAI2EXT_UMSK (~(((1U << CODEC_MISC_REG_X_WTHRE_BLAI2EXT_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_BLAI2EXT_POS))
#define CODEC_MISC_REG_X_WTHRE_VDO2PB CODEC_MISC_REG_X_WTHRE_VDO2PB
#define CODEC_MISC_REG_X_WTHRE_VDO2PB_POS (4U)
#define CODEC_MISC_REG_X_WTHRE_VDO2PB_LEN (2U)
#define CODEC_MISC_REG_X_WTHRE_VDO2PB_MSK (((1U << CODEC_MISC_REG_X_WTHRE_VDO2PB_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_VDO2PB_POS)
#define CODEC_MISC_REG_X_WTHRE_VDO2PB_UMSK (~(((1U << CODEC_MISC_REG_X_WTHRE_VDO2PB_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_VDO2PB_POS))
#define CODEC_MISC_REG_X_WTHRE_VDO2PA CODEC_MISC_REG_X_WTHRE_VDO2PA
#define CODEC_MISC_REG_X_WTHRE_VDO2PA_POS (6U)
#define CODEC_MISC_REG_X_WTHRE_VDO2PA_LEN (2U)
#define CODEC_MISC_REG_X_WTHRE_VDO2PA_MSK (((1U << CODEC_MISC_REG_X_WTHRE_VDO2PA_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_VDO2PA_POS)
#define CODEC_MISC_REG_X_WTHRE_VDO2PA_UMSK (~(((1U << CODEC_MISC_REG_X_WTHRE_VDO2PA_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_VDO2PA_POS))
#define CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM
#define CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_POS (8U)
#define CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_LEN (2U)
#define CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_MSK (((1U << CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_POS)
#define CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_UMSK (~(((1U << CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_LEN) - 1) << CODEC_MISC_REG_X_WTHRE_VDO2SYSRAM_POS))
/* 0x10 : codec_bus_dec_err */
#define CODEC_MISC_CODEC_BUS_DEC_ERR_OFFSET (0x10)
#define CODEC_MISC_REG_DEC_ERR_CLR CODEC_MISC_REG_DEC_ERR_CLR
#define CODEC_MISC_REG_DEC_ERR_CLR_POS (0U)
#define CODEC_MISC_REG_DEC_ERR_CLR_LEN (1U)
#define CODEC_MISC_REG_DEC_ERR_CLR_MSK (((1U << CODEC_MISC_REG_DEC_ERR_CLR_LEN) - 1) << CODEC_MISC_REG_DEC_ERR_CLR_POS)
#define CODEC_MISC_REG_DEC_ERR_CLR_UMSK (~(((1U << CODEC_MISC_REG_DEC_ERR_CLR_LEN) - 1) << CODEC_MISC_REG_DEC_ERR_CLR_POS))
#define CODEC_MISC_REG_DEC_ERR_LATCH_LAST CODEC_MISC_REG_DEC_ERR_LATCH_LAST
#define CODEC_MISC_REG_DEC_ERR_LATCH_LAST_POS (1U)
#define CODEC_MISC_REG_DEC_ERR_LATCH_LAST_LEN (1U)
#define CODEC_MISC_REG_DEC_ERR_LATCH_LAST_MSK (((1U << CODEC_MISC_REG_DEC_ERR_LATCH_LAST_LEN) - 1) << CODEC_MISC_REG_DEC_ERR_LATCH_LAST_POS)
#define CODEC_MISC_REG_DEC_ERR_LATCH_LAST_UMSK (~(((1U << CODEC_MISC_REG_DEC_ERR_LATCH_LAST_LEN) - 1) << CODEC_MISC_REG_DEC_ERR_LATCH_LAST_POS))
#define CODEC_MISC_CODEC_HS_DEC_ERR_LAT CODEC_MISC_CODEC_HS_DEC_ERR_LAT
#define CODEC_MISC_CODEC_HS_DEC_ERR_LAT_POS (8U)
#define CODEC_MISC_CODEC_HS_DEC_ERR_LAT_LEN (1U)
#define CODEC_MISC_CODEC_HS_DEC_ERR_LAT_MSK (((1U << CODEC_MISC_CODEC_HS_DEC_ERR_LAT_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_LAT_POS)
#define CODEC_MISC_CODEC_HS_DEC_ERR_LAT_UMSK (~(((1U << CODEC_MISC_CODEC_HS_DEC_ERR_LAT_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_LAT_POS))
#define CODEC_MISC_CODEC_HS_DEC_ERR_WRITE CODEC_MISC_CODEC_HS_DEC_ERR_WRITE
#define CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_POS (9U)
#define CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_LEN (1U)
#define CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_MSK (((1U << CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_POS)
#define CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_UMSK (~(((1U << CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_WRITE_POS))
#define CODEC_MISC_CODEC_HS_DEC_ERR_SRC CODEC_MISC_CODEC_HS_DEC_ERR_SRC
#define CODEC_MISC_CODEC_HS_DEC_ERR_SRC_POS (12U)
#define CODEC_MISC_CODEC_HS_DEC_ERR_SRC_LEN (2U)
#define CODEC_MISC_CODEC_HS_DEC_ERR_SRC_MSK (((1U << CODEC_MISC_CODEC_HS_DEC_ERR_SRC_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_SRC_POS)
#define CODEC_MISC_CODEC_HS_DEC_ERR_SRC_UMSK (~(((1U << CODEC_MISC_CODEC_HS_DEC_ERR_SRC_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_SRC_POS))
#define CODEC_MISC_CODEC_HS_DEC_ERR_ID CODEC_MISC_CODEC_HS_DEC_ERR_ID
#define CODEC_MISC_CODEC_HS_DEC_ERR_ID_POS (16U)
#define CODEC_MISC_CODEC_HS_DEC_ERR_ID_LEN (1U)
#define CODEC_MISC_CODEC_HS_DEC_ERR_ID_MSK (((1U << CODEC_MISC_CODEC_HS_DEC_ERR_ID_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_ID_POS)
#define CODEC_MISC_CODEC_HS_DEC_ERR_ID_UMSK (~(((1U << CODEC_MISC_CODEC_HS_DEC_ERR_ID_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_ID_POS))
/* 0x14 : codec_bus_dec_err_addr */
#define CODEC_MISC_CODEC_BUS_DEC_ERR_ADDR_OFFSET (0x14)
#define CODEC_MISC_CODEC_HS_DEC_ERR_ADDR CODEC_MISC_CODEC_HS_DEC_ERR_ADDR
#define CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_POS (0U)
#define CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_LEN (32U)
#define CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_MSK (((1U << CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_POS)
#define CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_UMSK (~(((1U << CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_LEN) - 1) << CODEC_MISC_CODEC_HS_DEC_ERR_ADDR_POS))
/* 0x20 : blai_lmtr_rd */
#define CODEC_MISC_BLAI_LMTR_RD_OFFSET (0x20)
#define CODEC_MISC_REG_BLAI_RCMD_CNT CODEC_MISC_REG_BLAI_RCMD_CNT
#define CODEC_MISC_REG_BLAI_RCMD_CNT_POS (0U)
#define CODEC_MISC_REG_BLAI_RCMD_CNT_LEN (16U)
#define CODEC_MISC_REG_BLAI_RCMD_CNT_MSK (((1U << CODEC_MISC_REG_BLAI_RCMD_CNT_LEN) - 1) << CODEC_MISC_REG_BLAI_RCMD_CNT_POS)
#define CODEC_MISC_REG_BLAI_RCMD_CNT_UMSK (~(((1U << CODEC_MISC_REG_BLAI_RCMD_CNT_LEN) - 1) << CODEC_MISC_REG_BLAI_RCMD_CNT_POS))
#define CODEC_MISC_REG_BLAI_RCMD_MODE CODEC_MISC_REG_BLAI_RCMD_MODE
#define CODEC_MISC_REG_BLAI_RCMD_MODE_POS (31U)
#define CODEC_MISC_REG_BLAI_RCMD_MODE_LEN (1U)
#define CODEC_MISC_REG_BLAI_RCMD_MODE_MSK (((1U << CODEC_MISC_REG_BLAI_RCMD_MODE_LEN) - 1) << CODEC_MISC_REG_BLAI_RCMD_MODE_POS)
#define CODEC_MISC_REG_BLAI_RCMD_MODE_UMSK (~(((1U << CODEC_MISC_REG_BLAI_RCMD_MODE_LEN) - 1) << CODEC_MISC_REG_BLAI_RCMD_MODE_POS))
/* 0x24 : blai_lmtr_wr */
#define CODEC_MISC_BLAI_LMTR_WR_OFFSET (0x24)
#define CODEC_MISC_REG_BLAI_WCMD_CNT CODEC_MISC_REG_BLAI_WCMD_CNT
#define CODEC_MISC_REG_BLAI_WCMD_CNT_POS (0U)
#define CODEC_MISC_REG_BLAI_WCMD_CNT_LEN (16U)
#define CODEC_MISC_REG_BLAI_WCMD_CNT_MSK (((1U << CODEC_MISC_REG_BLAI_WCMD_CNT_LEN) - 1) << CODEC_MISC_REG_BLAI_WCMD_CNT_POS)
#define CODEC_MISC_REG_BLAI_WCMD_CNT_UMSK (~(((1U << CODEC_MISC_REG_BLAI_WCMD_CNT_LEN) - 1) << CODEC_MISC_REG_BLAI_WCMD_CNT_POS))
#define CODEC_MISC_REG_BLAI_WCMD_MODE CODEC_MISC_REG_BLAI_WCMD_MODE
#define CODEC_MISC_REG_BLAI_WCMD_MODE_POS (31U)
#define CODEC_MISC_REG_BLAI_WCMD_MODE_LEN (1U)
#define CODEC_MISC_REG_BLAI_WCMD_MODE_MSK (((1U << CODEC_MISC_REG_BLAI_WCMD_MODE_LEN) - 1) << CODEC_MISC_REG_BLAI_WCMD_MODE_POS)
#define CODEC_MISC_REG_BLAI_WCMD_MODE_UMSK (~(((1U << CODEC_MISC_REG_BLAI_WCMD_MODE_LEN) - 1) << CODEC_MISC_REG_BLAI_WCMD_MODE_POS))
/* 0x28 : id_selection */
#define CODEC_MISC_ID_SELECTION_OFFSET (0x28)
#define CODEC_MISC_RG_JENC_ID_SEL CODEC_MISC_RG_JENC_ID_SEL
#define CODEC_MISC_RG_JENC_ID_SEL_POS (0U)
#define CODEC_MISC_RG_JENC_ID_SEL_LEN (1U)
#define CODEC_MISC_RG_JENC_ID_SEL_MSK (((1U << CODEC_MISC_RG_JENC_ID_SEL_LEN) - 1) << CODEC_MISC_RG_JENC_ID_SEL_POS)
#define CODEC_MISC_RG_JENC_ID_SEL_UMSK (~(((1U << CODEC_MISC_RG_JENC_ID_SEL_LEN) - 1) << CODEC_MISC_RG_JENC_ID_SEL_POS))
/* 0xFC : CODEC_MISC_Dummy */
#define CODEC_MISC_DUMMY_OFFSET (0xFC)
#define CODEC_MISC_DUMMY_REG CODEC_MISC_DUMMY_REG
#define CODEC_MISC_DUMMY_REG_POS (0U)
#define CODEC_MISC_DUMMY_REG_LEN (32U)
#define CODEC_MISC_DUMMY_REG_MSK (((1U << CODEC_MISC_DUMMY_REG_LEN) - 1) << CODEC_MISC_DUMMY_REG_POS)
#define CODEC_MISC_DUMMY_REG_UMSK (~(((1U << CODEC_MISC_DUMMY_REG_LEN) - 1) << CODEC_MISC_DUMMY_REG_POS))
struct codec_misc_reg {
/* 0x00 : codec_bus_ctrl */
union {
struct {
uint32_t rg_pclk_force_on : 16; /* [15: 0], r/w, 0xffff */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} codec_bus_ctrl;
/* 0x04 : codec_qos_ctrl */
union {
struct {
uint32_t reg_jenc_awqos : 1; /* [ 0], r/w, 0x0 */
uint32_t reg_jenc_arqos : 1; /* [ 1], r/w, 0x0 */
uint32_t reg_jdec_awqos : 1; /* [ 2], r/w, 0x0 */
uint32_t reg_jdec_arqos : 1; /* [ 3], r/w, 0x0 */
uint32_t reg_vdo0_awqos : 1; /* [ 4], r/w, 0x0 */
uint32_t reg_vdo0_arqos : 1; /* [ 5], r/w, 0x0 */
uint32_t reg_vdo1_awqos : 1; /* [ 6], r/w, 0x0 */
uint32_t reg_vdo1_arqos : 1; /* [ 7], r/w, 0x0 */
uint32_t reg_ref_awqos : 1; /* [ 8], r/w, 0x0 */
uint32_t reg_ref_arqos : 1; /* [ 9], r/w, 0x0 */
uint32_t reg_cnn_awqos : 1; /* [ 10], r/w, 0x0 */
uint32_t reg_cnn_arqos : 1; /* [ 11], r/w, 0x0 */
uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
} BF;
uint32_t WORD;
} codec_qos_ctrl;
/* 0x08 : codec_bus_thre */
union {
struct {
uint32_t reg_x_wthre_blai2sysram : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t reg_x_wthre_blai2ext : 2; /* [ 3: 2], r/w, 0x0 */
uint32_t reg_x_wthre_vdo2pb : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t reg_x_wthre_vdo2pa : 2; /* [ 7: 6], r/w, 0x0 */
uint32_t reg_x_wthre_vdo2sysram : 2; /* [ 9: 8], r/w, 0x0 */
uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
} BF;
uint32_t WORD;
} codec_bus_thre;
/* 0xc reserved */
uint8_t RESERVED0xc[20];
/* 0x10 : codec_bus_dec_err */
union {
struct
{
uint32_t reg_dec_err_clr : 1; /* [ 0], r/w, 0x0 */
uint32_t reg_dec_err_latch_last : 1; /* [ 1], r/w, 0x0 */
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
uint32_t codec_hs_dec_err_lat : 1; /* [ 8], r, 0x0 */
uint32_t codec_hs_dec_err_write : 1; /* [ 9], r, 0x0 */
uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */
uint32_t codec_hs_dec_err_src : 2; /* [13:12], r, 0x0 */
uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
uint32_t codec_hs_dec_err_id : 1; /* [ 16], r, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
} BF;
uint32_t WORD;
} codec_bus_dec_err;
/* 0x14 : codec_bus_dec_err_addr */
union {
struct
{
uint32_t codec_hs_dec_err_addr : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} codec_bus_dec_err_addr;
/* 0x18 reserved */
uint8_t RESERVED0x18[8];
/* 0x20 : blai_lmtr_rd */
union {
struct {
uint32_t reg_blai_rcmd_cnt : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_30 : 15; /* [30:16], rsvd, 0x0 */
uint32_t reg_blai_rcmd_mode : 1; /* [ 31], r/w, 0x0 */
} BF;
uint32_t WORD;
} blai_lmtr_rd;
/* 0x24 : blai_lmtr_wr */
union {
struct {
uint32_t reg_blai_wcmd_cnt : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_30 : 15; /* [30:16], rsvd, 0x0 */
uint32_t reg_blai_wcmd_mode : 1; /* [ 31], r/w, 0x0 */
} BF;
uint32_t WORD;
} blai_lmtr_wr;
/* 0x28 : id_selection */
union {
struct {
uint32_t rg_jenc_id_sel : 1; /* [ 0], r/w, 0x0 */
uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
} BF;
uint32_t WORD;
} id_selection;
/* 0x2c reserved */
uint8_t RESERVED0x2c[208];
/* 0xFC : CODEC_MISC_Dummy */
union {
struct {
uint32_t dummy_reg : 32; /* [31: 0], r/w, 0xffff0000 */
} BF;
uint32_t WORD;
} CODEC_MISC_Dummy;
};
#endif /* __CODEC_MISC_REG_H__ */

121
include/bl808/dac_reg.h Normal file
View File

@ -0,0 +1,121 @@
/**
******************************************************************************
* @file dac_reg.h
* @version V1.0
* @date 2022-08-05
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_DAC_H__
#define __HARDWARE_DAC_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
/* gpip base */
#define GPIP_GPDAC_CONFIG_OFFSET (0x40) /* gpdac_config */
#define GPIP_GPDAC_DMA_CONFIG_OFFSET (0x44) /* gpdac_dma_config */
#define GPIP_GPDAC_DMA_WDATA_OFFSET (0x48) /* gpdac_dma_wdata */
#define GPIP_GPDAC_TX_FIFO_STATUS_OFFSET (0x4C) /* gpdac_tx_fifo_status */
/* glb base */
#define GLB_GPDAC_CTRL_OFFSET (0x120) /* gpdac_ctrl */
#define GLB_GPDAC_ACTRL_OFFSET (0x124) /* gpdac_actrl */
#define GLB_GPDAC_BCTRL_OFFSET (0x128) /* gpdac_bctrl */
#define GLB_GPDAC_DATA_OFFSET (0x12C) /* gpdac_data */
/* Register Bitfield definitions *****************************************************/
/* 0x40 : gpdac_config */
#define GPIP_GPDAC_EN (1 << 0U)
#define GPIP_GPDAC_MODE_SHIFT (8U)
#define GPIP_GPDAC_MODE_MASK (0x7 << GPIP_GPDAC_MODE_SHIFT)
#define GPIP_GPDAC_CH_A_SEL_SHIFT (16U)
#define GPIP_GPDAC_CH_A_SEL_MASK (0xf << GPIP_GPDAC_CH_A_SEL_SHIFT)
#define GPIP_GPDAC_CH_B_SEL_SHIFT (20U)
#define GPIP_GPDAC_CH_B_SEL_MASK (0xf << GPIP_GPDAC_CH_B_SEL_SHIFT)
/* 0x44 : gpdac_dma_config */
#define GPIP_GPDAC_DMA_TX_EN (1 << 0U)
#define GPIP_GPDAC_DMA_INV_MSB (1 << 1U)
#define GPIP_GPDAC_DMA_FORMAT_SHIFT (4U)
#define GPIP_GPDAC_DMA_FORMAT_MASK (0x3 << GPIP_GPDAC_DMA_FORMAT_SHIFT)
/* 0x48 : gpdac_dma_wdata */
#define GPIP_GPDAC_DMA_WDATA_SHIFT (0U)
#define GPIP_GPDAC_DMA_WDATA_MASK (0xffffffff << GPIP_GPDAC_DMA_WDATA_SHIFT)
/* 0x4C : gpdac_tx_fifo_status */
#define GPIP_TX_FIFO_EMPTY (1 << 0U)
#define GPIP_TX_FIFO_FULL (1 << 1U)
#define GPIP_TX_CS_SHIFT (2U)
#define GPIP_TX_CS_MASK (0x3 << GPIP_TX_CS_SHIFT)
#define GPIP_TXFIFORDPTR_SHIFT (4U)
#define GPIP_TXFIFORDPTR_MASK (0x7 << GPIP_TXFIFORDPTR_SHIFT)
#define GPIP_TXFIFOWRPTR_SHIFT (8U)
#define GPIP_TXFIFOWRPTR_MASK (0x3 << GPIP_TXFIFOWRPTR_SHIFT)
/* 0x308 : gpdac_ctrl */
#define GLB_GPDACA_RSTN_ANA (1 << 0U)
#define GLB_GPDACB_RSTN_ANA (1 << 1U)
#define GLB_GPDAC_TEST_EN (1 << 7U)
#define GLB_GPDAC_REF_SEL (1 << 8U)
#define GLB_GPDAC_TEST_SEL_SHIFT (9U)
#define GLB_GPDAC_TEST_SEL_MASK (0x7 << GLB_GPDAC_TEST_SEL_SHIFT)
#define GLB_GPDAC_ANA_CLK_SEL (1 << 12U)
#define GLB_GPDAC_DAT_CHA_SEL (1 << 13U)
#define GLB_GPDAC_DAT_CHB_SEL (1 << 14U)
#define GLB_GPDAC_RESERVED_SHIFT (24U)
#define GLB_GPDAC_RESERVED_MASK (0xff << GLB_GPDAC_RESERVED_SHIFT)
/* 0x30C : gpdac_actrl */
#define GLB_GPDAC_A_EN (1 << 0U)
#define GLB_GPDAC_IOA_EN (1 << 1U)
#define GLB_GPDAC_A_RNG_SHIFT (18U)
#define GLB_GPDAC_A_RNG_MASK (0x3 << GLB_GPDAC_A_RNG_SHIFT)
#define GLB_GPDAC_A_OUTMUX_SHIFT (20U)
#define GLB_GPDAC_A_OUTMUX_MASK (0x7 << GLB_GPDAC_A_OUTMUX_SHIFT)
/* 0x310 : gpdac_bctrl */
#define GLB_GPDAC_B_EN (1 << 0U)
#define GLB_GPDAC_IOB_EN (1 << 1U)
#define GLB_GPDAC_B_RNG_SHIFT (18U)
#define GLB_GPDAC_B_RNG_MASK (0x3 << GLB_GPDAC_B_RNG_SHIFT)
#define GLB_GPDAC_B_OUTMUX_SHIFT (20U)
#define GLB_GPDAC_B_OUTMUX_MASK (0x7 << GLB_GPDAC_B_OUTMUX_SHIFT)
/* 0x314 : gpdac_data */
#define GLB_GPDAC_B_DATA_SHIFT (0U)
#define GLB_GPDAC_B_DATA_MASK (0x3ff << GLB_GPDAC_B_DATA_SHIFT)
#define GLB_GPDAC_A_DATA_SHIFT (16U)
#define GLB_GPDAC_A_DATA_MASK (0x3ff << GLB_GPDAC_A_DATA_SHIFT)
#endif /* __HARDWARE_DAC_H__ */

173
include/bl808/dma_reg.h Normal file
View File

@ -0,0 +1,173 @@
/**
******************************************************************************
* @file dma_reg.h
* @version V1.0
* @date 2022-06-20
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_DMA_H__
#define __HARDWARE_DMA_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define DMA_INTSTATUS_OFFSET (0x0) /* DMA_IntStatus */
#define DMA_INTTCSTATUS_OFFSET (0x4) /* DMA_IntTCStatus */
#define DMA_INTTCCLEAR_OFFSET (0x8) /* DMA_IntTCClear */
#define DMA_INTERRORSTATUS_OFFSET (0xC) /* DMA_IntErrorStatus */
#define DMA_INTERRCLR_OFFSET (0x10) /* DMA_IntErrClr */
#define DMA_RAWINTTCSTATUS_OFFSET (0x14) /* DMA_RawIntTCStatus */
#define DMA_RAWINTERRORSTATUS_OFFSET (0x18) /* DMA_RawIntErrorStatus */
#define DMA_ENBLDCHNS_OFFSET (0x1C) /* DMA_EnbldChns */
#define DMA_SOFTBREQ_OFFSET (0x20) /* DMA_SoftBReq */
#define DMA_SOFTSREQ_OFFSET (0x24) /* DMA_SoftSReq */
#define DMA_SOFTLBREQ_OFFSET (0x28) /* DMA_SoftLBReq */
#define DMA_SOFTLSREQ_OFFSET (0x2C) /* DMA_SoftLSReq */
#define DMA_TOP_CONFIG_OFFSET (0x30) /* DMA_Top_Config */
#define DMA_SYNC_OFFSET (0x34) /* DMA_Sync */
#define DMA_CxSRCADDR_OFFSET (0x00) /* DMA_CxSrcAddr */
#define DMA_CxDSTADDR_OFFSET (0x04) /* DMA_CxDstAddr */
#define DMA_CxLLI_OFFSET (0x08) /* DMA_CxLLI */
#define DMA_CxCONTROL_OFFSET (0x0C) /* DMA_CxControl */
#define DMA_CxCONFIG_OFFSET (0x10) /* DMA_CxConfig */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : DMA_IntStatus */
#define DMA_INTSTATUS_SHIFT (0U)
#define DMA_INTSTATUS_MASK (0xff << DMA_INTSTATUS_SHIFT)
/* 0x4 : DMA_IntTCStatus */
#define DMA_INTTCSTATUS_SHIFT (0U)
#define DMA_INTTCSTATUS_MASK (0xff << DMA_INTTCSTATUS_SHIFT)
/* 0x8 : DMA_IntTCClear */
#define DMA_INTTCCLEAR_SHIFT (0U)
#define DMA_INTTCCLEAR_MASK (0xff << DMA_INTTCCLEAR_SHIFT)
/* 0xC : DMA_IntErrorStatus */
#define DMA_INTERRORSTATUS_SHIFT (0U)
#define DMA_INTERRORSTATUS_MASK (0xff << DMA_INTERRORSTATUS_SHIFT)
/* 0x10 : DMA_IntErrClr */
#define DMA_INTERRCLR_SHIFT (0U)
#define DMA_INTERRCLR_MASK (0xff << DMA_INTERRCLR_SHIFT)
/* 0x14 : DMA_RawIntTCStatus */
#define DMA_RAWINTTCSTATUS_SHIFT (0U)
#define DMA_RAWINTTCSTATUS_MASK (0xff << DMA_RAWINTTCSTATUS_SHIFT)
/* 0x18 : DMA_RawIntErrorStatus */
#define DMA_RAWINTERRORSTATUS_SHIFT (0U)
#define DMA_RAWINTERRORSTATUS_MASK (0xff << DMA_RAWINTERRORSTATUS_SHIFT)
/* 0x1C : DMA_EnbldChns */
#define DMA_ENABLEDCHANNELS_SHIFT (0U)
#define DMA_ENABLEDCHANNELS_MASK (0xff << DMA_ENABLEDCHANNELS_SHIFT)
/* 0x20 : DMA_SoftBReq */
#define DMA_SOFTBREQ_SHIFT (0U)
#define DMA_SOFTBREQ_MASK (0xffffffff << DMA_SOFTBREQ_SHIFT)
/* 0x24 : DMA_SoftSReq */
#define DMA_SOFTSREQ_SHIFT (0U)
#define DMA_SOFTSREQ_MASK (0xffffffff << DMA_SOFTSREQ_SHIFT)
/* 0x28 : DMA_SoftLBReq */
#define DMA_SOFTLBREQ_SHIFT (0U)
#define DMA_SOFTLBREQ_MASK (0xffffffff << DMA_SOFTLBREQ_SHIFT)
/* 0x2C : DMA_SoftLSReq */
#define DMA_SOFTLSREQ_SHIFT (0U)
#define DMA_SOFTLSREQ_MASK (0xffffffff << DMA_SOFTLSREQ_SHIFT)
/* 0x30 : DMA_Top_Config */
#define DMA_E (1 << 0U)
#define DMA_M (1 << 1U)
/* 0x34 : DMA_Sync */
#define DMA_SYNC_SHIFT (0U)
#define DMA_SYNC_MASK (0xffffffff << DMA_SYNC_SHIFT)
/* 0x100 : DMA_CxSrcAddr */
#define DMA_SRCADDR_SHIFT (0U)
#define DMA_SRCADDR_MASK (0xffffffff << DMA_SRCADDR_SHIFT)
/* 0x104 : DMA_CxDstAddr */
#define DMA_DSTADDR_SHIFT (0U)
#define DMA_DSTADDR_MASK (0xffffffff << DMA_DSTADDR_SHIFT)
/* 0x108 : DMA_CxLLI */
#define DMA_LLI_SHIFT (0U)
#define DMA_LLI_MASK (0xffffffff << DMA_LLI_SHIFT)
/* 0x10C : DMA_CxControl */
#define DMA_TRANSFERSIZE_SHIFT (0U)
#define DMA_TRANSFERSIZE_MASK (0xfff << DMA_TRANSFERSIZE_SHIFT)
#define DMA_SBSIZE_SHIFT (12U)
#define DMA_SBSIZE_MASK (0x3 << DMA_SBSIZE_SHIFT)
#define DMA_DST_MIN_MODE (1 << 14U)
#define DMA_DBSIZE_SHIFT (15U)
#define DMA_DBSIZE_MASK (0x3 << DMA_DBSIZE_SHIFT)
#define DMA_DST_ADD_MODE (1 << 17U)
#define DMA_SWIDTH_SHIFT (18U)
#define DMA_SWIDTH_MASK (0x3 << DMA_SWIDTH_SHIFT)
#define DMA_DWIDTH_SHIFT (21U)
#define DMA_DWIDTH_MASK (0x3 << DMA_DWIDTH_SHIFT)
#define DMA_FIX_CNT_SHIFT (23U)
#define DMA_FIX_CNT_MASK (0x7 << DMA_FIX_CNT_SHIFT)
#define DMA_SI (1 << 26U)
#define DMA_DI (1 << 27U)
#define DMA_PROT_SHIFT (28U)
#define DMA_PROT_MASK (0x7 << DMA_PROT_SHIFT)
#define DMA_I (1 << 31U)
/* 0x110 : DMA_CxConfig */
#define DMA_E (1 << 0U)
#define DMA_SRCPERIPHERAL_SHIFT (1U)
#define DMA_SRCPERIPHERAL_MASK (0x1f << DMA_SRCPERIPHERAL_SHIFT)
#define DMA_DSTPERIPHERAL_SHIFT (6U)
#define DMA_DSTPERIPHERAL_MASK (0x1f << DMA_DSTPERIPHERAL_SHIFT)
#define DMA_FLOWCNTRL_SHIFT (11U)
#define DMA_FLOWCNTRL_MASK (0x7 << DMA_FLOWCNTRL_SHIFT)
#define DMA_IE (1 << 14U)
#define DMA_ITC (1 << 15U)
#define DMA_L (1 << 16U)
#define DMA_A (1 << 17U)
#define DMA_H (1 << 18U)
#define DMA_LLICOUNTER_SHIFT (20U)
#define DMA_LLICOUNTER_MASK (0x3ff << DMA_LLICOUNTER_SHIFT)
#endif /* __HARDWARE_DMA_H__ */

503
include/bl808/dtsrc_reg.h Normal file
View File

@ -0,0 +1,503 @@
/**
******************************************************************************
* @file dtsrc_reg.h
* @version V1.0
* @date 2021-09-10
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __DTSRC_REG_H__
#define __DTSRC_REG_H__
#include <linux/types.h>
/* 0x0 : config */
#define DTSRC_CONFIG_OFFSET (0x0)
#define DTSRC_CR_ENABLE DTSRC_CR_ENABLE
#define DTSRC_CR_ENABLE_POS (0U)
#define DTSRC_CR_ENABLE_LEN (1U)
#define DTSRC_CR_ENABLE_MSK (((1U << DTSRC_CR_ENABLE_LEN) - 1) << DTSRC_CR_ENABLE_POS)
#define DTSRC_CR_ENABLE_UMSK (~(((1U << DTSRC_CR_ENABLE_LEN) - 1) << DTSRC_CR_ENABLE_POS))
#define DTSRC_CR_AXI_EN DTSRC_CR_AXI_EN
#define DTSRC_CR_AXI_EN_POS (1U)
#define DTSRC_CR_AXI_EN_LEN (1U)
#define DTSRC_CR_AXI_EN_MSK (((1U << DTSRC_CR_AXI_EN_LEN) - 1) << DTSRC_CR_AXI_EN_POS)
#define DTSRC_CR_AXI_EN_UMSK (~(((1U << DTSRC_CR_AXI_EN_LEN) - 1) << DTSRC_CR_AXI_EN_POS))
#define DTSRC_CR_MODE_CEA_861 DTSRC_CR_MODE_CEA_861
#define DTSRC_CR_MODE_CEA_861_POS (2U)
#define DTSRC_CR_MODE_CEA_861_LEN (1U)
#define DTSRC_CR_MODE_CEA_861_MSK (((1U << DTSRC_CR_MODE_CEA_861_LEN) - 1) << DTSRC_CR_MODE_CEA_861_POS)
#define DTSRC_CR_MODE_CEA_861_UMSK (~(((1U << DTSRC_CR_MODE_CEA_861_LEN) - 1) << DTSRC_CR_MODE_CEA_861_POS))
#define DTSRC_CR_SNSR_EN DTSRC_CR_SNSR_EN
#define DTSRC_CR_SNSR_EN_POS (3U)
#define DTSRC_CR_SNSR_EN_LEN (1U)
#define DTSRC_CR_SNSR_EN_MSK (((1U << DTSRC_CR_SNSR_EN_LEN) - 1) << DTSRC_CR_SNSR_EN_POS)
#define DTSRC_CR_SNSR_EN_UMSK (~(((1U << DTSRC_CR_SNSR_EN_LEN) - 1) << DTSRC_CR_SNSR_EN_POS))
#define DTSRC_CR_SNSR_HSYNC_INV DTSRC_CR_SNSR_HSYNC_INV
#define DTSRC_CR_SNSR_HSYNC_INV_POS (4U)
#define DTSRC_CR_SNSR_HSYNC_INV_LEN (1U)
#define DTSRC_CR_SNSR_HSYNC_INV_MSK (((1U << DTSRC_CR_SNSR_HSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_HSYNC_INV_POS)
#define DTSRC_CR_SNSR_HSYNC_INV_UMSK (~(((1U << DTSRC_CR_SNSR_HSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_HSYNC_INV_POS))
#define DTSRC_CR_SNSR_VSYNC_INV DTSRC_CR_SNSR_VSYNC_INV
#define DTSRC_CR_SNSR_VSYNC_INV_POS (5U)
#define DTSRC_CR_SNSR_VSYNC_INV_LEN (1U)
#define DTSRC_CR_SNSR_VSYNC_INV_MSK (((1U << DTSRC_CR_SNSR_VSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_VSYNC_INV_POS)
#define DTSRC_CR_SNSR_VSYNC_INV_UMSK (~(((1U << DTSRC_CR_SNSR_VSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_VSYNC_INV_POS))
#define DTSRC_CR_AXI_SWAP_MODE DTSRC_CR_AXI_SWAP_MODE
#define DTSRC_CR_AXI_SWAP_MODE_POS (7U)
#define DTSRC_CR_AXI_SWAP_MODE_LEN (1U)
#define DTSRC_CR_AXI_SWAP_MODE_MSK (((1U << DTSRC_CR_AXI_SWAP_MODE_LEN) - 1) << DTSRC_CR_AXI_SWAP_MODE_POS)
#define DTSRC_CR_AXI_SWAP_MODE_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_MODE_LEN) - 1) << DTSRC_CR_AXI_SWAP_MODE_POS))
#define DTSRC_CR_AXI_SWAP_IDX_SEL DTSRC_CR_AXI_SWAP_IDX_SEL
#define DTSRC_CR_AXI_SWAP_IDX_SEL_POS (8U)
#define DTSRC_CR_AXI_SWAP_IDX_SEL_LEN (4U)
#define DTSRC_CR_AXI_SWAP_IDX_SEL_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SEL_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SEL_POS)
#define DTSRC_CR_AXI_SWAP_IDX_SEL_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SEL_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SEL_POS))
#define DTSRC_CR_AXI_SWAP_IDX_SWM DTSRC_CR_AXI_SWAP_IDX_SWM
#define DTSRC_CR_AXI_SWAP_IDX_SWM_POS (12U)
#define DTSRC_CR_AXI_SWAP_IDX_SWM_LEN (1U)
#define DTSRC_CR_AXI_SWAP_IDX_SWM_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SWM_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWM_POS)
#define DTSRC_CR_AXI_SWAP_IDX_SWM_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SWM_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWM_POS))
#define DTSRC_CR_AXI_SWAP_IDX_SWV DTSRC_CR_AXI_SWAP_IDX_SWV
#define DTSRC_CR_AXI_SWAP_IDX_SWV_POS (13U)
#define DTSRC_CR_AXI_SWAP_IDX_SWV_LEN (1U)
#define DTSRC_CR_AXI_SWAP_IDX_SWV_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SWV_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWV_POS)
#define DTSRC_CR_AXI_SWAP_IDX_SWV_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SWV_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWV_POS))
#define DTSRC_CR_AXI_DVP_DATA_MODE DTSRC_CR_AXI_DVP_DATA_MODE
#define DTSRC_CR_AXI_DVP_DATA_MODE_POS (16U)
#define DTSRC_CR_AXI_DVP_DATA_MODE_LEN (3U)
#define DTSRC_CR_AXI_DVP_DATA_MODE_MSK (((1U << DTSRC_CR_AXI_DVP_DATA_MODE_LEN) - 1) << DTSRC_CR_AXI_DVP_DATA_MODE_POS)
#define DTSRC_CR_AXI_DVP_DATA_MODE_UMSK (~(((1U << DTSRC_CR_AXI_DVP_DATA_MODE_LEN) - 1) << DTSRC_CR_AXI_DVP_DATA_MODE_POS))
#define DTSRC_CR_AXI_B0_SEL DTSRC_CR_AXI_B0_SEL
#define DTSRC_CR_AXI_B0_SEL_POS (20U)
#define DTSRC_CR_AXI_B0_SEL_LEN (2U)
#define DTSRC_CR_AXI_B0_SEL_MSK (((1U << DTSRC_CR_AXI_B0_SEL_LEN) - 1) << DTSRC_CR_AXI_B0_SEL_POS)
#define DTSRC_CR_AXI_B0_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B0_SEL_LEN) - 1) << DTSRC_CR_AXI_B0_SEL_POS))
#define DTSRC_CR_AXI_B1_SEL DTSRC_CR_AXI_B1_SEL
#define DTSRC_CR_AXI_B1_SEL_POS (22U)
#define DTSRC_CR_AXI_B1_SEL_LEN (2U)
#define DTSRC_CR_AXI_B1_SEL_MSK (((1U << DTSRC_CR_AXI_B1_SEL_LEN) - 1) << DTSRC_CR_AXI_B1_SEL_POS)
#define DTSRC_CR_AXI_B1_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B1_SEL_LEN) - 1) << DTSRC_CR_AXI_B1_SEL_POS))
#define DTSRC_CR_AXI_B2_SEL DTSRC_CR_AXI_B2_SEL
#define DTSRC_CR_AXI_B2_SEL_POS (24U)
#define DTSRC_CR_AXI_B2_SEL_LEN (2U)
#define DTSRC_CR_AXI_B2_SEL_MSK (((1U << DTSRC_CR_AXI_B2_SEL_LEN) - 1) << DTSRC_CR_AXI_B2_SEL_POS)
#define DTSRC_CR_AXI_B2_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B2_SEL_LEN) - 1) << DTSRC_CR_AXI_B2_SEL_POS))
/* 0x4 : frame_size_h */
#define DTSRC_FRAME_SIZE_H_OFFSET (0x4)
#define DTSRC_CR_TOTAL_H DTSRC_CR_TOTAL_H
#define DTSRC_CR_TOTAL_H_POS (0U)
#define DTSRC_CR_TOTAL_H_LEN (12U)
#define DTSRC_CR_TOTAL_H_MSK (((1U << DTSRC_CR_TOTAL_H_LEN) - 1) << DTSRC_CR_TOTAL_H_POS)
#define DTSRC_CR_TOTAL_H_UMSK (~(((1U << DTSRC_CR_TOTAL_H_LEN) - 1) << DTSRC_CR_TOTAL_H_POS))
#define DTSRC_CR_BLANK_H DTSRC_CR_BLANK_H
#define DTSRC_CR_BLANK_H_POS (16U)
#define DTSRC_CR_BLANK_H_LEN (12U)
#define DTSRC_CR_BLANK_H_MSK (((1U << DTSRC_CR_BLANK_H_LEN) - 1) << DTSRC_CR_BLANK_H_POS)
#define DTSRC_CR_BLANK_H_UMSK (~(((1U << DTSRC_CR_BLANK_H_LEN) - 1) << DTSRC_CR_BLANK_H_POS))
/* 0x8 : frame_size_v */
#define DTSRC_FRAME_SIZE_V_OFFSET (0x8)
#define DTSRC_CR_TOTAL_V DTSRC_CR_TOTAL_V
#define DTSRC_CR_TOTAL_V_POS (0U)
#define DTSRC_CR_TOTAL_V_LEN (12U)
#define DTSRC_CR_TOTAL_V_MSK (((1U << DTSRC_CR_TOTAL_V_LEN) - 1) << DTSRC_CR_TOTAL_V_POS)
#define DTSRC_CR_TOTAL_V_UMSK (~(((1U << DTSRC_CR_TOTAL_V_LEN) - 1) << DTSRC_CR_TOTAL_V_POS))
#define DTSRC_CR_BLANK_V DTSRC_CR_BLANK_V
#define DTSRC_CR_BLANK_V_POS (16U)
#define DTSRC_CR_BLANK_V_LEN (12U)
#define DTSRC_CR_BLANK_V_MSK (((1U << DTSRC_CR_BLANK_V_LEN) - 1) << DTSRC_CR_BLANK_V_POS)
#define DTSRC_CR_BLANK_V_UMSK (~(((1U << DTSRC_CR_BLANK_V_LEN) - 1) << DTSRC_CR_BLANK_V_POS))
/* 0xC : frame_size_cea_861 */
#define DTSRC_FRAME_SIZE_CEA_861_OFFSET (0xC)
#define DTSRC_CR_H_DURATION DTSRC_CR_H_DURATION
#define DTSRC_CR_H_DURATION_POS (0U)
#define DTSRC_CR_H_DURATION_LEN (8U)
#define DTSRC_CR_H_DURATION_MSK (((1U << DTSRC_CR_H_DURATION_LEN) - 1) << DTSRC_CR_H_DURATION_POS)
#define DTSRC_CR_H_DURATION_UMSK (~(((1U << DTSRC_CR_H_DURATION_LEN) - 1) << DTSRC_CR_H_DURATION_POS))
#define DTSRC_CR_H_PLACEMENT DTSRC_CR_H_PLACEMENT
#define DTSRC_CR_H_PLACEMENT_POS (8U)
#define DTSRC_CR_H_PLACEMENT_LEN (8U)
#define DTSRC_CR_H_PLACEMENT_MSK (((1U << DTSRC_CR_H_PLACEMENT_LEN) - 1) << DTSRC_CR_H_PLACEMENT_POS)
#define DTSRC_CR_H_PLACEMENT_UMSK (~(((1U << DTSRC_CR_H_PLACEMENT_LEN) - 1) << DTSRC_CR_H_PLACEMENT_POS))
#define DTSRC_CR_V_DURATION DTSRC_CR_V_DURATION
#define DTSRC_CR_V_DURATION_POS (16U)
#define DTSRC_CR_V_DURATION_LEN (8U)
#define DTSRC_CR_V_DURATION_MSK (((1U << DTSRC_CR_V_DURATION_LEN) - 1) << DTSRC_CR_V_DURATION_POS)
#define DTSRC_CR_V_DURATION_UMSK (~(((1U << DTSRC_CR_V_DURATION_LEN) - 1) << DTSRC_CR_V_DURATION_POS))
#define DTSRC_CR_V_PLACEMENT DTSRC_CR_V_PLACEMENT
#define DTSRC_CR_V_PLACEMENT_POS (24U)
#define DTSRC_CR_V_PLACEMENT_LEN (8U)
#define DTSRC_CR_V_PLACEMENT_MSK (((1U << DTSRC_CR_V_PLACEMENT_LEN) - 1) << DTSRC_CR_V_PLACEMENT_POS)
#define DTSRC_CR_V_PLACEMENT_UMSK (~(((1U << DTSRC_CR_V_PLACEMENT_LEN) - 1) << DTSRC_CR_V_PLACEMENT_POS))
/* 0x10 : pix_data_range */
#define DTSRC_PIX_DATA_RANGE_OFFSET (0x10)
#define DTSRC_CR_DATA_MIN DTSRC_CR_DATA_MIN
#define DTSRC_CR_DATA_MIN_POS (0U)
#define DTSRC_CR_DATA_MIN_LEN (16U)
#define DTSRC_CR_DATA_MIN_MSK (((1U << DTSRC_CR_DATA_MIN_LEN) - 1) << DTSRC_CR_DATA_MIN_POS)
#define DTSRC_CR_DATA_MIN_UMSK (~(((1U << DTSRC_CR_DATA_MIN_LEN) - 1) << DTSRC_CR_DATA_MIN_POS))
#define DTSRC_CR_DATA_MAX DTSRC_CR_DATA_MAX
#define DTSRC_CR_DATA_MAX_POS (16U)
#define DTSRC_CR_DATA_MAX_LEN (16U)
#define DTSRC_CR_DATA_MAX_MSK (((1U << DTSRC_CR_DATA_MAX_LEN) - 1) << DTSRC_CR_DATA_MAX_POS)
#define DTSRC_CR_DATA_MAX_UMSK (~(((1U << DTSRC_CR_DATA_MAX_LEN) - 1) << DTSRC_CR_DATA_MAX_POS))
/* 0x14 : pix_data_step */
#define DTSRC_PIX_DATA_STEP_OFFSET (0x14)
#define DTSRC_CR_DATA_STEP DTSRC_CR_DATA_STEP
#define DTSRC_CR_DATA_STEP_POS (0U)
#define DTSRC_CR_DATA_STEP_LEN (8U)
#define DTSRC_CR_DATA_STEP_MSK (((1U << DTSRC_CR_DATA_STEP_LEN) - 1) << DTSRC_CR_DATA_STEP_POS)
#define DTSRC_CR_DATA_STEP_UMSK (~(((1U << DTSRC_CR_DATA_STEP_LEN) - 1) << DTSRC_CR_DATA_STEP_POS))
/* 0x20 : axi2dvp_setting */
#define DTSRC_AXI2DVP_SETTING_OFFSET (0x20)
#define DTSRC_CR_AXI_XLEN DTSRC_CR_AXI_XLEN
#define DTSRC_CR_AXI_XLEN_POS (0U)
#define DTSRC_CR_AXI_XLEN_LEN (3U)
#define DTSRC_CR_AXI_XLEN_MSK (((1U << DTSRC_CR_AXI_XLEN_LEN) - 1) << DTSRC_CR_AXI_XLEN_POS)
#define DTSRC_CR_AXI_XLEN_UMSK (~(((1U << DTSRC_CR_AXI_XLEN_LEN) - 1) << DTSRC_CR_AXI_XLEN_POS))
#define DTSRC_CR_AXI_DRAIN_ERR_CLR DTSRC_CR_AXI_DRAIN_ERR_CLR
#define DTSRC_CR_AXI_DRAIN_ERR_CLR_POS (4U)
#define DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN (1U)
#define DTSRC_CR_AXI_DRAIN_ERR_CLR_MSK (((1U << DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN) - 1) << DTSRC_CR_AXI_DRAIN_ERR_CLR_POS)
#define DTSRC_CR_AXI_DRAIN_ERR_CLR_UMSK (~(((1U << DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN) - 1) << DTSRC_CR_AXI_DRAIN_ERR_CLR_POS))
#define DTSRC_CR_AXI_420_MODE DTSRC_CR_AXI_420_MODE
#define DTSRC_CR_AXI_420_MODE_POS (8U)
#define DTSRC_CR_AXI_420_MODE_LEN (1U)
#define DTSRC_CR_AXI_420_MODE_MSK (((1U << DTSRC_CR_AXI_420_MODE_LEN) - 1) << DTSRC_CR_AXI_420_MODE_POS)
#define DTSRC_CR_AXI_420_MODE_UMSK (~(((1U << DTSRC_CR_AXI_420_MODE_LEN) - 1) << DTSRC_CR_AXI_420_MODE_POS))
#define DTSRC_CR_AXI_420_UD_SEL DTSRC_CR_AXI_420_UD_SEL
#define DTSRC_CR_AXI_420_UD_SEL_POS (9U)
#define DTSRC_CR_AXI_420_UD_SEL_LEN (1U)
#define DTSRC_CR_AXI_420_UD_SEL_MSK (((1U << DTSRC_CR_AXI_420_UD_SEL_LEN) - 1) << DTSRC_CR_AXI_420_UD_SEL_POS)
#define DTSRC_CR_AXI_420_UD_SEL_UMSK (~(((1U << DTSRC_CR_AXI_420_UD_SEL_LEN) - 1) << DTSRC_CR_AXI_420_UD_SEL_POS))
#define DTSRC_CR_QOS_SW_MODE DTSRC_CR_QOS_SW_MODE
#define DTSRC_CR_QOS_SW_MODE_POS (10U)
#define DTSRC_CR_QOS_SW_MODE_LEN (1U)
#define DTSRC_CR_QOS_SW_MODE_MSK (((1U << DTSRC_CR_QOS_SW_MODE_LEN) - 1) << DTSRC_CR_QOS_SW_MODE_POS)
#define DTSRC_CR_QOS_SW_MODE_UMSK (~(((1U << DTSRC_CR_QOS_SW_MODE_LEN) - 1) << DTSRC_CR_QOS_SW_MODE_POS))
#define DTSRC_CR_QOS_SW DTSRC_CR_QOS_SW
#define DTSRC_CR_QOS_SW_POS (11U)
#define DTSRC_CR_QOS_SW_LEN (1U)
#define DTSRC_CR_QOS_SW_MSK (((1U << DTSRC_CR_QOS_SW_LEN) - 1) << DTSRC_CR_QOS_SW_POS)
#define DTSRC_CR_QOS_SW_UMSK (~(((1U << DTSRC_CR_QOS_SW_LEN) - 1) << DTSRC_CR_QOS_SW_POS))
/* 0x24 : axi2dvp_start_addr_by */
#define DTSRC_AXI2DVP_START_ADDR_BY_OFFSET (0x24)
#define DTSRC_CR_AXI_ADDR_START_BY DTSRC_CR_AXI_ADDR_START_BY
#define DTSRC_CR_AXI_ADDR_START_BY_POS (0U)
#define DTSRC_CR_AXI_ADDR_START_BY_LEN (32U)
#define DTSRC_CR_AXI_ADDR_START_BY_MSK (((1U << DTSRC_CR_AXI_ADDR_START_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_BY_POS)
#define DTSRC_CR_AXI_ADDR_START_BY_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_START_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_BY_POS))
/* 0x28 : axi2dvp_burst_cnt */
#define DTSRC_AXI2DVP_BURST_CNT_OFFSET (0x28)
#define DTSRC_CR_AXI_FRAME_BC DTSRC_CR_AXI_FRAME_BC
#define DTSRC_CR_AXI_FRAME_BC_POS (0U)
#define DTSRC_CR_AXI_FRAME_BC_LEN (32U)
#define DTSRC_CR_AXI_FRAME_BC_MSK (((1U << DTSRC_CR_AXI_FRAME_BC_LEN) - 1) << DTSRC_CR_AXI_FRAME_BC_POS)
#define DTSRC_CR_AXI_FRAME_BC_UMSK (~(((1U << DTSRC_CR_AXI_FRAME_BC_LEN) - 1) << DTSRC_CR_AXI_FRAME_BC_POS))
/* 0x2C : axi2dvp_status */
#define DTSRC_AXI2DVP_STATUS_OFFSET (0x2C)
#define DTSRC_ST_AXI_FIFO_CNT_BY DTSRC_ST_AXI_FIFO_CNT_BY
#define DTSRC_ST_AXI_FIFO_CNT_BY_POS (0U)
#define DTSRC_ST_AXI_FIFO_CNT_BY_LEN (7U)
#define DTSRC_ST_AXI_FIFO_CNT_BY_MSK (((1U << DTSRC_ST_AXI_FIFO_CNT_BY_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_BY_POS)
#define DTSRC_ST_AXI_FIFO_CNT_BY_UMSK (~(((1U << DTSRC_ST_AXI_FIFO_CNT_BY_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_BY_POS))
#define DTSRC_ST_AXI_DRAIN_ERROR_BY DTSRC_ST_AXI_DRAIN_ERROR_BY
#define DTSRC_ST_AXI_DRAIN_ERROR_BY_POS (7U)
#define DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN (1U)
#define DTSRC_ST_AXI_DRAIN_ERROR_BY_MSK (((1U << DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_BY_POS)
#define DTSRC_ST_AXI_DRAIN_ERROR_BY_UMSK (~(((1U << DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_BY_POS))
#define DTSRC_ST_AXI_STATE_IDLE_BY DTSRC_ST_AXI_STATE_IDLE_BY
#define DTSRC_ST_AXI_STATE_IDLE_BY_POS (8U)
#define DTSRC_ST_AXI_STATE_IDLE_BY_LEN (1U)
#define DTSRC_ST_AXI_STATE_IDLE_BY_MSK (((1U << DTSRC_ST_AXI_STATE_IDLE_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_BY_POS)
#define DTSRC_ST_AXI_STATE_IDLE_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_IDLE_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_BY_POS))
#define DTSRC_ST_AXI_STATE_FUNC_BY DTSRC_ST_AXI_STATE_FUNC_BY
#define DTSRC_ST_AXI_STATE_FUNC_BY_POS (9U)
#define DTSRC_ST_AXI_STATE_FUNC_BY_LEN (1U)
#define DTSRC_ST_AXI_STATE_FUNC_BY_MSK (((1U << DTSRC_ST_AXI_STATE_FUNC_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_BY_POS)
#define DTSRC_ST_AXI_STATE_FUNC_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FUNC_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_BY_POS))
#define DTSRC_ST_AXI_STATE_FLSH_BY DTSRC_ST_AXI_STATE_FLSH_BY
#define DTSRC_ST_AXI_STATE_FLSH_BY_POS (10U)
#define DTSRC_ST_AXI_STATE_FLSH_BY_LEN (1U)
#define DTSRC_ST_AXI_STATE_FLSH_BY_MSK (((1U << DTSRC_ST_AXI_STATE_FLSH_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_BY_POS)
#define DTSRC_ST_AXI_STATE_FLSH_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FLSH_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_BY_POS))
#define DTSRC_ST_AXI_FIFO_CNT_UV DTSRC_ST_AXI_FIFO_CNT_UV
#define DTSRC_ST_AXI_FIFO_CNT_UV_POS (16U)
#define DTSRC_ST_AXI_FIFO_CNT_UV_LEN (7U)
#define DTSRC_ST_AXI_FIFO_CNT_UV_MSK (((1U << DTSRC_ST_AXI_FIFO_CNT_UV_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_UV_POS)
#define DTSRC_ST_AXI_FIFO_CNT_UV_UMSK (~(((1U << DTSRC_ST_AXI_FIFO_CNT_UV_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_UV_POS))
#define DTSRC_ST_AXI_DRAIN_ERROR_UV DTSRC_ST_AXI_DRAIN_ERROR_UV
#define DTSRC_ST_AXI_DRAIN_ERROR_UV_POS (23U)
#define DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN (1U)
#define DTSRC_ST_AXI_DRAIN_ERROR_UV_MSK (((1U << DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_UV_POS)
#define DTSRC_ST_AXI_DRAIN_ERROR_UV_UMSK (~(((1U << DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_UV_POS))
#define DTSRC_ST_AXI_STATE_IDLE_UV DTSRC_ST_AXI_STATE_IDLE_UV
#define DTSRC_ST_AXI_STATE_IDLE_UV_POS (24U)
#define DTSRC_ST_AXI_STATE_IDLE_UV_LEN (1U)
#define DTSRC_ST_AXI_STATE_IDLE_UV_MSK (((1U << DTSRC_ST_AXI_STATE_IDLE_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_UV_POS)
#define DTSRC_ST_AXI_STATE_IDLE_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_IDLE_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_UV_POS))
#define DTSRC_ST_AXI_STATE_FUNC_UV DTSRC_ST_AXI_STATE_FUNC_UV
#define DTSRC_ST_AXI_STATE_FUNC_UV_POS (25U)
#define DTSRC_ST_AXI_STATE_FUNC_UV_LEN (1U)
#define DTSRC_ST_AXI_STATE_FUNC_UV_MSK (((1U << DTSRC_ST_AXI_STATE_FUNC_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_UV_POS)
#define DTSRC_ST_AXI_STATE_FUNC_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FUNC_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_UV_POS))
#define DTSRC_ST_AXI_STATE_FLSH_UV DTSRC_ST_AXI_STATE_FLSH_UV
#define DTSRC_ST_AXI_STATE_FLSH_UV_POS (26U)
#define DTSRC_ST_AXI_STATE_FLSH_UV_LEN (1U)
#define DTSRC_ST_AXI_STATE_FLSH_UV_MSK (((1U << DTSRC_ST_AXI_STATE_FLSH_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_UV_POS)
#define DTSRC_ST_AXI_STATE_FLSH_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FLSH_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_UV_POS))
/* 0x30 : axi2dvp_swap_addr_by */
#define DTSRC_AXI2DVP_SWAP_ADDR_BY_OFFSET (0x30)
#define DTSRC_CR_AXI_ADDR_SWAP_BY DTSRC_CR_AXI_ADDR_SWAP_BY
#define DTSRC_CR_AXI_ADDR_SWAP_BY_POS (0U)
#define DTSRC_CR_AXI_ADDR_SWAP_BY_LEN (32U)
#define DTSRC_CR_AXI_ADDR_SWAP_BY_MSK (((1U << DTSRC_CR_AXI_ADDR_SWAP_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_BY_POS)
#define DTSRC_CR_AXI_ADDR_SWAP_BY_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_SWAP_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_BY_POS))
/* 0x34 : axi2dvp_prefetch */
#define DTSRC_AXI2DVP_PREFETCH_OFFSET (0x34)
#define DTSRC_CR_PREFETCH_V DTSRC_CR_PREFETCH_V
#define DTSRC_CR_PREFETCH_V_POS (0U)
#define DTSRC_CR_PREFETCH_V_LEN (12U)
#define DTSRC_CR_PREFETCH_V_MSK (((1U << DTSRC_CR_PREFETCH_V_LEN) - 1) << DTSRC_CR_PREFETCH_V_POS)
#define DTSRC_CR_PREFETCH_V_UMSK (~(((1U << DTSRC_CR_PREFETCH_V_LEN) - 1) << DTSRC_CR_PREFETCH_V_POS))
/* 0x38 : snsr2dvp_wait_pos */
#define DTSRC_SNSR2DVP_WAIT_POS_OFFSET (0x38)
#define DTSRC_CR_SNSR_FIFO_TH DTSRC_CR_SNSR_FIFO_TH
#define DTSRC_CR_SNSR_FIFO_TH_POS (0U)
#define DTSRC_CR_SNSR_FIFO_TH_LEN (11U)
#define DTSRC_CR_SNSR_FIFO_TH_MSK (((1U << DTSRC_CR_SNSR_FIFO_TH_LEN) - 1) << DTSRC_CR_SNSR_FIFO_TH_POS)
#define DTSRC_CR_SNSR_FIFO_TH_UMSK (~(((1U << DTSRC_CR_SNSR_FIFO_TH_LEN) - 1) << DTSRC_CR_SNSR_FIFO_TH_POS))
/* 0x40 : axi2dvp_start_addr_uv */
#define DTSRC_AXI2DVP_START_ADDR_UV_OFFSET (0x40)
#define DTSRC_CR_AXI_ADDR_START_UV DTSRC_CR_AXI_ADDR_START_UV
#define DTSRC_CR_AXI_ADDR_START_UV_POS (0U)
#define DTSRC_CR_AXI_ADDR_START_UV_LEN (32U)
#define DTSRC_CR_AXI_ADDR_START_UV_MSK (((1U << DTSRC_CR_AXI_ADDR_START_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_UV_POS)
#define DTSRC_CR_AXI_ADDR_START_UV_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_START_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_UV_POS))
/* 0x44 : axi2dvp_swap_addr_uv */
#define DTSRC_AXI2DVP_SWAP_ADDR_UV_OFFSET (0x44)
#define DTSRC_CR_AXI_ADDR_SWAP_UV DTSRC_CR_AXI_ADDR_SWAP_UV
#define DTSRC_CR_AXI_ADDR_SWAP_UV_POS (0U)
#define DTSRC_CR_AXI_ADDR_SWAP_UV_LEN (32U)
#define DTSRC_CR_AXI_ADDR_SWAP_UV_MSK (((1U << DTSRC_CR_AXI_ADDR_SWAP_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_UV_POS)
#define DTSRC_CR_AXI_ADDR_SWAP_UV_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_SWAP_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_UV_POS))
struct dtsrc_reg {
/* 0x0 : config */
union {
struct {
uint32_t cr_enable : 1; /* [ 0], r/w, 0x0 */
uint32_t cr_axi_en : 1; /* [ 1], r/w, 0x0 */
uint32_t cr_mode_cea_861 : 1; /* [ 2], r/w, 0x0 */
uint32_t cr_snsr_en : 1; /* [ 3], r/w, 0x0 */
uint32_t cr_snsr_hsync_inv : 1; /* [ 4], r/w, 0x0 */
uint32_t cr_snsr_vsync_inv : 1; /* [ 5], r/w, 0x0 */
uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
uint32_t cr_axi_swap_mode : 1; /* [ 7], r/w, 0x0 */
uint32_t cr_axi_swap_idx_sel : 4; /* [11: 8], r/w, 0x0 */
uint32_t cr_axi_swap_idx_swm : 1; /* [ 12], r/w, 0x0 */
uint32_t cr_axi_swap_idx_swv : 1; /* [ 13], r/w, 0x0 */
uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
uint32_t cr_axi_dvp_data_mode : 3; /* [18:16], r/w, 0x0 */
uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
uint32_t cr_axi_b0_sel : 2; /* [21:20], r/w, 0x0 */
uint32_t cr_axi_b1_sel : 2; /* [23:22], r/w, 0x1 */
uint32_t cr_axi_b2_sel : 2; /* [25:24], r/w, 0x2 */
uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
} BF;
uint32_t WORD;
} config;
/* 0x4 : frame_size_h */
union {
struct {
uint32_t cr_total_h : 12; /* [11: 0], r/w, 0x897 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t cr_blank_h : 12; /* [27:16], r/w, 0x117 */
uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
} BF;
uint32_t WORD;
} frame_size_h;
/* 0x8 : frame_size_v */
union {
struct {
uint32_t cr_total_v : 12; /* [11: 0], r/w, 0x464 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t cr_blank_v : 12; /* [27:16], r/w, 0x2c */
uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
} BF;
uint32_t WORD;
} frame_size_v;
/* 0xC : frame_size_cea_861 */
union {
struct {
uint32_t cr_h_duration : 8; /* [ 7: 0], r/w, 0x83 */
uint32_t cr_h_placement : 8; /* [15: 8], r/w, 0x57 */
uint32_t cr_v_duration : 8; /* [23:16], r/w, 0x8 */
uint32_t cr_v_placement : 8; /* [31:24], r/w, 0x3 */
} BF;
uint32_t WORD;
} frame_size_cea_861;
/* 0x10 : pix_data_range */
union {
struct {
uint32_t cr_data_min : 16; /* [15: 0], r/w, 0x0 */
uint32_t cr_data_max : 16; /* [31:16], r/w, 0xffff */
} BF;
uint32_t WORD;
} pix_data_range;
/* 0x14 : pix_data_step */
union {
struct {
uint32_t cr_data_step : 8; /* [ 7: 0], r/w, 0x1 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} pix_data_step;
/* 0x18 reserved */
uint8_t RESERVED0x18[8];
/* 0x20 : axi2dvp_setting */
union {
struct {
uint32_t cr_axi_xlen : 3; /* [ 2: 0], r/w, 0x3 */
uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
uint32_t cr_axi_drain_err_clr : 1; /* [ 4], w1p, 0x0 */
uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
uint32_t cr_axi_420_mode : 1; /* [ 8], r/w, 0x0 */
uint32_t cr_axi_420_ud_sel : 1; /* [ 9], r/w, 0x0 */
uint32_t cr_qos_sw_mode : 1; /* [ 10], r/w, 0x0 */
uint32_t cr_qos_sw : 1; /* [ 11], r/w, 0x0 */
uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
} BF;
uint32_t WORD;
} axi2dvp_setting;
/* 0x24 : axi2dvp_start_addr_by */
union {
struct {
uint32_t cr_axi_addr_start_by : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} axi2dvp_start_addr_by;
/* 0x28 : axi2dvp_burst_cnt */
union {
struct {
uint32_t cr_axi_frame_bc : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} axi2dvp_burst_cnt;
/* 0x2C : axi2dvp_status */
union {
struct {
uint32_t st_axi_fifo_cnt_by : 7; /* [ 6: 0], r, 0x0 */
uint32_t st_axi_drain_error_by : 1; /* [ 7], r, 0x0 */
uint32_t st_axi_state_idle_by : 1; /* [ 8], r, 0x0 */
uint32_t st_axi_state_func_by : 1; /* [ 9], r, 0x0 */
uint32_t st_axi_state_flsh_by : 1; /* [ 10], r, 0x0 */
uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */
uint32_t st_axi_fifo_cnt_uv : 7; /* [22:16], r, 0x0 */
uint32_t st_axi_drain_error_uv : 1; /* [ 23], r, 0x0 */
uint32_t st_axi_state_idle_uv : 1; /* [ 24], r, 0x0 */
uint32_t st_axi_state_func_uv : 1; /* [ 25], r, 0x0 */
uint32_t st_axi_state_flsh_uv : 1; /* [ 26], r, 0x0 */
uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
} BF;
uint32_t WORD;
} axi2dvp_status;
/* 0x30 : axi2dvp_swap_addr_by */
union {
struct {
uint32_t cr_axi_addr_swap_by : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} axi2dvp_swap_addr_by;
/* 0x34 : axi2dvp_prefetch */
union {
struct {
uint32_t cr_prefetch_v : 12; /* [11: 0], r/w, 0x28 */
uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
} BF;
uint32_t WORD;
} axi2dvp_prefetch;
/* 0x38 : snsr2dvp_wait_pos */
union {
struct {
uint32_t cr_snsr_fifo_th : 11; /* [10: 0], r/w, 0x8b */
uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
} BF;
uint32_t WORD;
} snsr2dvp_wait_pos;
/* 0x3c reserved */
uint8_t RESERVED0x3c[4];
/* 0x40 : axi2dvp_start_addr_uv */
union {
struct {
uint32_t cr_axi_addr_start_uv : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} axi2dvp_start_addr_uv;
/* 0x44 : axi2dvp_swap_addr_uv */
union {
struct {
uint32_t cr_axi_addr_swap_uv : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} axi2dvp_swap_addr_uv;
};
#endif /* __DTSRC_REG_H__ */

940
include/bl808/ef_ctrl_reg.h Normal file
View File

@ -0,0 +1,940 @@
/**
******************************************************************************
* @file ef_ctrl_reg.h
* @version V1.0
* @date 2021-07-31
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __EF_CTRL_REG_H__
#define __EF_CTRL_REG_H__
#include <linux/types.h>
/* 0x800 : ef_if_ctrl_0 */
#define EF_CTRL_EF_IF_CTRL_0_OFFSET (0x800)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS (0U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN (1U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MSK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS))
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE EF_CTRL_EF_IF_0_AUTOLOAD_DONE
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS (1U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN (1U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MSK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS)
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS))
#define EF_CTRL_EF_IF_0_BUSY EF_CTRL_EF_IF_0_BUSY
#define EF_CTRL_EF_IF_0_BUSY_POS (2U)
#define EF_CTRL_EF_IF_0_BUSY_LEN (1U)
#define EF_CTRL_EF_IF_0_BUSY_MSK (((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS)
#define EF_CTRL_EF_IF_0_BUSY_UMSK (~(((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS))
#define EF_CTRL_EF_IF_0_RW EF_CTRL_EF_IF_0_RW
#define EF_CTRL_EF_IF_0_RW_POS (3U)
#define EF_CTRL_EF_IF_0_RW_LEN (1U)
#define EF_CTRL_EF_IF_0_RW_MSK (((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS)
#define EF_CTRL_EF_IF_0_RW_UMSK (~(((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS))
#define EF_CTRL_EF_IF_0_TRIG EF_CTRL_EF_IF_0_TRIG
#define EF_CTRL_EF_IF_0_TRIG_POS (4U)
#define EF_CTRL_EF_IF_0_TRIG_LEN (1U)
#define EF_CTRL_EF_IF_0_TRIG_MSK (((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS)
#define EF_CTRL_EF_IF_0_TRIG_UMSK (~(((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS))
#define EF_CTRL_EF_IF_0_MANUAL_EN EF_CTRL_EF_IF_0_MANUAL_EN
#define EF_CTRL_EF_IF_0_MANUAL_EN_POS (5U)
#define EF_CTRL_EF_IF_0_MANUAL_EN_LEN (1U)
#define EF_CTRL_EF_IF_0_MANUAL_EN_MSK (((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS)
#define EF_CTRL_EF_IF_0_MANUAL_EN_UMSK (~(((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS))
#define EF_CTRL_EF_IF_0_CYC_MODIFY EF_CTRL_EF_IF_0_CYC_MODIFY
#define EF_CTRL_EF_IF_0_CYC_MODIFY_POS (6U)
#define EF_CTRL_EF_IF_0_CYC_MODIFY_LEN (1U)
#define EF_CTRL_EF_IF_0_CYC_MODIFY_MSK (((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
#define EF_CTRL_EF_IF_0_CYC_MODIFY_UMSK (~(((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS))
#define EF_CTRL_EF_IF_PROT_CODE_CTRL EF_CTRL_EF_IF_PROT_CODE_CTRL
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_POS (8U)
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN (8U)
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS)
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS))
#define EF_CTRL_EF_IF_POR_DIG EF_CTRL_EF_IF_POR_DIG
#define EF_CTRL_EF_IF_POR_DIG_POS (16U)
#define EF_CTRL_EF_IF_POR_DIG_LEN (1U)
#define EF_CTRL_EF_IF_POR_DIG_MSK (((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS)
#define EF_CTRL_EF_IF_POR_DIG_UMSK (~(((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS))
#define EF_CTRL_EF_PCLK_FORCE_ON EF_CTRL_EF_PCLK_FORCE_ON
#define EF_CTRL_EF_PCLK_FORCE_ON_POS (17U)
#define EF_CTRL_EF_PCLK_FORCE_ON_LEN (1U)
#define EF_CTRL_EF_PCLK_FORCE_ON_MSK (((1U << EF_CTRL_EF_PCLK_FORCE_ON_LEN) - 1) << EF_CTRL_EF_PCLK_FORCE_ON_POS)
#define EF_CTRL_EF_PCLK_FORCE_ON_UMSK (~(((1U << EF_CTRL_EF_PCLK_FORCE_ON_LEN) - 1) << EF_CTRL_EF_PCLK_FORCE_ON_POS))
#define EF_CTRL_EF_IF_AUTO_RD_EN EF_CTRL_EF_IF_AUTO_RD_EN
#define EF_CTRL_EF_IF_AUTO_RD_EN_POS (18U)
#define EF_CTRL_EF_IF_AUTO_RD_EN_LEN (1U)
#define EF_CTRL_EF_IF_AUTO_RD_EN_MSK (((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS)
#define EF_CTRL_EF_IF_AUTO_RD_EN_UMSK (~(((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS))
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK EF_CTRL_EF_IF_CYC_MODIFY_LOCK
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS (19U)
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN (1U)
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_MSK (((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS)
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS))
#define EF_CTRL_EF_IF_0_INT EF_CTRL_EF_IF_0_INT
#define EF_CTRL_EF_IF_0_INT_POS (20U)
#define EF_CTRL_EF_IF_0_INT_LEN (1U)
#define EF_CTRL_EF_IF_0_INT_MSK (((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS)
#define EF_CTRL_EF_IF_0_INT_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS))
#define EF_CTRL_EF_IF_0_INT_CLR EF_CTRL_EF_IF_0_INT_CLR
#define EF_CTRL_EF_IF_0_INT_CLR_POS (21U)
#define EF_CTRL_EF_IF_0_INT_CLR_LEN (1U)
#define EF_CTRL_EF_IF_0_INT_CLR_MSK (((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS)
#define EF_CTRL_EF_IF_0_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS))
#define EF_CTRL_EF_IF_0_INT_SET EF_CTRL_EF_IF_0_INT_SET
#define EF_CTRL_EF_IF_0_INT_SET_POS (22U)
#define EF_CTRL_EF_IF_0_INT_SET_LEN (1U)
#define EF_CTRL_EF_IF_0_INT_SET_MSK (((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS)
#define EF_CTRL_EF_IF_0_INT_SET_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS))
#define EF_CTRL_EF_IF_PROT_CODE_CYC EF_CTRL_EF_IF_PROT_CODE_CYC
#define EF_CTRL_EF_IF_PROT_CODE_CYC_POS (24U)
#define EF_CTRL_EF_IF_PROT_CODE_CYC_LEN (8U)
#define EF_CTRL_EF_IF_PROT_CODE_CYC_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS)
#define EF_CTRL_EF_IF_PROT_CODE_CYC_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS))
/* 0x804 : ef_if_cyc_0 */
#define EF_CTRL_EF_IF_CYC_0_OFFSET (0x804)
#define EF_CTRL_EF_IF_CYC_RD_DMY EF_CTRL_EF_IF_CYC_RD_DMY
#define EF_CTRL_EF_IF_CYC_RD_DMY_POS (0U)
#define EF_CTRL_EF_IF_CYC_RD_DMY_LEN (6U)
#define EF_CTRL_EF_IF_CYC_RD_DMY_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS)
#define EF_CTRL_EF_IF_CYC_RD_DMY_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS))
#define EF_CTRL_EF_IF_CYC_RD_DAT EF_CTRL_EF_IF_CYC_RD_DAT
#define EF_CTRL_EF_IF_CYC_RD_DAT_POS (6U)
#define EF_CTRL_EF_IF_CYC_RD_DAT_LEN (6U)
#define EF_CTRL_EF_IF_CYC_RD_DAT_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS)
#define EF_CTRL_EF_IF_CYC_RD_DAT_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS))
#define EF_CTRL_EF_IF_CYC_RD_ADR EF_CTRL_EF_IF_CYC_RD_ADR
#define EF_CTRL_EF_IF_CYC_RD_ADR_POS (12U)
#define EF_CTRL_EF_IF_CYC_RD_ADR_LEN (6U)
#define EF_CTRL_EF_IF_CYC_RD_ADR_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS)
#define EF_CTRL_EF_IF_CYC_RD_ADR_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS))
#define EF_CTRL_EF_IF_CYC_CS EF_CTRL_EF_IF_CYC_CS
#define EF_CTRL_EF_IF_CYC_CS_POS (18U)
#define EF_CTRL_EF_IF_CYC_CS_LEN (6U)
#define EF_CTRL_EF_IF_CYC_CS_MSK (((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS)
#define EF_CTRL_EF_IF_CYC_CS_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS))
#define EF_CTRL_EF_IF_CYC_PD_CS_S EF_CTRL_EF_IF_CYC_PD_CS_S
#define EF_CTRL_EF_IF_CYC_PD_CS_S_POS (24U)
#define EF_CTRL_EF_IF_CYC_PD_CS_S_LEN (8U)
#define EF_CTRL_EF_IF_CYC_PD_CS_S_MSK (((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS)
#define EF_CTRL_EF_IF_CYC_PD_CS_S_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS))
/* 0x808 : ef_if_cyc_1 */
#define EF_CTRL_EF_IF_CYC_1_OFFSET (0x808)
#define EF_CTRL_EF_IF_CYC_PI EF_CTRL_EF_IF_CYC_PI
#define EF_CTRL_EF_IF_CYC_PI_POS (0U)
#define EF_CTRL_EF_IF_CYC_PI_LEN (6U)
#define EF_CTRL_EF_IF_CYC_PI_MSK (((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS)
#define EF_CTRL_EF_IF_CYC_PI_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS))
#define EF_CTRL_EF_IF_CYC_PP EF_CTRL_EF_IF_CYC_PP
#define EF_CTRL_EF_IF_CYC_PP_POS (6U)
#define EF_CTRL_EF_IF_CYC_PP_LEN (8U)
#define EF_CTRL_EF_IF_CYC_PP_MSK (((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS)
#define EF_CTRL_EF_IF_CYC_PP_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS))
#define EF_CTRL_EF_IF_CYC_WR_ADR EF_CTRL_EF_IF_CYC_WR_ADR
#define EF_CTRL_EF_IF_CYC_WR_ADR_POS (14U)
#define EF_CTRL_EF_IF_CYC_WR_ADR_LEN (6U)
#define EF_CTRL_EF_IF_CYC_WR_ADR_MSK (((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS)
#define EF_CTRL_EF_IF_CYC_WR_ADR_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS))
#define EF_CTRL_EF_IF_CYC_PS_CS EF_CTRL_EF_IF_CYC_PS_CS
#define EF_CTRL_EF_IF_CYC_PS_CS_POS (20U)
#define EF_CTRL_EF_IF_CYC_PS_CS_LEN (6U)
#define EF_CTRL_EF_IF_CYC_PS_CS_MSK (((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS)
#define EF_CTRL_EF_IF_CYC_PS_CS_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS))
#define EF_CTRL_EF_IF_CYC_PD_CS_H EF_CTRL_EF_IF_CYC_PD_CS_H
#define EF_CTRL_EF_IF_CYC_PD_CS_H_POS (26U)
#define EF_CTRL_EF_IF_CYC_PD_CS_H_LEN (6U)
#define EF_CTRL_EF_IF_CYC_PD_CS_H_MSK (((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS)
#define EF_CTRL_EF_IF_CYC_PD_CS_H_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS))
/* 0x80C : ef_if_0_manual */
#define EF_CTRL_EF_IF_0_MANUAL_OFFSET (0x80C)
#define EF_CTRL_EF_IF_A EF_CTRL_EF_IF_A
#define EF_CTRL_EF_IF_A_POS (0U)
#define EF_CTRL_EF_IF_A_LEN (10U)
#define EF_CTRL_EF_IF_A_MSK (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)
#define EF_CTRL_EF_IF_A_UMSK (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS))
#define EF_CTRL_EF_IF_PD EF_CTRL_EF_IF_PD
#define EF_CTRL_EF_IF_PD_POS (10U)
#define EF_CTRL_EF_IF_PD_LEN (1U)
#define EF_CTRL_EF_IF_PD_MSK (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)
#define EF_CTRL_EF_IF_PD_UMSK (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS))
#define EF_CTRL_EF_IF_PS EF_CTRL_EF_IF_PS
#define EF_CTRL_EF_IF_PS_POS (11U)
#define EF_CTRL_EF_IF_PS_LEN (1U)
#define EF_CTRL_EF_IF_PS_MSK (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)
#define EF_CTRL_EF_IF_PS_UMSK (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS))
#define EF_CTRL_EF_IF_STROBE EF_CTRL_EF_IF_STROBE
#define EF_CTRL_EF_IF_STROBE_POS (12U)
#define EF_CTRL_EF_IF_STROBE_LEN (1U)
#define EF_CTRL_EF_IF_STROBE_MSK (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)
#define EF_CTRL_EF_IF_STROBE_UMSK (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS))
#define EF_CTRL_EF_IF_PGENB EF_CTRL_EF_IF_PGENB
#define EF_CTRL_EF_IF_PGENB_POS (13U)
#define EF_CTRL_EF_IF_PGENB_LEN (1U)
#define EF_CTRL_EF_IF_PGENB_MSK (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)
#define EF_CTRL_EF_IF_PGENB_UMSK (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS))
#define EF_CTRL_EF_IF_LOAD EF_CTRL_EF_IF_LOAD
#define EF_CTRL_EF_IF_LOAD_POS (14U)
#define EF_CTRL_EF_IF_LOAD_LEN (1U)
#define EF_CTRL_EF_IF_LOAD_MSK (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)
#define EF_CTRL_EF_IF_LOAD_UMSK (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS))
#define EF_CTRL_EF_IF_CSB EF_CTRL_EF_IF_CSB
#define EF_CTRL_EF_IF_CSB_POS (15U)
#define EF_CTRL_EF_IF_CSB_LEN (1U)
#define EF_CTRL_EF_IF_CSB_MSK (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)
#define EF_CTRL_EF_IF_CSB_UMSK (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS))
#define EF_CTRL_EF_IF_0_Q EF_CTRL_EF_IF_0_Q
#define EF_CTRL_EF_IF_0_Q_POS (16U)
#define EF_CTRL_EF_IF_0_Q_LEN (8U)
#define EF_CTRL_EF_IF_0_Q_MSK (((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS)
#define EF_CTRL_EF_IF_0_Q_UMSK (~(((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS))
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL EF_CTRL_EF_IF_PROT_CODE_MANUAL
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS (24U)
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN (8U)
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS))
/* 0x810 : ef_if_0_status */
#define EF_CTRL_EF_IF_0_STATUS_OFFSET (0x810)
#define EF_CTRL_EF_IF_0_STATUS EF_CTRL_EF_IF_0_STATUS
#define EF_CTRL_EF_IF_0_STATUS_POS (0U)
#define EF_CTRL_EF_IF_0_STATUS_LEN (32U)
#define EF_CTRL_EF_IF_0_STATUS_MSK (((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS)
#define EF_CTRL_EF_IF_0_STATUS_UMSK (~(((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS))
/* 0x814 : ef_if_cfg_0 */
#define EF_CTRL_EF_IF_CFG_0_OFFSET (0x814)
#define EF_CTRL_EF_IF_SF_AES_MODE EF_CTRL_EF_IF_SF_AES_MODE
#define EF_CTRL_EF_IF_SF_AES_MODE_POS (0U)
#define EF_CTRL_EF_IF_SF_AES_MODE_LEN (2U)
#define EF_CTRL_EF_IF_SF_AES_MODE_MSK (((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS)
#define EF_CTRL_EF_IF_SF_AES_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS))
#define EF_CTRL_EF_IF_AI_DIS EF_CTRL_EF_IF_AI_DIS
#define EF_CTRL_EF_IF_AI_DIS_POS (2U)
#define EF_CTRL_EF_IF_AI_DIS_LEN (1U)
#define EF_CTRL_EF_IF_AI_DIS_MSK (((1U << EF_CTRL_EF_IF_AI_DIS_LEN) - 1) << EF_CTRL_EF_IF_AI_DIS_POS)
#define EF_CTRL_EF_IF_AI_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_AI_DIS_LEN) - 1) << EF_CTRL_EF_IF_AI_DIS_POS))
#define EF_CTRL_EF_IF_CPU0_DIS EF_CTRL_EF_IF_CPU0_DIS
#define EF_CTRL_EF_IF_CPU0_DIS_POS (3U)
#define EF_CTRL_EF_IF_CPU0_DIS_LEN (1U)
#define EF_CTRL_EF_IF_CPU0_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU0_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU0_DIS_POS)
#define EF_CTRL_EF_IF_CPU0_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU0_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU0_DIS_POS))
#define EF_CTRL_EF_IF_SBOOT_EN EF_CTRL_EF_IF_SBOOT_EN
#define EF_CTRL_EF_IF_SBOOT_EN_POS (4U)
#define EF_CTRL_EF_IF_SBOOT_EN_LEN (2U)
#define EF_CTRL_EF_IF_SBOOT_EN_MSK (((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS)
#define EF_CTRL_EF_IF_SBOOT_EN_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS))
#define EF_CTRL_EF_IF_UART_DIS EF_CTRL_EF_IF_UART_DIS
#define EF_CTRL_EF_IF_UART_DIS_POS (6U)
#define EF_CTRL_EF_IF_UART_DIS_LEN (4U)
#define EF_CTRL_EF_IF_UART_DIS_MSK (((1U << EF_CTRL_EF_IF_UART_DIS_LEN) - 1) << EF_CTRL_EF_IF_UART_DIS_POS)
#define EF_CTRL_EF_IF_UART_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_UART_DIS_LEN) - 1) << EF_CTRL_EF_IF_UART_DIS_POS))
#define EF_CTRL_EF_IF_BLE2_DIS EF_CTRL_EF_IF_BLE2_DIS
#define EF_CTRL_EF_IF_BLE2_DIS_POS (10U)
#define EF_CTRL_EF_IF_BLE2_DIS_LEN (1U)
#define EF_CTRL_EF_IF_BLE2_DIS_MSK (((1U << EF_CTRL_EF_IF_BLE2_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE2_DIS_POS)
#define EF_CTRL_EF_IF_BLE2_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_BLE2_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE2_DIS_POS))
#define EF_CTRL_EF_IF_M1542_DIS EF_CTRL_EF_IF_M1542_DIS
#define EF_CTRL_EF_IF_M1542_DIS_POS (11U)
#define EF_CTRL_EF_IF_M1542_DIS_LEN (1U)
#define EF_CTRL_EF_IF_M1542_DIS_MSK (((1U << EF_CTRL_EF_IF_M1542_DIS_LEN) - 1) << EF_CTRL_EF_IF_M1542_DIS_POS)
#define EF_CTRL_EF_IF_M1542_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_M1542_DIS_LEN) - 1) << EF_CTRL_EF_IF_M1542_DIS_POS))
#define EF_CTRL_EF_IF_SF_KEY_RE_SEL EF_CTRL_EF_IF_SF_KEY_RE_SEL
#define EF_CTRL_EF_IF_SF_KEY_RE_SEL_POS (12U)
#define EF_CTRL_EF_IF_SF_KEY_RE_SEL_LEN (2U)
#define EF_CTRL_EF_IF_SF_KEY_RE_SEL_MSK (((1U << EF_CTRL_EF_IF_SF_KEY_RE_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_RE_SEL_POS)
#define EF_CTRL_EF_IF_SF_KEY_RE_SEL_UMSK (~(((1U << EF_CTRL_EF_IF_SF_KEY_RE_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_RE_SEL_POS))
#define EF_CTRL_EF_IF_SDU_DIS EF_CTRL_EF_IF_SDU_DIS
#define EF_CTRL_EF_IF_SDU_DIS_POS (14U)
#define EF_CTRL_EF_IF_SDU_DIS_LEN (1U)
#define EF_CTRL_EF_IF_SDU_DIS_MSK (((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS)
#define EF_CTRL_EF_IF_SDU_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS))
#define EF_CTRL_EF_IF_BTDM_DIS EF_CTRL_EF_IF_BTDM_DIS
#define EF_CTRL_EF_IF_BTDM_DIS_POS (15U)
#define EF_CTRL_EF_IF_BTDM_DIS_LEN (1U)
#define EF_CTRL_EF_IF_BTDM_DIS_MSK (((1U << EF_CTRL_EF_IF_BTDM_DIS_LEN) - 1) << EF_CTRL_EF_IF_BTDM_DIS_POS)
#define EF_CTRL_EF_IF_BTDM_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_BTDM_DIS_LEN) - 1) << EF_CTRL_EF_IF_BTDM_DIS_POS))
#define EF_CTRL_EF_IF_WIFI_DIS EF_CTRL_EF_IF_WIFI_DIS
#define EF_CTRL_EF_IF_WIFI_DIS_POS (16U)
#define EF_CTRL_EF_IF_WIFI_DIS_LEN (1U)
#define EF_CTRL_EF_IF_WIFI_DIS_MSK (((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS)
#define EF_CTRL_EF_IF_WIFI_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS))
#define EF_CTRL_EF_IF_0_KEY_ENC_EN EF_CTRL_EF_IF_0_KEY_ENC_EN
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_POS (17U)
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN (1U)
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS)
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS))
#define EF_CTRL_EF_IF_CAM_DIS EF_CTRL_EF_IF_CAM_DIS
#define EF_CTRL_EF_IF_CAM_DIS_POS (18U)
#define EF_CTRL_EF_IF_CAM_DIS_LEN (1U)
#define EF_CTRL_EF_IF_CAM_DIS_MSK (((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS)
#define EF_CTRL_EF_IF_CAM_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS))
#define EF_CTRL_EF_IF_M154_DIS EF_CTRL_EF_IF_M154_DIS
#define EF_CTRL_EF_IF_M154_DIS_POS (19U)
#define EF_CTRL_EF_IF_M154_DIS_LEN (1U)
#define EF_CTRL_EF_IF_M154_DIS_MSK (((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS)
#define EF_CTRL_EF_IF_M154_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS))
#define EF_CTRL_EF_IF_CPU1_DIS EF_CTRL_EF_IF_CPU1_DIS
#define EF_CTRL_EF_IF_CPU1_DIS_POS (20U)
#define EF_CTRL_EF_IF_CPU1_DIS_LEN (1U)
#define EF_CTRL_EF_IF_CPU1_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS)
#define EF_CTRL_EF_IF_CPU1_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS))
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS EF_CTRL_EF_IF_CPU_RST_DBG_DIS
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS (21U)
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS)
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS))
#define EF_CTRL_EF_IF_SE_DBG_DIS EF_CTRL_EF_IF_SE_DBG_DIS
#define EF_CTRL_EF_IF_SE_DBG_DIS_POS (22U)
#define EF_CTRL_EF_IF_SE_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_IF_SE_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS)
#define EF_CTRL_EF_IF_SE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS))
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS EF_CTRL_EF_IF_EFUSE_DBG_DIS
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS (23U)
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS)
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS))
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS EF_CTRL_EF_IF_DBG_JTAG_1_DIS
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS (24U)
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN (2U)
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_MSK (((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS)
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS))
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS EF_CTRL_EF_IF_DBG_JTAG_0_DIS
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS (26U)
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN (2U)
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_MSK (((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS)
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS))
#define EF_CTRL_EF_IF_DBG_MODE EF_CTRL_EF_IF_DBG_MODE
#define EF_CTRL_EF_IF_DBG_MODE_POS (28U)
#define EF_CTRL_EF_IF_DBG_MODE_LEN (4U)
#define EF_CTRL_EF_IF_DBG_MODE_MSK (((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS)
#define EF_CTRL_EF_IF_DBG_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS))
/* 0x818 : ef_sw_cfg_0 */
#define EF_CTRL_EF_SW_CFG_0_OFFSET (0x818)
#define EF_CTRL_EF_SW_SF_AES_MODE EF_CTRL_EF_SW_SF_AES_MODE
#define EF_CTRL_EF_SW_SF_AES_MODE_POS (0U)
#define EF_CTRL_EF_SW_SF_AES_MODE_LEN (2U)
#define EF_CTRL_EF_SW_SF_AES_MODE_MSK (((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS)
#define EF_CTRL_EF_SW_SF_AES_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS))
#define EF_CTRL_EF_SW_AI_DIS EF_CTRL_EF_SW_AI_DIS
#define EF_CTRL_EF_SW_AI_DIS_POS (2U)
#define EF_CTRL_EF_SW_AI_DIS_LEN (1U)
#define EF_CTRL_EF_SW_AI_DIS_MSK (((1U << EF_CTRL_EF_SW_AI_DIS_LEN) - 1) << EF_CTRL_EF_SW_AI_DIS_POS)
#define EF_CTRL_EF_SW_AI_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_AI_DIS_LEN) - 1) << EF_CTRL_EF_SW_AI_DIS_POS))
#define EF_CTRL_EF_SW_CPU0_DIS EF_CTRL_EF_SW_CPU0_DIS
#define EF_CTRL_EF_SW_CPU0_DIS_POS (3U)
#define EF_CTRL_EF_SW_CPU0_DIS_LEN (1U)
#define EF_CTRL_EF_SW_CPU0_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU0_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU0_DIS_POS)
#define EF_CTRL_EF_SW_CPU0_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU0_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU0_DIS_POS))
#define EF_CTRL_EF_SW_SBOOT_EN EF_CTRL_EF_SW_SBOOT_EN
#define EF_CTRL_EF_SW_SBOOT_EN_POS (4U)
#define EF_CTRL_EF_SW_SBOOT_EN_LEN (2U)
#define EF_CTRL_EF_SW_SBOOT_EN_MSK (((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS)
#define EF_CTRL_EF_SW_SBOOT_EN_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS))
#define EF_CTRL_EF_SW_UART_DIS EF_CTRL_EF_SW_UART_DIS
#define EF_CTRL_EF_SW_UART_DIS_POS (6U)
#define EF_CTRL_EF_SW_UART_DIS_LEN (4U)
#define EF_CTRL_EF_SW_UART_DIS_MSK (((1U << EF_CTRL_EF_SW_UART_DIS_LEN) - 1) << EF_CTRL_EF_SW_UART_DIS_POS)
#define EF_CTRL_EF_SW_UART_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_UART_DIS_LEN) - 1) << EF_CTRL_EF_SW_UART_DIS_POS))
#define EF_CTRL_EF_SW_BLE2_DIS EF_CTRL_EF_SW_BLE2_DIS
#define EF_CTRL_EF_SW_BLE2_DIS_POS (10U)
#define EF_CTRL_EF_SW_BLE2_DIS_LEN (1U)
#define EF_CTRL_EF_SW_BLE2_DIS_MSK (((1U << EF_CTRL_EF_SW_BLE2_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE2_DIS_POS)
#define EF_CTRL_EF_SW_BLE2_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_BLE2_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE2_DIS_POS))
#define EF_CTRL_EF_SW_M1542_DIS EF_CTRL_EF_SW_M1542_DIS
#define EF_CTRL_EF_SW_M1542_DIS_POS (11U)
#define EF_CTRL_EF_SW_M1542_DIS_LEN (1U)
#define EF_CTRL_EF_SW_M1542_DIS_MSK (((1U << EF_CTRL_EF_SW_M1542_DIS_LEN) - 1) << EF_CTRL_EF_SW_M1542_DIS_POS)
#define EF_CTRL_EF_SW_M1542_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_M1542_DIS_LEN) - 1) << EF_CTRL_EF_SW_M1542_DIS_POS))
#define EF_CTRL_EF_SW_SF_KEY_RE_SEL EF_CTRL_EF_SW_SF_KEY_RE_SEL
#define EF_CTRL_EF_SW_SF_KEY_RE_SEL_POS (12U)
#define EF_CTRL_EF_SW_SF_KEY_RE_SEL_LEN (2U)
#define EF_CTRL_EF_SW_SF_KEY_RE_SEL_MSK (((1U << EF_CTRL_EF_SW_SF_KEY_RE_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_RE_SEL_POS)
#define EF_CTRL_EF_SW_SF_KEY_RE_SEL_UMSK (~(((1U << EF_CTRL_EF_SW_SF_KEY_RE_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_RE_SEL_POS))
#define EF_CTRL_EF_SW_SDU_DIS EF_CTRL_EF_SW_SDU_DIS
#define EF_CTRL_EF_SW_SDU_DIS_POS (14U)
#define EF_CTRL_EF_SW_SDU_DIS_LEN (1U)
#define EF_CTRL_EF_SW_SDU_DIS_MSK (((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS)
#define EF_CTRL_EF_SW_SDU_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS))
#define EF_CTRL_EF_SW_BTDM_DIS EF_CTRL_EF_SW_BTDM_DIS
#define EF_CTRL_EF_SW_BTDM_DIS_POS (15U)
#define EF_CTRL_EF_SW_BTDM_DIS_LEN (1U)
#define EF_CTRL_EF_SW_BTDM_DIS_MSK (((1U << EF_CTRL_EF_SW_BTDM_DIS_LEN) - 1) << EF_CTRL_EF_SW_BTDM_DIS_POS)
#define EF_CTRL_EF_SW_BTDM_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_BTDM_DIS_LEN) - 1) << EF_CTRL_EF_SW_BTDM_DIS_POS))
#define EF_CTRL_EF_SW_WIFI_DIS EF_CTRL_EF_SW_WIFI_DIS
#define EF_CTRL_EF_SW_WIFI_DIS_POS (16U)
#define EF_CTRL_EF_SW_WIFI_DIS_LEN (1U)
#define EF_CTRL_EF_SW_WIFI_DIS_MSK (((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS)
#define EF_CTRL_EF_SW_WIFI_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS))
#define EF_CTRL_EF_SW_0_KEY_ENC_EN EF_CTRL_EF_SW_0_KEY_ENC_EN
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_POS (17U)
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN (1U)
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS)
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS))
#define EF_CTRL_EF_SW_CAM_DIS EF_CTRL_EF_SW_CAM_DIS
#define EF_CTRL_EF_SW_CAM_DIS_POS (18U)
#define EF_CTRL_EF_SW_CAM_DIS_LEN (1U)
#define EF_CTRL_EF_SW_CAM_DIS_MSK (((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS)
#define EF_CTRL_EF_SW_CAM_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS))
#define EF_CTRL_EF_SW_M154_DIS EF_CTRL_EF_SW_M154_DIS
#define EF_CTRL_EF_SW_M154_DIS_POS (19U)
#define EF_CTRL_EF_SW_M154_DIS_LEN (1U)
#define EF_CTRL_EF_SW_M154_DIS_MSK (((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS)
#define EF_CTRL_EF_SW_M154_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS))
#define EF_CTRL_EF_SW_CPU1_DIS EF_CTRL_EF_SW_CPU1_DIS
#define EF_CTRL_EF_SW_CPU1_DIS_POS (20U)
#define EF_CTRL_EF_SW_CPU1_DIS_LEN (1U)
#define EF_CTRL_EF_SW_CPU1_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS)
#define EF_CTRL_EF_SW_CPU1_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS))
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS EF_CTRL_EF_SW_CPU_RST_DBG_DIS
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS (21U)
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS)
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS))
#define EF_CTRL_EF_SW_SE_DBG_DIS EF_CTRL_EF_SW_SE_DBG_DIS
#define EF_CTRL_EF_SW_SE_DBG_DIS_POS (22U)
#define EF_CTRL_EF_SW_SE_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_SW_SE_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS)
#define EF_CTRL_EF_SW_SE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS))
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS EF_CTRL_EF_SW_EFUSE_DBG_DIS
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS (23U)
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS)
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS))
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS EF_CTRL_EF_SW_DBG_JTAG_1_DIS
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS (24U)
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN (2U)
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_MSK (((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS)
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS))
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS EF_CTRL_EF_SW_DBG_JTAG_0_DIS
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS (26U)
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN (2U)
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_MSK (((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS)
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS))
#define EF_CTRL_EF_SW_DBG_MODE EF_CTRL_EF_SW_DBG_MODE
#define EF_CTRL_EF_SW_DBG_MODE_POS (28U)
#define EF_CTRL_EF_SW_DBG_MODE_LEN (4U)
#define EF_CTRL_EF_SW_DBG_MODE_MSK (((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS)
#define EF_CTRL_EF_SW_DBG_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS))
/* 0x81C : ef_reserved */
#define EF_CTRL_EF_RESERVED_OFFSET (0x81C)
#define EF_CTRL_EF_RESERVED EF_CTRL_EF_RESERVED
#define EF_CTRL_EF_RESERVED_POS (0U)
#define EF_CTRL_EF_RESERVED_LEN (32U)
#define EF_CTRL_EF_RESERVED_MSK (((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS)
#define EF_CTRL_EF_RESERVED_UMSK (~(((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS))
/* 0x820 : ef_if_sw_usage_0 */
#define EF_CTRL_EF_IF_SW_USAGE_0_OFFSET (0x820)
#define EF_CTRL_EF_IF_SW_USAGE_0 EF_CTRL_EF_IF_SW_USAGE_0
#define EF_CTRL_EF_IF_SW_USAGE_0_POS (0U)
#define EF_CTRL_EF_IF_SW_USAGE_0_LEN (32U)
#define EF_CTRL_EF_IF_SW_USAGE_0_MSK (((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS)
#define EF_CTRL_EF_IF_SW_USAGE_0_UMSK (~(((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS))
/* 0x824 : ef_if_sw_usage_1 */
#define EF_CTRL_EF_IF_SW_USAGE_1_OFFSET (0x824)
#define EF_CTRL_EF_IF_SW_USAGE_1 EF_CTRL_EF_IF_SW_USAGE_1
#define EF_CTRL_EF_IF_SW_USAGE_1_POS (0U)
#define EF_CTRL_EF_IF_SW_USAGE_1_LEN (32U)
#define EF_CTRL_EF_IF_SW_USAGE_1_MSK (((1U << EF_CTRL_EF_IF_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_1_POS)
#define EF_CTRL_EF_IF_SW_USAGE_1_UMSK (~(((1U << EF_CTRL_EF_IF_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_1_POS))
/* 0x900 : ef_if_ctrl_1 */
#define EF_CTRL_EF_IF_CTRL_1_OFFSET (0x900)
#define EF_CTRL_EF_IF_1_BUSY EF_CTRL_EF_IF_1_BUSY
#define EF_CTRL_EF_IF_1_BUSY_POS (2U)
#define EF_CTRL_EF_IF_1_BUSY_LEN (1U)
#define EF_CTRL_EF_IF_1_BUSY_MSK (((1U << EF_CTRL_EF_IF_1_BUSY_LEN) - 1) << EF_CTRL_EF_IF_1_BUSY_POS)
#define EF_CTRL_EF_IF_1_BUSY_UMSK (~(((1U << EF_CTRL_EF_IF_1_BUSY_LEN) - 1) << EF_CTRL_EF_IF_1_BUSY_POS))
#define EF_CTRL_EF_IF_1_RW EF_CTRL_EF_IF_1_RW
#define EF_CTRL_EF_IF_1_RW_POS (3U)
#define EF_CTRL_EF_IF_1_RW_LEN (1U)
#define EF_CTRL_EF_IF_1_RW_MSK (((1U << EF_CTRL_EF_IF_1_RW_LEN) - 1) << EF_CTRL_EF_IF_1_RW_POS)
#define EF_CTRL_EF_IF_1_RW_UMSK (~(((1U << EF_CTRL_EF_IF_1_RW_LEN) - 1) << EF_CTRL_EF_IF_1_RW_POS))
#define EF_CTRL_EF_IF_1_TRIG EF_CTRL_EF_IF_1_TRIG
#define EF_CTRL_EF_IF_1_TRIG_POS (4U)
#define EF_CTRL_EF_IF_1_TRIG_LEN (1U)
#define EF_CTRL_EF_IF_1_TRIG_MSK (((1U << EF_CTRL_EF_IF_1_TRIG_LEN) - 1) << EF_CTRL_EF_IF_1_TRIG_POS)
#define EF_CTRL_EF_IF_1_TRIG_UMSK (~(((1U << EF_CTRL_EF_IF_1_TRIG_LEN) - 1) << EF_CTRL_EF_IF_1_TRIG_POS))
#define EF_CTRL_EF_IF_1_MANUAL_EN EF_CTRL_EF_IF_1_MANUAL_EN
#define EF_CTRL_EF_IF_1_MANUAL_EN_POS (5U)
#define EF_CTRL_EF_IF_1_MANUAL_EN_LEN (1U)
#define EF_CTRL_EF_IF_1_MANUAL_EN_MSK (((1U << EF_CTRL_EF_IF_1_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_1_MANUAL_EN_POS)
#define EF_CTRL_EF_IF_1_MANUAL_EN_UMSK (~(((1U << EF_CTRL_EF_IF_1_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_1_MANUAL_EN_POS))
#define EF_CTRL_EF_IF_1_CYC_MODIFY EF_CTRL_EF_IF_1_CYC_MODIFY
#define EF_CTRL_EF_IF_1_CYC_MODIFY_POS (6U)
#define EF_CTRL_EF_IF_1_CYC_MODIFY_LEN (1U)
#define EF_CTRL_EF_IF_1_CYC_MODIFY_MSK (((1U << EF_CTRL_EF_IF_1_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_1_CYC_MODIFY_POS)
#define EF_CTRL_EF_IF_1_CYC_MODIFY_UMSK (~(((1U << EF_CTRL_EF_IF_1_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_1_CYC_MODIFY_POS))
#define EF_CTRL_EF_IF_1_INT EF_CTRL_EF_IF_1_INT
#define EF_CTRL_EF_IF_1_INT_POS (20U)
#define EF_CTRL_EF_IF_1_INT_LEN (1U)
#define EF_CTRL_EF_IF_1_INT_MSK (((1U << EF_CTRL_EF_IF_1_INT_LEN) - 1) << EF_CTRL_EF_IF_1_INT_POS)
#define EF_CTRL_EF_IF_1_INT_UMSK (~(((1U << EF_CTRL_EF_IF_1_INT_LEN) - 1) << EF_CTRL_EF_IF_1_INT_POS))
#define EF_CTRL_EF_IF_1_INT_CLR EF_CTRL_EF_IF_1_INT_CLR
#define EF_CTRL_EF_IF_1_INT_CLR_POS (21U)
#define EF_CTRL_EF_IF_1_INT_CLR_LEN (1U)
#define EF_CTRL_EF_IF_1_INT_CLR_MSK (((1U << EF_CTRL_EF_IF_1_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_1_INT_CLR_POS)
#define EF_CTRL_EF_IF_1_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_IF_1_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_1_INT_CLR_POS))
#define EF_CTRL_EF_IF_1_INT_SET EF_CTRL_EF_IF_1_INT_SET
#define EF_CTRL_EF_IF_1_INT_SET_POS (22U)
#define EF_CTRL_EF_IF_1_INT_SET_LEN (1U)
#define EF_CTRL_EF_IF_1_INT_SET_MSK (((1U << EF_CTRL_EF_IF_1_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_1_INT_SET_POS)
#define EF_CTRL_EF_IF_1_INT_SET_UMSK (~(((1U << EF_CTRL_EF_IF_1_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_1_INT_SET_POS))
/* 0x904 : ef_if_1_manual */
#define EF_CTRL_EF_IF_1_MANUAL_OFFSET (0x904)
#define EF_CTRL_EF_IF_1_Q EF_CTRL_EF_IF_1_Q
#define EF_CTRL_EF_IF_1_Q_POS (16U)
#define EF_CTRL_EF_IF_1_Q_LEN (8U)
#define EF_CTRL_EF_IF_1_Q_MSK (((1U << EF_CTRL_EF_IF_1_Q_LEN) - 1) << EF_CTRL_EF_IF_1_Q_POS)
#define EF_CTRL_EF_IF_1_Q_UMSK (~(((1U << EF_CTRL_EF_IF_1_Q_LEN) - 1) << EF_CTRL_EF_IF_1_Q_POS))
/* 0x908 : ef_if_1_status */
#define EF_CTRL_EF_IF_1_STATUS_OFFSET (0x908)
#define EF_CTRL_EF_IF_1_STATUS EF_CTRL_EF_IF_1_STATUS
#define EF_CTRL_EF_IF_1_STATUS_POS (0U)
#define EF_CTRL_EF_IF_1_STATUS_LEN (32U)
#define EF_CTRL_EF_IF_1_STATUS_MSK (((1U << EF_CTRL_EF_IF_1_STATUS_LEN) - 1) << EF_CTRL_EF_IF_1_STATUS_POS)
#define EF_CTRL_EF_IF_1_STATUS_UMSK (~(((1U << EF_CTRL_EF_IF_1_STATUS_LEN) - 1) << EF_CTRL_EF_IF_1_STATUS_POS))
/* 0x910 : ef_if_ctrl_2 */
#define EF_CTRL_EF_IF_CTRL_2_OFFSET (0x910)
/* 0x914 : ef_if_2_manual */
#define EF_CTRL_EF_IF_2_MANUAL_OFFSET (0x914)
/* 0x918 : ef_if_2_status */
#define EF_CTRL_EF_IF_2_STATUS_OFFSET (0x918)
/* 0xA00 : ef_crc_ctrl_0 */
#define EF_CTRL_EF_CRC_CTRL_0_OFFSET (0xA00)
#define EF_CTRL_EF_CRC_BUSY EF_CTRL_EF_CRC_BUSY
#define EF_CTRL_EF_CRC_BUSY_POS (0U)
#define EF_CTRL_EF_CRC_BUSY_LEN (1U)
#define EF_CTRL_EF_CRC_BUSY_MSK (((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS)
#define EF_CTRL_EF_CRC_BUSY_UMSK (~(((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS))
#define EF_CTRL_EF_CRC_TRIG EF_CTRL_EF_CRC_TRIG
#define EF_CTRL_EF_CRC_TRIG_POS (1U)
#define EF_CTRL_EF_CRC_TRIG_LEN (1U)
#define EF_CTRL_EF_CRC_TRIG_MSK (((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS)
#define EF_CTRL_EF_CRC_TRIG_UMSK (~(((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS))
#define EF_CTRL_EF_CRC_EN EF_CTRL_EF_CRC_EN
#define EF_CTRL_EF_CRC_EN_POS (2U)
#define EF_CTRL_EF_CRC_EN_LEN (1U)
#define EF_CTRL_EF_CRC_EN_MSK (((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS)
#define EF_CTRL_EF_CRC_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS))
#define EF_CTRL_EF_CRC_MODE EF_CTRL_EF_CRC_MODE
#define EF_CTRL_EF_CRC_MODE_POS (3U)
#define EF_CTRL_EF_CRC_MODE_LEN (1U)
#define EF_CTRL_EF_CRC_MODE_MSK (((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS)
#define EF_CTRL_EF_CRC_MODE_UMSK (~(((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS))
#define EF_CTRL_EF_CRC_ERROR EF_CTRL_EF_CRC_ERROR
#define EF_CTRL_EF_CRC_ERROR_POS (4U)
#define EF_CTRL_EF_CRC_ERROR_LEN (1U)
#define EF_CTRL_EF_CRC_ERROR_MSK (((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS)
#define EF_CTRL_EF_CRC_ERROR_UMSK (~(((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS))
#define EF_CTRL_EF_CRC_DOUT_INV_EN EF_CTRL_EF_CRC_DOUT_INV_EN
#define EF_CTRL_EF_CRC_DOUT_INV_EN_POS (5U)
#define EF_CTRL_EF_CRC_DOUT_INV_EN_LEN (1U)
#define EF_CTRL_EF_CRC_DOUT_INV_EN_MSK (((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS)
#define EF_CTRL_EF_CRC_DOUT_INV_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS))
#define EF_CTRL_EF_CRC_DOUT_ENDIAN EF_CTRL_EF_CRC_DOUT_ENDIAN
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_POS (6U)
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN (1U)
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_MSK (((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS)
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS))
#define EF_CTRL_EF_CRC_DIN_ENDIAN EF_CTRL_EF_CRC_DIN_ENDIAN
#define EF_CTRL_EF_CRC_DIN_ENDIAN_POS (7U)
#define EF_CTRL_EF_CRC_DIN_ENDIAN_LEN (1U)
#define EF_CTRL_EF_CRC_DIN_ENDIAN_MSK (((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS)
#define EF_CTRL_EF_CRC_DIN_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS))
#define EF_CTRL_EF_CRC_INT EF_CTRL_EF_CRC_INT
#define EF_CTRL_EF_CRC_INT_POS (8U)
#define EF_CTRL_EF_CRC_INT_LEN (1U)
#define EF_CTRL_EF_CRC_INT_MSK (((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS)
#define EF_CTRL_EF_CRC_INT_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS))
#define EF_CTRL_EF_CRC_INT_CLR EF_CTRL_EF_CRC_INT_CLR
#define EF_CTRL_EF_CRC_INT_CLR_POS (9U)
#define EF_CTRL_EF_CRC_INT_CLR_LEN (1U)
#define EF_CTRL_EF_CRC_INT_CLR_MSK (((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS)
#define EF_CTRL_EF_CRC_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS))
#define EF_CTRL_EF_CRC_INT_SET EF_CTRL_EF_CRC_INT_SET
#define EF_CTRL_EF_CRC_INT_SET_POS (10U)
#define EF_CTRL_EF_CRC_INT_SET_LEN (1U)
#define EF_CTRL_EF_CRC_INT_SET_MSK (((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS)
#define EF_CTRL_EF_CRC_INT_SET_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS))
#define EF_CTRL_EF_CRC_LOCK EF_CTRL_EF_CRC_LOCK
#define EF_CTRL_EF_CRC_LOCK_POS (11U)
#define EF_CTRL_EF_CRC_LOCK_LEN (1U)
#define EF_CTRL_EF_CRC_LOCK_MSK (((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS)
#define EF_CTRL_EF_CRC_LOCK_UMSK (~(((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS))
#define EF_CTRL_EF_CRC_SLP_N EF_CTRL_EF_CRC_SLP_N
#define EF_CTRL_EF_CRC_SLP_N_POS (16U)
#define EF_CTRL_EF_CRC_SLP_N_LEN (16U)
#define EF_CTRL_EF_CRC_SLP_N_MSK (((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS)
#define EF_CTRL_EF_CRC_SLP_N_UMSK (~(((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS))
/* 0xA04 : ef_crc_ctrl_1 */
#define EF_CTRL_EF_CRC_CTRL_1_OFFSET (0xA04)
#define EF_CTRL_EF_CRC_DATA_0_EN EF_CTRL_EF_CRC_DATA_0_EN
#define EF_CTRL_EF_CRC_DATA_0_EN_POS (0U)
#define EF_CTRL_EF_CRC_DATA_0_EN_LEN (32U)
#define EF_CTRL_EF_CRC_DATA_0_EN_MSK (((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS)
#define EF_CTRL_EF_CRC_DATA_0_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS))
/* 0xA08 : ef_crc_ctrl_2 */
#define EF_CTRL_EF_CRC_CTRL_2_OFFSET (0xA08)
#define EF_CTRL_EF_CRC_DATA_1_EN EF_CTRL_EF_CRC_DATA_1_EN
#define EF_CTRL_EF_CRC_DATA_1_EN_POS (0U)
#define EF_CTRL_EF_CRC_DATA_1_EN_LEN (32U)
#define EF_CTRL_EF_CRC_DATA_1_EN_MSK (((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS)
#define EF_CTRL_EF_CRC_DATA_1_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS))
/* 0xA0C : ef_crc_ctrl_3 */
#define EF_CTRL_EF_CRC_CTRL_3_OFFSET (0xA0C)
#define EF_CTRL_EF_CRC_IV EF_CTRL_EF_CRC_IV
#define EF_CTRL_EF_CRC_IV_POS (0U)
#define EF_CTRL_EF_CRC_IV_LEN (32U)
#define EF_CTRL_EF_CRC_IV_MSK (((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS)
#define EF_CTRL_EF_CRC_IV_UMSK (~(((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS))
/* 0xA10 : ef_crc_ctrl_4 */
#define EF_CTRL_EF_CRC_CTRL_4_OFFSET (0xA10)
#define EF_CTRL_EF_CRC_GOLDEN EF_CTRL_EF_CRC_GOLDEN
#define EF_CTRL_EF_CRC_GOLDEN_POS (0U)
#define EF_CTRL_EF_CRC_GOLDEN_LEN (32U)
#define EF_CTRL_EF_CRC_GOLDEN_MSK (((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS)
#define EF_CTRL_EF_CRC_GOLDEN_UMSK (~(((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS))
/* 0xA14 : ef_crc_ctrl_5 */
#define EF_CTRL_EF_CRC_CTRL_5_OFFSET (0xA14)
#define EF_CTRL_EF_CRC_DOUT EF_CTRL_EF_CRC_DOUT
#define EF_CTRL_EF_CRC_DOUT_POS (0U)
#define EF_CTRL_EF_CRC_DOUT_LEN (32U)
#define EF_CTRL_EF_CRC_DOUT_MSK (((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS)
#define EF_CTRL_EF_CRC_DOUT_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS))
struct ef_ctrl_reg {
/* 0x0 reserved */
uint8_t RESERVED0x0[2048];
/* 0x800 : ef_if_ctrl_0 */
union {
struct {
uint32_t ef_if_0_autoload_p1_done : 1; /* [ 0], r, 0x1 */
uint32_t ef_if_0_autoload_done : 1; /* [ 1], r, 0x1 */
uint32_t ef_if_0_busy : 1; /* [ 2], r, 0x0 */
uint32_t ef_if_0_rw : 1; /* [ 3], r/w, 0x0 */
uint32_t ef_if_0_trig : 1; /* [ 4], r/w, 0x0 */
uint32_t ef_if_0_manual_en : 1; /* [ 5], r/w, 0x0 */
uint32_t ef_if_0_cyc_modify : 1; /* [ 6], r/w, 0x0 */
uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t ef_if_prot_code_ctrl : 8; /* [15: 8], r/w, 0x0 */
uint32_t ef_if_por_dig : 1; /* [ 16], r/w, 0x0 */
uint32_t ef_pclk_force_on : 1; /* [ 17], r/w, 0x0 */
uint32_t ef_if_auto_rd_en : 1; /* [ 18], r/w, 0x1 */
uint32_t ef_if_cyc_modify_lock : 1; /* [ 19], r/w, 0x0 */
uint32_t ef_if_0_int : 1; /* [ 20], r, 0x0 */
uint32_t ef_if_0_int_clr : 1; /* [ 21], r/w, 0x1 */
uint32_t ef_if_0_int_set : 1; /* [ 22], r/w, 0x0 */
uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
uint32_t ef_if_prot_code_cyc : 8; /* [31:24], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_if_ctrl_0;
/* 0x804 : ef_if_cyc_0 */
union {
struct {
uint32_t ef_if_cyc_rd_dmy : 6; /* [ 5: 0], r/w, 0x0 */
uint32_t ef_if_cyc_rd_dat : 6; /* [11: 6], r/w, 0x1 */
uint32_t ef_if_cyc_rd_adr : 6; /* [17:12], r/w, 0x0 */
uint32_t ef_if_cyc_cs : 6; /* [23:18], r/w, 0x0 */
uint32_t ef_if_cyc_pd_cs_s : 8; /* [31:24], r/w, 0x16 */
} BF;
uint32_t WORD;
} ef_if_cyc_0;
/* 0x808 : ef_if_cyc_1 */
union {
struct {
uint32_t ef_if_cyc_pi : 6; /* [ 5: 0], r/w, 0x9 */
uint32_t ef_if_cyc_pp : 8; /* [13: 6], r/w, 0x98 */
uint32_t ef_if_cyc_wr_adr : 6; /* [19:14], r/w, 0x1 */
uint32_t ef_if_cyc_ps_cs : 6; /* [25:20], r/w, 0x2 */
uint32_t ef_if_cyc_pd_cs_h : 6; /* [31:26], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_if_cyc_1;
/* 0x80C : ef_if_0_manual */
union {
struct {
uint32_t ef_if_a : 10; /* [ 9: 0], r/w, 0x0 */
uint32_t ef_if_pd : 1; /* [ 10], r/w, 0x1 */
uint32_t ef_if_ps : 1; /* [ 11], r/w, 0x0 */
uint32_t ef_if_strobe : 1; /* [ 12], r/w, 0x0 */
uint32_t ef_if_pgenb : 1; /* [ 13], r/w, 0x1 */
uint32_t ef_if_load : 1; /* [ 14], r/w, 0x1 */
uint32_t ef_if_csb : 1; /* [ 15], r/w, 0x1 */
uint32_t ef_if_0_q : 8; /* [23:16], r, 0x0 */
uint32_t ef_if_prot_code_manual : 8; /* [31:24], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_if_0_manual;
/* 0x810 : ef_if_0_status */
union {
struct {
uint32_t ef_if_0_status : 32; /* [31: 0], r, 0xe400 */
} BF;
uint32_t WORD;
} ef_if_0_status;
/* 0x814 : ef_if_cfg_0 */
union {
struct {
uint32_t ef_if_sf_aes_mode : 2; /* [ 1: 0], r, 0x0 */
uint32_t ef_if_ai_dis : 1; /* [ 2], r, 0x0 */
uint32_t ef_if_cpu0_dis : 1; /* [ 3], r, 0x0 */
uint32_t ef_if_sboot_en : 2; /* [ 5: 4], r, 0x0 */
uint32_t ef_if_uart_dis : 4; /* [ 9: 6], r, 0x0 */
uint32_t ef_if_ble2_dis : 1; /* [ 10], r, 0x0 */
uint32_t ef_if_m1542_dis : 1; /* [ 11], r, 0x0 */
uint32_t ef_if_sf_key_re_sel : 2; /* [13:12], r, 0x0 */
uint32_t ef_if_sdu_dis : 1; /* [ 14], r, 0x0 */
uint32_t ef_if_btdm_dis : 1; /* [ 15], r, 0x0 */
uint32_t ef_if_wifi_dis : 1; /* [ 16], r, 0x0 */
uint32_t ef_if_0_key_enc_en : 1; /* [ 17], r, 0x0 */
uint32_t ef_if_cam_dis : 1; /* [ 18], r, 0x0 */
uint32_t ef_if_m154_dis : 1; /* [ 19], r, 0x0 */
uint32_t ef_if_cpu1_dis : 1; /* [ 20], r, 0x0 */
uint32_t ef_if_cpu_rst_dbg_dis : 1; /* [ 21], r, 0x0 */
uint32_t ef_if_se_dbg_dis : 1; /* [ 22], r, 0x0 */
uint32_t ef_if_efuse_dbg_dis : 1; /* [ 23], r, 0x0 */
uint32_t ef_if_dbg_jtag_1_dis : 2; /* [25:24], r, 0x0 */
uint32_t ef_if_dbg_jtag_0_dis : 2; /* [27:26], r, 0x0 */
uint32_t ef_if_dbg_mode : 4; /* [31:28], r, 0x0 */
} BF;
uint32_t WORD;
} ef_if_cfg_0;
/* 0x818 : ef_sw_cfg_0 */
union {
struct {
uint32_t ef_sw_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t ef_sw_ai_dis : 1; /* [ 2], r/w, 0x0 */
uint32_t ef_sw_cpu0_dis : 1; /* [ 3], r/w, 0x0 */
uint32_t ef_sw_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t ef_sw_uart_dis : 4; /* [ 9: 6], r/w, 0x0 */
uint32_t ef_sw_ble2_dis : 1; /* [ 10], r/w, 0x0 */
uint32_t ef_sw_m1542_dis : 1; /* [ 11], r/w, 0x0 */
uint32_t ef_sw_sf_key_re_sel : 2; /* [13:12], r/w, 0x0 */
uint32_t ef_sw_sdu_dis : 1; /* [ 14], r/w, 0x0 */
uint32_t ef_sw_btdm_dis : 1; /* [ 15], r/w, 0x0 */
uint32_t ef_sw_wifi_dis : 1; /* [ 16], r/w, 0x0 */
uint32_t ef_sw_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */
uint32_t ef_sw_cam_dis : 1; /* [ 18], r/w, 0x0 */
uint32_t ef_sw_m154_dis : 1; /* [ 19], r/w, 0x0 */
uint32_t ef_sw_cpu1_dis : 1; /* [ 20], r/w, 0x0 */
uint32_t ef_sw_cpu_rst_dbg_dis : 1; /* [ 21], r/w, 0x0 */
uint32_t ef_sw_se_dbg_dis : 1; /* [ 22], r/w, 0x0 */
uint32_t ef_sw_efuse_dbg_dis : 1; /* [ 23], r/w, 0x0 */
uint32_t ef_sw_dbg_jtag_1_dis : 2; /* [25:24], r/w, 0x0 */
uint32_t ef_sw_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */
uint32_t ef_sw_dbg_mode : 4; /* [31:28], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_sw_cfg_0;
/* 0x81C : ef_reserved */
union {
struct {
uint32_t ef_reserved : 32; /* [31: 0], r/w, 0xffff */
} BF;
uint32_t WORD;
} ef_reserved;
/* 0x820 : ef_if_sw_usage_0 */
union {
struct {
uint32_t ef_if_sw_usage_0 : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} ef_if_sw_usage_0;
/* 0x824 : ef_if_sw_usage_1 */
union {
struct {
uint32_t ef_if_sw_usage_1 : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} ef_if_sw_usage_1;
/* 0x828 reserved */
uint8_t RESERVED0x828[216];
/* 0x900 : ef_if_ctrl_1 */
union {
struct {
uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
uint32_t ef_if_1_busy : 1; /* [ 2], r, 0x0 */
uint32_t ef_if_1_rw : 1; /* [ 3], r/w, 0x0 */
uint32_t ef_if_1_trig : 1; /* [ 4], r/w, 0x0 */
uint32_t ef_if_1_manual_en : 1; /* [ 5], r/w, 0x0 */
uint32_t ef_if_1_cyc_modify : 1; /* [ 6], r/w, 0x0 */
uint32_t reserved_7_19 : 13; /* [19: 7], rsvd, 0x0 */
uint32_t ef_if_1_int : 1; /* [ 20], r, 0x0 */
uint32_t ef_if_1_int_clr : 1; /* [ 21], r/w, 0x1 */
uint32_t ef_if_1_int_set : 1; /* [ 22], r/w, 0x0 */
uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */
} BF;
uint32_t WORD;
} ef_if_ctrl_1;
/* 0x904 : ef_if_1_manual */
union {
struct {
uint32_t reserved_0_15 : 16; /* [15: 0], rsvd, 0x0 */
uint32_t ef_if_1_q : 8; /* [23:16], r, 0x0 */
uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
} BF;
uint32_t WORD;
} ef_if_1_manual;
/* 0x908 : ef_if_1_status */
union {
struct {
uint32_t ef_if_1_status : 32; /* [31: 0], r, 0xe400 */
} BF;
uint32_t WORD;
} ef_if_1_status;
/* 0x90c reserved */
uint8_t RESERVED0x90c[4];
/* 0x910 : ef_if_ctrl_2 */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
} BF;
uint32_t WORD;
} ef_if_ctrl_2;
/* 0x914 : ef_if_2_manual */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
} BF;
uint32_t WORD;
} ef_if_2_manual;
/* 0x918 : ef_if_2_status */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
} BF;
uint32_t WORD;
} ef_if_2_status;
/* 0x91c reserved */
uint8_t RESERVED0x91c[228];
/* 0xA00 : ef_crc_ctrl_0 */
union {
struct {
uint32_t ef_crc_busy : 1; /* [ 0], r, 0x0 */
uint32_t ef_crc_trig : 1; /* [ 1], r/w, 0x0 */
uint32_t ef_crc_en : 1; /* [ 2], r/w, 0x1 */
uint32_t ef_crc_mode : 1; /* [ 3], r/w, 0x0 */
uint32_t ef_crc_error : 1; /* [ 4], r, 0x0 */
uint32_t ef_crc_dout_inv_en : 1; /* [ 5], r/w, 0x1 */
uint32_t ef_crc_dout_endian : 1; /* [ 6], r/w, 0x0 */
uint32_t ef_crc_din_endian : 1; /* [ 7], r/w, 0x0 */
uint32_t ef_crc_int : 1; /* [ 8], r, 0x0 */
uint32_t ef_crc_int_clr : 1; /* [ 9], r/w, 0x1 */
uint32_t ef_crc_int_set : 1; /* [ 10], r/w, 0x0 */
uint32_t ef_crc_lock : 1; /* [ 11], r/w, 0x0 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t ef_crc_slp_n : 16; /* [31:16], r/w, 0xff */
} BF;
uint32_t WORD;
} ef_crc_ctrl_0;
/* 0xA04 : ef_crc_ctrl_1 */
union {
struct {
uint32_t ef_crc_data_0_en : 32; /* [31: 0], r/w, 0xffffffffL */
} BF;
uint32_t WORD;
} ef_crc_ctrl_1;
/* 0xA08 : ef_crc_ctrl_2 */
union {
struct {
uint32_t ef_crc_data_1_en : 32; /* [31: 0], r/w, 0xffffffffL */
} BF;
uint32_t WORD;
} ef_crc_ctrl_2;
/* 0xA0C : ef_crc_ctrl_3 */
union {
struct {
uint32_t ef_crc_iv : 32; /* [31: 0], r/w, 0xffffffffL */
} BF;
uint32_t WORD;
} ef_crc_ctrl_3;
/* 0xA10 : ef_crc_ctrl_4 */
union {
struct {
uint32_t ef_crc_golden : 32; /* [31: 0], r/w, 0xc2a8fa9dL */
} BF;
uint32_t WORD;
} ef_crc_ctrl_4;
/* 0xA14 : ef_crc_ctrl_5 */
union {
struct {
uint32_t ef_crc_dout : 32; /* [31: 0], r, 0xffffffffL */
} BF;
uint32_t WORD;
} ef_crc_ctrl_5;
};
#endif /* __EF_CTRL_REG_H__ */

795
include/bl808/ef_data_0_reg.h Normal file
View File

@ -0,0 +1,795 @@
/**
******************************************************************************
* @file ef_data_0_reg.h
* @version V1.0
* @date 2021-07-31
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __EF_DATA_0_REG_H__
#define __EF_DATA_0_REG_H__
#include <linux/types.h>
/* 0x0 : ef_cfg_0 */
#define EF_DATA_0_EF_CFG_0_OFFSET (0x0)
#define EF_DATA_0_EF_SF_AES_MODE EF_DATA_0_EF_SF_AES_MODE
#define EF_DATA_0_EF_SF_AES_MODE_POS (0U)
#define EF_DATA_0_EF_SF_AES_MODE_LEN (2U)
#define EF_DATA_0_EF_SF_AES_MODE_MSK (((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS)
#define EF_DATA_0_EF_SF_AES_MODE_UMSK (~(((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS))
#define EF_DATA_0_EF_AI_DIS EF_DATA_0_EF_AI_DIS
#define EF_DATA_0_EF_AI_DIS_POS (2U)
#define EF_DATA_0_EF_AI_DIS_LEN (1U)
#define EF_DATA_0_EF_AI_DIS_MSK (((1U << EF_DATA_0_EF_AI_DIS_LEN) - 1) << EF_DATA_0_EF_AI_DIS_POS)
#define EF_DATA_0_EF_AI_DIS_UMSK (~(((1U << EF_DATA_0_EF_AI_DIS_LEN) - 1) << EF_DATA_0_EF_AI_DIS_POS))
#define EF_DATA_0_EF_CPU0_DIS EF_DATA_0_EF_CPU0_DIS
#define EF_DATA_0_EF_CPU0_DIS_POS (3U)
#define EF_DATA_0_EF_CPU0_DIS_LEN (1U)
#define EF_DATA_0_EF_CPU0_DIS_MSK (((1U << EF_DATA_0_EF_CPU0_DIS_LEN) - 1) << EF_DATA_0_EF_CPU0_DIS_POS)
#define EF_DATA_0_EF_CPU0_DIS_UMSK (~(((1U << EF_DATA_0_EF_CPU0_DIS_LEN) - 1) << EF_DATA_0_EF_CPU0_DIS_POS))
#define EF_DATA_0_EF_SBOOT_EN EF_DATA_0_EF_SBOOT_EN
#define EF_DATA_0_EF_SBOOT_EN_POS (4U)
#define EF_DATA_0_EF_SBOOT_EN_LEN (2U)
#define EF_DATA_0_EF_SBOOT_EN_MSK (((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS)
#define EF_DATA_0_EF_SBOOT_EN_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS))
#define EF_DATA_0_EF_UART_DIS EF_DATA_0_EF_UART_DIS
#define EF_DATA_0_EF_UART_DIS_POS (6U)
#define EF_DATA_0_EF_UART_DIS_LEN (4U)
#define EF_DATA_0_EF_UART_DIS_MSK (((1U << EF_DATA_0_EF_UART_DIS_LEN) - 1) << EF_DATA_0_EF_UART_DIS_POS)
#define EF_DATA_0_EF_UART_DIS_UMSK (~(((1U << EF_DATA_0_EF_UART_DIS_LEN) - 1) << EF_DATA_0_EF_UART_DIS_POS))
#define EF_DATA_0_EF_NO_XTAL EF_DATA_0_EF_NO_XTAL
#define EF_DATA_0_EF_NO_XTAL_POS (10U)
#define EF_DATA_0_EF_NO_XTAL_LEN (1U)
#define EF_DATA_0_EF_NO_XTAL_MSK (((1U << EF_DATA_0_EF_NO_XTAL_LEN) - 1) << EF_DATA_0_EF_NO_XTAL_POS)
#define EF_DATA_0_EF_NO_XTAL_UMSK (~(((1U << EF_DATA_0_EF_NO_XTAL_LEN) - 1) << EF_DATA_0_EF_NO_XTAL_POS))
#define EF_DATA_0_EF_FORCE_NO_TRIM EF_DATA_0_EF_FORCE_NO_TRIM
#define EF_DATA_0_EF_FORCE_NO_TRIM_POS (11U)
#define EF_DATA_0_EF_FORCE_NO_TRIM_LEN (1U)
#define EF_DATA_0_EF_FORCE_NO_TRIM_MSK (((1U << EF_DATA_0_EF_FORCE_NO_TRIM_LEN) - 1) << EF_DATA_0_EF_FORCE_NO_TRIM_POS)
#define EF_DATA_0_EF_FORCE_NO_TRIM_UMSK (~(((1U << EF_DATA_0_EF_FORCE_NO_TRIM_LEN) - 1) << EF_DATA_0_EF_FORCE_NO_TRIM_POS))
#define EF_DATA_0_EF_SF_KEY_RE_SEL EF_DATA_0_EF_SF_KEY_RE_SEL
#define EF_DATA_0_EF_SF_KEY_RE_SEL_POS (12U)
#define EF_DATA_0_EF_SF_KEY_RE_SEL_LEN (2U)
#define EF_DATA_0_EF_SF_KEY_RE_SEL_MSK (((1U << EF_DATA_0_EF_SF_KEY_RE_SEL_LEN) - 1) << EF_DATA_0_EF_SF_KEY_RE_SEL_POS)
#define EF_DATA_0_EF_SF_KEY_RE_SEL_UMSK (~(((1U << EF_DATA_0_EF_SF_KEY_RE_SEL_LEN) - 1) << EF_DATA_0_EF_SF_KEY_RE_SEL_POS))
#define EF_DATA_0_EF_SDU_DIS EF_DATA_0_EF_SDU_DIS
#define EF_DATA_0_EF_SDU_DIS_POS (14U)
#define EF_DATA_0_EF_SDU_DIS_LEN (1U)
#define EF_DATA_0_EF_SDU_DIS_MSK (((1U << EF_DATA_0_EF_SDU_DIS_LEN) - 1) << EF_DATA_0_EF_SDU_DIS_POS)
#define EF_DATA_0_EF_SDU_DIS_UMSK (~(((1U << EF_DATA_0_EF_SDU_DIS_LEN) - 1) << EF_DATA_0_EF_SDU_DIS_POS))
#define EF_DATA_0_EF_BTDM_DIS EF_DATA_0_EF_BTDM_DIS
#define EF_DATA_0_EF_BTDM_DIS_POS (15U)
#define EF_DATA_0_EF_BTDM_DIS_LEN (1U)
#define EF_DATA_0_EF_BTDM_DIS_MSK (((1U << EF_DATA_0_EF_BTDM_DIS_LEN) - 1) << EF_DATA_0_EF_BTDM_DIS_POS)
#define EF_DATA_0_EF_BTDM_DIS_UMSK (~(((1U << EF_DATA_0_EF_BTDM_DIS_LEN) - 1) << EF_DATA_0_EF_BTDM_DIS_POS))
#define EF_DATA_0_EF_WIFI_DIS EF_DATA_0_EF_WIFI_DIS
#define EF_DATA_0_EF_WIFI_DIS_POS (16U)
#define EF_DATA_0_EF_WIFI_DIS_LEN (1U)
#define EF_DATA_0_EF_WIFI_DIS_MSK (((1U << EF_DATA_0_EF_WIFI_DIS_LEN) - 1) << EF_DATA_0_EF_WIFI_DIS_POS)
#define EF_DATA_0_EF_WIFI_DIS_UMSK (~(((1U << EF_DATA_0_EF_WIFI_DIS_LEN) - 1) << EF_DATA_0_EF_WIFI_DIS_POS))
#define EF_DATA_0_EF_0_KEY_ENC_EN EF_DATA_0_EF_0_KEY_ENC_EN
#define EF_DATA_0_EF_0_KEY_ENC_EN_POS (17U)
#define EF_DATA_0_EF_0_KEY_ENC_EN_LEN (1U)
#define EF_DATA_0_EF_0_KEY_ENC_EN_MSK (((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS)
#define EF_DATA_0_EF_0_KEY_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS))
#define EF_DATA_0_EF_CAM_DIS EF_DATA_0_EF_CAM_DIS
#define EF_DATA_0_EF_CAM_DIS_POS (18U)
#define EF_DATA_0_EF_CAM_DIS_LEN (1U)
#define EF_DATA_0_EF_CAM_DIS_MSK (((1U << EF_DATA_0_EF_CAM_DIS_LEN) - 1) << EF_DATA_0_EF_CAM_DIS_POS)
#define EF_DATA_0_EF_CAM_DIS_UMSK (~(((1U << EF_DATA_0_EF_CAM_DIS_LEN) - 1) << EF_DATA_0_EF_CAM_DIS_POS))
#define EF_DATA_0_EF_M154_DIS EF_DATA_0_EF_M154_DIS
#define EF_DATA_0_EF_M154_DIS_POS (19U)
#define EF_DATA_0_EF_M154_DIS_LEN (1U)
#define EF_DATA_0_EF_M154_DIS_MSK (((1U << EF_DATA_0_EF_M154_DIS_LEN) - 1) << EF_DATA_0_EF_M154_DIS_POS)
#define EF_DATA_0_EF_M154_DIS_UMSK (~(((1U << EF_DATA_0_EF_M154_DIS_LEN) - 1) << EF_DATA_0_EF_M154_DIS_POS))
#define EF_DATA_0_EF_CPU1_DIS EF_DATA_0_EF_CPU1_DIS
#define EF_DATA_0_EF_CPU1_DIS_POS (20U)
#define EF_DATA_0_EF_CPU1_DIS_LEN (1U)
#define EF_DATA_0_EF_CPU1_DIS_MSK (((1U << EF_DATA_0_EF_CPU1_DIS_LEN) - 1) << EF_DATA_0_EF_CPU1_DIS_POS)
#define EF_DATA_0_EF_CPU1_DIS_UMSK (~(((1U << EF_DATA_0_EF_CPU1_DIS_LEN) - 1) << EF_DATA_0_EF_CPU1_DIS_POS))
#define EF_DATA_0_EF_CPU_RST_DBG_DIS EF_DATA_0_EF_CPU_RST_DBG_DIS
#define EF_DATA_0_EF_CPU_RST_DBG_DIS_POS (21U)
#define EF_DATA_0_EF_CPU_RST_DBG_DIS_LEN (1U)
#define EF_DATA_0_EF_CPU_RST_DBG_DIS_MSK (((1U << EF_DATA_0_EF_CPU_RST_DBG_DIS_LEN) - 1) << EF_DATA_0_EF_CPU_RST_DBG_DIS_POS)
#define EF_DATA_0_EF_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_DATA_0_EF_CPU_RST_DBG_DIS_LEN) - 1) << EF_DATA_0_EF_CPU_RST_DBG_DIS_POS))
#define EF_DATA_0_EF_SE_DBG_DIS EF_DATA_0_EF_SE_DBG_DIS
#define EF_DATA_0_EF_SE_DBG_DIS_POS (22U)
#define EF_DATA_0_EF_SE_DBG_DIS_LEN (1U)
#define EF_DATA_0_EF_SE_DBG_DIS_MSK (((1U << EF_DATA_0_EF_SE_DBG_DIS_LEN) - 1) << EF_DATA_0_EF_SE_DBG_DIS_POS)
#define EF_DATA_0_EF_SE_DBG_DIS_UMSK (~(((1U << EF_DATA_0_EF_SE_DBG_DIS_LEN) - 1) << EF_DATA_0_EF_SE_DBG_DIS_POS))
#define EF_DATA_0_EF_EFUSE_DBG_DIS EF_DATA_0_EF_EFUSE_DBG_DIS
#define EF_DATA_0_EF_EFUSE_DBG_DIS_POS (23U)
#define EF_DATA_0_EF_EFUSE_DBG_DIS_LEN (1U)
#define EF_DATA_0_EF_EFUSE_DBG_DIS_MSK (((1U << EF_DATA_0_EF_EFUSE_DBG_DIS_LEN) - 1) << EF_DATA_0_EF_EFUSE_DBG_DIS_POS)
#define EF_DATA_0_EF_EFUSE_DBG_DIS_UMSK (~(((1U << EF_DATA_0_EF_EFUSE_DBG_DIS_LEN) - 1) << EF_DATA_0_EF_EFUSE_DBG_DIS_POS))
#define EF_DATA_0_EF_DBG_JTAG_1_DIS EF_DATA_0_EF_DBG_JTAG_1_DIS
#define EF_DATA_0_EF_DBG_JTAG_1_DIS_POS (24U)
#define EF_DATA_0_EF_DBG_JTAG_1_DIS_LEN (2U)
#define EF_DATA_0_EF_DBG_JTAG_1_DIS_MSK (((1U << EF_DATA_0_EF_DBG_JTAG_1_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_1_DIS_POS)
#define EF_DATA_0_EF_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_DATA_0_EF_DBG_JTAG_1_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_1_DIS_POS))
#define EF_DATA_0_EF_DBG_JTAG_0_DIS EF_DATA_0_EF_DBG_JTAG_0_DIS
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_POS (26U)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN (2U)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_MSK (((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS))
#define EF_DATA_0_EF_DBG_MODE EF_DATA_0_EF_DBG_MODE
#define EF_DATA_0_EF_DBG_MODE_POS (28U)
#define EF_DATA_0_EF_DBG_MODE_LEN (4U)
#define EF_DATA_0_EF_DBG_MODE_MSK (((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS)
#define EF_DATA_0_EF_DBG_MODE_UMSK (~(((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS))
/* 0x4 : ef_dbg_pwd_low */
#define EF_DATA_0_EF_DBG_PWD_LOW_OFFSET (0x4)
#define EF_DATA_0_EF_DBG_PWD_LOW EF_DATA_0_EF_DBG_PWD_LOW
#define EF_DATA_0_EF_DBG_PWD_LOW_POS (0U)
#define EF_DATA_0_EF_DBG_PWD_LOW_LEN (32U)
#define EF_DATA_0_EF_DBG_PWD_LOW_MSK (((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS)
#define EF_DATA_0_EF_DBG_PWD_LOW_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS))
/* 0x8 : ef_dbg_pwd_high */
#define EF_DATA_0_EF_DBG_PWD_HIGH_OFFSET (0x8)
#define EF_DATA_0_EF_DBG_PWD_HIGH EF_DATA_0_EF_DBG_PWD_HIGH
#define EF_DATA_0_EF_DBG_PWD_HIGH_POS (0U)
#define EF_DATA_0_EF_DBG_PWD_HIGH_LEN (32U)
#define EF_DATA_0_EF_DBG_PWD_HIGH_MSK (((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS)
#define EF_DATA_0_EF_DBG_PWD_HIGH_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS))
/* 0xC : ef_dbg_pwd2_low */
#define EF_DATA_0_EF_DBG_PWD2_LOW_OFFSET (0xC)
#define EF_DATA_0_EF_DBG_PWD2_LOW EF_DATA_0_EF_DBG_PWD2_LOW
#define EF_DATA_0_EF_DBG_PWD2_LOW_POS (0U)
#define EF_DATA_0_EF_DBG_PWD2_LOW_LEN (32U)
#define EF_DATA_0_EF_DBG_PWD2_LOW_MSK (((1U << EF_DATA_0_EF_DBG_PWD2_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD2_LOW_POS)
#define EF_DATA_0_EF_DBG_PWD2_LOW_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD2_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD2_LOW_POS))
/* 0x10 : ef_dbg_pwd2_high */
#define EF_DATA_0_EF_DBG_PWD2_HIGH_OFFSET (0x10)
#define EF_DATA_0_EF_DBG_PWD2_HIGH EF_DATA_0_EF_DBG_PWD2_HIGH
#define EF_DATA_0_EF_DBG_PWD2_HIGH_POS (0U)
#define EF_DATA_0_EF_DBG_PWD2_HIGH_LEN (32U)
#define EF_DATA_0_EF_DBG_PWD2_HIGH_MSK (((1U << EF_DATA_0_EF_DBG_PWD2_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD2_HIGH_POS)
#define EF_DATA_0_EF_DBG_PWD2_HIGH_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD2_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD2_HIGH_POS))
/* 0x14 : ef_wifi_mac_low */
#define EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET (0x14)
#define EF_DATA_0_EF_WIFI_MAC_LOW EF_DATA_0_EF_WIFI_MAC_LOW
#define EF_DATA_0_EF_WIFI_MAC_LOW_POS (0U)
#define EF_DATA_0_EF_WIFI_MAC_LOW_LEN (32U)
#define EF_DATA_0_EF_WIFI_MAC_LOW_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS)
#define EF_DATA_0_EF_WIFI_MAC_LOW_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS))
/* 0x18 : ef_wifi_mac_high */
#define EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET (0x18)
#define EF_DATA_0_EF_WIFI_MAC_HIGH EF_DATA_0_EF_WIFI_MAC_HIGH
#define EF_DATA_0_EF_WIFI_MAC_HIGH_POS (0U)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_LEN (32U)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS))
/* 0x1C : ef_key_slot_0_w0 */
#define EF_DATA_0_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
#define EF_DATA_0_EF_KEY_SLOT_0_W0 EF_DATA_0_EF_KEY_SLOT_0_W0
#define EF_DATA_0_EF_KEY_SLOT_0_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS))
/* 0x20 : ef_key_slot_0_w1 */
#define EF_DATA_0_EF_KEY_SLOT_0_W1_OFFSET (0x20)
#define EF_DATA_0_EF_KEY_SLOT_0_W1 EF_DATA_0_EF_KEY_SLOT_0_W1
#define EF_DATA_0_EF_KEY_SLOT_0_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS))
/* 0x24 : ef_key_slot_0_w2 */
#define EF_DATA_0_EF_KEY_SLOT_0_W2_OFFSET (0x24)
#define EF_DATA_0_EF_KEY_SLOT_0_W2 EF_DATA_0_EF_KEY_SLOT_0_W2
#define EF_DATA_0_EF_KEY_SLOT_0_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS))
/* 0x28 : ef_key_slot_0_w3 */
#define EF_DATA_0_EF_KEY_SLOT_0_W3_OFFSET (0x28)
#define EF_DATA_0_EF_KEY_SLOT_0_W3 EF_DATA_0_EF_KEY_SLOT_0_W3
#define EF_DATA_0_EF_KEY_SLOT_0_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS))
/* 0x2C : ef_key_slot_1_w0 */
#define EF_DATA_0_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
#define EF_DATA_0_EF_KEY_SLOT_1_W0 EF_DATA_0_EF_KEY_SLOT_1_W0
#define EF_DATA_0_EF_KEY_SLOT_1_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS))
/* 0x30 : ef_key_slot_1_w1 */
#define EF_DATA_0_EF_KEY_SLOT_1_W1_OFFSET (0x30)
#define EF_DATA_0_EF_KEY_SLOT_1_W1 EF_DATA_0_EF_KEY_SLOT_1_W1
#define EF_DATA_0_EF_KEY_SLOT_1_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS))
/* 0x34 : ef_key_slot_1_w2 */
#define EF_DATA_0_EF_KEY_SLOT_1_W2_OFFSET (0x34)
#define EF_DATA_0_EF_KEY_SLOT_1_W2 EF_DATA_0_EF_KEY_SLOT_1_W2
#define EF_DATA_0_EF_KEY_SLOT_1_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS))
/* 0x38 : ef_key_slot_1_w3 */
#define EF_DATA_0_EF_KEY_SLOT_1_W3_OFFSET (0x38)
#define EF_DATA_0_EF_KEY_SLOT_1_W3 EF_DATA_0_EF_KEY_SLOT_1_W3
#define EF_DATA_0_EF_KEY_SLOT_1_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS))
/* 0x3C : ef_key_slot_2_w0 */
#define EF_DATA_0_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
#define EF_DATA_0_EF_KEY_SLOT_2_W0 EF_DATA_0_EF_KEY_SLOT_2_W0
#define EF_DATA_0_EF_KEY_SLOT_2_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS))
/* 0x40 : ef_key_slot_2_w1 */
#define EF_DATA_0_EF_KEY_SLOT_2_W1_OFFSET (0x40)
#define EF_DATA_0_EF_KEY_SLOT_2_W1 EF_DATA_0_EF_KEY_SLOT_2_W1
#define EF_DATA_0_EF_KEY_SLOT_2_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS))
/* 0x44 : ef_key_slot_2_w2 */
#define EF_DATA_0_EF_KEY_SLOT_2_W2_OFFSET (0x44)
#define EF_DATA_0_EF_KEY_SLOT_2_W2 EF_DATA_0_EF_KEY_SLOT_2_W2
#define EF_DATA_0_EF_KEY_SLOT_2_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS))
/* 0x48 : ef_key_slot_2_w3 */
#define EF_DATA_0_EF_KEY_SLOT_2_W3_OFFSET (0x48)
#define EF_DATA_0_EF_KEY_SLOT_2_W3 EF_DATA_0_EF_KEY_SLOT_2_W3
#define EF_DATA_0_EF_KEY_SLOT_2_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS))
/* 0x4C : ef_key_slot_3_w0 */
#define EF_DATA_0_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
#define EF_DATA_0_EF_KEY_SLOT_3_W0 EF_DATA_0_EF_KEY_SLOT_3_W0
#define EF_DATA_0_EF_KEY_SLOT_3_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS))
/* 0x50 : ef_key_slot_3_w1 */
#define EF_DATA_0_EF_KEY_SLOT_3_W1_OFFSET (0x50)
#define EF_DATA_0_EF_KEY_SLOT_3_W1 EF_DATA_0_EF_KEY_SLOT_3_W1
#define EF_DATA_0_EF_KEY_SLOT_3_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS))
/* 0x54 : ef_key_slot_3_w2 */
#define EF_DATA_0_EF_KEY_SLOT_3_W2_OFFSET (0x54)
#define EF_DATA_0_EF_KEY_SLOT_3_W2 EF_DATA_0_EF_KEY_SLOT_3_W2
#define EF_DATA_0_EF_KEY_SLOT_3_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS))
/* 0x58 : ef_key_slot_3_w3 */
#define EF_DATA_0_EF_KEY_SLOT_3_W3_OFFSET (0x58)
#define EF_DATA_0_EF_KEY_SLOT_3_W3 EF_DATA_0_EF_KEY_SLOT_3_W3
#define EF_DATA_0_EF_KEY_SLOT_3_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS))
/* 0x5C : ef_sw_usage_0 */
#define EF_DATA_0_EF_SW_USAGE_0_OFFSET (0x5C)
#define EF_DATA_0_EF_SW_USAGE_0 EF_DATA_0_EF_SW_USAGE_0
#define EF_DATA_0_EF_SW_USAGE_0_POS (0U)
#define EF_DATA_0_EF_SW_USAGE_0_LEN (32U)
#define EF_DATA_0_EF_SW_USAGE_0_MSK (((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS)
#define EF_DATA_0_EF_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS))
#define EF_DATA_0_EF_SBOOT_SIGN_MODE EF_DATA_0_EF_SBOOT_SIGN_MODE
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_POS (8U)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN (2U)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK (((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS))
/* 0x60 : ef_sw_usage_1 */
#define EF_DATA_0_EF_SW_USAGE_1_OFFSET (0x60)
#define EF_DATA_0_EF_SW_USAGE_1 EF_DATA_0_EF_SW_USAGE_1
#define EF_DATA_0_EF_SW_USAGE_1_POS (0U)
#define EF_DATA_0_EF_SW_USAGE_1_LEN (32U)
#define EF_DATA_0_EF_SW_USAGE_1_MSK (((1U << EF_DATA_0_EF_SW_USAGE_1_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_1_POS)
#define EF_DATA_0_EF_SW_USAGE_1_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_1_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_1_POS))
/* 0x64 : ef_sw_usage_2 */
#define EF_DATA_0_EF_SW_USAGE_2_OFFSET (0x64)
#define EF_DATA_0_EF_SW_USAGE_2 EF_DATA_0_EF_SW_USAGE_2
#define EF_DATA_0_EF_SW_USAGE_2_POS (0U)
#define EF_DATA_0_EF_SW_USAGE_2_LEN (32U)
#define EF_DATA_0_EF_SW_USAGE_2_MSK (((1U << EF_DATA_0_EF_SW_USAGE_2_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_2_POS)
#define EF_DATA_0_EF_SW_USAGE_2_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_2_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_2_POS))
/* 0x68 : ef_sw_usage_3 */
#define EF_DATA_0_EF_SW_USAGE_3_OFFSET (0x68)
#define EF_DATA_0_EF_SW_USAGE_3 EF_DATA_0_EF_SW_USAGE_3
#define EF_DATA_0_EF_SW_USAGE_3_POS (0U)
#define EF_DATA_0_EF_SW_USAGE_3_LEN (32U)
#define EF_DATA_0_EF_SW_USAGE_3_MSK (((1U << EF_DATA_0_EF_SW_USAGE_3_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_3_POS)
#define EF_DATA_0_EF_SW_USAGE_3_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_3_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_3_POS))
/* 0x6C : ef_key_slot_11_w0 */
#define EF_DATA_0_EF_KEY_SLOT_11_W0_OFFSET (0x6C)
#define EF_DATA_0_EF_KEY_SLOT_11_W0 EF_DATA_0_EF_KEY_SLOT_11_W0
#define EF_DATA_0_EF_KEY_SLOT_11_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_11_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_11_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_11_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_11_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_11_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W0_POS))
/* 0x70 : ef_key_slot_11_w1 */
#define EF_DATA_0_EF_KEY_SLOT_11_W1_OFFSET (0x70)
#define EF_DATA_0_EF_KEY_SLOT_11_W1 EF_DATA_0_EF_KEY_SLOT_11_W1
#define EF_DATA_0_EF_KEY_SLOT_11_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_11_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_11_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_11_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_11_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_11_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W1_POS))
/* 0x74 : ef_key_slot_11_w2 */
#define EF_DATA_0_EF_KEY_SLOT_11_W2_OFFSET (0x74)
#define EF_DATA_0_EF_KEY_SLOT_11_W2 EF_DATA_0_EF_KEY_SLOT_11_W2
#define EF_DATA_0_EF_KEY_SLOT_11_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_11_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_11_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_11_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_11_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_11_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W2_POS))
/* 0x78 : ef_key_slot_11_w3 */
#define EF_DATA_0_EF_KEY_SLOT_11_W3_OFFSET (0x78)
#define EF_DATA_0_EF_KEY_SLOT_11_W3 EF_DATA_0_EF_KEY_SLOT_11_W3
#define EF_DATA_0_EF_KEY_SLOT_11_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_11_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_11_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_11_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_11_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_11_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_11_W3_POS))
/* 0x7C : ef_data_0_lock */
#define EF_DATA_0_LOCK_OFFSET (0x7C)
#define EF_DATA_0_EF_SEC_LIFECYCLE EF_DATA_0_EF_SEC_LIFECYCLE
#define EF_DATA_0_EF_SEC_LIFECYCLE_POS (0U)
#define EF_DATA_0_EF_SEC_LIFECYCLE_LEN (4U)
#define EF_DATA_0_EF_SEC_LIFECYCLE_MSK (((1U << EF_DATA_0_EF_SEC_LIFECYCLE_LEN) - 1) << EF_DATA_0_EF_SEC_LIFECYCLE_POS)
#define EF_DATA_0_EF_SEC_LIFECYCLE_UMSK (~(((1U << EF_DATA_0_EF_SEC_LIFECYCLE_LEN) - 1) << EF_DATA_0_EF_SEC_LIFECYCLE_POS))
#define EF_DATA_0_WR_LOCK_RSVD_0 EF_DATA_0_WR_LOCK_RSVD_0
#define EF_DATA_0_WR_LOCK_RSVD_0_POS (4U)
#define EF_DATA_0_WR_LOCK_RSVD_0_LEN (10U)
#define EF_DATA_0_WR_LOCK_RSVD_0_MSK (((1U << EF_DATA_0_WR_LOCK_RSVD_0_LEN) - 1) << EF_DATA_0_WR_LOCK_RSVD_0_POS)
#define EF_DATA_0_WR_LOCK_RSVD_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_RSVD_0_LEN) - 1) << EF_DATA_0_WR_LOCK_RSVD_0_POS))
#define EF_DATA_0_WR_LOCK_BOOT_MODE EF_DATA_0_WR_LOCK_BOOT_MODE
#define EF_DATA_0_WR_LOCK_BOOT_MODE_POS (14U)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_LEN (1U)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_MSK (((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_UMSK (~(((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS))
#define EF_DATA_0_WR_LOCK_DBG_PWD EF_DATA_0_WR_LOCK_DBG_PWD
#define EF_DATA_0_WR_LOCK_DBG_PWD_POS (15U)
#define EF_DATA_0_WR_LOCK_DBG_PWD_LEN (1U)
#define EF_DATA_0_WR_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS)
#define EF_DATA_0_WR_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS))
#define EF_DATA_0_WR_LOCK_WIFI_MAC EF_DATA_0_WR_LOCK_WIFI_MAC
#define EF_DATA_0_WR_LOCK_WIFI_MAC_POS (16U)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_LEN (1U)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_MSK (((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_UMSK (~(((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0 EF_DATA_0_WR_LOCK_KEY_SLOT_0
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS (17U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1 EF_DATA_0_WR_LOCK_KEY_SLOT_1
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS (18U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2 EF_DATA_0_WR_LOCK_KEY_SLOT_2
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS (19U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3 EF_DATA_0_WR_LOCK_KEY_SLOT_3
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS (20U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS))
#define EF_DATA_0_WR_LOCK_SW_USAGE_0 EF_DATA_0_WR_LOCK_SW_USAGE_0
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_POS (21U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN (1U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS))
#define EF_DATA_0_WR_LOCK_SW_USAGE_1 EF_DATA_0_WR_LOCK_SW_USAGE_1
#define EF_DATA_0_WR_LOCK_SW_USAGE_1_POS (22U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_1_LEN (1U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_1_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_1_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_1_POS)
#define EF_DATA_0_WR_LOCK_SW_USAGE_1_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_1_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_1_POS))
#define EF_DATA_0_WR_LOCK_SW_USAGE_2 EF_DATA_0_WR_LOCK_SW_USAGE_2
#define EF_DATA_0_WR_LOCK_SW_USAGE_2_POS (23U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_2_LEN (1U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_2_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_2_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_2_POS)
#define EF_DATA_0_WR_LOCK_SW_USAGE_2_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_2_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_2_POS))
#define EF_DATA_0_WR_LOCK_SW_USAGE_3 EF_DATA_0_WR_LOCK_SW_USAGE_3
#define EF_DATA_0_WR_LOCK_SW_USAGE_3_POS (24U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_3_LEN (1U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_3_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_3_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_3_POS)
#define EF_DATA_0_WR_LOCK_SW_USAGE_3_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_3_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_3_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_11 EF_DATA_0_WR_LOCK_KEY_SLOT_11
#define EF_DATA_0_WR_LOCK_KEY_SLOT_11_POS (25U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_11_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_11_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_11_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_11_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_11_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_11_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_11_POS))
#define EF_DATA_0_RD_LOCK_DBG_PWD EF_DATA_0_RD_LOCK_DBG_PWD
#define EF_DATA_0_RD_LOCK_DBG_PWD_POS (26U)
#define EF_DATA_0_RD_LOCK_DBG_PWD_LEN (1U)
#define EF_DATA_0_RD_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS)
#define EF_DATA_0_RD_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0 EF_DATA_0_RD_LOCK_KEY_SLOT_0
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS (27U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1 EF_DATA_0_RD_LOCK_KEY_SLOT_1
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS (28U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2 EF_DATA_0_RD_LOCK_KEY_SLOT_2
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS (29U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3 EF_DATA_0_RD_LOCK_KEY_SLOT_3
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS (30U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_11 EF_DATA_0_RD_LOCK_KEY_SLOT_11
#define EF_DATA_0_RD_LOCK_KEY_SLOT_11_POS (31U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_11_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_11_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_11_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_11_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_11_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_11_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_11_POS))
struct ef_data_0_reg {
/* 0x0 : ef_cfg_0 */
union {
struct {
uint32_t ef_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t ef_ai_dis : 1; /* [ 2], r/w, 0x0 */
uint32_t ef_cpu0_dis : 1; /* [ 3], r/w, 0x0 */
uint32_t ef_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t ef_uart_dis : 4; /* [ 9: 6], r/w, 0x0 */
uint32_t ef_ble2_dis : 1; /* [ 10], r/w, 0x0 */
uint32_t ef_m1542_dis : 1; /* [ 11], r/w, 0x0 */
uint32_t ef_sf_key_re_sel : 2; /* [13:12], r/w, 0x0 */
uint32_t ef_sdu_dis : 1; /* [ 14], r/w, 0x0 */
uint32_t ef_btdm_dis : 1; /* [ 15], r/w, 0x0 */
uint32_t ef_wifi_dis : 1; /* [ 16], r/w, 0x0 */
uint32_t ef_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */
uint32_t ef_cam_dis : 1; /* [ 18], r/w, 0x0 */
uint32_t ef_m154_dis : 1; /* [ 19], r/w, 0x0 */
uint32_t ef_cpu1_dis : 1; /* [ 20], r/w, 0x0 */
uint32_t ef_cpu_rst_dbg_dis : 1; /* [ 21], r/w, 0x0 */
uint32_t ef_se_dbg_dis : 1; /* [ 22], r/w, 0x0 */
uint32_t ef_efuse_dbg_dis : 1; /* [ 23], r/w, 0x0 */
uint32_t ef_dbg_jtag_1_dis : 2; /* [25:24], r/w, 0x0 */
uint32_t ef_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */
uint32_t ef_dbg_mode : 4; /* [31:28], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_cfg_0;
/* 0x4 : ef_dbg_pwd_low */
union {
struct {
uint32_t ef_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dbg_pwd_low;
/* 0x8 : ef_dbg_pwd_high */
union {
struct {
uint32_t ef_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dbg_pwd_high;
/* 0xC : ef_dbg_pwd2_low */
union {
struct {
uint32_t ef_dbg_pwd2_low : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dbg_pwd2_low;
/* 0x10 : ef_dbg_pwd2_high */
union {
struct {
uint32_t ef_dbg_pwd2_high : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dbg_pwd2_high;
/* 0x14 : ef_wifi_mac_low */
union {
struct {
uint32_t ef_wifi_mac_low : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_wifi_mac_low;
/* 0x18 : ef_wifi_mac_high */
union {
struct {
uint32_t ef_wifi_mac_high : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_wifi_mac_high;
/* 0x1C : ef_key_slot_0_w0 */
union {
struct {
uint32_t ef_key_slot_0_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w0;
/* 0x20 : ef_key_slot_0_w1 */
union {
struct {
uint32_t ef_key_slot_0_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w1;
/* 0x24 : ef_key_slot_0_w2 */
union {
struct {
uint32_t ef_key_slot_0_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w2;
/* 0x28 : ef_key_slot_0_w3 */
union {
struct {
uint32_t ef_key_slot_0_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w3;
/* 0x2C : ef_key_slot_1_w0 */
union {
struct {
uint32_t ef_key_slot_1_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w0;
/* 0x30 : ef_key_slot_1_w1 */
union {
struct {
uint32_t ef_key_slot_1_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w1;
/* 0x34 : ef_key_slot_1_w2 */
union {
struct {
uint32_t ef_key_slot_1_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w2;
/* 0x38 : ef_key_slot_1_w3 */
union {
struct {
uint32_t ef_key_slot_1_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w3;
/* 0x3C : ef_key_slot_2_w0 */
union {
struct {
uint32_t ef_key_slot_2_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w0;
/* 0x40 : ef_key_slot_2_w1 */
union {
struct {
uint32_t ef_key_slot_2_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w1;
/* 0x44 : ef_key_slot_2_w2 */
union {
struct {
uint32_t ef_key_slot_2_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w2;
/* 0x48 : ef_key_slot_2_w3 */
union {
struct {
uint32_t ef_key_slot_2_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w3;
/* 0x4C : ef_key_slot_3_w0 */
union {
struct {
uint32_t ef_key_slot_3_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w0;
/* 0x50 : ef_key_slot_3_w1 */
union {
struct {
uint32_t ef_key_slot_3_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w1;
/* 0x54 : ef_key_slot_3_w2 */
union {
struct {
uint32_t ef_key_slot_3_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w2;
/* 0x58 : ef_key_slot_3_w3 */
union {
struct {
uint32_t ef_key_slot_3_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w3;
/* 0x5C : ef_sw_usage_0 */
union {
struct {
uint32_t ef_sw_usage_0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_sw_usage_0;
/* 0x60 : ef_sw_usage_1 */
union {
struct {
uint32_t ef_sw_usage_1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_sw_usage_1;
/* 0x64 : ef_sw_usage_2 */
union {
struct {
uint32_t ef_sw_usage_2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_sw_usage_2;
/* 0x68 : ef_sw_usage_3 */
union {
struct {
uint32_t ef_sw_usage_3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_sw_usage_3;
/* 0x6C : ef_key_slot_11_w0 */
union {
struct {
uint32_t ef_key_slot_11_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_11_w0;
/* 0x70 : ef_key_slot_11_w1 */
union {
struct {
uint32_t ef_key_slot_11_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_11_w1;
/* 0x74 : ef_key_slot_11_w2 */
union {
struct {
uint32_t ef_key_slot_11_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_11_w2;
/* 0x78 : ef_key_slot_11_w3 */
union {
struct {
uint32_t ef_key_slot_11_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_11_w3;
/* 0x7C : ef_data_0_lock */
union {
struct {
uint32_t ef_sec_lifecycle : 4; /* [ 3: 0], r/w, 0x0 */
uint32_t wr_lock_rsvd_0 : 10; /* [13: 4], r/w, 0x0 */
uint32_t wr_lock_boot_mode : 1; /* [ 14], r/w, 0x0 */
uint32_t wr_lock_dbg_pwd : 1; /* [ 15], r/w, 0x0 */
uint32_t wr_lock_wifi_mac : 1; /* [ 16], r/w, 0x0 */
uint32_t wr_lock_key_slot_0 : 1; /* [ 17], r/w, 0x0 */
uint32_t wr_lock_key_slot_1 : 1; /* [ 18], r/w, 0x0 */
uint32_t wr_lock_key_slot_2 : 1; /* [ 19], r/w, 0x0 */
uint32_t wr_lock_key_slot_3 : 1; /* [ 20], r/w, 0x0 */
uint32_t wr_lock_sw_usage_0 : 1; /* [ 21], r/w, 0x0 */
uint32_t wr_lock_sw_usage_1 : 1; /* [ 22], r/w, 0x0 */
uint32_t wr_lock_sw_usage_2 : 1; /* [ 23], r/w, 0x0 */
uint32_t wr_lock_sw_usage_3 : 1; /* [ 24], r/w, 0x0 */
uint32_t wr_lock_key_slot_11 : 1; /* [ 25], r/w, 0x0 */
uint32_t rd_lock_dbg_pwd : 1; /* [ 26], r/w, 0x0 */
uint32_t rd_lock_key_slot_0 : 1; /* [ 27], r/w, 0x0 */
uint32_t rd_lock_key_slot_1 : 1; /* [ 28], r/w, 0x0 */
uint32_t rd_lock_key_slot_2 : 1; /* [ 29], r/w, 0x0 */
uint32_t rd_lock_key_slot_3 : 1; /* [ 30], r/w, 0x0 */
uint32_t rd_lock_key_slot_11 : 1; /* [ 31], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_data_0_lock;
};
#endif /* __EF_DATA_0_REG_H__ */

660
include/bl808/ef_data_1_reg.h Normal file
View File

@ -0,0 +1,660 @@
/**
******************************************************************************
* @file ef_data_1_reg.h
* @version V1.0
* @date 2021-07-31
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __EF_DATA_1_REG_H__
#define __EF_DATA_1_REG_H__
#include <linux/types.h>
/* 0x80 : ef_key_slot_4_w0 */
#define EF_DATA_1_EF_KEY_SLOT_4_W0_OFFSET (0x80)
#define EF_DATA_1_EF_KEY_SLOT_4_W0 EF_DATA_1_EF_KEY_SLOT_4_W0
#define EF_DATA_1_EF_KEY_SLOT_4_W0_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_4_W0_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_4_W0_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W0_POS)
#define EF_DATA_1_EF_KEY_SLOT_4_W0_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W0_POS))
/* 0x84 : ef_key_slot_4_w1 */
#define EF_DATA_1_EF_KEY_SLOT_4_W1_OFFSET (0x84)
#define EF_DATA_1_EF_KEY_SLOT_4_W1 EF_DATA_1_EF_KEY_SLOT_4_W1
#define EF_DATA_1_EF_KEY_SLOT_4_W1_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_4_W1_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_4_W1_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W1_POS)
#define EF_DATA_1_EF_KEY_SLOT_4_W1_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W1_POS))
/* 0x88 : ef_key_slot_4_w2 */
#define EF_DATA_1_EF_KEY_SLOT_4_W2_OFFSET (0x88)
#define EF_DATA_1_EF_KEY_SLOT_4_W2 EF_DATA_1_EF_KEY_SLOT_4_W2
#define EF_DATA_1_EF_KEY_SLOT_4_W2_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_4_W2_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_4_W2_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W2_POS)
#define EF_DATA_1_EF_KEY_SLOT_4_W2_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W2_POS))
/* 0x8C : ef_key_slot_4_w3 */
#define EF_DATA_1_EF_KEY_SLOT_4_W3_OFFSET (0x8C)
#define EF_DATA_1_EF_KEY_SLOT_4_W3 EF_DATA_1_EF_KEY_SLOT_4_W3
#define EF_DATA_1_EF_KEY_SLOT_4_W3_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_4_W3_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_4_W3_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W3_POS)
#define EF_DATA_1_EF_KEY_SLOT_4_W3_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_4_W3_POS))
/* 0x90 : ef_key_slot_5_w0 */
#define EF_DATA_1_EF_KEY_SLOT_5_W0_OFFSET (0x90)
#define EF_DATA_1_EF_KEY_SLOT_5_W0 EF_DATA_1_EF_KEY_SLOT_5_W0
#define EF_DATA_1_EF_KEY_SLOT_5_W0_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_5_W0_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_5_W0_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W0_POS)
#define EF_DATA_1_EF_KEY_SLOT_5_W0_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W0_POS))
/* 0x94 : ef_key_slot_5_w1 */
#define EF_DATA_1_EF_KEY_SLOT_5_W1_OFFSET (0x94)
#define EF_DATA_1_EF_KEY_SLOT_5_W1 EF_DATA_1_EF_KEY_SLOT_5_W1
#define EF_DATA_1_EF_KEY_SLOT_5_W1_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_5_W1_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_5_W1_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W1_POS)
#define EF_DATA_1_EF_KEY_SLOT_5_W1_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W1_POS))
/* 0x98 : ef_key_slot_5_w2 */
#define EF_DATA_1_EF_KEY_SLOT_5_W2_OFFSET (0x98)
#define EF_DATA_1_EF_KEY_SLOT_5_W2 EF_DATA_1_EF_KEY_SLOT_5_W2
#define EF_DATA_1_EF_KEY_SLOT_5_W2_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_5_W2_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_5_W2_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W2_POS)
#define EF_DATA_1_EF_KEY_SLOT_5_W2_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W2_POS))
/* 0x9C : ef_key_slot_5_w3 */
#define EF_DATA_1_EF_KEY_SLOT_5_W3_OFFSET (0x9C)
#define EF_DATA_1_EF_KEY_SLOT_5_W3 EF_DATA_1_EF_KEY_SLOT_5_W3
#define EF_DATA_1_EF_KEY_SLOT_5_W3_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_5_W3_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_5_W3_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W3_POS)
#define EF_DATA_1_EF_KEY_SLOT_5_W3_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_5_W3_POS))
/* 0xA0 : ef_key_slot_6_w0 */
#define EF_DATA_1_EF_KEY_SLOT_6_W0_OFFSET (0xA0)
#define EF_DATA_1_EF_KEY_SLOT_6_W0 EF_DATA_1_EF_KEY_SLOT_6_W0
#define EF_DATA_1_EF_KEY_SLOT_6_W0_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_6_W0_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_6_W0_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_6_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W0_POS)
#define EF_DATA_1_EF_KEY_SLOT_6_W0_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_6_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W0_POS))
/* 0xA4 : ef_key_slot_6_w1 */
#define EF_DATA_1_EF_KEY_SLOT_6_W1_OFFSET (0xA4)
#define EF_DATA_1_EF_KEY_SLOT_6_W1 EF_DATA_1_EF_KEY_SLOT_6_W1
#define EF_DATA_1_EF_KEY_SLOT_6_W1_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_6_W1_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_6_W1_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_6_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W1_POS)
#define EF_DATA_1_EF_KEY_SLOT_6_W1_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_6_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W1_POS))
/* 0xA8 : ef_key_slot_6_w2 */
#define EF_DATA_1_EF_KEY_SLOT_6_W2_OFFSET (0xA8)
#define EF_DATA_1_EF_KEY_SLOT_6_W2 EF_DATA_1_EF_KEY_SLOT_6_W2
#define EF_DATA_1_EF_KEY_SLOT_6_W2_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_6_W2_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_6_W2_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_6_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W2_POS)
#define EF_DATA_1_EF_KEY_SLOT_6_W2_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_6_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W2_POS))
/* 0xAC : ef_key_slot_6_w3 */
#define EF_DATA_1_EF_KEY_SLOT_6_W3_OFFSET (0xAC)
#define EF_DATA_1_EF_KEY_SLOT_6_W3 EF_DATA_1_EF_KEY_SLOT_6_W3
#define EF_DATA_1_EF_KEY_SLOT_6_W3_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_6_W3_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_6_W3_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_6_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W3_POS)
#define EF_DATA_1_EF_KEY_SLOT_6_W3_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_6_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_6_W3_POS))
/* 0xB0 : ef_key_slot_7_w0 */
#define EF_DATA_1_EF_KEY_SLOT_7_W0_OFFSET (0xB0)
#define EF_DATA_1_EF_KEY_SLOT_7_W0 EF_DATA_1_EF_KEY_SLOT_7_W0
#define EF_DATA_1_EF_KEY_SLOT_7_W0_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_7_W0_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_7_W0_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_7_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W0_POS)
#define EF_DATA_1_EF_KEY_SLOT_7_W0_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_7_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W0_POS))
/* 0xB4 : ef_key_slot_7_w1 */
#define EF_DATA_1_EF_KEY_SLOT_7_W1_OFFSET (0xB4)
#define EF_DATA_1_EF_KEY_SLOT_7_W1 EF_DATA_1_EF_KEY_SLOT_7_W1
#define EF_DATA_1_EF_KEY_SLOT_7_W1_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_7_W1_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_7_W1_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_7_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W1_POS)
#define EF_DATA_1_EF_KEY_SLOT_7_W1_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_7_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W1_POS))
/* 0xB8 : ef_key_slot_7_w2 */
#define EF_DATA_1_EF_KEY_SLOT_7_W2_OFFSET (0xB8)
#define EF_DATA_1_EF_KEY_SLOT_7_W2 EF_DATA_1_EF_KEY_SLOT_7_W2
#define EF_DATA_1_EF_KEY_SLOT_7_W2_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_7_W2_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_7_W2_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_7_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W2_POS)
#define EF_DATA_1_EF_KEY_SLOT_7_W2_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_7_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W2_POS))
/* 0xBC : ef_key_slot_7_w3 */
#define EF_DATA_1_EF_KEY_SLOT_7_W3_OFFSET (0xBC)
#define EF_DATA_1_EF_KEY_SLOT_7_W3 EF_DATA_1_EF_KEY_SLOT_7_W3
#define EF_DATA_1_EF_KEY_SLOT_7_W3_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_7_W3_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_7_W3_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_7_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W3_POS)
#define EF_DATA_1_EF_KEY_SLOT_7_W3_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_7_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_7_W3_POS))
/* 0xC0 : ef_key_slot_8_w0 */
#define EF_DATA_1_EF_KEY_SLOT_8_W0_OFFSET (0xC0)
#define EF_DATA_1_EF_KEY_SLOT_8_W0 EF_DATA_1_EF_KEY_SLOT_8_W0
#define EF_DATA_1_EF_KEY_SLOT_8_W0_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_8_W0_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_8_W0_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_8_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W0_POS)
#define EF_DATA_1_EF_KEY_SLOT_8_W0_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_8_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W0_POS))
/* 0xC4 : ef_key_slot_8_w1 */
#define EF_DATA_1_EF_KEY_SLOT_8_W1_OFFSET (0xC4)
#define EF_DATA_1_EF_KEY_SLOT_8_W1 EF_DATA_1_EF_KEY_SLOT_8_W1
#define EF_DATA_1_EF_KEY_SLOT_8_W1_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_8_W1_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_8_W1_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_8_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W1_POS)
#define EF_DATA_1_EF_KEY_SLOT_8_W1_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_8_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W1_POS))
/* 0xC8 : ef_key_slot_8_w2 */
#define EF_DATA_1_EF_KEY_SLOT_8_W2_OFFSET (0xC8)
#define EF_DATA_1_EF_KEY_SLOT_8_W2 EF_DATA_1_EF_KEY_SLOT_8_W2
#define EF_DATA_1_EF_KEY_SLOT_8_W2_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_8_W2_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_8_W2_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_8_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W2_POS)
#define EF_DATA_1_EF_KEY_SLOT_8_W2_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_8_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W2_POS))
/* 0xCC : ef_key_slot_8_w3 */
#define EF_DATA_1_EF_KEY_SLOT_8_W3_OFFSET (0xCC)
#define EF_DATA_1_EF_KEY_SLOT_8_W3 EF_DATA_1_EF_KEY_SLOT_8_W3
#define EF_DATA_1_EF_KEY_SLOT_8_W3_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_8_W3_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_8_W3_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_8_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W3_POS)
#define EF_DATA_1_EF_KEY_SLOT_8_W3_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_8_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_8_W3_POS))
/* 0xD0 : ef_key_slot_9_w0 */
#define EF_DATA_1_EF_KEY_SLOT_9_W0_OFFSET (0xD0)
#define EF_DATA_1_EF_KEY_SLOT_9_W0 EF_DATA_1_EF_KEY_SLOT_9_W0
#define EF_DATA_1_EF_KEY_SLOT_9_W0_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_9_W0_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_9_W0_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_9_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W0_POS)
#define EF_DATA_1_EF_KEY_SLOT_9_W0_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_9_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W0_POS))
/* 0xD4 : ef_key_slot_9_w1 */
#define EF_DATA_1_EF_KEY_SLOT_9_W1_OFFSET (0xD4)
#define EF_DATA_1_EF_KEY_SLOT_9_W1 EF_DATA_1_EF_KEY_SLOT_9_W1
#define EF_DATA_1_EF_KEY_SLOT_9_W1_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_9_W1_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_9_W1_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_9_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W1_POS)
#define EF_DATA_1_EF_KEY_SLOT_9_W1_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_9_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W1_POS))
/* 0xD8 : ef_key_slot_9_w2 */
#define EF_DATA_1_EF_KEY_SLOT_9_W2_OFFSET (0xD8)
#define EF_DATA_1_EF_KEY_SLOT_9_W2 EF_DATA_1_EF_KEY_SLOT_9_W2
#define EF_DATA_1_EF_KEY_SLOT_9_W2_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_9_W2_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_9_W2_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_9_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W2_POS)
#define EF_DATA_1_EF_KEY_SLOT_9_W2_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_9_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W2_POS))
/* 0xDC : ef_key_slot_9_w3 */
#define EF_DATA_1_EF_KEY_SLOT_9_W3_OFFSET (0xDC)
#define EF_DATA_1_EF_KEY_SLOT_9_W3 EF_DATA_1_EF_KEY_SLOT_9_W3
#define EF_DATA_1_EF_KEY_SLOT_9_W3_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_9_W3_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_9_W3_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_9_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W3_POS)
#define EF_DATA_1_EF_KEY_SLOT_9_W3_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_9_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_9_W3_POS))
/* 0xE0 : ef_key_slot_10_w0 */
#define EF_DATA_1_EF_KEY_SLOT_10_W0_OFFSET (0xE0)
#define EF_DATA_1_EF_KEY_SLOT_10_W0 EF_DATA_1_EF_KEY_SLOT_10_W0
#define EF_DATA_1_EF_KEY_SLOT_10_W0_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_10_W0_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_10_W0_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_10_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W0_POS)
#define EF_DATA_1_EF_KEY_SLOT_10_W0_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_10_W0_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W0_POS))
/* 0xE4 : ef_key_slot_10_w1 */
#define EF_DATA_1_EF_KEY_SLOT_10_W1_OFFSET (0xE4)
#define EF_DATA_1_EF_KEY_SLOT_10_W1 EF_DATA_1_EF_KEY_SLOT_10_W1
#define EF_DATA_1_EF_KEY_SLOT_10_W1_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_10_W1_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_10_W1_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_10_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W1_POS)
#define EF_DATA_1_EF_KEY_SLOT_10_W1_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_10_W1_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W1_POS))
/* 0xE8 : ef_key_slot_10_w2 */
#define EF_DATA_1_EF_KEY_SLOT_10_W2_OFFSET (0xE8)
#define EF_DATA_1_EF_KEY_SLOT_10_W2 EF_DATA_1_EF_KEY_SLOT_10_W2
#define EF_DATA_1_EF_KEY_SLOT_10_W2_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_10_W2_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_10_W2_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_10_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W2_POS)
#define EF_DATA_1_EF_KEY_SLOT_10_W2_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_10_W2_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W2_POS))
/* 0xEC : ef_key_slot_10_w3 */
#define EF_DATA_1_EF_KEY_SLOT_10_W3_OFFSET (0xEC)
#define EF_DATA_1_EF_KEY_SLOT_10_W3 EF_DATA_1_EF_KEY_SLOT_10_W3
#define EF_DATA_1_EF_KEY_SLOT_10_W3_POS (0U)
#define EF_DATA_1_EF_KEY_SLOT_10_W3_LEN (32U)
#define EF_DATA_1_EF_KEY_SLOT_10_W3_MSK (((1U << EF_DATA_1_EF_KEY_SLOT_10_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W3_POS)
#define EF_DATA_1_EF_KEY_SLOT_10_W3_UMSK (~(((1U << EF_DATA_1_EF_KEY_SLOT_10_W3_LEN) - 1) << EF_DATA_1_EF_KEY_SLOT_10_W3_POS))
/* 0xF0 : ef_dat_1_rsvd_0 */
#define EF_DATA_1_EF_DAT_1_RSVD_0_OFFSET (0xF0)
#define EF_DATA_1_EF_DAT_1_RSVD_0 EF_DATA_1_EF_DAT_1_RSVD_0
#define EF_DATA_1_EF_DAT_1_RSVD_0_POS (0U)
#define EF_DATA_1_EF_DAT_1_RSVD_0_LEN (32U)
#define EF_DATA_1_EF_DAT_1_RSVD_0_MSK (((1U << EF_DATA_1_EF_DAT_1_RSVD_0_LEN) - 1) << EF_DATA_1_EF_DAT_1_RSVD_0_POS)
#define EF_DATA_1_EF_DAT_1_RSVD_0_UMSK (~(((1U << EF_DATA_1_EF_DAT_1_RSVD_0_LEN) - 1) << EF_DATA_1_EF_DAT_1_RSVD_0_POS))
/* 0xF4 : ef_dat_1_rsvd_1 */
#define EF_DATA_1_EF_DAT_1_RSVD_1_OFFSET (0xF4)
#define EF_DATA_1_EF_DAT_1_RSVD_1 EF_DATA_1_EF_DAT_1_RSVD_1
#define EF_DATA_1_EF_DAT_1_RSVD_1_POS (0U)
#define EF_DATA_1_EF_DAT_1_RSVD_1_LEN (32U)
#define EF_DATA_1_EF_DAT_1_RSVD_1_MSK (((1U << EF_DATA_1_EF_DAT_1_RSVD_1_LEN) - 1) << EF_DATA_1_EF_DAT_1_RSVD_1_POS)
#define EF_DATA_1_EF_DAT_1_RSVD_1_UMSK (~(((1U << EF_DATA_1_EF_DAT_1_RSVD_1_LEN) - 1) << EF_DATA_1_EF_DAT_1_RSVD_1_POS))
/* 0xF8 : ef_dat_1_rsvd_2 */
#define EF_DATA_1_EF_DAT_1_RSVD_2_OFFSET (0xF8)
#define EF_DATA_1_EF_DAT_1_RSVD_2 EF_DATA_1_EF_DAT_1_RSVD_2
#define EF_DATA_1_EF_DAT_1_RSVD_2_POS (0U)
#define EF_DATA_1_EF_DAT_1_RSVD_2_LEN (32U)
#define EF_DATA_1_EF_DAT_1_RSVD_2_MSK (((1U << EF_DATA_1_EF_DAT_1_RSVD_2_LEN) - 1) << EF_DATA_1_EF_DAT_1_RSVD_2_POS)
#define EF_DATA_1_EF_DAT_1_RSVD_2_UMSK (~(((1U << EF_DATA_1_EF_DAT_1_RSVD_2_LEN) - 1) << EF_DATA_1_EF_DAT_1_RSVD_2_POS))
/* 0xFC : ef_data_1_lock */
#define EF_DATA_1_LOCK_OFFSET (0xFC)
#define EF_DATA_1_WR_LOCK_RSVD_1 EF_DATA_1_WR_LOCK_RSVD_1
#define EF_DATA_1_WR_LOCK_RSVD_1_POS (0U)
#define EF_DATA_1_WR_LOCK_RSVD_1_LEN (15U)
#define EF_DATA_1_WR_LOCK_RSVD_1_MSK (((1U << EF_DATA_1_WR_LOCK_RSVD_1_LEN) - 1) << EF_DATA_1_WR_LOCK_RSVD_1_POS)
#define EF_DATA_1_WR_LOCK_RSVD_1_UMSK (~(((1U << EF_DATA_1_WR_LOCK_RSVD_1_LEN) - 1) << EF_DATA_1_WR_LOCK_RSVD_1_POS))
#define EF_DATA_1_WR_LOCK_KEY_SLOT_4 EF_DATA_1_WR_LOCK_KEY_SLOT_4
#define EF_DATA_1_WR_LOCK_KEY_SLOT_4_POS (15U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_4_LEN (1U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_4_MSK (((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_4_POS)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_4_UMSK (~(((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_4_POS))
#define EF_DATA_1_WR_LOCK_KEY_SLOT_5 EF_DATA_1_WR_LOCK_KEY_SLOT_5
#define EF_DATA_1_WR_LOCK_KEY_SLOT_5_POS (16U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_5_LEN (1U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_5_MSK (((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_5_POS)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_5_UMSK (~(((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_5_POS))
#define EF_DATA_1_WR_LOCK_KEY_SLOT_6 EF_DATA_1_WR_LOCK_KEY_SLOT_6
#define EF_DATA_1_WR_LOCK_KEY_SLOT_6_POS (17U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_6_LEN (1U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_6_MSK (((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_6_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_6_POS)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_6_UMSK (~(((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_6_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_6_POS))
#define EF_DATA_1_WR_LOCK_KEY_SLOT_7 EF_DATA_1_WR_LOCK_KEY_SLOT_7
#define EF_DATA_1_WR_LOCK_KEY_SLOT_7_POS (18U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_7_LEN (1U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_7_MSK (((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_7_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_7_POS)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_7_UMSK (~(((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_7_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_7_POS))
#define EF_DATA_1_WR_LOCK_KEY_SLOT_8 EF_DATA_1_WR_LOCK_KEY_SLOT_8
#define EF_DATA_1_WR_LOCK_KEY_SLOT_8_POS (19U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_8_LEN (1U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_8_MSK (((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_8_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_8_POS)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_8_UMSK (~(((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_8_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_8_POS))
#define EF_DATA_1_WR_LOCK_KEY_SLOT_9 EF_DATA_1_WR_LOCK_KEY_SLOT_9
#define EF_DATA_1_WR_LOCK_KEY_SLOT_9_POS (20U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_9_LEN (1U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_9_MSK (((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_9_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_9_POS)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_9_UMSK (~(((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_9_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_9_POS))
#define EF_DATA_1_WR_LOCK_KEY_SLOT_10 EF_DATA_1_WR_LOCK_KEY_SLOT_10
#define EF_DATA_1_WR_LOCK_KEY_SLOT_10_POS (21U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_10_LEN (1U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_10_MSK (((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_10_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_10_POS)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_10_UMSK (~(((1U << EF_DATA_1_WR_LOCK_KEY_SLOT_10_LEN) - 1) << EF_DATA_1_WR_LOCK_KEY_SLOT_10_POS))
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_0 EF_DATA_1_WR_LOCK_DAT_1_RSVD_0
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_POS (22U)
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_LEN (1U)
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_MSK (((1U << EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_LEN) - 1) << EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_POS)
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_UMSK (~(((1U << EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_LEN) - 1) << EF_DATA_1_WR_LOCK_DAT_1_RSVD_0_POS))
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_1 EF_DATA_1_WR_LOCK_DAT_1_RSVD_1
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_POS (23U)
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_LEN (1U)
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_MSK (((1U << EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_LEN) - 1) << EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_POS)
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_UMSK (~(((1U << EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_LEN) - 1) << EF_DATA_1_WR_LOCK_DAT_1_RSVD_1_POS))
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_2 EF_DATA_1_WR_LOCK_DAT_1_RSVD_2
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_POS (24U)
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_LEN (1U)
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_MSK (((1U << EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_LEN) - 1) << EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_POS)
#define EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_UMSK (~(((1U << EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_LEN) - 1) << EF_DATA_1_WR_LOCK_DAT_1_RSVD_2_POS))
#define EF_DATA_1_RD_LOCK_KEY_SLOT_4 EF_DATA_1_RD_LOCK_KEY_SLOT_4
#define EF_DATA_1_RD_LOCK_KEY_SLOT_4_POS (25U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_4_LEN (1U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_4_MSK (((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_4_POS)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_4_UMSK (~(((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_4_POS))
#define EF_DATA_1_RD_LOCK_KEY_SLOT_5 EF_DATA_1_RD_LOCK_KEY_SLOT_5
#define EF_DATA_1_RD_LOCK_KEY_SLOT_5_POS (26U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_5_LEN (1U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_5_MSK (((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_5_POS)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_5_UMSK (~(((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_5_POS))
#define EF_DATA_1_RD_LOCK_KEY_SLOT_6 EF_DATA_1_RD_LOCK_KEY_SLOT_6
#define EF_DATA_1_RD_LOCK_KEY_SLOT_6_POS (27U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_6_LEN (1U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_6_MSK (((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_6_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_6_POS)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_6_UMSK (~(((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_6_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_6_POS))
#define EF_DATA_1_RD_LOCK_KEY_SLOT_7 EF_DATA_1_RD_LOCK_KEY_SLOT_7
#define EF_DATA_1_RD_LOCK_KEY_SLOT_7_POS (28U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_7_LEN (1U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_7_MSK (((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_7_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_7_POS)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_7_UMSK (~(((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_7_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_7_POS))
#define EF_DATA_1_RD_LOCK_KEY_SLOT_8 EF_DATA_1_RD_LOCK_KEY_SLOT_8
#define EF_DATA_1_RD_LOCK_KEY_SLOT_8_POS (29U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_8_LEN (1U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_8_MSK (((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_8_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_8_POS)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_8_UMSK (~(((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_8_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_8_POS))
#define EF_DATA_1_RD_LOCK_KEY_SLOT_9 EF_DATA_1_RD_LOCK_KEY_SLOT_9
#define EF_DATA_1_RD_LOCK_KEY_SLOT_9_POS (30U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_9_LEN (1U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_9_MSK (((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_9_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_9_POS)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_9_UMSK (~(((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_9_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_9_POS))
#define EF_DATA_1_RD_LOCK_KEY_SLOT_10 EF_DATA_1_RD_LOCK_KEY_SLOT_10
#define EF_DATA_1_RD_LOCK_KEY_SLOT_10_POS (31U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_10_LEN (1U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_10_MSK (((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_10_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_10_POS)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_10_UMSK (~(((1U << EF_DATA_1_RD_LOCK_KEY_SLOT_10_LEN) - 1) << EF_DATA_1_RD_LOCK_KEY_SLOT_10_POS))
struct ef_data_1_reg {
/* 0x0 reserved */
uint8_t RESERVED0x0[128];
/* 0x80 : ef_key_slot_4_w0 */
union {
struct {
uint32_t ef_key_slot_4_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w0;
/* 0x84 : ef_key_slot_4_w1 */
union {
struct {
uint32_t ef_key_slot_4_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w1;
/* 0x88 : ef_key_slot_4_w2 */
union {
struct {
uint32_t ef_key_slot_4_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w2;
/* 0x8C : ef_key_slot_4_w3 */
union {
struct {
uint32_t ef_key_slot_4_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w3;
/* 0x90 : ef_key_slot_5_w0 */
union {
struct {
uint32_t ef_key_slot_5_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w0;
/* 0x94 : ef_key_slot_5_w1 */
union {
struct {
uint32_t ef_key_slot_5_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w1;
/* 0x98 : ef_key_slot_5_w2 */
union {
struct {
uint32_t ef_key_slot_5_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w2;
/* 0x9C : ef_key_slot_5_w3 */
union {
struct {
uint32_t ef_key_slot_5_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w3;
/* 0xA0 : ef_key_slot_6_w0 */
union {
struct {
uint32_t ef_key_slot_6_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_6_w0;
/* 0xA4 : ef_key_slot_6_w1 */
union {
struct {
uint32_t ef_key_slot_6_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_6_w1;
/* 0xA8 : ef_key_slot_6_w2 */
union {
struct {
uint32_t ef_key_slot_6_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_6_w2;
/* 0xAC : ef_key_slot_6_w3 */
union {
struct {
uint32_t ef_key_slot_6_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_6_w3;
/* 0xB0 : ef_key_slot_7_w0 */
union {
struct {
uint32_t ef_key_slot_7_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_7_w0;
/* 0xB4 : ef_key_slot_7_w1 */
union {
struct {
uint32_t ef_key_slot_7_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_7_w1;
/* 0xB8 : ef_key_slot_7_w2 */
union {
struct {
uint32_t ef_key_slot_7_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_7_w2;
/* 0xBC : ef_key_slot_7_w3 */
union {
struct {
uint32_t ef_key_slot_7_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_7_w3;
/* 0xC0 : ef_key_slot_8_w0 */
union {
struct {
uint32_t ef_key_slot_8_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_8_w0;
/* 0xC4 : ef_key_slot_8_w1 */
union {
struct {
uint32_t ef_key_slot_8_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_8_w1;
/* 0xC8 : ef_key_slot_8_w2 */
union {
struct {
uint32_t ef_key_slot_8_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_8_w2;
/* 0xCC : ef_key_slot_8_w3 */
union {
struct {
uint32_t ef_key_slot_8_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_8_w3;
/* 0xD0 : ef_key_slot_9_w0 */
union {
struct {
uint32_t ef_key_slot_9_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_9_w0;
/* 0xD4 : ef_key_slot_9_w1 */
union {
struct {
uint32_t ef_key_slot_9_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_9_w1;
/* 0xD8 : ef_key_slot_9_w2 */
union {
struct {
uint32_t ef_key_slot_9_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_9_w2;
/* 0xDC : ef_key_slot_9_w3 */
union {
struct {
uint32_t ef_key_slot_9_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_9_w3;
/* 0xE0 : ef_key_slot_10_w0 */
union {
struct {
uint32_t ef_key_slot_10_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_10_w0;
/* 0xE4 : ef_key_slot_10_w1 */
union {
struct {
uint32_t ef_key_slot_10_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_10_w1;
/* 0xE8 : ef_key_slot_10_w2 */
union {
struct {
uint32_t ef_key_slot_10_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_10_w2;
/* 0xEC : ef_key_slot_10_w3 */
union {
struct {
uint32_t ef_key_slot_10_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_10_w3;
/* 0xF0 : ef_dat_1_rsvd_0 */
union {
struct {
uint32_t ef_dat_1_rsvd_0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dat_1_rsvd_0;
/* 0xF4 : ef_dat_1_rsvd_1 */
union {
struct {
uint32_t ef_dat_1_rsvd_1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dat_1_rsvd_1;
/* 0xF8 : ef_dat_1_rsvd_2 */
union {
struct {
uint32_t ef_dat_1_rsvd_2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dat_1_rsvd_2;
/* 0xFC : ef_data_1_lock */
union {
struct {
uint32_t wr_lock_rsvd_1 : 15; /* [14: 0], r/w, 0x0 */
uint32_t wr_lock_key_slot_4 : 1; /* [ 15], r/w, 0x0 */
uint32_t wr_lock_key_slot_5 : 1; /* [ 16], r/w, 0x0 */
uint32_t wr_lock_key_slot_6 : 1; /* [ 17], r/w, 0x0 */
uint32_t wr_lock_key_slot_7 : 1; /* [ 18], r/w, 0x0 */
uint32_t wr_lock_key_slot_8 : 1; /* [ 19], r/w, 0x0 */
uint32_t wr_lock_key_slot_9 : 1; /* [ 20], r/w, 0x0 */
uint32_t wr_lock_key_slot_10 : 1; /* [ 21], r/w, 0x0 */
uint32_t wr_lock_dat_1_rsvd_0 : 1; /* [ 22], r/w, 0x0 */
uint32_t wr_lock_dat_1_rsvd_1 : 1; /* [ 23], r/w, 0x0 */
uint32_t wr_lock_dat_1_rsvd_2 : 1; /* [ 24], r/w, 0x0 */
uint32_t rd_lock_key_slot_4 : 1; /* [ 25], r/w, 0x0 */
uint32_t rd_lock_key_slot_5 : 1; /* [ 26], r/w, 0x0 */
uint32_t rd_lock_key_slot_6 : 1; /* [ 27], r/w, 0x0 */
uint32_t rd_lock_key_slot_7 : 1; /* [ 28], r/w, 0x0 */
uint32_t rd_lock_key_slot_8 : 1; /* [ 29], r/w, 0x0 */
uint32_t rd_lock_key_slot_9 : 1; /* [ 30], r/w, 0x0 */
uint32_t rd_lock_key_slot_10 : 1; /* [ 31], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_data_1_lock;
};
#endif /* __EF_DATA_1_REG_H__ */

237
include/bl808/emac_reg.h Normal file
View File

@ -0,0 +1,237 @@
/**
******************************************************************************
* @file emac_reg.h
* @version V1.0
* @date 2022-09-27
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2022 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_EMAC_H__
#define __HARDWARE_EMAC_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define EMAC_MODE_OFFSET (0x0)
#define EMAC_INT_SOURCE_OFFSET (0x4)
#define EMAC_INT_MASK_OFFSET (0x8)
#define EMAC_IPGT_OFFSET (0xC)
#define EMAC_PACKETLEN_OFFSET (0x18)
#define EMAC_COLLCONFIG_OFFSET (0x1C)
#define EMAC_TX_BD_NUM_OFFSET (0x20)
#define EMAC_MIIMODE_OFFSET (0x28)
#define EMAC_MIICOMMAND_OFFSET (0x2C)
#define EMAC_MIIADDRESS_OFFSET (0x30)
#define EMAC_MIITX_DATA_OFFSET (0x34)
#define EMAC_MIIRX_DATA_OFFSET (0x38)
#define EMAC_MIISTATUS_OFFSET (0x3C)
#define EMAC_MAC_ADDR0_OFFSET (0x40)
#define EMAC_MAC_ADDR1_OFFSET (0x44)
#define EMAC_HASH0_ADDR_OFFSET (0x48)
#define EMAC_HASH1_ADDR_OFFSET (0x4C)
#define EMAC_TXCTRL_OFFSET (0x50)
#define EMAC_DMA_DESC_OFFSET (0x400)
/* 0x0 : EMAC MODE config */
#define EMAC_RX_EN (1 << 0U)
#define EMAC_TX_EN (1 << 1U)
#define EMAC_NOPRE (1 << 2U)
#define EMAC_BRO (1 << 3U)
#define EMAC_PRO (1 << 5U)
#define EMAC_IFG (1 << 6U)
#define EMAC_FULLD (1 << 10U)
#define EMAC_CRCEN (1 << 13U)
#define EMAC_HUGEN (1 << 14U)
#define EMAC_PAD (1 << 15U)
#define EMAC_RECSMALL (1 << 16U)
#define EMAC_RMII_EN (1 << 17U)
/* 0x4 : INT_SOURCE */
#define EMAC_TXB (1 << 0U)
#define EMAC_TXE (1 << 1U)
#define EMAC_RXB (1 << 2U)
#define EMAC_RXE (1 << 3U)
#define EMAC_BUSY (1 << 4U)
#define EMAC_TXC (1 << 5U)
#define EMAC_RXC (1 << 6U)
/* 0x8 : INT_MASK */
#define EMAC_TXB_M (1 << 0U)
#define EMAC_TXE_M (1 << 1U)
#define EMAC_RXB_M (1 << 2U)
#define EMAC_RXE_M (1 << 3U)
#define EMAC_BUSY_M (1 << 4U)
#define EMAC_TXC_M (1 << 5U)
#define EMAC_RXC_M (1 << 6U)
/* 0xC : IPGT */
#define EMAC_IPGT_SHIFT (0U)
#define EMAC_IPGT_MASK (0x7f << EMAC_IPGT_SHIFT)
/* 0x18 : PACKETLEN */
#define EMAC_MAXFL_SHIFT (0U)
#define EMAC_MAXFL_MASK (0xffff << EMAC_MAXFL_SHIFT)
#define EMAC_MINFL_SHIFT (16U)
#define EMAC_MINFL_MASK (0xffff << EMAC_MINFL_SHIFT)
/* 0x1C : COLLCONFIG */
#define EMAC_COLLVALID_SHIFT (0U)
#define EMAC_COLLVALID_MASK (0x3F << EMAC_COLLVALID_SHIFT)
#define EMAC_MAXRET_SHIFT (16U)
#define EMAC_MAXRET_MASK (0xF << EMAC_MAXRET_SHIFT)
/* 0x20 : TX_BD_NUM */
#define EMAC_TXBDNUM_SHIFT (0U)
#define EMAC_TXBDNUM_MASK (0xff << EMAC_TXBDNUM_SHIFT)
#define EMAC_TXBDPTR_SHIFT (16U)
#define EMAC_TXBDPTR_MASK (0x7f << EMAC_TXBDPTR_SHIFT)
#define EMAC_RXBDPTR_SHIFT (24U)
#define EMAC_RXBDPTR_MASK (0x7f << EMAC_RXBDPTR_SHIFT)
/* 0x28 : MIIMODE */
#define EMAC_CLKDIV_SHIFT (0U)
#define EMAC_CLKDIV_MASK (0xff << EMAC_CLKDIV_SHIFT)
#define EMAC_MIINOPRE (1 << 8U)
/* 0x2C : MIICOMMAND */
#define EMAC_SCANSTAT (1 << 0U)
#define EMAC_RSTAT (1 << 1U)
#define EMAC_WCTRLDATA (1 << 2U)
/* 0x30 : MIIADDRESS */
#define EMAC_FIAD_SHIFT (0U)
#define EMAC_FIAD_MASK (0x1f << EMAC_FIAD_SHIFT)
#define EMAC_RGAD_SHIFT (8U)
#define EMAC_RGAD_MASK (0x1f << EMAC_RGAD_SHIFT)
/* 0x34 : MIITX_DATA */
#define EMAC_CTRLDATA_SHIFT (0U)
#define EMAC_CTRLDATA_MASK (0xffff << EMAC_CTRLDATA_SHIFT)
/* 0x38 : MIIRX_DATA */
#define EMAC_PRSD_SHIFT (0U)
#define EMAC_PRSD_MASK (0xffff << EMAC_PRSD_SHIFT)
/* 0x3C : MIISTATUS */
#define EMAC_MIIM_LINKFAIL (1 << 0U)
#define EMAC_MIIM_BUSY (1 << 1U)
/* 0x40 : MAC_ADDR0 */
#define EMAC_MAC_B5_SHIFT (0U)
#define EMAC_MAC_B5_MASK (0xff << EMAC_MAC_B5_SHIFT)
#define EMAC_MAC_B4_SHIFT (8U)
#define EMAC_MAC_B4_MASK (0xff << EMAC_MAC_B4_SHIFT)
#define EMAC_MAC_B3_SHIFT (16U)
#define EMAC_MAC_B3_MASK (0xff << EMAC_MAC_B3_SHIFT)
#define EMAC_MAC_B2_SHIFT (24U)
#define EMAC_MAC_B2_MASK (0xff << EMAC_MAC_B2_SHIFT)
/* 0x44 : MAC_ADDR1 */
#define EMAC_MAC_B1_SHIFT (0U)
#define EMAC_MAC_B1_MASK (0xff << EMAC_MAC_B1_SHIFT)
#define EMAC_MAC_B0_SHIFT (8U)
#define EMAC_MAC_B0_MASK (0xff << EMAC_MAC_B0_SHIFT)
/* 0x48 : HASH0_ADDR */
#define EMAC_HASH0_SHIFT (0U)
#define EMAC_HASH0_MASK (0xffffffff << EMAC_HASH0_SHIFT)
/* 0x4C : HASH1_ADDR */
#define EMAC_HASH1_SHIFT (0U)
#define EMAC_HASH1_MASK (0xffffffff << EMAC_HASH1_SHIFT)
/* 0x50 : TXCTRL */
#define EMAC_TXPAUSETV_SHIFT (0U)
#define EMAC_TXPAUSETV_MASK (0xffff << EMAC_TXPAUSETV_SHIFT)
#define EMAC_TXPAUSERQ_SHIFT (16U)
#define EMAC_TXPAUSERQ_MASK (0x1 << EMAC_TXPAUSETV_SHIFT)
/* 0x400 ：EAMC DMA BD DESC */
/* EMAC TX BD DESC BASE: (TX_BD_NUM * 8) */
#define EMAC_BD_TX_CS_SHIFT (0) /*!< Carrier Sense Lost */
#define EMAC_BD_TX_CS_MASK (1 << EMAC_BD_TX_CS_SHIFT)
#define EMAC_BD_TX_DF_SHIFT (1) /*!< Defer Indication */
#define EMAC_BD_TX_DF_MASK (1 << EMAC_BD_TX_DF_SHIFT)
#define EMAC_BD_TX_LC_SHIFT (2) /*!< Late Collision */
#define EMAC_BD_TX_LC_MASK (1 << EMAC_BD_TX_LC_SHIFT)
#define EMAC_BD_TX_RL_SHIFT (3) /*!< Retransmission Limit */
#define EMAC_BD_TX_RL_MASK (1 << EMAC_BD_TX_RL_SHIFT)
#define EMAC_BD_TX_RTRY_SHIFT (4) /*!< Retry Count */
#define EMAC_BD_TX_RTRY_MASK (4 << EMAC_BD_TX_RTRY_SHIFT)
#define EMAC_BD_TX_UR_SHIFT (8) /*!< Underrun */
#define EMAC_BD_TX_UR_MASK (1 << EMAC_BD_TX_UR_SHIFT)
#define EMAC_BD_TX_EOF_SHIFT (10) /*!< EOF */
#define EMAC_BD_TX_EOF_MASK (1 << EMAC_BD_TX_EOF_SHIFT)
#define EMAC_BD_TX_CRC_SHIFT (11) /*!< CRC Enable */
#define EMAC_BD_TX_CRC_MASK (1 << EMAC_BD_TX_CRC_SHIFT)
#define EMAC_BD_TX_PAD_SHIFT (12) /*!< PAD enable */
#define EMAC_BD_TX_PAD_MASK (1 << EMAC_BD_TX_PAD_SHIFT)
#define EMAC_BD_TX_WR_SHIFT (13) /*!< Wrap */
#define EMAC_BD_TX_WR_MASK (1 << EMAC_BD_TX_WR_SHIFT)
#define EMAC_BD_TX_IRQ_SHIFT (14) /*!< Interrupt Request Enable */
#define EMAC_BD_TX_IRQ_MASK (1 << EMAC_BD_TX_IRQ_SHIFT)
#define EMAC_BD_TX_RD_SHIFT (15) /*!< The data buffer is ready for transmission or is currently being transmitted. You are not allowed to change it */
#define EMAC_BD_TX_RD_MASK (1 << EMAC_BD_TX_RD_SHIFT)
#define EMAC_BD_TX_LEN_SHIFT (16) /*!< TX Data buffer length */
#define EMAC_BD_TX_LEN_MASK (0xffff << EMAC_BD_TX_LEN_SHIFT)
/* RX BD DESC BASE: ((TX_BD_NUM + RX_BD_NUM) * 8) */
#define EMAC_BD_RX_LC_SHIFT (0) /*!< Late Collision */
#define EMAC_BD_RX_LC_MASK (1 << EMAC_BD_RX_LC_SHIFT)
#define EMAC_BD_RX_CRC_SHIFT (1) /*!< RX CRC Error */
#define EMAC_BD_RX_CRC_MASK (1 << EMAC_BD_RX_CRC_SHIFT)
#define EMAC_BD_RX_SF_SHIFT (2) /*!< Short Frame */
#define EMAC_BD_RX_SF_MASK (1 << EMAC_BD_RX_SF_SHIFT)
#define EMAC_BD_RX_TL_SHIFT (3) /*!< Too Long */
#define EMAC_BD_RX_TL_MASK (1 << EMAC_BD_RX_TL_SHIFT)
#define EMAC_BD_RX_DN_SHIFT (4) /*!< Dribble Nibble */
#define EMAC_BD_RX_DN_MASK (1 << EMAC_BD_RX_DN_SHIFT)
#define EMAC_BD_RX_RE_SHIFT (5) /*!< Receive Error */
#define EMAC_BD_RX_RE_MASK (1 << EMAC_BD_RX_RE_SHIFT)
#define EMAC_BD_RX_OR_SHIFT (6) /*!< Overrun */
#define EMAC_BD_RX_OR_MASK (1 << EMAC_BD_RX_OR_SHIFT)
#define EMAC_BD_RX_M_SHIFT (7) /*!< Miss */
#define EMAC_BD_RX_M_MASK (1 << EMAC_BD_RX_M_SHIFT)
#define EMAC_BD_RX_CF_SHIFT (8) /*!< Control Frame Received */
#define EMAC_BD_RX_CF_MASK (1 << EMAC_BD_RX_CF_SHIFT)
#define EMAC_BD_RX_WR_SHIFT (13) /*!< Wrap */
#define EMAC_BD_RX_WR_MASK (1 << EMAC_BD_RX_WR_SHIFT)
#define EMAC_BD_RX_IRQ_SHIFT (14) /*!< Interrupt Request Enable */
#define EMAC_BD_RX_IRQ_MASK (1 << EMAC_BD_RX_IRQ_SHIFT)
#define EMAC_BD_RX_E_SHIFT (15) /*!< The data buffer is empty (and ready for receiving data) or currently receiving data */
#define EMAC_BD_RX_E_MASK (1 << EMAC_BD_RX_E_SHIFT)
#define EMAC_BD_RX_LEN_SHIFT (16) /*!< RX Data buffer length */
#define EMAC_BD_RX_LEN_MASK (0xffff << EMAC_BD_RX_LEN_SHIFT)
/* MAX BD DESC 0x7FF */
#endif /* __HARDWARE_EMAC_H__ */

13188
include/bl808/glb_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

1472
include/bl808/gpio_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

336
include/bl808/gpip_reg.h Normal file
View File

@ -0,0 +1,336 @@
/**
******************************************************************************
* @file gpip_reg.h
* @version V1.2
* @date 2022-03-7
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2022 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __GPIP_REG_H__
#define __GPIP_REG_H__
#include <linux/types.h>
/* 0x0 : gpadc_config */
#define GPIP_GPADC_CONFIG_OFFSET (0x0)
#define GPIP_GPADC_DMA_EN GPIP_GPADC_DMA_EN
#define GPIP_GPADC_DMA_EN_POS (0U)
#define GPIP_GPADC_DMA_EN_LEN (1U)
#define GPIP_GPADC_DMA_EN_MSK (((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS)
#define GPIP_GPADC_DMA_EN_UMSK (~(((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS))
#define GPIP_GPADC_FIFO_CLR GPIP_GPADC_FIFO_CLR
#define GPIP_GPADC_FIFO_CLR_POS (1U)
#define GPIP_GPADC_FIFO_CLR_LEN (1U)
#define GPIP_GPADC_FIFO_CLR_MSK (((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS)
#define GPIP_GPADC_FIFO_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS))
#define GPIP_GPADC_FIFO_NE GPIP_GPADC_FIFO_NE
#define GPIP_GPADC_FIFO_NE_POS (2U)
#define GPIP_GPADC_FIFO_NE_LEN (1U)
#define GPIP_GPADC_FIFO_NE_MSK (((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS)
#define GPIP_GPADC_FIFO_NE_UMSK (~(((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS))
#define GPIP_GPADC_FIFO_FULL GPIP_GPADC_FIFO_FULL
#define GPIP_GPADC_FIFO_FULL_POS (3U)
#define GPIP_GPADC_FIFO_FULL_LEN (1U)
#define GPIP_GPADC_FIFO_FULL_MSK (((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS)
#define GPIP_GPADC_FIFO_FULL_UMSK (~(((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS))
#define GPIP_GPADC_RDY GPIP_GPADC_RDY
#define GPIP_GPADC_RDY_POS (4U)
#define GPIP_GPADC_RDY_LEN (1U)
#define GPIP_GPADC_RDY_MSK (((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS)
#define GPIP_GPADC_RDY_UMSK (~(((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS))
#define GPIP_GPADC_FIFO_OVERRUN GPIP_GPADC_FIFO_OVERRUN
#define GPIP_GPADC_FIFO_OVERRUN_POS (5U)
#define GPIP_GPADC_FIFO_OVERRUN_LEN (1U)
#define GPIP_GPADC_FIFO_OVERRUN_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS)
#define GPIP_GPADC_FIFO_OVERRUN_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS))
#define GPIP_GPADC_FIFO_UNDERRUN GPIP_GPADC_FIFO_UNDERRUN
#define GPIP_GPADC_FIFO_UNDERRUN_POS (6U)
#define GPIP_GPADC_FIFO_UNDERRUN_LEN (1U)
#define GPIP_GPADC_FIFO_UNDERRUN_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS)
#define GPIP_GPADC_FIFO_UNDERRUN_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS))
#define GPIP_GPADC_RDY_CLR GPIP_GPADC_RDY_CLR
#define GPIP_GPADC_RDY_CLR_POS (8U)
#define GPIP_GPADC_RDY_CLR_LEN (1U)
#define GPIP_GPADC_RDY_CLR_MSK (((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS)
#define GPIP_GPADC_RDY_CLR_UMSK (~(((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS))
#define GPIP_GPADC_FIFO_OVERRUN_CLR GPIP_GPADC_FIFO_OVERRUN_CLR
#define GPIP_GPADC_FIFO_OVERRUN_CLR_POS (9U)
#define GPIP_GPADC_FIFO_OVERRUN_CLR_LEN (1U)
#define GPIP_GPADC_FIFO_OVERRUN_CLR_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS)
#define GPIP_GPADC_FIFO_OVERRUN_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS))
#define GPIP_GPADC_FIFO_UNDERRUN_CLR GPIP_GPADC_FIFO_UNDERRUN_CLR
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_POS (10U)
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN (1U)
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS)
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS))
#define GPIP_GPADC_RDY_MASK GPIP_GPADC_RDY_MASK
#define GPIP_GPADC_RDY_MASK_POS (12U)
#define GPIP_GPADC_RDY_MASK_LEN (1U)
#define GPIP_GPADC_RDY_MASK_MSK (((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS)
#define GPIP_GPADC_RDY_MASK_UMSK (~(((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS))
#define GPIP_GPADC_FIFO_OVERRUN_MASK GPIP_GPADC_FIFO_OVERRUN_MASK
#define GPIP_GPADC_FIFO_OVERRUN_MASK_POS (13U)
#define GPIP_GPADC_FIFO_OVERRUN_MASK_LEN (1U)
#define GPIP_GPADC_FIFO_OVERRUN_MASK_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS)
#define GPIP_GPADC_FIFO_OVERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS))
#define GPIP_GPADC_FIFO_UNDERRUN_MASK GPIP_GPADC_FIFO_UNDERRUN_MASK
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_POS (14U)
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN (1U)
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS)
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS))
#define GPIP_GPADC_FIFO_DATA_COUNT GPIP_GPADC_FIFO_DATA_COUNT
#define GPIP_GPADC_FIFO_DATA_COUNT_POS (16U)
#define GPIP_GPADC_FIFO_DATA_COUNT_LEN (6U)
#define GPIP_GPADC_FIFO_DATA_COUNT_MSK (((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS)
#define GPIP_GPADC_FIFO_DATA_COUNT_UMSK (~(((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS))
#define GPIP_GPADC_FIFO_THL GPIP_GPADC_FIFO_THL
#define GPIP_GPADC_FIFO_THL_POS (22U)
#define GPIP_GPADC_FIFO_THL_LEN (2U)
#define GPIP_GPADC_FIFO_THL_MSK (((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS)
#define GPIP_GPADC_FIFO_THL_UMSK (~(((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS))
/* 0x4 : gpadc_dma_rdata */
#define GPIP_GPADC_DMA_RDATA_OFFSET (0x4)
#define GPIP_GPADC_DMA_RDATA GPIP_GPADC_DMA_RDATA
#define GPIP_GPADC_DMA_RDATA_POS (0U)
#define GPIP_GPADC_DMA_RDATA_LEN (26U)
#define GPIP_GPADC_DMA_RDATA_MSK (((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS)
#define GPIP_GPADC_DMA_RDATA_UMSK (~(((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS))
/* 0x20 : gpadc_pir_train */
#define GPIP_GPADC_PIR_TRAIN_OFFSET (0x20)
#define GPIP_PIR_EXTEND GPIP_PIR_EXTEND
#define GPIP_PIR_EXTEND_POS (0U)
#define GPIP_PIR_EXTEND_LEN (5U)
#define GPIP_PIR_EXTEND_MSK (((1U<<GPIP_PIR_EXTEND_LEN)-1)<<GPIP_PIR_EXTEND_POS)
#define GPIP_PIR_EXTEND_UMSK (~(((1U<<GPIP_PIR_EXTEND_LEN)-1)<<GPIP_PIR_EXTEND_POS))
#define GPIP_PIR_CNT_V GPIP_PIR_CNT_V
#define GPIP_PIR_CNT_V_POS (8U)
#define GPIP_PIR_CNT_V_LEN (5U)
#define GPIP_PIR_CNT_V_MSK (((1U<<GPIP_PIR_CNT_V_LEN)-1)<<GPIP_PIR_CNT_V_POS)
#define GPIP_PIR_CNT_V_UMSK (~(((1U<<GPIP_PIR_CNT_V_LEN)-1)<<GPIP_PIR_CNT_V_POS))
#define GPIP_PIR_TRAIN GPIP_PIR_TRAIN
#define GPIP_PIR_TRAIN_POS (16U)
#define GPIP_PIR_TRAIN_LEN (1U)
#define GPIP_PIR_TRAIN_MSK (((1U<<GPIP_PIR_TRAIN_LEN)-1)<<GPIP_PIR_TRAIN_POS)
#define GPIP_PIR_TRAIN_UMSK (~(((1U<<GPIP_PIR_TRAIN_LEN)-1)<<GPIP_PIR_TRAIN_POS))
#define GPIP_PIR_STOP GPIP_PIR_STOP
#define GPIP_PIR_STOP_POS (17U)
#define GPIP_PIR_STOP_LEN (1U)
#define GPIP_PIR_STOP_MSK (((1U<<GPIP_PIR_STOP_LEN)-1)<<GPIP_PIR_STOP_POS)
#define GPIP_PIR_STOP_UMSK (~(((1U<<GPIP_PIR_STOP_LEN)-1)<<GPIP_PIR_STOP_POS))
/* 0x40 : gpdac_config */
#define GPIP_GPDAC_CONFIG_OFFSET (0x40)
#define GPIP_GPDAC_EN GPIP_GPDAC_EN
#define GPIP_GPDAC_EN_POS (0U)
#define GPIP_GPDAC_EN_LEN (1U)
#define GPIP_GPDAC_EN_MSK (((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS)
#define GPIP_GPDAC_EN_UMSK (~(((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS))
#define GPIP_GPDAC_MODE GPIP_GPDAC_MODE
#define GPIP_GPDAC_MODE_POS (8U)
#define GPIP_GPDAC_MODE_LEN (3U)
#define GPIP_GPDAC_MODE_MSK (((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS)
#define GPIP_GPDAC_MODE_UMSK (~(((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS))
#define GPIP_GPDAC_CH_A_SEL GPIP_GPDAC_CH_A_SEL
#define GPIP_GPDAC_CH_A_SEL_POS (16U)
#define GPIP_GPDAC_CH_A_SEL_LEN (4U)
#define GPIP_GPDAC_CH_A_SEL_MSK (((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS)
#define GPIP_GPDAC_CH_A_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS))
#define GPIP_GPDAC_CH_B_SEL GPIP_GPDAC_CH_B_SEL
#define GPIP_GPDAC_CH_B_SEL_POS (20U)
#define GPIP_GPDAC_CH_B_SEL_LEN (4U)
#define GPIP_GPDAC_CH_B_SEL_MSK (((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS)
#define GPIP_GPDAC_CH_B_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS))
/* 0x44 : gpdac_dma_config */
#define GPIP_GPDAC_DMA_CONFIG_OFFSET (0x44)
#define GPIP_GPDAC_DMA_TX_EN GPIP_GPDAC_DMA_TX_EN
#define GPIP_GPDAC_DMA_TX_EN_POS (0U)
#define GPIP_GPDAC_DMA_TX_EN_LEN (1U)
#define GPIP_GPDAC_DMA_TX_EN_MSK (((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS)
#define GPIP_GPDAC_DMA_TX_EN_UMSK (~(((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS))
#define GPIP_GPDAC_DMA_INV_MSB GPIP_GPDAC_DMA_INV_MSB
#define GPIP_GPDAC_DMA_INV_MSB_POS (1U)
#define GPIP_GPDAC_DMA_INV_MSB_LEN (1U)
#define GPIP_GPDAC_DMA_INV_MSB_MSK (((1U<<GPIP_GPDAC_DMA_INV_MSB_LEN)-1)<<GPIP_GPDAC_DMA_INV_MSB_POS)
#define GPIP_GPDAC_DMA_INV_MSB_UMSK (~(((1U<<GPIP_GPDAC_DMA_INV_MSB_LEN)-1)<<GPIP_GPDAC_DMA_INV_MSB_POS))
#define GPIP_GPDAC_DMA_FORMAT GPIP_GPDAC_DMA_FORMAT
#define GPIP_GPDAC_DMA_FORMAT_POS (4U)
#define GPIP_GPDAC_DMA_FORMAT_LEN (4U)
#define GPIP_GPDAC_DMA_FORMAT_MSK (((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS)
#define GPIP_GPDAC_DMA_FORMAT_UMSK (~(((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS))
/* 0x48 : gpdac_dma_wdata */
#define GPIP_GPDAC_DMA_WDATA_OFFSET (0x48)
#define GPIP_GPDAC_DMA_WDATA GPIP_GPDAC_DMA_WDATA
#define GPIP_GPDAC_DMA_WDATA_POS (0U)
#define GPIP_GPDAC_DMA_WDATA_LEN (32U)
#define GPIP_GPDAC_DMA_WDATA_MSK (((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS)
#define GPIP_GPDAC_DMA_WDATA_UMSK (~(((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS))
/* 0x4C : gpdac_tx_fifo_status */
#define GPIP_GPDAC_TX_FIFO_STATUS_OFFSET (0x4C)
#define GPIP_TX_FIFO_EMPTY GPIP_TX_FIFO_EMPTY
#define GPIP_TX_FIFO_EMPTY_POS (0U)
#define GPIP_TX_FIFO_EMPTY_LEN (1U)
#define GPIP_TX_FIFO_EMPTY_MSK (((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS)
#define GPIP_TX_FIFO_EMPTY_UMSK (~(((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS))
#define GPIP_TX_FIFO_FULL GPIP_TX_FIFO_FULL
#define GPIP_TX_FIFO_FULL_POS (1U)
#define GPIP_TX_FIFO_FULL_LEN (1U)
#define GPIP_TX_FIFO_FULL_MSK (((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS)
#define GPIP_TX_FIFO_FULL_UMSK (~(((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS))
#define GPIP_TX_CS GPIP_TX_CS
#define GPIP_TX_CS_POS (2U)
#define GPIP_TX_CS_LEN (2U)
#define GPIP_TX_CS_MSK (((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS)
#define GPIP_TX_CS_UMSK (~(((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS))
#define GPIP_TXFIFORDPTR GPIP_TXFIFORDPTR
#define GPIP_TXFIFORDPTR_POS (4U)
#define GPIP_TXFIFORDPTR_LEN (4U)
#define GPIP_TXFIFORDPTR_MSK (((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS)
#define GPIP_TXFIFORDPTR_UMSK (~(((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS))
#define GPIP_TXFIFOWRPTR GPIP_TXFIFOWRPTR
#define GPIP_TXFIFOWRPTR_POS (8U)
#define GPIP_TXFIFOWRPTR_LEN (2U)
#define GPIP_TXFIFOWRPTR_MSK (((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS)
#define GPIP_TXFIFOWRPTR_UMSK (~(((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS))
struct gpip_reg {
/* 0x0 : gpadc_config */
union {
struct
{
uint32_t gpadc_dma_en : 1; /* [ 0], r/w, 0x0 */
uint32_t gpadc_fifo_clr : 1; /* [ 1], w1c, 0x0 */
uint32_t gpadc_fifo_ne : 1; /* [ 2], r, 0x0 */
uint32_t gpadc_fifo_full : 1; /* [ 3], r, 0x0 */
uint32_t gpadc_rdy : 1; /* [ 4], r, 0x0 */
uint32_t gpadc_fifo_overrun : 1; /* [ 5], r, 0x0 */
uint32_t gpadc_fifo_underrun : 1; /* [ 6], r, 0x0 */
uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t gpadc_rdy_clr : 1; /* [ 8], r/w, 0x0 */
uint32_t gpadc_fifo_overrun_clr : 1; /* [ 9], r/w, 0x0 */
uint32_t gpadc_fifo_underrun_clr : 1; /* [ 10], r/w, 0x0 */
uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
uint32_t gpadc_rdy_mask : 1; /* [ 12], r/w, 0x0 */
uint32_t gpadc_fifo_overrun_mask : 1; /* [ 13], r/w, 0x0 */
uint32_t gpadc_fifo_underrun_mask : 1; /* [ 14], r/w, 0x0 */
uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
uint32_t gpadc_fifo_data_count : 6; /* [21:16], r, 0x0 */
uint32_t gpadc_fifo_thl : 2; /* [23:22], r/w, 0x0 */
uint32_t rsvd_31_24 : 8; /* [31:24], rsvd, 0x0 */
} BF;
uint32_t WORD;
} gpadc_config;
/* 0x4 : gpadc_dma_rdata */
union {
struct
{
uint32_t gpadc_dma_rdata : 26; /* [25: 0], r, 0x0 */
uint32_t rsvd_31_26 : 6; /* [31:26], rsvd, 0x0 */
} BF;
uint32_t WORD;
} gpadc_dma_rdata;
/* 0x8 reserved */
uint8_t RESERVED0x8[24];
/* 0x20 : gpadc_pir_train */
union {
struct {
uint32_t pir_extend : 5; /* [ 4: 0], r/w, 0xf */
uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
uint32_t pir_cnt_v : 5; /* [12: 8], r, 0x0 */
uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
uint32_t pir_train : 1; /* [ 16], r/w, 0x0 */
uint32_t pir_stop : 1; /* [ 17], r, 0x0 */
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
}BF;
uint32_t WORD;
} gpadc_pir_train;
/* 0x24 reserved */
uint8_t RESERVED0x24[28];
/* 0x40 : gpdac_config */
union {
struct
{
uint32_t gpdac_en : 1; /* [ 0], r/w, 0x0 */
uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */
uint32_t gpdac_mode : 3; /* [10: 8], r/w, 0x0 */
uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */
uint32_t gpdac_ch_a_sel : 4; /* [19:16], r/w, 0x0 */
uint32_t gpdac_ch_b_sel : 4; /* [23:20], r/w, 0x0 */
uint32_t rsvd_31_24 : 8; /* [31:24], rsvd, 0xd */
} BF;
uint32_t WORD;
} gpdac_config;
/* 0x44 : gpdac_dma_config */
union {
struct
{
uint32_t gpdac_dma_tx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t gpdac_dma_inv_msb: 1; /* [ 1], r/w, 0x0 */
uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
uint32_t gpdac_dma_format : 4; /* [ 7: 4], r/w, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} gpdac_dma_config;
/* 0x48 : gpdac_dma_wdata */
union {
struct
{
uint32_t gpdac_dma_wdata : 32; /* [31: 0], w, x */
} BF;
uint32_t WORD;
} gpdac_dma_wdata;
/* 0x4C : gpdac_tx_fifo_status */
union {
struct
{
uint32_t tx_fifo_empty : 1; /* [ 0], r, 0x0 */
uint32_t tx_fifo_full : 1; /* [ 1], r, 0x0 */
uint32_t tx_cs : 2; /* [ 3: 2], r, 0x0 */
uint32_t TxFifoRdPtr : 4; /* [ 7: 4], r, 0x8 */
uint32_t TxFifoWrPtr : 2; /* [ 9: 8], r, 0x0 */
uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
} BF;
uint32_t WORD;
} gpdac_tx_fifo_status;
};
#endif /* __GPIP_REG_H__ */

894
include/bl808/hbn_reg.h Normal file
View File

@ -0,0 +1,894 @@
/**
******************************************************************************
* @file hbn_reg.h
* @version V1.0
* @date 2022-02-15
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HBN_REG_H__
#define __HBN_REG_H__
#include <linux/types.h>
/* 0x0 : HBN_CTL */
#define HBN_CTL_OFFSET (0x0)
#define HBN_RTC_CTL HBN_RTC_CTL
#define HBN_RTC_CTL_POS (0U)
#define HBN_RTC_CTL_LEN (4U)
#define HBN_RTC_CTL_MSK (((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS)
#define HBN_RTC_CTL_UMSK (~(((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS))
#define HBN_RTC_DLY_OPTION HBN_RTC_DLY_OPTION
#define HBN_RTC_DLY_OPTION_POS (4U)
#define HBN_RTC_DLY_OPTION_LEN (1U)
#define HBN_RTC_DLY_OPTION_MSK (((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS)
#define HBN_RTC_DLY_OPTION_UMSK (~(((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS))
#define HBN_PU_LDO18IO_AON HBN_PU_LDO18IO_AON
#define HBN_PU_LDO18IO_AON_POS (5U)
#define HBN_PU_LDO18IO_AON_LEN (1U)
#define HBN_PU_LDO18IO_AON_MSK (((1U << HBN_PU_LDO18IO_AON_LEN) - 1) << HBN_PU_LDO18IO_AON_POS)
#define HBN_PU_LDO18IO_AON_UMSK (~(((1U << HBN_PU_LDO18IO_AON_LEN) - 1) << HBN_PU_LDO18IO_AON_POS))
#define HBN_MODE HBN_MODE
#define HBN_MODE_POS (7U)
#define HBN_MODE_LEN (1U)
#define HBN_MODE_MSK (((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS)
#define HBN_MODE_UMSK (~(((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS))
#define HBN_TRAP_MODE HBN_TRAP_MODE
#define HBN_TRAP_MODE_POS (8U)
#define HBN_TRAP_MODE_LEN (1U)
#define HBN_TRAP_MODE_MSK (((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS)
#define HBN_TRAP_MODE_UMSK (~(((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS))
#define HBN_PWRDN_HBN_CORE HBN_PWRDN_HBN_CORE
#define HBN_PWRDN_HBN_CORE_POS (9U)
#define HBN_PWRDN_HBN_CORE_LEN (1U)
#define HBN_PWRDN_HBN_CORE_MSK (((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS)
#define HBN_PWRDN_HBN_CORE_UMSK (~(((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS))
#define HBN_SW_RST HBN_SW_RST
#define HBN_SW_RST_POS (12U)
#define HBN_SW_RST_LEN (1U)
#define HBN_SW_RST_MSK (((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS)
#define HBN_SW_RST_UMSK (~(((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS))
#define HBN_DIS_PWR_OFF_LDO11 HBN_DIS_PWR_OFF_LDO11
#define HBN_DIS_PWR_OFF_LDO11_POS (13U)
#define HBN_DIS_PWR_OFF_LDO11_LEN (1U)
#define HBN_DIS_PWR_OFF_LDO11_MSK (((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS)
#define HBN_DIS_PWR_OFF_LDO11_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS))
#define HBN_DIS_PWR_OFF_LDO11_RT HBN_DIS_PWR_OFF_LDO11_RT
#define HBN_DIS_PWR_OFF_LDO11_RT_POS (14U)
#define HBN_DIS_PWR_OFF_LDO11_RT_LEN (1U)
#define HBN_DIS_PWR_OFF_LDO11_RT_MSK (((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS)
#define HBN_DIS_PWR_OFF_LDO11_RT_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS))
#define HBN_LDO11_RT_VOUT_SEL HBN_LDO11_RT_VOUT_SEL
#define HBN_LDO11_RT_VOUT_SEL_POS (15U)
#define HBN_LDO11_RT_VOUT_SEL_LEN (4U)
#define HBN_LDO11_RT_VOUT_SEL_MSK (((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS)
#define HBN_LDO11_RT_VOUT_SEL_UMSK (~(((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS))
#define HBN_LDO11_AON_VOUT_SEL HBN_LDO11_AON_VOUT_SEL
#define HBN_LDO11_AON_VOUT_SEL_POS (19U)
#define HBN_LDO11_AON_VOUT_SEL_LEN (4U)
#define HBN_LDO11_AON_VOUT_SEL_MSK (((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS)
#define HBN_LDO11_AON_VOUT_SEL_UMSK (~(((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS))
#define HBN_PU_DCDC_AON HBN_PU_DCDC_AON
#define HBN_PU_DCDC_AON_POS (23U)
#define HBN_PU_DCDC_AON_LEN (1U)
#define HBN_PU_DCDC_AON_MSK (((1U << HBN_PU_DCDC_AON_LEN) - 1) << HBN_PU_DCDC_AON_POS)
#define HBN_PU_DCDC_AON_UMSK (~(((1U << HBN_PU_DCDC_AON_LEN) - 1) << HBN_PU_DCDC_AON_POS))
#define HBN_PU_DCDC18_AON HBN_PU_DCDC18_AON
#define HBN_PU_DCDC18_AON_POS (24U)
#define HBN_PU_DCDC18_AON_LEN (1U)
#define HBN_PU_DCDC18_AON_MSK (((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS)
#define HBN_PU_DCDC18_AON_UMSK (~(((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS))
#define HBN_PWR_ON_OPTION HBN_PWR_ON_OPTION
#define HBN_PWR_ON_OPTION_POS (25U)
#define HBN_PWR_ON_OPTION_LEN (1U)
#define HBN_PWR_ON_OPTION_MSK (((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS)
#define HBN_PWR_ON_OPTION_UMSK (~(((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS))
#define HBN_SRAM_SLP_OPTION HBN_SRAM_SLP_OPTION
#define HBN_SRAM_SLP_OPTION_POS (26U)
#define HBN_SRAM_SLP_OPTION_LEN (1U)
#define HBN_SRAM_SLP_OPTION_MSK (((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS)
#define HBN_SRAM_SLP_OPTION_UMSK (~(((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS))
#define HBN_SRAM_SLP HBN_SRAM_SLP
#define HBN_SRAM_SLP_POS (27U)
#define HBN_SRAM_SLP_LEN (1U)
#define HBN_SRAM_SLP_MSK (((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS)
#define HBN_SRAM_SLP_UMSK (~(((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS))
#define HBN_STATE HBN_STATE
#define HBN_STATE_POS (28U)
#define HBN_STATE_LEN (4U)
#define HBN_STATE_MSK (((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS)
#define HBN_STATE_UMSK (~(((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS))
/* 0x4 : HBN_TIME_L */
#define HBN_TIME_L_OFFSET (0x4)
#define HBN_TIME_L HBN_TIME_L
#define HBN_TIME_L_POS (0U)
#define HBN_TIME_L_LEN (32U)
#define HBN_TIME_L_MSK (((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS)
#define HBN_TIME_L_UMSK (~(((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS))
/* 0x8 : HBN_TIME_H */
#define HBN_TIME_H_OFFSET (0x8)
#define HBN_TIME_H HBN_TIME_H
#define HBN_TIME_H_POS (0U)
#define HBN_TIME_H_LEN (8U)
#define HBN_TIME_H_MSK (((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS)
#define HBN_TIME_H_UMSK (~(((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS))
/* 0xC : RTC_TIME_L */
#define HBN_RTC_TIME_L_OFFSET (0xC)
#define HBN_RTC_TIME_LATCH_L HBN_RTC_TIME_LATCH_L
#define HBN_RTC_TIME_LATCH_L_POS (0U)
#define HBN_RTC_TIME_LATCH_L_LEN (32U)
#define HBN_RTC_TIME_LATCH_L_MSK (((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS)
#define HBN_RTC_TIME_LATCH_L_UMSK (~(((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS))
/* 0x10 : RTC_TIME_H */
#define HBN_RTC_TIME_H_OFFSET (0x10)
#define HBN_RTC_TIME_LATCH_H HBN_RTC_TIME_LATCH_H
#define HBN_RTC_TIME_LATCH_H_POS (0U)
#define HBN_RTC_TIME_LATCH_H_LEN (8U)
#define HBN_RTC_TIME_LATCH_H_MSK (((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS)
#define HBN_RTC_TIME_LATCH_H_UMSK (~(((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS))
#define HBN_RTC_TIME_LATCH HBN_RTC_TIME_LATCH
#define HBN_RTC_TIME_LATCH_POS (31U)
#define HBN_RTC_TIME_LATCH_LEN (1U)
#define HBN_RTC_TIME_LATCH_MSK (((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS)
#define HBN_RTC_TIME_LATCH_UMSK (~(((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS))
/* 0x14 : HBN_IRQ_MODE */
#define HBN_IRQ_MODE_OFFSET (0x14)
#define HBN_PIN_WAKEUP_MODE HBN_PIN_WAKEUP_MODE
#define HBN_PIN_WAKEUP_MODE_POS (0U)
#define HBN_PIN_WAKEUP_MODE_LEN (4U)
#define HBN_PIN_WAKEUP_MODE_MSK (((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS)
#define HBN_PIN_WAKEUP_MODE_UMSK (~(((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS))
#define HBN_PIN_WAKEUP_MASK HBN_PIN_WAKEUP_MASK
#define HBN_PIN_WAKEUP_MASK_POS (4U)
#define HBN_PIN_WAKEUP_MASK_LEN (9U)
#define HBN_PIN_WAKEUP_MASK_MSK (((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS)
#define HBN_PIN_WAKEUP_MASK_UMSK (~(((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS))
#define HBN_REG_EN_HW_PU_PD HBN_REG_EN_HW_PU_PD
#define HBN_REG_EN_HW_PU_PD_POS (16U)
#define HBN_REG_EN_HW_PU_PD_LEN (1U)
#define HBN_REG_EN_HW_PU_PD_MSK (((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS)
#define HBN_REG_EN_HW_PU_PD_UMSK (~(((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS))
#define HBN_IRQ_BOR_EN HBN_IRQ_BOR_EN
#define HBN_IRQ_BOR_EN_POS (18U)
#define HBN_IRQ_BOR_EN_LEN (1U)
#define HBN_IRQ_BOR_EN_MSK (((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS)
#define HBN_IRQ_BOR_EN_UMSK (~(((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS))
#define HBN_IRQ_ACOMP0_EN HBN_IRQ_ACOMP0_EN
#define HBN_IRQ_ACOMP0_EN_POS (20U)
#define HBN_IRQ_ACOMP0_EN_LEN (2U)
#define HBN_IRQ_ACOMP0_EN_MSK (((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS)
#define HBN_IRQ_ACOMP0_EN_UMSK (~(((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS))
#define HBN_IRQ_ACOMP1_EN HBN_IRQ_ACOMP1_EN
#define HBN_IRQ_ACOMP1_EN_POS (22U)
#define HBN_IRQ_ACOMP1_EN_LEN (2U)
#define HBN_IRQ_ACOMP1_EN_MSK (((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS)
#define HBN_IRQ_ACOMP1_EN_UMSK (~(((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS))
#define HBN_PIN_WAKEUP_SEL HBN_PIN_WAKEUP_SEL
#define HBN_PIN_WAKEUP_SEL_POS (24U)
#define HBN_PIN_WAKEUP_SEL_LEN (3U)
#define HBN_PIN_WAKEUP_SEL_MSK (((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS)
#define HBN_PIN_WAKEUP_SEL_UMSK (~(((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS))
#define HBN_PIN_WAKEUP_EN HBN_PIN_WAKEUP_EN
#define HBN_PIN_WAKEUP_EN_POS (27U)
#define HBN_PIN_WAKEUP_EN_LEN (1U)
#define HBN_PIN_WAKEUP_EN_MSK (((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS)
#define HBN_PIN_WAKEUP_EN_UMSK (~(((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS))
/* 0x18 : HBN_IRQ_STAT */
#define HBN_IRQ_STAT_OFFSET (0x18)
#define HBN_IRQ_STAT HBN_IRQ_STAT
#define HBN_IRQ_STAT_POS (0U)
#define HBN_IRQ_STAT_LEN (32U)
#define HBN_IRQ_STAT_MSK (((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS)
#define HBN_IRQ_STAT_UMSK (~(((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS))
/* 0x1C : HBN_IRQ_CLR */
#define HBN_IRQ_CLR_OFFSET (0x1C)
#define HBN_IRQ_CLR HBN_IRQ_CLR
#define HBN_IRQ_CLR_POS (0U)
#define HBN_IRQ_CLR_LEN (32U)
#define HBN_IRQ_CLR_MSK (((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS)
#define HBN_IRQ_CLR_UMSK (~(((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS))
/* 0x20 : HBN_PIR_CFG */
#define HBN_PIR_CFG_OFFSET (0x20)
#define HBN_PIR_HPF_SEL HBN_PIR_HPF_SEL
#define HBN_PIR_HPF_SEL_POS (0U)
#define HBN_PIR_HPF_SEL_LEN (2U)
#define HBN_PIR_HPF_SEL_MSK (((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS)
#define HBN_PIR_HPF_SEL_UMSK (~(((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS))
#define HBN_PIR_LPF_SEL HBN_PIR_LPF_SEL
#define HBN_PIR_LPF_SEL_POS (2U)
#define HBN_PIR_LPF_SEL_LEN (1U)
#define HBN_PIR_LPF_SEL_MSK (((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS)
#define HBN_PIR_LPF_SEL_UMSK (~(((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS))
#define HBN_PIR_DIS HBN_PIR_DIS
#define HBN_PIR_DIS_POS (4U)
#define HBN_PIR_DIS_LEN (2U)
#define HBN_PIR_DIS_MSK (((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS)
#define HBN_PIR_DIS_UMSK (~(((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS))
#define HBN_PIR_EN HBN_PIR_EN
#define HBN_PIR_EN_POS (7U)
#define HBN_PIR_EN_LEN (1U)
#define HBN_PIR_EN_MSK (((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS)
#define HBN_PIR_EN_UMSK (~(((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS))
#define HBN_GPADC_CS HBN_GPADC_CS
#define HBN_GPADC_CS_POS (8U)
#define HBN_GPADC_CS_LEN (1U)
#define HBN_GPADC_CS_MSK (((1U << HBN_GPADC_CS_LEN) - 1) << HBN_GPADC_CS_POS)
#define HBN_GPADC_CS_UMSK (~(((1U << HBN_GPADC_CS_LEN) - 1) << HBN_GPADC_CS_POS))
/* 0x24 : HBN_PIR_VTH */
#define HBN_PIR_VTH_OFFSET (0x24)
#define HBN_PIR_VTH HBN_PIR_VTH
#define HBN_PIR_VTH_POS (0U)
#define HBN_PIR_VTH_LEN (14U)
#define HBN_PIR_VTH_MSK (((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS)
#define HBN_PIR_VTH_UMSK (~(((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS))
/* 0x28 : HBN_PIR_INTERVAL */
#define HBN_PIR_INTERVAL_OFFSET (0x28)
#define HBN_PIR_INTERVAL HBN_PIR_INTERVAL
#define HBN_PIR_INTERVAL_POS (0U)
#define HBN_PIR_INTERVAL_LEN (12U)
#define HBN_PIR_INTERVAL_MSK (((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS)
#define HBN_PIR_INTERVAL_UMSK (~(((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS))
/* 0x2C : HBN_BOR_CFG */
#define HBN_BOR_CFG_OFFSET (0x2C)
#define HBN_BOD_SEL HBN_BOD_SEL
#define HBN_BOD_SEL_POS (0U)
#define HBN_BOD_SEL_LEN (1U)
#define HBN_BOD_SEL_MSK (((1U << HBN_BOD_SEL_LEN) - 1) << HBN_BOD_SEL_POS)
#define HBN_BOD_SEL_UMSK (~(((1U << HBN_BOD_SEL_LEN) - 1) << HBN_BOD_SEL_POS))
#define HBN_BOD_VTH HBN_BOD_VTH
#define HBN_BOD_VTH_POS (1U)
#define HBN_BOD_VTH_LEN (3U)
#define HBN_BOD_VTH_MSK (((1U << HBN_BOD_VTH_LEN) - 1) << HBN_BOD_VTH_POS)
#define HBN_BOD_VTH_UMSK (~(((1U << HBN_BOD_VTH_LEN) - 1) << HBN_BOD_VTH_POS))
#define HBN_PU_BOD HBN_PU_BOD
#define HBN_PU_BOD_POS (4U)
#define HBN_PU_BOD_LEN (1U)
#define HBN_PU_BOD_MSK (((1U << HBN_PU_BOD_LEN) - 1) << HBN_PU_BOD_POS)
#define HBN_PU_BOD_UMSK (~(((1U << HBN_PU_BOD_LEN) - 1) << HBN_PU_BOD_POS))
#define HBN_R_BOD_OUT HBN_R_BOD_OUT
#define HBN_R_BOD_OUT_POS (5U)
#define HBN_R_BOD_OUT_LEN (1U)
#define HBN_R_BOD_OUT_MSK (((1U << HBN_R_BOD_OUT_LEN) - 1) << HBN_R_BOD_OUT_POS)
#define HBN_R_BOD_OUT_UMSK (~(((1U << HBN_R_BOD_OUT_LEN) - 1) << HBN_R_BOD_OUT_POS))
/* 0x30 : HBN_GLB */
#define HBN_GLB_OFFSET (0x30)
#define HBN_ROOT_CLK_SEL HBN_ROOT_CLK_SEL
#define HBN_ROOT_CLK_SEL_POS (0U)
#define HBN_ROOT_CLK_SEL_LEN (2U)
#define HBN_ROOT_CLK_SEL_MSK (((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS)
#define HBN_ROOT_CLK_SEL_UMSK (~(((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS))
#define HBN_UART_CLK_SEL HBN_UART_CLK_SEL
#define HBN_UART_CLK_SEL_POS (2U)
#define HBN_UART_CLK_SEL_LEN (1U)
#define HBN_UART_CLK_SEL_MSK (((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS)
#define HBN_UART_CLK_SEL_UMSK (~(((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS))
#define HBN_F32K_SEL HBN_F32K_SEL
#define HBN_F32K_SEL_POS (3U)
#define HBN_F32K_SEL_LEN (2U)
#define HBN_F32K_SEL_MSK (((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS)
#define HBN_F32K_SEL_UMSK (~(((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS))
#define HBN_RESET_EVENT HBN_RESET_EVENT
#define HBN_RESET_EVENT_POS (7U)
#define HBN_RESET_EVENT_LEN (6U)
#define HBN_RESET_EVENT_MSK (((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS)
#define HBN_RESET_EVENT_UMSK (~(((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS))
#define HBN_CLR_RESET_EVENT HBN_CLR_RESET_EVENT
#define HBN_CLR_RESET_EVENT_POS (13U)
#define HBN_CLR_RESET_EVENT_LEN (1U)
#define HBN_CLR_RESET_EVENT_MSK (((1U << HBN_CLR_RESET_EVENT_LEN) - 1) << HBN_CLR_RESET_EVENT_POS)
#define HBN_CLR_RESET_EVENT_UMSK (~(((1U << HBN_CLR_RESET_EVENT_LEN) - 1) << HBN_CLR_RESET_EVENT_POS))
#define HBN_UART_CLK_SEL2 HBN_UART_CLK_SEL2
#define HBN_UART_CLK_SEL2_POS (15U)
#define HBN_UART_CLK_SEL2_LEN (1U)
#define HBN_UART_CLK_SEL2_MSK (((1U << HBN_UART_CLK_SEL2_LEN) - 1) << HBN_UART_CLK_SEL2_POS)
#define HBN_UART_CLK_SEL2_UMSK (~(((1U << HBN_UART_CLK_SEL2_LEN) - 1) << HBN_UART_CLK_SEL2_POS))
#define HBN_SW_LDO11SOC_VOUT_SEL_AON HBN_SW_LDO11SOC_VOUT_SEL_AON
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS (16U)
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN (4U)
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_MSK (((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS)
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_UMSK (~(((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS))
#define HBN_SW_LDO11_RT_VOUT_SEL HBN_SW_LDO11_RT_VOUT_SEL
#define HBN_SW_LDO11_RT_VOUT_SEL_POS (24U)
#define HBN_SW_LDO11_RT_VOUT_SEL_LEN (4U)
#define HBN_SW_LDO11_RT_VOUT_SEL_MSK (((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS)
#define HBN_SW_LDO11_RT_VOUT_SEL_UMSK (~(((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS))
#define HBN_SW_LDO11_AON_VOUT_SEL HBN_SW_LDO11_AON_VOUT_SEL
#define HBN_SW_LDO11_AON_VOUT_SEL_POS (28U)
#define HBN_SW_LDO11_AON_VOUT_SEL_LEN (4U)
#define HBN_SW_LDO11_AON_VOUT_SEL_MSK (((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS)
#define HBN_SW_LDO11_AON_VOUT_SEL_UMSK (~(((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS))
/* 0x34 : HBN_SRAM */
#define HBN_SRAM_OFFSET (0x34)
#define HBN_RETRAM_RET HBN_RETRAM_RET
#define HBN_RETRAM_RET_POS (6U)
#define HBN_RETRAM_RET_LEN (1U)
#define HBN_RETRAM_RET_MSK (((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS)
#define HBN_RETRAM_RET_UMSK (~(((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS))
#define HBN_RETRAM_SLP HBN_RETRAM_SLP
#define HBN_RETRAM_SLP_POS (7U)
#define HBN_RETRAM_SLP_LEN (1U)
#define HBN_RETRAM_SLP_MSK (((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS)
#define HBN_RETRAM_SLP_UMSK (~(((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS))
/* 0x38 : HBN_PAD_CTRL_0 */
#define HBN_PAD_CTRL_0_OFFSET (0x38)
#define HBN_REG_AON_PAD_IE_SMT HBN_REG_AON_PAD_IE_SMT
#define HBN_REG_AON_PAD_IE_SMT_POS (0U)
#define HBN_REG_AON_PAD_IE_SMT_LEN (9U)
#define HBN_REG_AON_PAD_IE_SMT_MSK (((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS)
#define HBN_REG_AON_PAD_IE_SMT_UMSK (~(((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS))
#define HBN_REG_AON_LED_SEL HBN_REG_AON_LED_SEL
#define HBN_REG_AON_LED_SEL_POS (10U)
#define HBN_REG_AON_LED_SEL_LEN (9U)
#define HBN_REG_AON_LED_SEL_MSK (((1U << HBN_REG_AON_LED_SEL_LEN) - 1) << HBN_REG_AON_LED_SEL_POS)
#define HBN_REG_AON_LED_SEL_UMSK (~(((1U << HBN_REG_AON_LED_SEL_LEN) - 1) << HBN_REG_AON_LED_SEL_POS))
#define HBN_REG_EN_AON_CTRL_GPIO HBN_REG_EN_AON_CTRL_GPIO
#define HBN_REG_EN_AON_CTRL_GPIO_POS (20U)
#define HBN_REG_EN_AON_CTRL_GPIO_LEN (9U)
#define HBN_REG_EN_AON_CTRL_GPIO_MSK (((1U << HBN_REG_EN_AON_CTRL_GPIO_LEN) - 1) << HBN_REG_EN_AON_CTRL_GPIO_POS)
#define HBN_REG_EN_AON_CTRL_GPIO_UMSK (~(((1U << HBN_REG_EN_AON_CTRL_GPIO_LEN) - 1) << HBN_REG_EN_AON_CTRL_GPIO_POS))
#define HBN_REG_AON_GPIO_ISO_MODE HBN_REG_AON_GPIO_ISO_MODE
#define HBN_REG_AON_GPIO_ISO_MODE_POS (31U)
#define HBN_REG_AON_GPIO_ISO_MODE_LEN (1U)
#define HBN_REG_AON_GPIO_ISO_MODE_MSK (((1U << HBN_REG_AON_GPIO_ISO_MODE_LEN) - 1) << HBN_REG_AON_GPIO_ISO_MODE_POS)
#define HBN_REG_AON_GPIO_ISO_MODE_UMSK (~(((1U << HBN_REG_AON_GPIO_ISO_MODE_LEN) - 1) << HBN_REG_AON_GPIO_ISO_MODE_POS))
/* 0x3C : HBN_PAD_CTRL_1 */
#define HBN_PAD_CTRL_1_OFFSET (0x3C)
#define HBN_REG_AON_PAD_OE HBN_REG_AON_PAD_OE
#define HBN_REG_AON_PAD_OE_POS (0U)
#define HBN_REG_AON_PAD_OE_LEN (9U)
#define HBN_REG_AON_PAD_OE_MSK (((1U << HBN_REG_AON_PAD_OE_LEN) - 1) << HBN_REG_AON_PAD_OE_POS)
#define HBN_REG_AON_PAD_OE_UMSK (~(((1U << HBN_REG_AON_PAD_OE_LEN) - 1) << HBN_REG_AON_PAD_OE_POS))
#define HBN_REG_AON_PAD_PD HBN_REG_AON_PAD_PD
#define HBN_REG_AON_PAD_PD_POS (10U)
#define HBN_REG_AON_PAD_PD_LEN (9U)
#define HBN_REG_AON_PAD_PD_MSK (((1U << HBN_REG_AON_PAD_PD_LEN) - 1) << HBN_REG_AON_PAD_PD_POS)
#define HBN_REG_AON_PAD_PD_UMSK (~(((1U << HBN_REG_AON_PAD_PD_LEN) - 1) << HBN_REG_AON_PAD_PD_POS))
#define HBN_REG_AON_PAD_PU HBN_REG_AON_PAD_PU
#define HBN_REG_AON_PAD_PU_POS (20U)
#define HBN_REG_AON_PAD_PU_LEN (9U)
#define HBN_REG_AON_PAD_PU_MSK (((1U << HBN_REG_AON_PAD_PU_LEN) - 1) << HBN_REG_AON_PAD_PU_POS)
#define HBN_REG_AON_PAD_PU_UMSK (~(((1U << HBN_REG_AON_PAD_PU_LEN) - 1) << HBN_REG_AON_PAD_PU_POS))
/* 0x100 : HBN_RSV0 */
#define HBN_RSV0_OFFSET (0x100)
#define HBN_RSV0 HBN_RSV0
#define HBN_RSV0_POS (0U)
#define HBN_RSV0_LEN (32U)
#define HBN_RSV0_MSK (((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS)
#define HBN_RSV0_UMSK (~(((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS))
/* 0x104 : HBN_RSV1 */
#define HBN_RSV1_OFFSET (0x104)
#define HBN_RSV1 HBN_RSV1
#define HBN_RSV1_POS (0U)
#define HBN_RSV1_LEN (32U)
#define HBN_RSV1_MSK (((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS)
#define HBN_RSV1_UMSK (~(((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS))
/* 0x108 : HBN_RSV2 */
#define HBN_RSV2_OFFSET (0x108)
#define HBN_RSV2 HBN_RSV2
#define HBN_RSV2_POS (0U)
#define HBN_RSV2_LEN (32U)
#define HBN_RSV2_MSK (((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS)
#define HBN_RSV2_UMSK (~(((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS))
/* 0x10C : HBN_RSV3 */
#define HBN_RSV3_OFFSET (0x10C)
#define HBN_RSV3 HBN_RSV3
#define HBN_RSV3_POS (0U)
#define HBN_RSV3_LEN (32U)
#define HBN_RSV3_MSK (((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS)
#define HBN_RSV3_UMSK (~(((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS))
/* 0x200 : rc32k_ctrl0 */
#define HBN_RC32K_CTRL0_OFFSET (0x200)
#define HBN_RC32K_CAL_DONE HBN_RC32K_CAL_DONE
#define HBN_RC32K_CAL_DONE_POS (0U)
#define HBN_RC32K_CAL_DONE_LEN (1U)
#define HBN_RC32K_CAL_DONE_MSK (((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS)
#define HBN_RC32K_CAL_DONE_UMSK (~(((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS))
#define HBN_RC32K_RDY HBN_RC32K_RDY
#define HBN_RC32K_RDY_POS (1U)
#define HBN_RC32K_RDY_LEN (1U)
#define HBN_RC32K_RDY_MSK (((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS)
#define HBN_RC32K_RDY_UMSK (~(((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS))
#define HBN_RC32K_CAL_INPROGRESS HBN_RC32K_CAL_INPROGRESS
#define HBN_RC32K_CAL_INPROGRESS_POS (2U)
#define HBN_RC32K_CAL_INPROGRESS_LEN (1U)
#define HBN_RC32K_CAL_INPROGRESS_MSK (((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS)
#define HBN_RC32K_CAL_INPROGRESS_UMSK (~(((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS))
#define HBN_RC32K_CAL_DIV HBN_RC32K_CAL_DIV
#define HBN_RC32K_CAL_DIV_POS (3U)
#define HBN_RC32K_CAL_DIV_LEN (2U)
#define HBN_RC32K_CAL_DIV_MSK (((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS)
#define HBN_RC32K_CAL_DIV_UMSK (~(((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS))
#define HBN_RC32K_CAL_PRECHARGE HBN_RC32K_CAL_PRECHARGE
#define HBN_RC32K_CAL_PRECHARGE_POS (5U)
#define HBN_RC32K_CAL_PRECHARGE_LEN (1U)
#define HBN_RC32K_CAL_PRECHARGE_MSK (((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS)
#define HBN_RC32K_CAL_PRECHARGE_UMSK (~(((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS))
#define HBN_RC32K_DIG_CODE_FR_CAL HBN_RC32K_DIG_CODE_FR_CAL
#define HBN_RC32K_DIG_CODE_FR_CAL_POS (6U)
#define HBN_RC32K_DIG_CODE_FR_CAL_LEN (10U)
#define HBN_RC32K_DIG_CODE_FR_CAL_MSK (((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS)
#define HBN_RC32K_DIG_CODE_FR_CAL_UMSK (~(((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS))
#define HBN_RC32K_VREF_DLY HBN_RC32K_VREF_DLY
#define HBN_RC32K_VREF_DLY_POS (16U)
#define HBN_RC32K_VREF_DLY_LEN (2U)
#define HBN_RC32K_VREF_DLY_MSK (((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS)
#define HBN_RC32K_VREF_DLY_UMSK (~(((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS))
#define HBN_RC32K_ALLOW_CAL HBN_RC32K_ALLOW_CAL
#define HBN_RC32K_ALLOW_CAL_POS (18U)
#define HBN_RC32K_ALLOW_CAL_LEN (1U)
#define HBN_RC32K_ALLOW_CAL_MSK (((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS)
#define HBN_RC32K_ALLOW_CAL_UMSK (~(((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS))
#define HBN_RC32K_EXT_CODE_EN HBN_RC32K_EXT_CODE_EN
#define HBN_RC32K_EXT_CODE_EN_POS (19U)
#define HBN_RC32K_EXT_CODE_EN_LEN (1U)
#define HBN_RC32K_EXT_CODE_EN_MSK (((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS)
#define HBN_RC32K_EXT_CODE_EN_UMSK (~(((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS))
#define HBN_RC32K_CAL_EN HBN_RC32K_CAL_EN
#define HBN_RC32K_CAL_EN_POS (20U)
#define HBN_RC32K_CAL_EN_LEN (1U)
#define HBN_RC32K_CAL_EN_MSK (((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS)
#define HBN_RC32K_CAL_EN_UMSK (~(((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS))
#define HBN_PU_RC32K HBN_PU_RC32K
#define HBN_PU_RC32K_POS (21U)
#define HBN_PU_RC32K_LEN (1U)
#define HBN_PU_RC32K_MSK (((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS)
#define HBN_PU_RC32K_UMSK (~(((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS))
#define HBN_RC32K_CODE_FR_EXT HBN_RC32K_CODE_FR_EXT
#define HBN_RC32K_CODE_FR_EXT_POS (22U)
#define HBN_RC32K_CODE_FR_EXT_LEN (10U)
#define HBN_RC32K_CODE_FR_EXT_MSK (((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS)
#define HBN_RC32K_CODE_FR_EXT_UMSK (~(((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS))
/* 0x204 : xtal32k */
#define HBN_XTAL32K_OFFSET (0x204)
#define HBN_XTAL32K_EXT_SEL HBN_XTAL32K_EXT_SEL
#define HBN_XTAL32K_EXT_SEL_POS (2U)
#define HBN_XTAL32K_EXT_SEL_LEN (1U)
#define HBN_XTAL32K_EXT_SEL_MSK (((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS)
#define HBN_XTAL32K_EXT_SEL_UMSK (~(((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS))
#define HBN_XTAL32K_AMP_CTRL HBN_XTAL32K_AMP_CTRL
#define HBN_XTAL32K_AMP_CTRL_POS (3U)
#define HBN_XTAL32K_AMP_CTRL_LEN (2U)
#define HBN_XTAL32K_AMP_CTRL_MSK (((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS)
#define HBN_XTAL32K_AMP_CTRL_UMSK (~(((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS))
#define HBN_XTAL32K_REG HBN_XTAL32K_REG
#define HBN_XTAL32K_REG_POS (5U)
#define HBN_XTAL32K_REG_LEN (2U)
#define HBN_XTAL32K_REG_MSK (((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS)
#define HBN_XTAL32K_REG_UMSK (~(((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS))
#define HBN_XTAL32K_OUTBUF_STRE HBN_XTAL32K_OUTBUF_STRE
#define HBN_XTAL32K_OUTBUF_STRE_POS (7U)
#define HBN_XTAL32K_OUTBUF_STRE_LEN (1U)
#define HBN_XTAL32K_OUTBUF_STRE_MSK (((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS)
#define HBN_XTAL32K_OUTBUF_STRE_UMSK (~(((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS))
#define HBN_XTAL32K_OTF_SHORT HBN_XTAL32K_OTF_SHORT
#define HBN_XTAL32K_OTF_SHORT_POS (8U)
#define HBN_XTAL32K_OTF_SHORT_LEN (1U)
#define HBN_XTAL32K_OTF_SHORT_MSK (((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS)
#define HBN_XTAL32K_OTF_SHORT_UMSK (~(((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS))
#define HBN_XTAL32K_INV_STRE HBN_XTAL32K_INV_STRE
#define HBN_XTAL32K_INV_STRE_POS (9U)
#define HBN_XTAL32K_INV_STRE_LEN (2U)
#define HBN_XTAL32K_INV_STRE_MSK (((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS)
#define HBN_XTAL32K_INV_STRE_UMSK (~(((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS))
#define HBN_XTAL32K_CAPBANK HBN_XTAL32K_CAPBANK
#define HBN_XTAL32K_CAPBANK_POS (11U)
#define HBN_XTAL32K_CAPBANK_LEN (6U)
#define HBN_XTAL32K_CAPBANK_MSK (((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS)
#define HBN_XTAL32K_CAPBANK_UMSK (~(((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS))
#define HBN_XTAL32K_AC_CAP_SHORT HBN_XTAL32K_AC_CAP_SHORT
#define HBN_XTAL32K_AC_CAP_SHORT_POS (17U)
#define HBN_XTAL32K_AC_CAP_SHORT_LEN (1U)
#define HBN_XTAL32K_AC_CAP_SHORT_MSK (((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS)
#define HBN_XTAL32K_AC_CAP_SHORT_UMSK (~(((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS))
#define HBN_PU_XTAL32K_BUF HBN_PU_XTAL32K_BUF
#define HBN_PU_XTAL32K_BUF_POS (18U)
#define HBN_PU_XTAL32K_BUF_LEN (1U)
#define HBN_PU_XTAL32K_BUF_MSK (((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS)
#define HBN_PU_XTAL32K_BUF_UMSK (~(((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS))
#define HBN_PU_XTAL32K HBN_PU_XTAL32K
#define HBN_PU_XTAL32K_POS (19U)
#define HBN_PU_XTAL32K_LEN (1U)
#define HBN_PU_XTAL32K_MSK (((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS)
#define HBN_PU_XTAL32K_UMSK (~(((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS))
#define HBN_XTAL32K_HIZ_EN HBN_XTAL32K_HIZ_EN
#define HBN_XTAL32K_HIZ_EN_POS (20U)
#define HBN_XTAL32K_HIZ_EN_LEN (1U)
#define HBN_XTAL32K_HIZ_EN_MSK (((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS)
#define HBN_XTAL32K_HIZ_EN_UMSK (~(((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS))
#define HBN_DTEN_XTAL32K HBN_DTEN_XTAL32K
#define HBN_DTEN_XTAL32K_POS (22U)
#define HBN_DTEN_XTAL32K_LEN (1U)
#define HBN_DTEN_XTAL32K_MSK (((1U << HBN_DTEN_XTAL32K_LEN) - 1) << HBN_DTEN_XTAL32K_POS)
#define HBN_DTEN_XTAL32K_UMSK (~(((1U << HBN_DTEN_XTAL32K_LEN) - 1) << HBN_DTEN_XTAL32K_POS))
#define HBN_TEN_XTAL32K HBN_TEN_XTAL32K
#define HBN_TEN_XTAL32K_POS (23U)
#define HBN_TEN_XTAL32K_LEN (1U)
#define HBN_TEN_XTAL32K_MSK (((1U << HBN_TEN_XTAL32K_LEN) - 1) << HBN_TEN_XTAL32K_POS)
#define HBN_TEN_XTAL32K_UMSK (~(((1U << HBN_TEN_XTAL32K_LEN) - 1) << HBN_TEN_XTAL32K_POS))
#define HBN_F32K_SEL_RTC HBN_F32K_SEL_RTC
#define HBN_F32K_SEL_RTC_POS (24U)
#define HBN_F32K_SEL_RTC_LEN (1U)
#define HBN_F32K_SEL_RTC_MSK (((1U << HBN_F32K_SEL_RTC_LEN) - 1) << HBN_F32K_SEL_RTC_POS)
#define HBN_F32K_SEL_RTC_UMSK (~(((1U << HBN_F32K_SEL_RTC_LEN) - 1) << HBN_F32K_SEL_RTC_POS))
/* 0x208 : rtc_rst_ctrl */
#define HBN_RTC_RST_CTRL_OFFSET (0x208)
#define HBN_RTC_RST_WAIT_CNT_RTC HBN_RTC_RST_WAIT_CNT_RTC
#define HBN_RTC_RST_WAIT_CNT_RTC_POS (0U)
#define HBN_RTC_RST_WAIT_CNT_RTC_LEN (16U)
#define HBN_RTC_RST_WAIT_CNT_RTC_MSK (((1U << HBN_RTC_RST_WAIT_CNT_RTC_LEN) - 1) << HBN_RTC_RST_WAIT_CNT_RTC_POS)
#define HBN_RTC_RST_WAIT_CNT_RTC_UMSK (~(((1U << HBN_RTC_RST_WAIT_CNT_RTC_LEN) - 1) << HBN_RTC_RST_WAIT_CNT_RTC_POS))
#define HBN_RTC_RST_REFDIV_RTC HBN_RTC_RST_REFDIV_RTC
#define HBN_RTC_RST_REFDIV_RTC_POS (16U)
#define HBN_RTC_RST_REFDIV_RTC_LEN (3U)
#define HBN_RTC_RST_REFDIV_RTC_MSK (((1U << HBN_RTC_RST_REFDIV_RTC_LEN) - 1) << HBN_RTC_RST_REFDIV_RTC_POS)
#define HBN_RTC_RST_REFDIV_RTC_UMSK (~(((1U << HBN_RTC_RST_REFDIV_RTC_LEN) - 1) << HBN_RTC_RST_REFDIV_RTC_POS))
#define HBN_RTC_RST_CTRL_MISC HBN_RTC_RST_CTRL_MISC
#define HBN_RTC_RST_CTRL_MISC_POS (19U)
#define HBN_RTC_RST_CTRL_MISC_LEN (13U)
#define HBN_RTC_RST_CTRL_MISC_MSK (((1U << HBN_RTC_RST_CTRL_MISC_LEN) - 1) << HBN_RTC_RST_CTRL_MISC_POS)
#define HBN_RTC_RST_CTRL_MISC_UMSK (~(((1U << HBN_RTC_RST_CTRL_MISC_LEN) - 1) << HBN_RTC_RST_CTRL_MISC_POS))
/* 0x20C : rtc_rst_ctrl2 */
#define HBN_RTC_RST_CTRL2_OFFSET (0x20C)
#define HBN_RTC_RESV HBN_RTC_RESV
#define HBN_RTC_RESV_POS (0U)
#define HBN_RTC_RESV_LEN (8U)
#define HBN_RTC_RESV_MSK (((1U << HBN_RTC_RESV_LEN) - 1) << HBN_RTC_RESV_POS)
#define HBN_RTC_RESV_UMSK (~(((1U << HBN_RTC_RESV_LEN) - 1) << HBN_RTC_RESV_POS))
#define HBN_REG_EN_HW_PU_RC32K HBN_REG_EN_HW_PU_RC32K
#define HBN_REG_EN_HW_PU_RC32K_POS (8U)
#define HBN_REG_EN_HW_PU_RC32K_LEN (1U)
#define HBN_REG_EN_HW_PU_RC32K_MSK (((1U << HBN_REG_EN_HW_PU_RC32K_LEN) - 1) << HBN_REG_EN_HW_PU_RC32K_POS)
#define HBN_REG_EN_HW_PU_RC32K_UMSK (~(((1U << HBN_REG_EN_HW_PU_RC32K_LEN) - 1) << HBN_REG_EN_HW_PU_RC32K_POS))
struct hbn_reg {
/* 0x0 : HBN_CTL */
union {
struct {
uint32_t rtc_ctl : 4; /* [ 3: 0], r/w, 0x0 */
uint32_t rtc_dly_option : 1; /* [ 4], r/w, 0x0 */
uint32_t pu_ldo18io_aon : 1; /* [ 5], r/w, 0x1 */
uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
uint32_t hbn_mode : 1; /* [ 7], w, 0x0 */
uint32_t trap_mode : 1; /* [ 8], r, 0x0 */
uint32_t pwrdn_hbn_core : 1; /* [ 9], r/w, 0x0 */
uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */
uint32_t sw_rst : 1; /* [ 12], r/w, 0x0 */
uint32_t hbn_dis_pwr_off_ldo11 : 1; /* [ 13], r/w, 0x0 */
uint32_t hbn_dis_pwr_off_ldo11_rt : 1; /* [ 14], r/w, 0x0 */
uint32_t hbn_ldo11_rt_vout_sel : 4; /* [18:15], r/w, 0xa */
uint32_t hbn_ldo11_aon_vout_sel : 4; /* [22:19], r/w, 0xa */
uint32_t pu_dcdc_aon : 1; /* [ 23], r/w, 0x1 */
uint32_t pu_dcdc18_aon : 1; /* [ 24], r/w, 0x1 */
uint32_t pwr_on_option : 1; /* [ 25], r/w, 0x0 */
uint32_t sram_slp_option : 1; /* [ 26], r/w, 0x0 */
uint32_t sram_slp : 1; /* [ 27], r, 0x0 */
uint32_t hbn_state : 4; /* [31:28], r, 0x0 */
} BF;
uint32_t WORD;
} HBN_CTL;
/* 0x4 : HBN_TIME_L */
union {
struct {
uint32_t hbn_time_l : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} HBN_TIME_L;
/* 0x8 : HBN_TIME_H */
union {
struct {
uint32_t hbn_time_h : 8; /* [ 7: 0], r/w, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_TIME_H;
/* 0xC : RTC_TIME_L */
union {
struct {
uint32_t rtc_time_latch_l : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} RTC_TIME_L;
/* 0x10 : RTC_TIME_H */
union {
struct {
uint32_t rtc_time_latch_h : 8; /* [ 7: 0], r, 0x0 */
uint32_t reserved_8_30 : 23; /* [30: 8], rsvd, 0x0 */
uint32_t rtc_time_latch : 1; /* [ 31], w, 0x0 */
} BF;
uint32_t WORD;
} RTC_TIME_H;
/* 0x14 : HBN_IRQ_MODE */
union {
struct {
uint32_t hbn_pin_wakeup_mode : 4; /* [ 3: 0], r/w, 0x5 */
uint32_t hbn_pin_wakeup_mask : 9; /* [12: 4], r/w, 0x0 */
uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
uint32_t reg_en_hw_pu_pd : 1; /* [ 16], r/w, 0x1 */
uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */
uint32_t irq_bor_en : 1; /* [ 18], r/w, 0x0 */
uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
uint32_t irq_acomp0_en : 2; /* [21:20], r/w, 0x0 */
uint32_t irq_acomp1_en : 2; /* [23:22], r/w, 0x0 */
uint32_t pin_wakeup_sel : 3; /* [26:24], r/w, 0x3 */
uint32_t pin_wakeup_en : 1; /* [ 27], r/w, 0x0 */
uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_IRQ_MODE;
/* 0x18 : HBN_IRQ_STAT */
union {
struct {
uint32_t irq_stat : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} HBN_IRQ_STAT;
/* 0x1C : HBN_IRQ_CLR */
union {
struct {
uint32_t irq_clr : 32; /* [31: 0], w, 0x0 */
} BF;
uint32_t WORD;
} HBN_IRQ_CLR;
/* 0x20 : HBN_PIR_CFG */
union {
struct {
uint32_t pir_hpf_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pir_lpf_sel : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
uint32_t pir_dis : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
uint32_t pir_en : 1; /* [ 7], r/w, 0x0 */
uint32_t gpadc_cs : 1; /* [ 8], r/w, 0x0 */
uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_PIR_CFG;
/* 0x24 : HBN_PIR_VTH */
union {
struct {
uint32_t pir_vth : 14; /* [13: 0], r/w, 0x3ff */
uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_PIR_VTH;
/* 0x28 : HBN_PIR_INTERVAL */
union {
struct {
uint32_t pir_interval : 12; /* [11: 0], r/w, 0xa3d */
uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_PIR_INTERVAL;
/* 0x2C : HBN_BOR_CFG */
union {
struct {
uint32_t bod_sel : 1; /* [ 0], r/w, 0x0 */
uint32_t bod_vth : 3; /* [ 3: 1], r/w, 0x5 */
uint32_t pu_bod : 1; /* [ 4], r/w, 0x0 */
uint32_t r_bod_out : 1; /* [ 5], r, 0x0 */
uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_BOR_CFG;
/* 0x30 : HBN_GLB */
union {
struct {
uint32_t hbn_root_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t hbn_uart_clk_sel : 1; /* [ 2], r/w, 0x0 */
uint32_t hbn_f32k_sel : 2; /* [ 4: 3], r/w, 0x0 */
uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */
uint32_t hbn_reset_event : 6; /* [12: 7], r, 0x0 */
uint32_t hbn_clr_reset_event : 1; /* [ 13], r/w, 0x0 */
uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */
uint32_t hbn_uart_clk_sel2 : 1; /* [ 15], r/w, 0x0 */
uint32_t sw_ldo11soc_vout_sel_aon : 4; /* [19:16], r/w, 0xa */
uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */
uint32_t sw_ldo11_rt_vout_sel : 4; /* [27:24], r/w, 0xa */
uint32_t sw_ldo11_aon_vout_sel : 4; /* [31:28], r/w, 0xa */
} BF;
uint32_t WORD;
} HBN_GLB;
/* 0x34 : HBN_SRAM */
union {
struct {
uint32_t reserved_0_5 : 6; /* [ 5: 0], rsvd, 0x0 */
uint32_t retram_ret : 1; /* [ 6], r/w, 0x0 */
uint32_t retram_slp : 1; /* [ 7], r/w, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_SRAM;
/* 0x38 : HBN_PAD_CTRL_0 */
union {
struct {
uint32_t reg_aon_pad_ie_smt : 9; /* [ 8: 0], r/w, 0x0 */
uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */
uint32_t reg_aon_led_sel : 9; /* [18:10], r/w, 0x0 */
uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
uint32_t reg_en_aon_ctrl_gpio : 9; /* [28:20], r/w, 0x180 */
uint32_t reserved_29_30 : 2; /* [30:29], rsvd, 0x0 */
uint32_t reg_aon_gpio_iso_mode : 1; /* [ 31], r/w, 0x0 */
} BF;
uint32_t WORD;
} HBN_PAD_CTRL_0;
/* 0x3C : HBN_PAD_CTRL_1 */
union {
struct {
uint32_t reg_aon_pad_oe : 9; /* [ 8: 0], r/w, 0x0 */
uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */
uint32_t reg_aon_pad_pd : 9; /* [18:10], r/w, 0x0 */
uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
uint32_t reg_aon_pad_pu : 9; /* [28:20], r/w, 0x0 */
uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */
} BF;
uint32_t WORD;
} HBN_PAD_CTRL_1;
/* 0x40 reserved */
uint8_t RESERVED0x40[192];
/* 0x100 : HBN_RSV0 */
union {
struct {
uint32_t HBN_RSV0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} HBN_RSV0;
/* 0x104 : HBN_RSV1 */
union {
struct {
uint32_t HBN_RSV1 : 32; /* [31: 0], r/w, 0xffffffff */
} BF;
uint32_t WORD;
} HBN_RSV1;
/* 0x108 : HBN_RSV2 */
union {
struct {
uint32_t HBN_RSV2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} HBN_RSV2;
/* 0x10C : HBN_RSV3 */
union {
struct {
uint32_t HBN_RSV3 : 32; /* [31: 0], r/w, 0xffffffff */
} BF;
uint32_t WORD;
} HBN_RSV3;
/* 0x110 reserved */
uint8_t RESERVED0x110[240];
/* 0x200 : rc32k_ctrl0 */
union {
struct {
uint32_t rc32k_cal_done : 1; /* [ 0], r, 0x1 */
uint32_t rc32k_rdy : 1; /* [ 1], r, 0x1 */
uint32_t rc32k_cal_inprogress : 1; /* [ 2], r, 0x0 */
uint32_t rc32k_cal_div : 2; /* [ 4: 3], r/w, 0x3 */
uint32_t rc32k_cal_precharge : 1; /* [ 5], r, 0x0 */
uint32_t rc32k_dig_code_fr_cal : 10; /* [15: 6], r, 0x200 */
uint32_t rc32k_vref_dly : 2; /* [17:16], r/w, 0x0 */
uint32_t rc32k_allow_cal : 1; /* [ 18], r/w, 0x0 */
uint32_t rc32k_ext_code_en : 1; /* [ 19], r/w, 0x1 */
uint32_t rc32k_cal_en : 1; /* [ 20], r/w, 0x0 */
uint32_t pu_rc32k : 1; /* [ 21], r/w, 0x1 */
uint32_t rc32k_code_fr_ext : 10; /* [31:22], r/w, 0x12c */
} BF;
uint32_t WORD;
} rc32k_ctrl0;
/* 0x204 : xtal32k */
union {
struct {
uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
uint32_t xtal32k_ext_sel : 1; /* [ 2], r/w, 0x0 */
uint32_t xtal32k_amp_ctrl : 2; /* [ 4: 3], r/w, 0x1 */
uint32_t xtal32k_reg : 2; /* [ 6: 5], r/w, 0x1 */
uint32_t xtal32k_outbuf_stre : 1; /* [ 7], r/w, 0x0 */
uint32_t xtal32k_otf_short : 1; /* [ 8], r/w, 0x0 */
uint32_t xtal32k_inv_stre : 2; /* [10: 9], r/w, 0x1 */
uint32_t xtal32k_capbank : 6; /* [16:11], r/w, 0x20 */
uint32_t xtal32k_ac_cap_short : 1; /* [ 17], r/w, 0x0 */
uint32_t pu_xtal32k_buf : 1; /* [ 18], r/w, 0x1 */
uint32_t pu_xtal32k : 1; /* [ 19], r/w, 0x0 */
uint32_t xtal32k_hiz_en : 1; /* [ 20], r/w, 0x1 */
uint32_t reserved_21 : 1; /* [ 21], rsvd, 0x0 */
uint32_t dten_xtal32k : 1; /* [ 22], r/w, 0x0 */
uint32_t ten_xtal32k : 1; /* [ 23], r/w, 0x0 */
uint32_t f32k_sel_rtc : 1; /* [ 24], r/w, 0x0 */
uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
} BF;
uint32_t WORD;
} xtal32k;
/* 0x208 : rtc_rst_ctrl */
union {
struct {
uint32_t rtc_rst_wait_cnt_rtc : 16; /* [15: 0], r/w, 0x3c00 */
uint32_t rtc_rst_refdiv_rtc : 3; /* [18:16], r/w, 0x4 */
uint32_t rtc_rst_ctrl_misc : 13; /* [31:19], r/w, 0xa12 */
} BF;
uint32_t WORD;
} rtc_rst_ctrl;
/* 0x20C : rtc_rst_ctrl2 */
union {
struct {
uint32_t rtc_resv : 8; /* [ 7: 0], r/w, 0x0 */
uint32_t reg_en_hw_pu_rc32k : 1; /* [ 8], r/w, 0x0 */
uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
} BF;
uint32_t WORD;
} rtc_rst_ctrl2;
};
#endif /* __HBN_REG_H__ */

169
include/bl808/i2c_reg.h Normal file
View File

@ -0,0 +1,169 @@
/**
******************************************************************************
* @file i2c_reg.h
* @version V1.0
* @date 2022-06-16
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_I2C_H__
#define __HARDWARE_I2C_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define I2C_CONFIG_OFFSET (0x0) /* i2c_config */
#define I2C_INT_STS_OFFSET (0x4) /* i2c_int_sts */
#define I2C_SUB_ADDR_OFFSET (0x8) /* i2c_sub_addr */
#define I2C_BUS_BUSY_OFFSET (0xC) /* i2c_bus_busy */
#define I2C_PRD_START_OFFSET (0x10) /* i2c_prd_start */
#define I2C_PRD_STOP_OFFSET (0x14) /* i2c_prd_stop */
#define I2C_PRD_DATA_OFFSET (0x18) /* i2c_prd_data */
#define I2C_FIFO_CONFIG_0_OFFSET (0x80) /* i2c_fifo_config_0 */
#define I2C_FIFO_CONFIG_1_OFFSET (0x84) /* i2c_fifo_config_1 */
#define I2C_FIFO_WDATA_OFFSET (0x88) /* i2c_fifo_wdata */
#define I2C_FIFO_RDATA_OFFSET (0x8C) /* i2c_fifo_rdata */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : i2c_config */
#define I2C_CR_I2C_M_EN (1 << 0U)
#define I2C_CR_I2C_PKT_DIR (1 << 1U)
#define I2C_CR_I2C_DEG_EN (1 << 2U)
#define I2C_CR_I2C_SCL_SYNC_EN (1 << 3U)
#define I2C_CR_I2C_SUB_ADDR_EN (1 << 4U)
#define I2C_CR_I2C_SUB_ADDR_BC_SHIFT (5U)
#define I2C_CR_I2C_SUB_ADDR_BC_MASK (0x3 << I2C_CR_I2C_SUB_ADDR_BC_SHIFT)
#define I2C_CR_I2C_10B_ADDR_EN (1 << 7U)
#define I2C_CR_I2C_SLV_ADDR_SHIFT (8U)
#define I2C_CR_I2C_SLV_ADDR_MASK (0x3ff << I2C_CR_I2C_SLV_ADDR_SHIFT)
#define I2C_CR_I2C_PKT_LEN_SHIFT (20U)
#define I2C_CR_I2C_PKT_LEN_MASK (0xff << I2C_CR_I2C_PKT_LEN_SHIFT)
#define I2C_CR_I2C_DEG_CNT_SHIFT (28U)
#define I2C_CR_I2C_DEG_CNT_MASK (0xf << I2C_CR_I2C_DEG_CNT_SHIFT)
/* 0x4 : i2c_int_sts */
#define I2C_END_INT (1 << 0U)
#define I2C_TXF_INT (1 << 1U)
#define I2C_RXF_INT (1 << 2U)
#define I2C_NAK_INT (1 << 3U)
#define I2C_ARB_INT (1 << 4U)
#define I2C_FER_INT (1 << 5U)
#define I2C_CR_I2C_END_MASK (1 << 8U)
#define I2C_CR_I2C_TXF_MASK (1 << 9U)
#define I2C_CR_I2C_RXF_MASK (1 << 10U)
#define I2C_CR_I2C_NAK_MASK (1 << 11U)
#define I2C_CR_I2C_ARB_MASK (1 << 12U)
#define I2C_CR_I2C_FER_MASK (1 << 13U)
#define I2C_CR_I2C_END_CLR (1 << 16U)
#define I2C_CR_I2C_NAK_CLR (1 << 19U)
#define I2C_CR_I2C_ARB_CLR (1 << 20U)
#define I2C_CR_I2C_END_EN (1 << 24U)
#define I2C_CR_I2C_TXF_EN (1 << 25U)
#define I2C_CR_I2C_RXF_EN (1 << 26U)
#define I2C_CR_I2C_NAK_EN (1 << 27U)
#define I2C_CR_I2C_ARB_EN (1 << 28U)
#define I2C_CR_I2C_FER_EN (1 << 29U)
/* 0x8 : i2c_sub_addr */
#define I2C_CR_I2C_SUB_ADDR_B0_SHIFT (0U)
#define I2C_CR_I2C_SUB_ADDR_B0_MASK (0xff << I2C_CR_I2C_SUB_ADDR_B0_SHIFT)
#define I2C_CR_I2C_SUB_ADDR_B1_SHIFT (8U)
#define I2C_CR_I2C_SUB_ADDR_B1_MASK (0xff << I2C_CR_I2C_SUB_ADDR_B1_SHIFT)
#define I2C_CR_I2C_SUB_ADDR_B2_SHIFT (16U)
#define I2C_CR_I2C_SUB_ADDR_B2_MASK (0xff << I2C_CR_I2C_SUB_ADDR_B2_SHIFT)
#define I2C_CR_I2C_SUB_ADDR_B3_SHIFT (24U)
#define I2C_CR_I2C_SUB_ADDR_B3_MASK (0xff << I2C_CR_I2C_SUB_ADDR_B3_SHIFT)
/* 0xC : i2c_bus_busy */
#define I2C_STS_I2C_BUS_BUSY (1 << 0U)
#define I2C_CR_I2C_BUS_BUSY_CLR (1 << 1U)
/* 0x10 : i2c_prd_start */
#define I2C_CR_I2C_PRD_S_PH_0_SHIFT (0U)
#define I2C_CR_I2C_PRD_S_PH_0_MASK (0xff << I2C_CR_I2C_PRD_S_PH_0_SHIFT)
#define I2C_CR_I2C_PRD_S_PH_1_SHIFT (8U)
#define I2C_CR_I2C_PRD_S_PH_1_MASK (0xff << I2C_CR_I2C_PRD_S_PH_1_SHIFT)
#define I2C_CR_I2C_PRD_S_PH_2_SHIFT (16U)
#define I2C_CR_I2C_PRD_S_PH_2_MASK (0xff << I2C_CR_I2C_PRD_S_PH_2_SHIFT)
#define I2C_CR_I2C_PRD_S_PH_3_SHIFT (24U)
#define I2C_CR_I2C_PRD_S_PH_3_MASK (0xff << I2C_CR_I2C_PRD_S_PH_3_SHIFT)
/* 0x14 : i2c_prd_stop */
#define I2C_CR_I2C_PRD_P_PH_0_SHIFT (0U)
#define I2C_CR_I2C_PRD_P_PH_0_MASK (0xff << I2C_CR_I2C_PRD_P_PH_0_SHIFT)
#define I2C_CR_I2C_PRD_P_PH_1_SHIFT (8U)
#define I2C_CR_I2C_PRD_P_PH_1_MASK (0xff << I2C_CR_I2C_PRD_P_PH_1_SHIFT)
#define I2C_CR_I2C_PRD_P_PH_2_SHIFT (16U)
#define I2C_CR_I2C_PRD_P_PH_2_MASK (0xff << I2C_CR_I2C_PRD_P_PH_2_SHIFT)
#define I2C_CR_I2C_PRD_P_PH_3_SHIFT (24U)
#define I2C_CR_I2C_PRD_P_PH_3_MASK (0xff << I2C_CR_I2C_PRD_P_PH_3_SHIFT)
/* 0x18 : i2c_prd_data */
#define I2C_CR_I2C_PRD_D_PH_0_SHIFT (0U)
#define I2C_CR_I2C_PRD_D_PH_0_MASK (0xff << I2C_CR_I2C_PRD_D_PH_0_SHIFT)
#define I2C_CR_I2C_PRD_D_PH_1_SHIFT (8U)
#define I2C_CR_I2C_PRD_D_PH_1_MASK (0xff << I2C_CR_I2C_PRD_D_PH_1_SHIFT)
#define I2C_CR_I2C_PRD_D_PH_2_SHIFT (16U)
#define I2C_CR_I2C_PRD_D_PH_2_MASK (0xff << I2C_CR_I2C_PRD_D_PH_2_SHIFT)
#define I2C_CR_I2C_PRD_D_PH_3_SHIFT (24U)
#define I2C_CR_I2C_PRD_D_PH_3_MASK (0xff << I2C_CR_I2C_PRD_D_PH_3_SHIFT)
/* 0x80 : i2c_fifo_config_0 */
#define I2C_DMA_TX_EN (1 << 0U)
#define I2C_DMA_RX_EN (1 << 1U)
#define I2C_TX_FIFO_CLR (1 << 2U)
#define I2C_RX_FIFO_CLR (1 << 3U)
#define I2C_TX_FIFO_OVERFLOW (1 << 4U)
#define I2C_TX_FIFO_UNDERFLOW (1 << 5U)
#define I2C_RX_FIFO_OVERFLOW (1 << 6U)
#define I2C_RX_FIFO_UNDERFLOW (1 << 7U)
/* 0x84 : i2c_fifo_config_1 */
#define I2C_TX_FIFO_CNT_SHIFT (0U)
#define I2C_TX_FIFO_CNT_MASK (0x3 << I2C_TX_FIFO_CNT_SHIFT)
#define I2C_RX_FIFO_CNT_SHIFT (8U)
#define I2C_RX_FIFO_CNT_MASK (0x3 << I2C_RX_FIFO_CNT_SHIFT)
#define I2C_TX_FIFO_TH (1 << 16U)
#define I2C_RX_FIFO_TH (1 << 24U)
/* 0x88 : i2c_fifo_wdata */
#define I2C_FIFO_WDATA_SHIFT (0U)
#define I2C_FIFO_WDATA_MASK (0xffffffff << I2C_FIFO_WDATA_SHIFT)
/* 0x8C : i2c_fifo_rdata */
#define I2C_FIFO_RDATA_SHIFT (0U)
#define I2C_FIFO_RDATA_MASK (0xffffffff << I2C_FIFO_RDATA_SHIFT)
#endif /* __HARDWARE_I2C_H__ */

311
include/bl808/ipc_reg.h Normal file
View File

@ -0,0 +1,311 @@
/**
******************************************************************************
* @file ipc_reg.h
* @version V1.2
* @date 2020-09-21
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __IPC_REG_H__
#define __IPC_REG_H__
#include <linux/types.h>
/* 0x0 : Interrupt Set Write Register */
#define IPC_CPU1_IPC_ISWR_OFFSET (0x0)
#define IPC_CPU1_IPC_ISWR IPC_CPU1_IPC_ISWR
#define IPC_CPU1_IPC_ISWR_POS (0U)
#define IPC_CPU1_IPC_ISWR_LEN (16U)
#define IPC_CPU1_IPC_ISWR_MSK (((1U << IPC_CPU1_IPC_ISWR_LEN) - 1) << IPC_CPU1_IPC_ISWR_POS)
#define IPC_CPU1_IPC_ISWR_UMSK (~(((1U << IPC_CPU1_IPC_ISWR_LEN) - 1) << IPC_CPU1_IPC_ISWR_POS))
/* 0x4 : Interrupt raw status Register */
#define IPC_CPU1_IPC_IRSRR_OFFSET (0x4)
#define IPC_CPU1_IPC_IRSRR IPC_CPU1_IPC_IRSRR
#define IPC_CPU1_IPC_IRSRR_POS (0U)
#define IPC_CPU1_IPC_IRSRR_LEN (16U)
#define IPC_CPU1_IPC_IRSRR_MSK (((1U << IPC_CPU1_IPC_IRSRR_LEN) - 1) << IPC_CPU1_IPC_IRSRR_POS)
#define IPC_CPU1_IPC_IRSRR_UMSK (~(((1U << IPC_CPU1_IPC_IRSRR_LEN) - 1) << IPC_CPU1_IPC_IRSRR_POS))
/* 0x8 : Interrupt Clear Register */
#define IPC_CPU1_IPC_ICR_OFFSET (0x8)
#define IPC_CPU1_IPC_ICR IPC_CPU1_IPC_ICR
#define IPC_CPU1_IPC_ICR_POS (0U)
#define IPC_CPU1_IPC_ICR_LEN (16U)
#define IPC_CPU1_IPC_ICR_MSK (((1U << IPC_CPU1_IPC_ICR_LEN) - 1) << IPC_CPU1_IPC_ICR_POS)
#define IPC_CPU1_IPC_ICR_UMSK (~(((1U << IPC_CPU1_IPC_ICR_LEN) - 1) << IPC_CPU1_IPC_ICR_POS))
/* 0xc : Interrupt Unmask Set Register */
#define IPC_CPU1_IPC_IUSR_OFFSET (0xc)
#define IPC_CPU1_IPC_IUSR IPC_AP_IPC_IUSR
#define IPC_CPU1_IPC_IUSR_POS (0U)
#define IPC_CPU1_IPC_IUSR_LEN (16U)
#define IPC_CPU1_IPC_IUSR_MSK (((1U << IPC_CPU1_IPC_IUSR_LEN) - 1) << IPC_CPU1_IPC_IUSR_POS)
#define IPC_CPU1_IPC_IUSR_UMSK (~(((1U << IPC_CPU1_IPC_IUSR_LEN) - 1) << IPC_CPU1_IPC_IUSR_POS))
/* 0x10 : Interrupt Unmask Clear Register */
#define IPC_CPU1_IPC_IUCR_OFFSET (0x10)
#define IPC_CPU1_IPC_IUCR IPC_CPU1_IPC_IUCR
#define IPC_CPU1_IPC_IUCR_POS (0U)
#define IPC_CPU1_IPC_IUCR_LEN (16U)
#define IPC_CPU1_IPC_IUCR_MSK (((1U << IPC_CPU1_IPC_IUCR_LEN) - 1) << IPC_CPU1_IPC_IUCR_POS)
#define IPC_CPU1_IPC_IUCR_UMSK (~(((1U << IPC_CPU1_IPC_IUCR_LEN) - 1) << IPC_CPU1_IPC_IUCR_POS))
/* 0x14 : Interrupt Line Sel Low Register */
#define IPC_CPU1_IPC_ILSLR_OFFSET (0x14)
#define IPC_CPU1_IPC_ILSLR IPC_CPU1_IPC_ILSLR
#define IPC_CPU1_IPC_ILSLR_POS (0U)
#define IPC_CPU1_IPC_ILSLR_LEN (32U)
#define IPC_CPU1_IPC_ILSLR_MSK (((1U << IPC_CPU1_IPC_ILSLR_LEN) - 1) << IPC_CPU1_IPC_ILSLR_POS)
#define IPC_CPU1_IPC_ILSLR_UMSK (~(((1U << IPC_CPU1_IPC_ILSLR_LEN) - 1) << IPC_CPU1_IPC_ILSLR_POS))
/* 0x18 : Interrupt Line Sel High Register */
#define IPC_CPU1_IPC_ILSHR_OFFSET (0x18)
#define IPC_CPU1_IPC_ILSHR IPC_CPU1_IPC_ILSHR
#define IPC_CPU1_IPC_ILSHR_POS (0U)
#define IPC_CPU1_IPC_ILSHR_LEN (32U)
#define IPC_CPU1_IPC_ILSHR_MSK (((1U << IPC_CPU1_IPC_ILSHR_LEN) - 1) << IPC_CPU1_IPC_ILSHR_POS)
#define IPC_CPU1_IPC_ILSHR_UMSK (~(((1U << IPC_CPU1_IPC_ILSHR_LEN) - 1) << IPC_CPU1_IPC_ILSHR_POS))
/* 0x1C : Interrupt status Register */
#define IPC_CPU1_IPC_ISR_OFFSET (0x1C)
#define IPC_CPU1_IPC_ISR IPC_CPU1_IPC_ISR
#define IPC_CPU1_IPC_ISR_POS (0U)
#define IPC_CPU1_IPC_ISR_LEN (16U)
#define IPC_CPU1_IPC_ISR_MSK (((1U << IPC_CPU1_IPC_ISR_LEN) - 1) << IPC_CPU1_IPC_ISR_POS)
#define IPC_CPU1_IPC_ISR_UMSK (~(((1U << IPC_CPU1_IPC_ISR_LEN) - 1) << IPC_CPU1_IPC_ISR_POS))
/* 0x20 : Interrupt Set Write Register */
#define IPC_CPU0_IPC_ISWR_OFFSET (0x20)
#define IPC_CPU0_IPC_ISWR IPC_CPU0_IPC_ISWR
#define IPC_CPU0_IPC_ISWR_POS (0U)
#define IPC_CPU0_IPC_ISWR_LEN (16U)
#define IPC_CPU0_IPC_ISWR_MSK (((1U << IPC_CPU0_IPC_ISWR_LEN) - 1) << IPC_CPU0_IPC_ISWR_POS)
#define IPC_CPU0_IPC_ISWR_UMSK (~(((1U << IPC_CPU0_IPC_ISWR_LEN) - 1) << IPC_CPU0_IPC_ISWR_POS))
/* 0x24 : Interrupt raw status Register */
#define IPC_CPU0_IPC_IRSRR_OFFSET (0x24)
#define IPC_CPU0_IPC_IRSRR IPC_CPU0_IPC_IRSRR
#define IPC_CPU0_IPC_IRSRR_POS (0U)
#define IPC_CPU0_IPC_IRSRR_LEN (16U)
#define IPC_CPU0_IPC_IRSRR_MSK (((1U << IPC_CPU0_IPC_IRSRR_LEN) - 1) << IPC_CPU0_IPC_IRSRR_POS)
#define IPC_CPU0_IPC_IRSRR_UMSK (~(((1U << IPC_CPU0_IPC_IRSRR_LEN) - 1) << IPC_CPU0_IPC_IRSRR_POS))
/* 0x28 : Interrupt Clear Register */
#define IPC_CPU0_IPC_ICR_OFFSET (0x28)
#define IPC_CPU0_IPC_ICR IPC_CPU0_IPC_ICR
#define IPC_CPU0_IPC_ICR_POS (0U)
#define IPC_CPU0_IPC_ICR_LEN (16U)
#define IPC_CPU0_IPC_ICR_MSK (((1U << IPC_CPU0_IPC_ICR_LEN) - 1) << IPC_CPU0_IPC_ICR_POS)
#define IPC_CPU0_IPC_ICR_UMSK (~(((1U << IPC_CPU0_IPC_ICR_LEN) - 1) << IPC_CPU0_IPC_ICR_POS))
/* 0x2c : Interrupt Unmask Set Register */
#define IPC_CPU0_IPC_IUSR_OFFSET (0x2c)
#define IPC_CPU0_IPC_IUSR IPC_CPU0_IPC_IUSR
#define IPC_CPU0_IPC_IUSR_POS (0U)
#define IPC_NP_IPC_IUSR_LEN (16U)
#define IPC_CPU0_IPC_IUSR_MSK (((1U << IPC_CPU0_IPC_IUSR_LEN) - 1) << IPC_CPU0_IPC_IUSR_POS)
#define IPC_CPU0_IPC_IUSR_UMSK (~(((1U << IPC_CPU0_IPC_IUSR_LEN) - 1) << IPC_CPU0_IPC_IUSR_POS))
/* 0x30 : Interrupt Unmask Clear Register */
#define IPC_CPU0_IPC_IUCR_OFFSET (0x30)
#define IPC_CPU0_IPC_IUCR IPC_CPU0_IPC_IUCR
#define IPC_CPU0_IPC_IUCR_POS (0U)
#define IPC_CPU0_IPC_IUCR_LEN (16U)
#define IPC_CPU0_IPC_IUCR_MSK (((1U << IPC_CPU0_IPC_IUCR_LEN) - 1) << IPC_CPU0_IPC_IUCR_POS)
#define IPC_CPU0_IPC_IUCR_UMSK (~(((1U << IPC_CPU0_IPC_IUCR_LEN) - 1) << IPC_CPU0_IPC_IUCR_POS))
/* 0x34 : Interrupt Line Sel Low Register */
#define IPC_CPU0_IPC_ILSLR_OFFSET (0x34)
#define IPC_CPU0_IPC_ILSLR IPC_CPU0_IPC_ILSLR
#define IPC_CPU0_IPC_ILSLR_POS (0U)
#define IPC_CPU0_IPC_ILSLR_LEN (32U)
#define IPC_CPU0_IPC_ILSLR_MSK (((1U << IPC_CPU0_IPC_ILSLR_LEN) - 1) << IPC_CPU0_IPC_ILSLR_POS)
#define IPC_CPU0_IPC_ILSLR_UMSK (~(((1U << IPC_CPU0_IPC_ILSLR_LEN) - 1) << IPC_CPU0_IPC_ILSLR_POS))
/* 0x38 : Interrupt Line Sel High Register */
#define IPC_CPU0_IPC_ILSHR_OFFSET (0x38)
#define IPC_CPU0_IPC_ILSHR IPC_CPU0_IPC_ILSHR
#define IPC_CPU0_IPC_ILSHR_POS (0U)
#define IPC_CPU0_IPC_ILSHR_LEN (32U)
#define IPC_CPU0_IPC_ILSHR_MSK (((1U << IPC_CPU0_IPC_ILSHR_LEN) - 1) << IPC_CPU0_IPC_ILSHR_POS)
#define IPC_CPU0_IPC_ILSHR_UMSK (~(((1U << IPC_CPU0_IPC_ILSHR_LEN) - 1) << IPC_CPU0_IPC_ILSHR_POS))
/* 0x3C : Interrupt status Register */
#define IPC_CPU0_IPC_ISR_OFFSET (0x3C)
#define IPC_CPU0_IPC_ISR IPC_CPU0_IPC_ISR
#define IPC_CPU0_IPC_ISR_POS (0U)
#define IPC_CPU0_IPC_ISR_LEN (16U)
#define IPC_CPU0_IPC_ISR_MSK (((1U << IPC_CPU0_IPC_ISR_LEN) - 1) << IPC_CPU0_IPC_ISR_POS)
#define IPC_CPU0_IPC_ISR_UMSK (~(((1U << IPC_CPU0_IPC_ISR_LEN) - 1) << IPC_CPU0_IPC_ISR_POS))
struct ipc_reg {
/* 0x0 : Interrupt Set Write Register */
union {
struct {
uint32_t CPU1_IPC_ISWR : 16; /* [15: 0], WO, 0x0 */
uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
} BF;
uint32_t WORD;
} CPU1_IPC_ISWR;
/* 0x4 : Interrupt raw status Register */
union {
struct {
uint32_t CPU1_IPC_IRSRR : 16; /* [15: 0], RO, 0x0 */
uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
} BF;
uint32_t WORD;
} CPU1_IPC_IRSRR;
/* 0x8 : Interrupt Clear Register */
union {
struct {
uint32_t CPU1_IPC_ICR : 16; /* [15: 0], WO, 0x0 */
uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
} BF;
uint32_t WORD;
} CPU1_IPC_ICR;
/* 0xc : Interrupt Unmask Set Register */
union {
struct {
uint32_t CPU1_IPC_IUSR : 16; /* [15: 0], RO, 0x0 */
uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
} BF;
uint32_t WORD;
} CPU1_IPC_IUSR;
/* 0x10 : Interrupt Unmask Clear Register */
union {
struct {
uint32_t CPU1_IPC_IUCR : 16; /* [15: 0], WO, 0x0 */
uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
} BF;
uint32_t WORD;
} CPU1_IPC_IUCR;
/* 0x14 : Interrupt Line Sel Low Register */
union {
struct {
uint32_t CPU1_IPC_ILSLR : 32; /* [31: 0], RW, 0x0 */
} BF;
uint32_t WORD;
} CPU1_IPC_ILSLR;
/* 0x18 : Interrupt Line Sel High Register */
union {
struct {
uint32_t CPU1_IPC_ILSHR : 32; /* [31: 0], RW, 0x0 */
} BF;
uint32_t WORD;
} CPU1_IPC_ILSHR;
/* 0x1C : Interrupt status Register */
union {
struct {
uint32_t CPU1_IPC_ISR : 16; /* [15: 0], RO, 0x0 */
uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
} BF;
uint32_t WORD;
} CPU1_IPC_ISR;
/* 0x20 : Interrupt Set Write Register */
union {
struct {
uint32_t CPU0_IPC_ISWR : 16; /* [15: 0], WO, 0x0 */
uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
} BF;
uint32_t WORD;
} CPU0_IPC_ISWR;
/* 0x24 : Interrupt raw status Register */
union {
struct {
uint32_t CPU0_IPC_IRSRR : 16; /* [15: 0], RO, 0x0 */
uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
} BF;
uint32_t WORD;
} CPU0_IPC_IRSRR;
/* 0x28 : Interrupt Clear Register */
union {
struct {
uint32_t CPU0_IPC_ICR : 16; /* [15: 0], WO, 0x0 */
uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
} BF;
uint32_t WORD;
} CPU0_IPC_ICR;
/* 0x2c : Interrupt Unmask Set Register */
union {
struct {
uint32_t CPU0_IPC_IUSR : 16; /* [15: 0], RO, 0x0 */
uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
} BF;
uint32_t WORD;
} CPU0_IPC_IUSR;
/* 0x30 : Interrupt Unmask Clear Register */
union {
struct {
uint32_t CPU0_IPC_IUCR : 16; /* [15: 0], RO, 0x0 */
uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
} BF;
uint32_t WORD;
} CPU0_IPC_IUCR;
/* 0x34 : Interrupt Line Sel Low Register */
union {
struct {
uint32_t CPU0_IPC_ILSLR : 32; /* [31: 0], RW, 0x0 */
} BF;
uint32_t WORD;
} CPU0_IPC_ILSLR;
/* 0x38 : Interrupt Line Sel High Register */
union {
struct {
uint32_t CPU0_IPC_ILSHR : 32; /* [31: 0], RW, 0x0 */
} BF;
uint32_t WORD;
} CPU0_IPC_ILSHR;
/* 0x3C : Interrupt status Register */
union {
struct {
uint32_t CPU0_IPC_ISR : 16; /* [15: 0], RO, 0x0 */
uint32_t Reserved_31_16 : 16; /* [31:16], RSVD, 0x0 */
} BF;
uint32_t WORD;
} CPU0_IPC_ISR;
};
#endif /* __IPC_REG_H__ */

188
include/bl808/ir_reg.h Normal file
View File

@ -0,0 +1,188 @@
/**
******************************************************************************
* @file ir_reg.h
* @version V1.0
* @date 2022-09-28
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_IR_H__
#define __HARDWARE_IR_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define IRTX_CONFIG_OFFSET (0x0) /* irtx_config */
#define IRTX_INT_STS_OFFSET (0x4) /* irtx_int_sts */
#define IRTX_PULSE_WIDTH_OFFSET (0x10) /* irtx_pulse_width */
#define IRTX_PW_0_OFFSET (0x14) /* irtx_pw_0 */
#define IRTX_PW_1_OFFSET (0x18) /* irtx_pw_1 */
#define IRRX_CONFIG_OFFSET (0x40) /* irrx_config */
#define IRRX_INT_STS_OFFSET (0x44) /* irrx_int_sts */
#define IRRX_PW_CONFIG_OFFSET (0x48) /* irrx_pw_config */
#define IRRX_DATA_COUNT_OFFSET (0x50) /* irrx_data_count */
#define IRRX_DATA_WORD0_OFFSET (0x54) /* irrx_data_word0 */
#define IRRX_DATA_WORD1_OFFSET (0x58) /* irrx_data_word1 */
#define IR_FIFO_CONFIG_0_OFFSET (0x80) /* ir_fifo_config_0 */
#define IR_FIFO_CONFIG_1_OFFSET (0x84) /* ir_fifo_config_1 */
#define IR_FIFO_WDATA_OFFSET (0x88) /* ir_fifo_wdata */
#define IR_FIFO_RDATA_OFFSET (0x8C) /* ir_fifo_rdata */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : irtx_config */
#define IR_CR_IRTX_EN (1 << 0U)
#define IR_CR_IRTX_OUT_INV (1 << 1U)
#define IR_CR_IRTX_MOD_EN (1 << 2U)
#define IR_CR_IRTX_SWM_EN (1 << 3U)
#define IR_CR_IRTX_DATA_EN (1 << 4U)
#define IR_CR_IRTX_LOGIC0_HL_INV (1 << 5U)
#define IR_CR_IRTX_LOGIC1_HL_INV (1 << 6U)
#define IR_CR_IRTX_HEAD_EN (1 << 8U)
#define IR_CR_IRTX_HEAD_HL_INV (1 << 9U)
#define IR_CR_IRTX_TAIL_EN (1 << 10U)
#define IR_CR_IRTX_TAIL_HL_INV (1 << 11U)
#define IR_CR_IRTX_FRM_EN (1 << 12U)
#define IR_CR_IRTX_FRM_CONT_EN (1 << 13U)
#define IR_CR_IRTX_FRM_FRAME_SIZE_SHIFT (14U)
#define IR_CR_IRTX_FRM_FRAME_SIZE_MASK (0x3 << IR_CR_IRTX_FRM_FRAME_SIZE_SHIFT)
#define IR_CR_IRTX_DATA_NUM_SHIFT (16U)
#define IR_CR_IRTX_DATA_NUM_MASK (0x7f << IR_CR_IRTX_DATA_NUM_SHIFT)
/* 0x4 : irtx_int_sts */
#define IRTX_END_INT (1 << 0U)
#define IRTX_FRDY_INT (1 << 1U)
#define IRTX_FER_INT (1 << 2U)
#define IR_CR_IRTX_END_MASK (1 << 8U)
#define IR_CR_IRTX_FRDY_MASK (1 << 9U)
#define IR_CR_IRTX_FER_MASK (1 << 10U)
#define IR_CR_IRTX_END_CLR (1 << 16U)
#define IR_CR_IRTX_END_EN (1 << 24U)
#define IR_CR_IRTX_FRDY_EN (1 << 25U)
#define IR_CR_IRTX_FER_EN (1 << 26U)
/* 0x10 : irtx_pulse_width */
#define IR_CR_IRTX_PW_UNIT_SHIFT (0U)
#define IR_CR_IRTX_PW_UNIT_MASK (0xfff << IR_CR_IRTX_PW_UNIT_SHIFT)
#define IR_CR_IRTX_MOD_PH0_W_SHIFT (16U)
#define IR_CR_IRTX_MOD_PH0_W_MASK (0xff << IR_CR_IRTX_MOD_PH0_W_SHIFT)
#define IR_CR_IRTX_MOD_PH1_W_SHIFT (24U)
#define IR_CR_IRTX_MOD_PH1_W_MASK (0xff << IR_CR_IRTX_MOD_PH1_W_SHIFT)
/* 0x14 : irtx_pw_0 */
#define IR_CR_IRTX_LOGIC0_PH0_W_SHIFT (0U)
#define IR_CR_IRTX_LOGIC0_PH0_W_MASK (0xff << IR_CR_IRTX_LOGIC0_PH0_W_SHIFT)
#define IR_CR_IRTX_LOGIC0_PH1_W_SHIFT (8U)
#define IR_CR_IRTX_LOGIC0_PH1_W_MASK (0xff << IR_CR_IRTX_LOGIC0_PH1_W_SHIFT)
#define IR_CR_IRTX_LOGIC1_PH0_W_SHIFT (16U)
#define IR_CR_IRTX_LOGIC1_PH0_W_MASK (0xff << IR_CR_IRTX_LOGIC1_PH0_W_SHIFT)
#define IR_CR_IRTX_LOGIC1_PH1_W_SHIFT (24U)
#define IR_CR_IRTX_LOGIC1_PH1_W_MASK (0xff << IR_CR_IRTX_LOGIC1_PH1_W_SHIFT)
/* 0x18 : irtx_pw_1 */
#define IR_CR_IRTX_HEAD_PH0_W_SHIFT (0U)
#define IR_CR_IRTX_HEAD_PH0_W_MASK (0xff << IR_CR_IRTX_HEAD_PH0_W_SHIFT)
#define IR_CR_IRTX_HEAD_PH1_W_SHIFT (8U)
#define IR_CR_IRTX_HEAD_PH1_W_MASK (0xff << IR_CR_IRTX_HEAD_PH1_W_SHIFT)
#define IR_CR_IRTX_TAIL_PH0_W_SHIFT (16U)
#define IR_CR_IRTX_TAIL_PH0_W_MASK (0xff << IR_CR_IRTX_TAIL_PH0_W_SHIFT)
#define IR_CR_IRTX_TAIL_PH1_W_SHIFT (24U)
#define IR_CR_IRTX_TAIL_PH1_W_MASK (0xff << IR_CR_IRTX_TAIL_PH1_W_SHIFT)
/* 0x40 : irrx_config */
#define IR_CR_IRRX_EN (1 << 0U)
#define IR_CR_IRRX_IN_INV (1 << 1U)
#define IR_CR_IRRX_MODE_SHIFT (2U)
#define IR_CR_IRRX_MODE_MASK (0x3 << IR_CR_IRRX_MODE_SHIFT)
#define IR_CR_IRRX_DEG_EN (1 << 4U)
#define IR_CR_IRRX_DEG_CNT_SHIFT (8U)
#define IR_CR_IRRX_DEG_CNT_MASK (0xf << IR_CR_IRRX_DEG_CNT_SHIFT)
/* 0x44 : irrx_int_sts */
#define IRRX_END_INT (1 << 0U)
#define IRRX_FRDY_INT (1 << 1U)
#define IRRX_FER_INT (1 << 2U)
#define IR_CR_IRRX_END_MASK (1 << 8U)
#define IR_CR_IRRX_FRDY_MASK (1 << 9U)
#define IR_CR_IRRX_FER_MASK (1 << 10U)
#define IR_CR_IRRX_END_CLR (1 << 16U)
#define IR_CR_IRRX_END_EN (1 << 24U)
#define IR_CR_IRRX_FRDY_EN (1 << 25U)
#define IR_CR_IRRX_FER_EN (1 << 26U)
/* 0x48 : irrx_pw_config */
#define IR_CR_IRRX_DATA_TH_SHIFT (0U)
#define IR_CR_IRRX_DATA_TH_MASK (0xffff << IR_CR_IRRX_DATA_TH_SHIFT)
#define IR_CR_IRRX_END_TH_SHIFT (16U)
#define IR_CR_IRRX_END_TH_MASK (0xffff << IR_CR_IRRX_END_TH_SHIFT)
/* 0x50 : irrx_data_count */
#define IR_STS_IRRX_DATA_CNT_SHIFT (0U)
#define IR_STS_IRRX_DATA_CNT_MASK (0x7f << IR_STS_IRRX_DATA_CNT_SHIFT)
/* 0x54 : irrx_data_word0 */
#define IR_STS_IRRX_DATA_WORD0_SHIFT (0U)
#define IR_STS_IRRX_DATA_WORD0_MASK (0xffffffff << IR_STS_IRRX_DATA_WORD0_SHIFT)
/* 0x58 : irrx_data_word1 */
#define IR_STS_IRRX_DATA_WORD1_SHIFT (0U)
#define IR_STS_IRRX_DATA_WORD1_MASK (0xffffffff << IR_STS_IRRX_DATA_WORD1_SHIFT)
/* 0x80 : ir_fifo_config_0 */
#define IRTX_DMA_EN (1 << 0U)
#define IR_TX_FIFO_CLR (1 << 2U)
#define IR_RX_FIFO_CLR (1 << 3U)
#define IR_TX_FIFO_OVERFLOW (1 << 4U)
#define IR_TX_FIFO_UNDERFLOW (1 << 5U)
#define IR_RX_FIFO_OVERFLOW (1 << 6U)
#define IR_RX_FIFO_UNDERFLOW (1 << 7U)
/* 0x84 : ir_fifo_config_1 */
#define IR_TX_FIFO_CNT_SHIFT (0U)
#define IR_TX_FIFO_CNT_MASK (0x7 << IR_TX_FIFO_CNT_SHIFT)
#define IR_RX_FIFO_CNT_SHIFT (8U)
#define IR_RX_FIFO_CNT_MASK (0x7f << IR_RX_FIFO_CNT_SHIFT)
#define IR_TX_FIFO_TH_SHIFT (16U)
#define IR_TX_FIFO_TH_MASK (0x3 << IR_TX_FIFO_TH_SHIFT)
#define IR_RX_FIFO_TH_SHIFT (24U)
#define IR_RX_FIFO_TH_MASK (0x3f << IR_RX_FIFO_TH_SHIFT)
/* 0x88 : ir_fifo_wdata */
#define IR_TX_FIFO_WDATA_SHIFT (0U)
#define IR_TX_FIFO_WDATA_MASK (0xffffffff << IR_TX_FIFO_WDATA_SHIFT)
/* 0x8C : ir_fifo_rdata */
#define IR_RX_FIFO_RDATA_SHIFT (0U)
#define IR_RX_FIFO_RDATA_MASK (0xffff << IR_RX_FIFO_RDATA_SHIFT)
#endif /* __HARDWARE_IR_H__ */

350
include/bl808/mcu_misc_reg.h Normal file
View File

@ -0,0 +1,350 @@
/**
******************************************************************************
* @file mcu_misc_reg.h
* @version V1.0
* @date 2021-07-12
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __MCU_MISC_REG_H__
#define __MCU_MISC_REG_H__
#include <linux/types.h>
/* 0x0 : mcu_bus_cfg0 */
#define MCU_MISC_MCU_BUS_CFG0_OFFSET (0x0)
#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN
#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_POS (0U)
#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_LEN (1U)
#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_MSK (((1U << MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_POS)
#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_UMSK (~(((1U << MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_POS))
#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR
#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_POS (1U)
#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_LEN (1U)
#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_MSK (((1U << MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_POS)
#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_UMSK (~(((1U << MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_POS))
#define MCU_MISC_STS_MCU_INFRA_TIMEOUT MCU_MISC_STS_MCU_INFRA_TIMEOUT
#define MCU_MISC_STS_MCU_INFRA_TIMEOUT_POS (16U)
#define MCU_MISC_STS_MCU_INFRA_TIMEOUT_LEN (1U)
#define MCU_MISC_STS_MCU_INFRA_TIMEOUT_MSK (((1U << MCU_MISC_STS_MCU_INFRA_TIMEOUT_LEN) - 1) << MCU_MISC_STS_MCU_INFRA_TIMEOUT_POS)
#define MCU_MISC_STS_MCU_INFRA_TIMEOUT_UMSK (~(((1U << MCU_MISC_STS_MCU_INFRA_TIMEOUT_LEN) - 1) << MCU_MISC_STS_MCU_INFRA_TIMEOUT_POS))
/* 0x4 : mcu_bus_cfg1 */
#define MCU_MISC_MCU_BUS_CFG1_OFFSET (0x4)
#define MCU_MISC_REG_MCU1_HQOS MCU_MISC_REG_MCU1_HQOS
#define MCU_MISC_REG_MCU1_HQOS_POS (0U)
#define MCU_MISC_REG_MCU1_HQOS_LEN (1U)
#define MCU_MISC_REG_MCU1_HQOS_MSK (((1U << MCU_MISC_REG_MCU1_HQOS_LEN) - 1) << MCU_MISC_REG_MCU1_HQOS_POS)
#define MCU_MISC_REG_MCU1_HQOS_UMSK (~(((1U << MCU_MISC_REG_MCU1_HQOS_LEN) - 1) << MCU_MISC_REG_MCU1_HQOS_POS))
#define MCU_MISC_REG_MCU1_AWQOS MCU_MISC_REG_MCU1_AWQOS
#define MCU_MISC_REG_MCU1_AWQOS_POS (1U)
#define MCU_MISC_REG_MCU1_AWQOS_LEN (1U)
#define MCU_MISC_REG_MCU1_AWQOS_MSK (((1U << MCU_MISC_REG_MCU1_AWQOS_LEN) - 1) << MCU_MISC_REG_MCU1_AWQOS_POS)
#define MCU_MISC_REG_MCU1_AWQOS_UMSK (~(((1U << MCU_MISC_REG_MCU1_AWQOS_LEN) - 1) << MCU_MISC_REG_MCU1_AWQOS_POS))
#define MCU_MISC_REG_MCU1_ARQOS MCU_MISC_REG_MCU1_ARQOS
#define MCU_MISC_REG_MCU1_ARQOS_POS (2U)
#define MCU_MISC_REG_MCU1_ARQOS_LEN (1U)
#define MCU_MISC_REG_MCU1_ARQOS_MSK (((1U << MCU_MISC_REG_MCU1_ARQOS_LEN) - 1) << MCU_MISC_REG_MCU1_ARQOS_POS)
#define MCU_MISC_REG_MCU1_ARQOS_UMSK (~(((1U << MCU_MISC_REG_MCU1_ARQOS_LEN) - 1) << MCU_MISC_REG_MCU1_ARQOS_POS))
#define MCU_MISC_REG_MCU_X2HS_SP_BYPASS MCU_MISC_REG_MCU_X2HS_SP_BYPASS
#define MCU_MISC_REG_MCU_X2HS_SP_BYPASS_POS (3U)
#define MCU_MISC_REG_MCU_X2HS_SP_BYPASS_LEN (1U)
#define MCU_MISC_REG_MCU_X2HS_SP_BYPASS_MSK (((1U << MCU_MISC_REG_MCU_X2HS_SP_BYPASS_LEN) - 1) << MCU_MISC_REG_MCU_X2HS_SP_BYPASS_POS)
#define MCU_MISC_REG_MCU_X2HS_SP_BYPASS_UMSK (~(((1U << MCU_MISC_REG_MCU_X2HS_SP_BYPASS_LEN) - 1) << MCU_MISC_REG_MCU_X2HS_SP_BYPASS_POS))
#define MCU_MISC_REG_X_WTHRE_MCU2EXT MCU_MISC_REG_X_WTHRE_MCU2EXT
#define MCU_MISC_REG_X_WTHRE_MCU2EXT_POS (7U)
#define MCU_MISC_REG_X_WTHRE_MCU2EXT_LEN (2U)
#define MCU_MISC_REG_X_WTHRE_MCU2EXT_MSK (((1U << MCU_MISC_REG_X_WTHRE_MCU2EXT_LEN) - 1) << MCU_MISC_REG_X_WTHRE_MCU2EXT_POS)
#define MCU_MISC_REG_X_WTHRE_MCU2EXT_UMSK (~(((1U << MCU_MISC_REG_X_WTHRE_MCU2EXT_LEN) - 1) << MCU_MISC_REG_X_WTHRE_MCU2EXT_POS))
#define MCU_MISC_REG_MCU_INFRA_ARB_MODE MCU_MISC_REG_MCU_INFRA_ARB_MODE
#define MCU_MISC_REG_MCU_INFRA_ARB_MODE_POS (16U)
#define MCU_MISC_REG_MCU_INFRA_ARB_MODE_LEN (1U)
#define MCU_MISC_REG_MCU_INFRA_ARB_MODE_MSK (((1U << MCU_MISC_REG_MCU_INFRA_ARB_MODE_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_ARB_MODE_POS)
#define MCU_MISC_REG_MCU_INFRA_ARB_MODE_UMSK (~(((1U << MCU_MISC_REG_MCU_INFRA_ARB_MODE_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_ARB_MODE_POS))
/* 0x14 : mcu_e907_rtc */
#define MCU_MISC_MCU_E907_RTC_OFFSET (0x14)
#define MCU_MISC_REG_MCU_RTC_DIV MCU_MISC_REG_MCU_RTC_DIV
#define MCU_MISC_REG_MCU_RTC_DIV_POS (0U)
#define MCU_MISC_REG_MCU_RTC_DIV_LEN (10U)
#define MCU_MISC_REG_MCU_RTC_DIV_MSK (((1U << MCU_MISC_REG_MCU_RTC_DIV_LEN) - 1) << MCU_MISC_REG_MCU_RTC_DIV_POS)
#define MCU_MISC_REG_MCU_RTC_DIV_UMSK (~(((1U << MCU_MISC_REG_MCU_RTC_DIV_LEN) - 1) << MCU_MISC_REG_MCU_RTC_DIV_POS))
#define MCU_MISC_REG_MCU_RTC_RST MCU_MISC_REG_MCU_RTC_RST
#define MCU_MISC_REG_MCU_RTC_RST_POS (30U)
#define MCU_MISC_REG_MCU_RTC_RST_LEN (1U)
#define MCU_MISC_REG_MCU_RTC_RST_MSK (((1U << MCU_MISC_REG_MCU_RTC_RST_LEN) - 1) << MCU_MISC_REG_MCU_RTC_RST_POS)
#define MCU_MISC_REG_MCU_RTC_RST_UMSK (~(((1U << MCU_MISC_REG_MCU_RTC_RST_LEN) - 1) << MCU_MISC_REG_MCU_RTC_RST_POS))
#define MCU_MISC_REG_MCU_RTC_EN MCU_MISC_REG_MCU_RTC_EN
#define MCU_MISC_REG_MCU_RTC_EN_POS (31U)
#define MCU_MISC_REG_MCU_RTC_EN_LEN (1U)
#define MCU_MISC_REG_MCU_RTC_EN_MSK (((1U << MCU_MISC_REG_MCU_RTC_EN_LEN) - 1) << MCU_MISC_REG_MCU_RTC_EN_POS)
#define MCU_MISC_REG_MCU_RTC_EN_UMSK (~(((1U << MCU_MISC_REG_MCU_RTC_EN_LEN) - 1) << MCU_MISC_REG_MCU_RTC_EN_POS))
/* 0x100 : mcu_cfg1 */
#define MCU_MISC_MCU_CFG1_OFFSET (0x100)
#define MCU_MISC_REG_MCU1_DFS_REQ MCU_MISC_REG_MCU1_DFS_REQ
#define MCU_MISC_REG_MCU1_DFS_REQ_POS (0U)
#define MCU_MISC_REG_MCU1_DFS_REQ_LEN (1U)
#define MCU_MISC_REG_MCU1_DFS_REQ_MSK (((1U << MCU_MISC_REG_MCU1_DFS_REQ_LEN) - 1) << MCU_MISC_REG_MCU1_DFS_REQ_POS)
#define MCU_MISC_REG_MCU1_DFS_REQ_UMSK (~(((1U << MCU_MISC_REG_MCU1_DFS_REQ_LEN) - 1) << MCU_MISC_REG_MCU1_DFS_REQ_POS))
#define MCU_MISC_STS_MCU1_DFS_ACK MCU_MISC_STS_MCU1_DFS_ACK
#define MCU_MISC_STS_MCU1_DFS_ACK_POS (2U)
#define MCU_MISC_STS_MCU1_DFS_ACK_LEN (1U)
#define MCU_MISC_STS_MCU1_DFS_ACK_MSK (((1U << MCU_MISC_STS_MCU1_DFS_ACK_LEN) - 1) << MCU_MISC_STS_MCU1_DFS_ACK_POS)
#define MCU_MISC_STS_MCU1_DFS_ACK_UMSK (~(((1U << MCU_MISC_STS_MCU1_DFS_ACK_LEN) - 1) << MCU_MISC_STS_MCU1_DFS_ACK_POS))
#define MCU_MISC_REG_MCU1_SRST_EN MCU_MISC_REG_MCU1_SRST_EN
#define MCU_MISC_REG_MCU1_SRST_EN_POS (4U)
#define MCU_MISC_REG_MCU1_SRST_EN_LEN (2U)
#define MCU_MISC_REG_MCU1_SRST_EN_MSK (((1U << MCU_MISC_REG_MCU1_SRST_EN_LEN) - 1) << MCU_MISC_REG_MCU1_SRST_EN_POS)
#define MCU_MISC_REG_MCU1_SRST_EN_UMSK (~(((1U << MCU_MISC_REG_MCU1_SRST_EN_LEN) - 1) << MCU_MISC_REG_MCU1_SRST_EN_POS))
#define MCU_MISC_STS_MCU1_LPMD_B MCU_MISC_STS_MCU1_LPMD_B
#define MCU_MISC_STS_MCU1_LPMD_B_POS (10U)
#define MCU_MISC_STS_MCU1_LPMD_B_LEN (2U)
#define MCU_MISC_STS_MCU1_LPMD_B_MSK (((1U << MCU_MISC_STS_MCU1_LPMD_B_LEN) - 1) << MCU_MISC_STS_MCU1_LPMD_B_POS)
#define MCU_MISC_STS_MCU1_LPMD_B_UMSK (~(((1U << MCU_MISC_STS_MCU1_LPMD_B_LEN) - 1) << MCU_MISC_STS_MCU1_LPMD_B_POS))
#define MCU_MISC_MCU1_WFI_FORCE MCU_MISC_MCU1_WFI_FORCE
#define MCU_MISC_MCU1_WFI_FORCE_POS (16U)
#define MCU_MISC_MCU1_WFI_FORCE_LEN (1U)
#define MCU_MISC_MCU1_WFI_FORCE_MSK (((1U << MCU_MISC_MCU1_WFI_FORCE_LEN) - 1) << MCU_MISC_MCU1_WFI_FORCE_POS)
#define MCU_MISC_MCU1_WFI_FORCE_UMSK (~(((1U << MCU_MISC_MCU1_WFI_FORCE_LEN) - 1) << MCU_MISC_MCU1_WFI_FORCE_POS))
#define MCU_MISC_MCU1_NDM_RSTN_EN MCU_MISC_MCU1_NDM_RSTN_EN
#define MCU_MISC_MCU1_NDM_RSTN_EN_POS (28U)
#define MCU_MISC_MCU1_NDM_RSTN_EN_LEN (1U)
#define MCU_MISC_MCU1_NDM_RSTN_EN_MSK (((1U << MCU_MISC_MCU1_NDM_RSTN_EN_LEN) - 1) << MCU_MISC_MCU1_NDM_RSTN_EN_POS)
#define MCU_MISC_MCU1_NDM_RSTN_EN_UMSK (~(((1U << MCU_MISC_MCU1_NDM_RSTN_EN_LEN) - 1) << MCU_MISC_MCU1_NDM_RSTN_EN_POS))
#define MCU_MISC_MCU1_HART_RSTN_EN MCU_MISC_MCU1_HART_RSTN_EN
#define MCU_MISC_MCU1_HART_RSTN_EN_POS (29U)
#define MCU_MISC_MCU1_HART_RSTN_EN_LEN (1U)
#define MCU_MISC_MCU1_HART_RSTN_EN_MSK (((1U << MCU_MISC_MCU1_HART_RSTN_EN_LEN) - 1) << MCU_MISC_MCU1_HART_RSTN_EN_POS)
#define MCU_MISC_MCU1_HART_RSTN_EN_UMSK (~(((1U << MCU_MISC_MCU1_HART_RSTN_EN_LEN) - 1) << MCU_MISC_MCU1_HART_RSTN_EN_POS))
/* 0x110 : mcu1_log1 */
#define MCU_MISC_MCU1_LOG1_OFFSET (0x110)
#define MCU_MISC_STS_MCU1_MCAUSE MCU_MISC_STS_MCU1_MCAUSE
#define MCU_MISC_STS_MCU1_MCAUSE_POS (0U)
#define MCU_MISC_STS_MCU1_MCAUSE_LEN (32U)
#define MCU_MISC_STS_MCU1_MCAUSE_MSK (((1U << MCU_MISC_STS_MCU1_MCAUSE_LEN) - 1) << MCU_MISC_STS_MCU1_MCAUSE_POS)
#define MCU_MISC_STS_MCU1_MCAUSE_UMSK (~(((1U << MCU_MISC_STS_MCU1_MCAUSE_LEN) - 1) << MCU_MISC_STS_MCU1_MCAUSE_POS))
/* 0x114 : mcu1_log2 */
#define MCU_MISC_MCU1_LOG2_OFFSET (0x114)
#define MCU_MISC_STS_MCU1_MINTSTATUS MCU_MISC_STS_MCU1_MINTSTATUS
#define MCU_MISC_STS_MCU1_MINTSTATUS_POS (0U)
#define MCU_MISC_STS_MCU1_MINTSTATUS_LEN (32U)
#define MCU_MISC_STS_MCU1_MINTSTATUS_MSK (((1U << MCU_MISC_STS_MCU1_MINTSTATUS_LEN) - 1) << MCU_MISC_STS_MCU1_MINTSTATUS_POS)
#define MCU_MISC_STS_MCU1_MINTSTATUS_UMSK (~(((1U << MCU_MISC_STS_MCU1_MINTSTATUS_LEN) - 1) << MCU_MISC_STS_MCU1_MINTSTATUS_POS))
/* 0x118 : mcu1_log3 */
#define MCU_MISC_MCU1_LOG3_OFFSET (0x118)
#define MCU_MISC_STS_MCU1_MSTATUS MCU_MISC_STS_MCU1_MSTATUS
#define MCU_MISC_STS_MCU1_MSTATUS_POS (0U)
#define MCU_MISC_STS_MCU1_MSTATUS_LEN (32U)
#define MCU_MISC_STS_MCU1_MSTATUS_MSK (((1U << MCU_MISC_STS_MCU1_MSTATUS_LEN) - 1) << MCU_MISC_STS_MCU1_MSTATUS_POS)
#define MCU_MISC_STS_MCU1_MSTATUS_UMSK (~(((1U << MCU_MISC_STS_MCU1_MSTATUS_LEN) - 1) << MCU_MISC_STS_MCU1_MSTATUS_POS))
/* 0x11C : mcu1_log4 */
#define MCU_MISC_MCU1_LOG4_OFFSET (0x11C)
#define MCU_MISC_STS_MCU1_SP MCU_MISC_STS_MCU1_SP
#define MCU_MISC_STS_MCU1_SP_POS (0U)
#define MCU_MISC_STS_MCU1_SP_LEN (1U)
#define MCU_MISC_STS_MCU1_SP_MSK (((1U << MCU_MISC_STS_MCU1_SP_LEN) - 1) << MCU_MISC_STS_MCU1_SP_POS)
#define MCU_MISC_STS_MCU1_SP_UMSK (~(((1U << MCU_MISC_STS_MCU1_SP_LEN) - 1) << MCU_MISC_STS_MCU1_SP_POS))
#define MCU_MISC_STS_MCU1_PC MCU_MISC_STS_MCU1_PC
#define MCU_MISC_STS_MCU1_PC_POS (1U)
#define MCU_MISC_STS_MCU1_PC_LEN (31U)
#define MCU_MISC_STS_MCU1_PC_MSK (((1U << MCU_MISC_STS_MCU1_PC_LEN) - 1) << MCU_MISC_STS_MCU1_PC_POS)
#define MCU_MISC_STS_MCU1_PC_UMSK (~(((1U << MCU_MISC_STS_MCU1_PC_LEN) - 1) << MCU_MISC_STS_MCU1_PC_POS))
/* 0x120 : mcu1_log5 */
#define MCU_MISC_MCU1_LOG5_OFFSET (0x120)
#define MCU_MISC_STS_MCU1_LOCKUP MCU_MISC_STS_MCU1_LOCKUP
#define MCU_MISC_STS_MCU1_LOCKUP_POS (24U)
#define MCU_MISC_STS_MCU1_LOCKUP_LEN (1U)
#define MCU_MISC_STS_MCU1_LOCKUP_MSK (((1U << MCU_MISC_STS_MCU1_LOCKUP_LEN) - 1) << MCU_MISC_STS_MCU1_LOCKUP_POS)
#define MCU_MISC_STS_MCU1_LOCKUP_UMSK (~(((1U << MCU_MISC_STS_MCU1_LOCKUP_LEN) - 1) << MCU_MISC_STS_MCU1_LOCKUP_POS))
#define MCU_MISC_STS_MCU1_HALTED MCU_MISC_STS_MCU1_HALTED
#define MCU_MISC_STS_MCU1_HALTED_POS (25U)
#define MCU_MISC_STS_MCU1_HALTED_LEN (1U)
#define MCU_MISC_STS_MCU1_HALTED_MSK (((1U << MCU_MISC_STS_MCU1_HALTED_LEN) - 1) << MCU_MISC_STS_MCU1_HALTED_POS)
#define MCU_MISC_STS_MCU1_HALTED_UMSK (~(((1U << MCU_MISC_STS_MCU1_HALTED_LEN) - 1) << MCU_MISC_STS_MCU1_HALTED_POS))
#define MCU_MISC_MCU1_NDM_RSTN_REQ MCU_MISC_MCU1_NDM_RSTN_REQ
#define MCU_MISC_MCU1_NDM_RSTN_REQ_POS (28U)
#define MCU_MISC_MCU1_NDM_RSTN_REQ_LEN (1U)
#define MCU_MISC_MCU1_NDM_RSTN_REQ_MSK (((1U << MCU_MISC_MCU1_NDM_RSTN_REQ_LEN) - 1) << MCU_MISC_MCU1_NDM_RSTN_REQ_POS)
#define MCU_MISC_MCU1_NDM_RSTN_REQ_UMSK (~(((1U << MCU_MISC_MCU1_NDM_RSTN_REQ_LEN) - 1) << MCU_MISC_MCU1_NDM_RSTN_REQ_POS))
#define MCU_MISC_MCU1_HART_RSTN_REQ MCU_MISC_MCU1_HART_RSTN_REQ
#define MCU_MISC_MCU1_HART_RSTN_REQ_POS (29U)
#define MCU_MISC_MCU1_HART_RSTN_REQ_LEN (1U)
#define MCU_MISC_MCU1_HART_RSTN_REQ_MSK (((1U << MCU_MISC_MCU1_HART_RSTN_REQ_LEN) - 1) << MCU_MISC_MCU1_HART_RSTN_REQ_POS)
#define MCU_MISC_MCU1_HART_RSTN_REQ_UMSK (~(((1U << MCU_MISC_MCU1_HART_RSTN_REQ_LEN) - 1) << MCU_MISC_MCU1_HART_RSTN_REQ_POS))
/* 0x208 : irom1_misr_dataout_0 */
#define MCU_MISC_IROM1_MISR_DATAOUT_0_OFFSET (0x208)
/* 0x20C : irom1_misr_dataout_1 */
#define MCU_MISC_IROM1_MISR_DATAOUT_1_OFFSET (0x20C)
struct mcu_misc_reg {
/* 0x0 : mcu_bus_cfg0 */
union {
struct {
uint32_t reg_mcu_infra_timeout_en : 1; /* [ 0], r/w, 0x0 */
uint32_t reg_mcu_infra_timeout_clr : 1; /* [ 1], r/w, 0x0 */
uint32_t reserved_2_15 : 14; /* [15: 2], rsvd, 0x0 */
uint32_t sts_mcu_infra_timeout : 1; /* [ 16], r, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
} BF;
uint32_t WORD;
} mcu_bus_cfg0;
/* 0x4 : mcu_bus_cfg1 */
union {
struct {
uint32_t reg_mcu1_hqos : 1; /* [ 0], r/w, 0x0 */
uint32_t reg_mcu1_awqos : 1; /* [ 1], r/w, 0x0 */
uint32_t reg_mcu1_arqos : 1; /* [ 2], r/w, 0x0 */
uint32_t reg_mcu_x2hs_sp_bypass : 1; /* [ 3], r/w, 0x0 */
uint32_t reserved_4_6 : 3; /* [ 6: 4], rsvd, 0x0 */
uint32_t reg_x_wthre_mcu2ext : 2; /* [ 8: 7], r/w, 0x0 */
uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */
uint32_t reg_mcu_infra_arb_mode : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
} BF;
uint32_t WORD;
} mcu_bus_cfg1;
/* 0x8 reserved */
uint8_t RESERVED0x8[12];
/* 0x14 : mcu_e907_rtc */
union {
struct {
uint32_t reg_mcu_rtc_div : 10; /* [ 9: 0], r/w, 0xa */
uint32_t reserved_10_29 : 20; /* [29:10], rsvd, 0x0 */
uint32_t reg_mcu_rtc_rst : 1; /* [ 30], r/w, 0x0 */
uint32_t reg_mcu_rtc_en : 1; /* [ 31], r/w, 0x1 */
} BF;
uint32_t WORD;
} mcu_e907_rtc;
/* 0x18 reserved */
uint8_t RESERVED0x18[232];
/* 0x100 : mcu_cfg1 */
union {
struct {
uint32_t reg_mcu1_dfs_req : 1; /* [ 0], r/w, 0x0 */
uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
uint32_t sts_mcu1_dfs_ack : 1; /* [ 2], r, 0x0 */
uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
uint32_t reg_mcu1_srst_en : 2; /* [ 5: 4], r/w, 0x3 */
uint32_t reserved_6_9 : 4; /* [ 9: 6], rsvd, 0x0 */
uint32_t sts_mcu1_lpmd_b : 2; /* [11:10], r, 0x0 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t MCU1_WFI_FORCE : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_27 : 11; /* [27:17], rsvd, 0x0 */
uint32_t mcu1_ndm_rstn_en : 1; /* [ 28], r/w, 0x0 */
uint32_t mcu1_hart_rstn_en : 1; /* [ 29], r/w, 0x0 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
} BF;
uint32_t WORD;
} mcu_cfg1;
/* 0x104 reserved */
uint8_t RESERVED0x104[12];
/* 0x110 : mcu1_log1 */
union {
struct {
uint32_t sts_mcu1_mcause : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} mcu1_log1;
/* 0x114 : mcu1_log2 */
union {
struct {
uint32_t sts_mcu1_mintstatus : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} mcu1_log2;
/* 0x118 : mcu1_log3 */
union {
struct {
uint32_t sts_mcu1_mstatus : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} mcu1_log3;
/* 0x11C : mcu1_log4 */
union {
struct {
uint32_t sts_mcu1_sp : 1; /* [ 0], r, 0x0 */
uint32_t sts_mcu1_pc : 31; /* [31: 1], r, 0x0 */
} BF;
uint32_t WORD;
} mcu1_log4;
/* 0x120 : mcu1_log5 */
union {
struct {
uint32_t reserved_0_23 : 24; /* [23: 0], rsvd, 0x0 */
uint32_t sts_mcu1_lockup : 1; /* [ 24], r, 0x0 */
uint32_t sts_mcu1_halted : 1; /* [ 25], r, 0x0 */
uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */
uint32_t mcu1_ndm_rstn_req : 1; /* [ 28], r, 0x0 */
uint32_t mcu1_hart_rstn_req : 1; /* [ 29], r, 0x0 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
} BF;
uint32_t WORD;
} mcu1_log5;
/* 0x124 reserved */
uint8_t RESERVED0x124[228];
/* 0x208 : irom1_misr_dataout_0 */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
} BF;
uint32_t WORD;
} irom1_misr_dataout_0;
/* 0x20C : irom1_misr_dataout_1 */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
} BF;
uint32_t WORD;
} irom1_misr_dataout_1;
};
#endif /* __MCU_MISC_REG_H__ */

319
include/bl808/mjpeg_reg.h Normal file
View File

@ -0,0 +1,319 @@
/**
******************************************************************************
* @file mjpeg_reg.h
* @version V1.0
* @date 2022-11-01
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_MJPEG_REG_H__
#define __HARDWARE_MJPEG_REG_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define MJPEG_CONTROL_1_OFFSET (0x0)/* mjpeg_control_1 */
#define MJPEG_CONTROL_2_OFFSET (0x4)/* mjpeg_control_2 */
#define MJPEG_YY_FRAME_ADDR_OFFSET (0x08)/* mjpeg_yy_frame_addr */
#define MJPEG_UV_FRAME_ADDR_OFFSET (0x0C)/* mjpeg_uv_frame_addr */
#define MJPEG_YUV_MEM_OFFSET (0x10)/* mjpeg_yuv_mem */
#define MJPEG_JPEG_FRAME_ADDR_OFFSET (0x14)/* jpeg_frame_addr */
#define MJPEG_JPEG_STORE_MEMORY_OFFSET (0x18)/* jpeg_store_memory */
#define MJPEG_CONTROL_3_OFFSET (0x1C)/* mjpeg_control_3 */
#define MJPEG_FRAME_FIFO_POP_OFFSET (0x20)/* mjpeg_frame_fifo_pop */
#define MJPEG_FRAME_SIZE_OFFSET (0x24)/* mjpeg_frame_size */
#define MJPEG_HEADER_BYTE_OFFSET (0x28)/* mjpeg_header_byte */
#define MJPEG_SWAP_MODE_OFFSET (0x30)/* mjpeg_swap_mode */
#define MJPEG_SWAP_BIT_CNT_OFFSET (0x34)/* mjpeg_swap_bit_cnt */
#define MJPEG_YUV_MEM_SW_OFFSET (0x38)/* mjpeg_yuv_mem_sw */
#define MJPEG_Y_FRAME_READ_STATUS_1_OFFSET (0x40)/* mjpeg_Y_frame_read_status_1 */
#define MJPEG_Y_FRAME_READ_STATUS_2_OFFSET (0x44)/* mjpeg_Y_frame_read_status_2 */
#define MJPEG_Y_FRAME_WRITE_STATUS_OFFSET (0x48)/* mjpeg_Y_frame_write_status */
#define MJPEG_UV_FRAME_READ_STATUS_1_OFFSET (0x4C)/* mjpeg_UV_frame_read_status_1 */
#define MJPEG_UV_FRAME_READ_STATUS_2_OFFSET (0x50)/* mjpeg_UV_frame_read_status_2 */
#define MJPEG_UV_FRAME_WRITE_STATUS_OFFSET (0x54)/* mjpeg_UV_frame_write_status */
#define MJPEG_FRAME_W_HBLK_STATUS_OFFSET (0x58)/* mjpeg_frame_w_hblk_status */
#define MJPEG_START_ADDR0_OFFSET (0x80)/* mjpeg_start_addr0 */
#define MJPEG_BIT_CNT0_OFFSET (0x84)/* mjpeg_bit_cnt0 */
#define MJPEG_START_ADDR1_OFFSET (0x88)/* mjpeg_start_addr1 */
#define MJPEG_BIT_CNT1_OFFSET (0x8C)/* mjpeg_bit_cnt1 */
#define MJPEG_START_ADDR2_OFFSET (0x90)/* mjpeg_start_addr2 */
#define MJPEG_BIT_CNT2_OFFSET (0x94)/* mjpeg_bit_cnt2 */
#define MJPEG_START_ADDR3_OFFSET (0x98)/* mjpeg_start_addr3 */
#define MJPEG_BIT_CNT3_OFFSET (0x9C)/* mjpeg_bit_cnt3 */
#define MJPEG_Q_ENC_OFFSET (0x100)/* mjpeg_q_enc */
#define MJPEG_FRAME_ID_10_OFFSET (0x110)/* mjpeg_frame_id_10 */
#define MJPEG_FRAME_ID_32_OFFSET (0x114)/* mjpeg_frame_id_32 */
#define MJPEG_DEBUG_OFFSET (0x1F0)/* mjpeg_debug */
#define MJPEG_DUMMY_REG_OFFSET (0x1FC)/* mjpeg_dummy_reg */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : mjpeg_control_1 */
#define MJPEG_REG_MJPEG_ENABLE (1<<0U)
#define MJPEG_REG_MJPEG_BIT_ORDER (1<<1U)
#define MJPEG_REG_ORDER_U_EVEN (1<<2U)
#define MJPEG_REG_HW_MODE_SWEN (1<<3U)
#define MJPEG_REG_LAST_HF_WBLK_DMY (1<<4U)
#define MJPEG_REG_LAST_HF_HBLK_DMY (1<<5U)
#define MJPEG_REG_REFLECT_DMY (1<<6U)
#define MJPEG_REG_READ_FWRAP (1<<7U)
#define MJPEG_REG_W_XLEN_SHIFT (8U)
#define MJPEG_REG_W_XLEN_MASK (0x7<<MJPEG_REG_W_XLEN_SHIFT)
#define MJPEG_REG_YUV_MODE_SHIFT (12U)
#define MJPEG_REG_YUV_MODE_MASK (0x3<<MJPEG_REG_YUV_MODE_SHIFT)
#define MJPEG_REG_MJPEG_HW_FRAME_SHIFT (24U)
#define MJPEG_REG_MJPEG_HW_FRAME_MASK (0x3f<<MJPEG_REG_MJPEG_HW_FRAME_SHIFT)
/* 0x4 : mjpeg_control_2 */
#define MJPEG_REG_SW_FRAME_SHIFT (0U)
#define MJPEG_REG_SW_FRAME_MASK (0x1f<<MJPEG_REG_SW_FRAME_SHIFT)
#define MJPEG_REG_SW_KICK (1<<6U)
#define MJPEG_REG_SW_KICK_MODE (1<<7U)
#define MJPEG_REG_MJPEG_SW_MODE (1<<8U)
#define MJPEG_REG_MJPEG_SW_RUN (1<<9U)
#define MJPEG_REG_YY_DVP2AXI_SEL_SHIFT (10U)
#define MJPEG_REG_YY_DVP2AXI_SEL_MASK (0x7<<MJPEG_REG_YY_DVP2AXI_SEL_SHIFT)
#define MJPEG_REG_UV_DVP2AXI_SEL_SHIFT (13U)
#define MJPEG_REG_UV_DVP2AXI_SEL_MASK (0x7<<MJPEG_REG_UV_DVP2AXI_SEL_SHIFT)
#define MJPEG_REG_MJPEG_WAIT_CYCLE_SHIFT (16U)
#define MJPEG_REG_MJPEG_WAIT_CYCLE_MASK (0xffff<<MJPEG_REG_MJPEG_WAIT_CYCLE_SHIFT)
/* 0x08 : mjpeg_yy_frame_addr */
#define MJPEG_REG_YY_ADDR_START_SHIFT (0U)
#define MJPEG_REG_YY_ADDR_START_MASK (0xffffffff<<MJPEG_REG_YY_ADDR_START_SHIFT)
/* 0x0C : mjpeg_uv_frame_addr */
#define MJPEG_REG_UV_ADDR_START_SHIFT (0U)
#define MJPEG_REG_UV_ADDR_START_MASK (0xffffffff<<MJPEG_REG_UV_ADDR_START_SHIFT)
/* 0x10 : mjpeg_yuv_mem */
#define MJPEG_REG_YY_MEM_HBLK_SHIFT (0U)
#define MJPEG_REG_YY_MEM_HBLK_MASK (0x1fff<<MJPEG_REG_YY_MEM_HBLK_SHIFT)
#define MJPEG_REG_UV_MEM_HBLK_SHIFT (16U)
#define MJPEG_REG_UV_MEM_HBLK_MASK (0x1fff<<MJPEG_REG_UV_MEM_HBLK_SHIFT)
/* 0x14 : jpeg_frame_addr */
#define MJPEG_REG_W_ADDR_START_SHIFT (0U)
#define MJPEG_REG_W_ADDR_START_MASK (0xffffffff<<MJPEG_REG_W_ADDR_START_SHIFT)
/* 0x18 : jpeg_store_memory */
#define MJPEG_REG_W_BURST_CNT_SHIFT (0U)
#define MJPEG_REG_W_BURST_CNT_MASK (0xffffffff<<MJPEG_REG_W_BURST_CNT_SHIFT)
/* 0x1C : mjpeg_control_3 */
#define MJPEG_REG_INT_NORMAL_EN (1<<0U)
#define MJPEG_REG_INT_CAM_EN (1<<1U)
#define MJPEG_REG_INT_MEM_EN (1<<2U)
#define MJPEG_REG_INT_FRAME_EN (1<<3U)
#define MJPEG_STS_NORMAL_INT (1<<4U)
#define MJPEG_STS_CAM_INT (1<<5U)
#define MJPEG_STS_MEM_INT (1<<6U)
#define MJPEG_STS_FRAME_INT (1<<7U)
#define MJPEG_IDLE (1<<8U)
#define MJPEG_FUNC (1<<9U)
#define MJPEG_WAIT (1<<10U)
#define MJPEG_FLSH (1<<11U)
#define MJPEG_MANS (1<<12U)
#define MJPEG_MANF (1<<13U)
#define MJPEG_AXI_READ_IDLE (1<<14U)
#define MJPEG_AXI_WRITE_IDLE (1<<15U)
#define MJPEG_REG_FRAME_CNT_TRGR_INT_SHIFT (16U)
#define MJPEG_REG_FRAME_CNT_TRGR_INT_MASK (0x1f<<MJPEG_REG_FRAME_CNT_TRGR_INT_SHIFT)
#define MJPEG_REG_INT_IDLE_EN (1<<21U)
#define MJPEG_STS_IDLE_INT (1<<22U)
#define MJPEG_FRAME_VALID_CNT_SHIFT (24U)
#define MJPEG_FRAME_VALID_CNT_MASK (0x1f<<MJPEG_FRAME_VALID_CNT_SHIFT)
#define MJPEG_REG_INT_SWAP_EN (1<<29U)
#define MJPEG_STS_SWAP_INT (1<<30U)
/* 0x20 : mjpeg_frame_fifo_pop */
#define MJPEG_RFIFO_POP (1<<0U)
#define MJPEG_REG_W_SWAP_CLR (1<<1U)
#define MJPEG_REG_INT_NORMAL_CLR (1<<8U)
#define MJPEG_REG_INT_CAM_CLR (1<<9U)
#define MJPEG_REG_INT_MEM_CLR (1<<10U)
#define MJPEG_REG_INT_FRAME_CLR (1<<11U)
#define MJPEG_REG_INT_IDLE_CLR (1<<12U)
#define MJPEG_REG_INT_SWAP_CLR (1<<13U)
/* 0x24 : mjpeg_frame_size */
#define MJPEG_REG_FRAME_WBLK_SHIFT (0U)
#define MJPEG_REG_FRAME_WBLK_MASK (0xfff<<MJPEG_REG_FRAME_WBLK_SHIFT)
#define MJPEG_REG_FRAME_HBLK_SHIFT (16U)
#define MJPEG_REG_FRAME_HBLK_MASK (0xfff<<MJPEG_REG_FRAME_HBLK_SHIFT)
/* 0x28 : mjpeg_header_byte */
#define MJPEG_REG_HEAD_BYTE_SHIFT (0U)
#define MJPEG_REG_HEAD_BYTE_MASK (0xfff<<MJPEG_REG_HEAD_BYTE_SHIFT)
#define MJPEG_REG_TAIL_EXP (1<<16U)
#define MJPEG_REG_Y0_ORDER_SHIFT (24U)
#define MJPEG_REG_Y0_ORDER_MASK (0x3<<MJPEG_REG_Y0_ORDER_SHIFT)
#define MJPEG_REG_U0_ORDER_SHIFT (26U)
#define MJPEG_REG_U0_ORDER_MASK (0x3<<MJPEG_REG_U0_ORDER_SHIFT)
#define MJPEG_REG_Y1_ORDER_SHIFT (28U)
#define MJPEG_REG_Y1_ORDER_MASK (0x3<<MJPEG_REG_Y1_ORDER_SHIFT)
#define MJPEG_REG_V0_ORDER_SHIFT (30U)
#define MJPEG_REG_V0_ORDER_MASK (0x3<<MJPEG_REG_V0_ORDER_SHIFT)
/* 0x30 : mjpeg_swap_mode */
#define MJPEG_REG_W_SWAP_MODE (1<<0U)
#define MJPEG_STS_SWAP0_FULL (1<<8U)
#define MJPEG_STS_SWAP1_FULL (1<<9U)
#define MJPEG_STS_READ_SWAP_IDX (1<<10U)
#define MJPEG_STS_SWAP_FSTART (1<<11U)
#define MJPEG_STS_SWAP_FEND (1<<12U)
/* 0x34 : mjpeg_swap_bit_cnt */
#define MJPEG_FRAME_SWAP_END_BIT_CNT_SHIFT (0U)
#define MJPEG_FRAME_SWAP_END_BIT_CNT_MASK (0xffffffff<<MJPEG_FRAME_SWAP_END_BIT_CNT_SHIFT)
/* 0x38 : mjpeg_yuv_mem_sw */
#define MJPEG_REG_SW_KICK_HBLK_SHIFT (0U)
#define MJPEG_REG_SW_KICK_HBLK_MASK (0x1fff<<MJPEG_REG_SW_KICK_HBLK_SHIFT)
/* 0x40 : mjpeg_Y_frame_read_status_1 */
#define MJPEG_YY_MEM_HBLK_R_SHIFT (0U)
#define MJPEG_YY_MEM_HBLK_R_MASK (0x1fff<<MJPEG_YY_MEM_HBLK_R_SHIFT)
#define MJPEG_YY_FRM_HBLK_R_SHIFT (16U)
#define MJPEG_YY_FRM_HBLK_R_MASK (0x1fff<<MJPEG_YY_FRM_HBLK_R_SHIFT)
/* 0x44 : mjpeg_Y_frame_read_status_2 */
#define MJPEG_YY_WBLK_R_SHIFT (0U)
#define MJPEG_YY_WBLK_R_MASK (0x1fff<<MJPEG_YY_WBLK_R_SHIFT)
#define MJPEG_YY_MEM_RND_R_SHIFT (16U)
#define MJPEG_YY_MEM_RND_R_MASK (0xff<<MJPEG_YY_MEM_RND_R_SHIFT)
#define MJPEG_YY_FRM_CNT_R_SHIFT (24U)
#define MJPEG_YY_FRM_CNT_R_MASK (0xff<<MJPEG_YY_FRM_CNT_R_SHIFT)
/* 0x48 : mjpeg_Y_frame_write_status */
#define MJPEG_YY_MEM_HBLK_W_SHIFT (0U)
#define MJPEG_YY_MEM_HBLK_W_MASK (0x1fff<<MJPEG_YY_MEM_HBLK_W_SHIFT)
#define MJPEG_YY_MEM_RND_W_SHIFT (16U)
#define MJPEG_YY_MEM_RND_W_MASK (0xff<<MJPEG_YY_MEM_RND_W_SHIFT)
#define MJPEG_YY_FRM_CNT_W_SHIFT (24U)
#define MJPEG_YY_FRM_CNT_W_MASK (0xff<<MJPEG_YY_FRM_CNT_W_SHIFT)
/* 0x4C : mjpeg_UV_frame_read_status_1 */
#define MJPEG_UV_MEM_HBLK_R_SHIFT (0U)
#define MJPEG_UV_MEM_HBLK_R_MASK (0x1fff<<MJPEG_UV_MEM_HBLK_R_SHIFT)
#define MJPEG_UV_FRM_HBLK_R_SHIFT (16U)
#define MJPEG_UV_FRM_HBLK_R_MASK (0x1fff<<MJPEG_UV_FRM_HBLK_R_SHIFT)
/* 0x50 : mjpeg_UV_frame_read_status_2 */
#define MJPEG_UV_WBLK_R_SHIFT (0U)
#define MJPEG_UV_WBLK_R_MASK (0x1fff<<MJPEG_UV_WBLK_R_SHIFT)
#define MJPEG_UV_MEM_RND_R_SHIFT (16U)
#define MJPEG_UV_MEM_RND_R_MASK (0xff<<MJPEG_UV_MEM_RND_R_SHIFT)
#define MJPEG_UV_FRM_CNT_R_SHIFT (24U)
#define MJPEG_UV_FRM_CNT_R_MASK (0xff<<MJPEG_UV_FRM_CNT_R_SHIFT)
/* 0x54 : mjpeg_UV_frame_write_status */
#define MJPEG_UV_MEM_HBLK_W_SHIFT (0U)
#define MJPEG_UV_MEM_HBLK_W_MASK (0x1fff<<MJPEG_UV_MEM_HBLK_W_SHIFT)
#define MJPEG_UV_MEM_RND_W_SHIFT (16U)
#define MJPEG_UV_MEM_RND_W_MASK (0xff<<MJPEG_UV_MEM_RND_W_SHIFT)
#define MJPEG_UV_FRM_CNT_W_SHIFT (24U)
#define MJPEG_UV_FRM_CNT_W_MASK (0xff<<MJPEG_UV_FRM_CNT_W_SHIFT)
/* 0x58 : mjpeg_frame_w_hblk_status */
#define MJPEG_YY_FRM_HBLK_W_SHIFT (0U)
#define MJPEG_YY_FRM_HBLK_W_MASK (0x1fff<<MJPEG_YY_FRM_HBLK_W_SHIFT)
#define MJPEG_UV_FRM_HBLK_W_SHIFT (16U)
#define MJPEG_UV_FRM_HBLK_W_MASK (0x1fff<<MJPEG_UV_FRM_HBLK_W_SHIFT)
/* 0x80 : mjpeg_start_addr0 */
#define MJPEG_FRAME_START_ADDR_0_SHIFT (0U)
#define MJPEG_FRAME_START_ADDR_0_MASK (0xffffffff<<MJPEG_FRAME_START_ADDR_0_SHIFT)
/* 0x84 : mjpeg_bit_cnt0 */
#define MJPEG_FRAME_BIT_CNT_0_SHIFT (0U)
#define MJPEG_FRAME_BIT_CNT_0_MASK (0xffffffff<<MJPEG_FRAME_BIT_CNT_0_SHIFT)
/* 0x88 : mjpeg_start_addr1 */
#define MJPEG_FRAME_START_ADDR_1_SHIFT (0U)
#define MJPEG_FRAME_START_ADDR_1_MASK (0xffffffff<<MJPEG_FRAME_START_ADDR_1_SHIFT)
/* 0x8C : mjpeg_bit_cnt1 */
#define MJPEG_FRAME_BIT_CNT_1_SHIFT (0U)
#define MJPEG_FRAME_BIT_CNT_1_MASK (0xffffffff<<MJPEG_FRAME_BIT_CNT_1_SHIFT)
/* 0x90 : mjpeg_start_addr2 */
#define MJPEG_FRAME_START_ADDR_2_SHIFT (0U)
#define MJPEG_FRAME_START_ADDR_2_MASK (0xffffffff<<MJPEG_FRAME_START_ADDR_2_SHIFT)
/* 0x94 : mjpeg_bit_cnt2 */
#define MJPEG_FRAME_BIT_CNT_2_SHIFT (0U)
#define MJPEG_FRAME_BIT_CNT_2_MASK (0xffffffff<<MJPEG_FRAME_BIT_CNT_2_SHIFT)
/* 0x98 : mjpeg_start_addr3 */
#define MJPEG_FRAME_START_ADDR_3_SHIFT (0U)
#define MJPEG_FRAME_START_ADDR_3_MASK (0xffffffff<<MJPEG_FRAME_START_ADDR_3_SHIFT)
/* 0x9C : mjpeg_bit_cnt3 */
#define MJPEG_FRAME_BIT_CNT_3_SHIFT (0U)
#define MJPEG_FRAME_BIT_CNT_3_MASK (0xffffffff<<MJPEG_FRAME_BIT_CNT_3_SHIFT)
/* 0x100 : mjpeg_q_enc */
#define MJPEG_FRAME_Q_SRAM_0 (1<<0U)
#define MJPEG_FRAME_Q_SRAM_1 (1<<1U)
#define MJPEG_FRAME_Q_SRAM_2 (1<<2U)
#define MJPEG_FRAME_Q_SRAM_3 (1<<3U)
#define MJPEG_REG_Q_SRAM_SW (1<<24U)
#define MJPEG_STS_Q_SRAM_ENC (1<<25U)
/* 0x110 : mjpeg_frame_id_10 */
#define MJPEG_FRAME_ID_0_SHIFT (0U)
#define MJPEG_FRAME_ID_0_MASK (0xffff<<MJPEG_FRAME_ID_0_SHIFT)
#define MJPEG_FRAME_ID_1_SHIFT (16U)
#define MJPEG_FRAME_ID_1_MASK (0xffff<<MJPEG_FRAME_ID_1_SHIFT)
/* 0x114 : mjpeg_frame_id_32 */
#define MJPEG_FRAME_ID_2_SHIFT (0U)
#define MJPEG_FRAME_ID_2_MASK (0xffff<<MJPEG_FRAME_ID_2_SHIFT)
#define MJPEG_FRAME_ID_3_SHIFT (16U)
#define MJPEG_FRAME_ID_3_MASK (0xffff<<MJPEG_FRAME_ID_3_SHIFT)
/* 0x1F0 : mjpeg_debug */
#define MJPEG_REG_MJPEG_DBG_EN (1<<0U)
#define MJPEG_REG_MJPEG_DBG_SEL_SHIFT (4U)
#define MJPEG_REG_MJPEG_DBG_SEL_MASK (0xf<<MJPEG_REG_MJPEG_DBG_SEL_SHIFT)
#define MJPEG_REG_ID_LATCH_HBLK_SHIFT (8U)
#define MJPEG_REG_ID_LATCH_HBLK_MASK (0xf<<MJPEG_REG_ID_LATCH_HBLK_SHIFT)
/* 0x1FC : mjpeg_dummy_reg */
#define MJPEG_DUMMY_REG_SHIFT (0U)
#define MJPEG_DUMMY_REG_MASK (0xffffffff<<MJPEG_DUMMY_REG_SHIFT)
#endif /* __HARDWARE_MJPEG_REG_H__ */

724
include/bl808/mm_glb_reg.h Normal file
View File

@ -0,0 +1,724 @@
/**
******************************************************************************
* @file mm_glb_reg.h
* @version V1.0
* @date 2021-07-12
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __MM_GLB_REG_H__
#define __MM_GLB_REG_H__
#include <linux/types.h>
/* 0x0 : mm_clk_ctrl_cpu */
#define MM_GLB_MM_CLK_CTRL_CPU_OFFSET (0x0)
#define MM_GLB_REG_PLL_EN MM_GLB_REG_PLL_EN
#define MM_GLB_REG_PLL_EN_POS (0U)
#define MM_GLB_REG_PLL_EN_LEN (1U)
#define MM_GLB_REG_PLL_EN_MSK (((1U << MM_GLB_REG_PLL_EN_LEN) - 1) << MM_GLB_REG_PLL_EN_POS)
#define MM_GLB_REG_PLL_EN_UMSK (~(((1U << MM_GLB_REG_PLL_EN_LEN) - 1) << MM_GLB_REG_PLL_EN_POS))
#define MM_GLB_REG_CPU_CLK_EN MM_GLB_REG_CPU_CLK_EN
#define MM_GLB_REG_CPU_CLK_EN_POS (1U)
#define MM_GLB_REG_CPU_CLK_EN_LEN (1U)
#define MM_GLB_REG_CPU_CLK_EN_MSK (((1U << MM_GLB_REG_CPU_CLK_EN_LEN) - 1) << MM_GLB_REG_CPU_CLK_EN_POS)
#define MM_GLB_REG_CPU_CLK_EN_UMSK (~(((1U << MM_GLB_REG_CPU_CLK_EN_LEN) - 1) << MM_GLB_REG_CPU_CLK_EN_POS))
#define MM_GLB_REG_BCLK_EN MM_GLB_REG_BCLK_EN
#define MM_GLB_REG_BCLK_EN_POS (2U)
#define MM_GLB_REG_BCLK_EN_LEN (1U)
#define MM_GLB_REG_BCLK_EN_MSK (((1U << MM_GLB_REG_BCLK_EN_LEN) - 1) << MM_GLB_REG_BCLK_EN_POS)
#define MM_GLB_REG_BCLK_EN_UMSK (~(((1U << MM_GLB_REG_BCLK_EN_LEN) - 1) << MM_GLB_REG_BCLK_EN_POS))
#define MM_GLB_REG_MM_CPU_CLK_EN MM_GLB_REG_MM_CPU_CLK_EN
#define MM_GLB_REG_MM_CPU_CLK_EN_POS (3U)
#define MM_GLB_REG_MM_CPU_CLK_EN_LEN (1U)
#define MM_GLB_REG_MM_CPU_CLK_EN_MSK (((1U << MM_GLB_REG_MM_CPU_CLK_EN_LEN) - 1) << MM_GLB_REG_MM_CPU_CLK_EN_POS)
#define MM_GLB_REG_MM_CPU_CLK_EN_UMSK (~(((1U << MM_GLB_REG_MM_CPU_CLK_EN_LEN) - 1) << MM_GLB_REG_MM_CPU_CLK_EN_POS))
#define MM_GLB_REG_UART_CLK_SEL MM_GLB_REG_UART_CLK_SEL
#define MM_GLB_REG_UART_CLK_SEL_POS (4U)
#define MM_GLB_REG_UART_CLK_SEL_LEN (2U)
#define MM_GLB_REG_UART_CLK_SEL_MSK (((1U << MM_GLB_REG_UART_CLK_SEL_LEN) - 1) << MM_GLB_REG_UART_CLK_SEL_POS)
#define MM_GLB_REG_UART_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_UART_CLK_SEL_LEN) - 1) << MM_GLB_REG_UART_CLK_SEL_POS))
#define MM_GLB_REG_I2C_CLK_SEL MM_GLB_REG_I2C_CLK_SEL
#define MM_GLB_REG_I2C_CLK_SEL_POS (6U)
#define MM_GLB_REG_I2C_CLK_SEL_LEN (1U)
#define MM_GLB_REG_I2C_CLK_SEL_MSK (((1U << MM_GLB_REG_I2C_CLK_SEL_LEN) - 1) << MM_GLB_REG_I2C_CLK_SEL_POS)
#define MM_GLB_REG_I2C_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_I2C_CLK_SEL_LEN) - 1) << MM_GLB_REG_I2C_CLK_SEL_POS))
#define MM_GLB_REG_SPI_CLK_SEL MM_GLB_REG_SPI_CLK_SEL
#define MM_GLB_REG_SPI_CLK_SEL_POS (7U)
#define MM_GLB_REG_SPI_CLK_SEL_LEN (1U)
#define MM_GLB_REG_SPI_CLK_SEL_MSK (((1U << MM_GLB_REG_SPI_CLK_SEL_LEN) - 1) << MM_GLB_REG_SPI_CLK_SEL_POS)
#define MM_GLB_REG_SPI_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_SPI_CLK_SEL_LEN) - 1) << MM_GLB_REG_SPI_CLK_SEL_POS))
#define MM_GLB_REG_CPU_CLK_SEL MM_GLB_REG_CPU_CLK_SEL
#define MM_GLB_REG_CPU_CLK_SEL_POS (8U)
#define MM_GLB_REG_CPU_CLK_SEL_LEN (2U)
#define MM_GLB_REG_CPU_CLK_SEL_MSK (((1U << MM_GLB_REG_CPU_CLK_SEL_LEN) - 1) << MM_GLB_REG_CPU_CLK_SEL_POS)
#define MM_GLB_REG_CPU_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_CPU_CLK_SEL_LEN) - 1) << MM_GLB_REG_CPU_CLK_SEL_POS))
#define MM_GLB_REG_XCLK_CLK_SEL MM_GLB_REG_XCLK_CLK_SEL
#define MM_GLB_REG_XCLK_CLK_SEL_POS (10U)
#define MM_GLB_REG_XCLK_CLK_SEL_LEN (1U)
#define MM_GLB_REG_XCLK_CLK_SEL_MSK (((1U << MM_GLB_REG_XCLK_CLK_SEL_LEN) - 1) << MM_GLB_REG_XCLK_CLK_SEL_POS)
#define MM_GLB_REG_XCLK_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_XCLK_CLK_SEL_LEN) - 1) << MM_GLB_REG_XCLK_CLK_SEL_POS))
#define MM_GLB_REG_CPU_ROOT_CLK_SEL MM_GLB_REG_CPU_ROOT_CLK_SEL
#define MM_GLB_REG_CPU_ROOT_CLK_SEL_POS (11U)
#define MM_GLB_REG_CPU_ROOT_CLK_SEL_LEN (1U)
#define MM_GLB_REG_CPU_ROOT_CLK_SEL_MSK (((1U << MM_GLB_REG_CPU_ROOT_CLK_SEL_LEN) - 1) << MM_GLB_REG_CPU_ROOT_CLK_SEL_POS)
#define MM_GLB_REG_CPU_ROOT_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_CPU_ROOT_CLK_SEL_LEN) - 1) << MM_GLB_REG_CPU_ROOT_CLK_SEL_POS))
#define MM_GLB_REG_MMCPU0_CLK_EN MM_GLB_REG_MMCPU0_CLK_EN
#define MM_GLB_REG_MMCPU0_CLK_EN_POS (12U)
#define MM_GLB_REG_MMCPU0_CLK_EN_LEN (1U)
#define MM_GLB_REG_MMCPU0_CLK_EN_MSK (((1U << MM_GLB_REG_MMCPU0_CLK_EN_LEN) - 1) << MM_GLB_REG_MMCPU0_CLK_EN_POS)
#define MM_GLB_REG_MMCPU0_CLK_EN_UMSK (~(((1U << MM_GLB_REG_MMCPU0_CLK_EN_LEN) - 1) << MM_GLB_REG_MMCPU0_CLK_EN_POS))
#define MM_GLB_REG_BCLK1X_SEL MM_GLB_REG_BCLK1X_SEL
#define MM_GLB_REG_BCLK1X_SEL_POS (13U)
#define MM_GLB_REG_BCLK1X_SEL_LEN (2U)
#define MM_GLB_REG_BCLK1X_SEL_MSK (((1U << MM_GLB_REG_BCLK1X_SEL_LEN) - 1) << MM_GLB_REG_BCLK1X_SEL_POS)
#define MM_GLB_REG_BCLK1X_SEL_UMSK (~(((1U << MM_GLB_REG_BCLK1X_SEL_LEN) - 1) << MM_GLB_REG_BCLK1X_SEL_POS))
#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE MM_GLB_REG_BCLK2X_DIV_ACT_PULSE
#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_POS (18U)
#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_LEN (1U)
#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_MSK (((1U << MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_POS)
#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_UMSK (~(((1U << MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_POS))
#define MM_GLB_REG_BCLK2X_DIV_BYPASS MM_GLB_REG_BCLK2X_DIV_BYPASS
#define MM_GLB_REG_BCLK2X_DIV_BYPASS_POS (19U)
#define MM_GLB_REG_BCLK2X_DIV_BYPASS_LEN (1U)
#define MM_GLB_REG_BCLK2X_DIV_BYPASS_MSK (((1U << MM_GLB_REG_BCLK2X_DIV_BYPASS_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_BYPASS_POS)
#define MM_GLB_REG_BCLK2X_DIV_BYPASS_UMSK (~(((1U << MM_GLB_REG_BCLK2X_DIV_BYPASS_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_BYPASS_POS))
#define MM_GLB_STS_BCLK2X_PROT_DONE MM_GLB_STS_BCLK2X_PROT_DONE
#define MM_GLB_STS_BCLK2X_PROT_DONE_POS (20U)
#define MM_GLB_STS_BCLK2X_PROT_DONE_LEN (1U)
#define MM_GLB_STS_BCLK2X_PROT_DONE_MSK (((1U << MM_GLB_STS_BCLK2X_PROT_DONE_LEN) - 1) << MM_GLB_STS_BCLK2X_PROT_DONE_POS)
#define MM_GLB_STS_BCLK2X_PROT_DONE_UMSK (~(((1U << MM_GLB_STS_BCLK2X_PROT_DONE_LEN) - 1) << MM_GLB_STS_BCLK2X_PROT_DONE_POS))
#define MM_GLB_REG_BCLK2X_SW_DONE_CNT MM_GLB_REG_BCLK2X_SW_DONE_CNT
#define MM_GLB_REG_BCLK2X_SW_DONE_CNT_POS (24U)
#define MM_GLB_REG_BCLK2X_SW_DONE_CNT_LEN (4U)
#define MM_GLB_REG_BCLK2X_SW_DONE_CNT_MSK (((1U << MM_GLB_REG_BCLK2X_SW_DONE_CNT_LEN) - 1) << MM_GLB_REG_BCLK2X_SW_DONE_CNT_POS)
#define MM_GLB_REG_BCLK2X_SW_DONE_CNT_UMSK (~(((1U << MM_GLB_REG_BCLK2X_SW_DONE_CNT_LEN) - 1) << MM_GLB_REG_BCLK2X_SW_DONE_CNT_POS))
#define MM_GLB_CPU_CLK_SW_STATE MM_GLB_CPU_CLK_SW_STATE
#define MM_GLB_CPU_CLK_SW_STATE_POS (28U)
#define MM_GLB_CPU_CLK_SW_STATE_LEN (3U)
#define MM_GLB_CPU_CLK_SW_STATE_MSK (((1U << MM_GLB_CPU_CLK_SW_STATE_LEN) - 1) << MM_GLB_CPU_CLK_SW_STATE_POS)
#define MM_GLB_CPU_CLK_SW_STATE_UMSK (~(((1U << MM_GLB_CPU_CLK_SW_STATE_LEN) - 1) << MM_GLB_CPU_CLK_SW_STATE_POS))
/* 0x4 : mm_clk_cpu */
#define MM_GLB_MM_CLK_CPU_OFFSET (0x4)
#define MM_GLB_REG_CPU_CLK_DIV MM_GLB_REG_CPU_CLK_DIV
#define MM_GLB_REG_CPU_CLK_DIV_POS (0U)
#define MM_GLB_REG_CPU_CLK_DIV_LEN (8U)
#define MM_GLB_REG_CPU_CLK_DIV_MSK (((1U << MM_GLB_REG_CPU_CLK_DIV_LEN) - 1) << MM_GLB_REG_CPU_CLK_DIV_POS)
#define MM_GLB_REG_CPU_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_CPU_CLK_DIV_LEN) - 1) << MM_GLB_REG_CPU_CLK_DIV_POS))
#define MM_GLB_REG_CNN_CLK_DIV_EN MM_GLB_REG_CNN_CLK_DIV_EN
#define MM_GLB_REG_CNN_CLK_DIV_EN_POS (8U)
#define MM_GLB_REG_CNN_CLK_DIV_EN_LEN (1U)
#define MM_GLB_REG_CNN_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_CNN_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_CNN_CLK_DIV_EN_POS)
#define MM_GLB_REG_CNN_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_CNN_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_CNN_CLK_DIV_EN_POS))
#define MM_GLB_REG_CNN_CLK_SEL MM_GLB_REG_CNN_CLK_SEL
#define MM_GLB_REG_CNN_CLK_SEL_POS (9U)
#define MM_GLB_REG_CNN_CLK_SEL_LEN (2U)
#define MM_GLB_REG_CNN_CLK_SEL_MSK (((1U << MM_GLB_REG_CNN_CLK_SEL_LEN) - 1) << MM_GLB_REG_CNN_CLK_SEL_POS)
#define MM_GLB_REG_CNN_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_CNN_CLK_SEL_LEN) - 1) << MM_GLB_REG_CNN_CLK_SEL_POS))
#define MM_GLB_REG_CNN_CLK_DIV MM_GLB_REG_CNN_CLK_DIV
#define MM_GLB_REG_CNN_CLK_DIV_POS (12U)
#define MM_GLB_REG_CNN_CLK_DIV_LEN (3U)
#define MM_GLB_REG_CNN_CLK_DIV_MSK (((1U << MM_GLB_REG_CNN_CLK_DIV_LEN) - 1) << MM_GLB_REG_CNN_CLK_DIV_POS)
#define MM_GLB_REG_CNN_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_CNN_CLK_DIV_LEN) - 1) << MM_GLB_REG_CNN_CLK_DIV_POS))
#define MM_GLB_REG_BCLK2X_DIV MM_GLB_REG_BCLK2X_DIV
#define MM_GLB_REG_BCLK2X_DIV_POS (16U)
#define MM_GLB_REG_BCLK2X_DIV_LEN (8U)
#define MM_GLB_REG_BCLK2X_DIV_MSK (((1U << MM_GLB_REG_BCLK2X_DIV_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_POS)
#define MM_GLB_REG_BCLK2X_DIV_UMSK (~(((1U << MM_GLB_REG_BCLK2X_DIV_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_POS))
#define MM_GLB_REG_BCLK1X_DIV MM_GLB_REG_BCLK1X_DIV
#define MM_GLB_REG_BCLK1X_DIV_POS (24U)
#define MM_GLB_REG_BCLK1X_DIV_LEN (8U)
#define MM_GLB_REG_BCLK1X_DIV_MSK (((1U << MM_GLB_REG_BCLK1X_DIV_LEN) - 1) << MM_GLB_REG_BCLK1X_DIV_POS)
#define MM_GLB_REG_BCLK1X_DIV_UMSK (~(((1U << MM_GLB_REG_BCLK1X_DIV_LEN) - 1) << MM_GLB_REG_BCLK1X_DIV_POS))
/* 0x8 : dp_clk */
#define MM_GLB_DP_CLK_OFFSET (0x8)
#define MM_GLB_REG_CLK_DIV_EN MM_GLB_REG_CLK_DIV_EN
#define MM_GLB_REG_CLK_DIV_EN_POS (0U)
#define MM_GLB_REG_CLK_DIV_EN_LEN (1U)
#define MM_GLB_REG_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_CLK_DIV_EN_POS)
#define MM_GLB_REG_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_CLK_DIV_EN_POS))
#define MM_GLB_REG_CLK_SEL MM_GLB_REG_CLK_SEL
#define MM_GLB_REG_CLK_SEL_POS (1U)
#define MM_GLB_REG_CLK_SEL_LEN (2U)
#define MM_GLB_REG_CLK_SEL_MSK (((1U << MM_GLB_REG_CLK_SEL_LEN) - 1) << MM_GLB_REG_CLK_SEL_POS)
#define MM_GLB_REG_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_CLK_SEL_LEN) - 1) << MM_GLB_REG_CLK_SEL_POS))
#define MM_GLB_REG_CLK_DIV MM_GLB_REG_CLK_DIV
#define MM_GLB_REG_CLK_DIV_POS (8U)
#define MM_GLB_REG_CLK_DIV_LEN (8U)
#define MM_GLB_REG_CLK_DIV_MSK (((1U << MM_GLB_REG_CLK_DIV_LEN) - 1) << MM_GLB_REG_CLK_DIV_POS)
#define MM_GLB_REG_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_CLK_DIV_LEN) - 1) << MM_GLB_REG_CLK_DIV_POS))
#define MM_GLB_REG_DP_CLK_DIV_EN MM_GLB_REG_DP_CLK_DIV_EN
#define MM_GLB_REG_DP_CLK_DIV_EN_POS (16U)
#define MM_GLB_REG_DP_CLK_DIV_EN_LEN (1U)
#define MM_GLB_REG_DP_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_DP_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_DP_CLK_DIV_EN_POS)
#define MM_GLB_REG_DP_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_DP_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_DP_CLK_DIV_EN_POS))
#define MM_GLB_REG_DP_CLK_SEL MM_GLB_REG_DP_CLK_SEL
#define MM_GLB_REG_DP_CLK_SEL_POS (17U)
#define MM_GLB_REG_DP_CLK_SEL_LEN (1U)
#define MM_GLB_REG_DP_CLK_SEL_MSK (((1U << MM_GLB_REG_DP_CLK_SEL_LEN) - 1) << MM_GLB_REG_DP_CLK_SEL_POS)
#define MM_GLB_REG_DP_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_DP_CLK_SEL_LEN) - 1) << MM_GLB_REG_DP_CLK_SEL_POS))
#define MM_GLB_REG_DP_CLK_DIV MM_GLB_REG_DP_CLK_DIV
#define MM_GLB_REG_DP_CLK_DIV_POS (20U)
#define MM_GLB_REG_DP_CLK_DIV_LEN (4U)
#define MM_GLB_REG_DP_CLK_DIV_MSK (((1U << MM_GLB_REG_DP_CLK_DIV_LEN) - 1) << MM_GLB_REG_DP_CLK_DIV_POS)
#define MM_GLB_REG_DP_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_DP_CLK_DIV_LEN) - 1) << MM_GLB_REG_DP_CLK_DIV_POS))
/* 0xC : codec_clk */
#define MM_GLB_CODEC_CLK_OFFSET (0xC)
#define MM_GLB_REG_H264_CLK_DIV_EN MM_GLB_REG_H264_CLK_DIV_EN
#define MM_GLB_REG_H264_CLK_DIV_EN_POS (8U)
#define MM_GLB_REG_H264_CLK_DIV_EN_LEN (1U)
#define MM_GLB_REG_H264_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_H264_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_H264_CLK_DIV_EN_POS)
#define MM_GLB_REG_H264_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_H264_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_H264_CLK_DIV_EN_POS))
#define MM_GLB_REG_H264_CLK_SEL MM_GLB_REG_H264_CLK_SEL
#define MM_GLB_REG_H264_CLK_SEL_POS (9U)
#define MM_GLB_REG_H264_CLK_SEL_LEN (2U)
#define MM_GLB_REG_H264_CLK_SEL_MSK (((1U << MM_GLB_REG_H264_CLK_SEL_LEN) - 1) << MM_GLB_REG_H264_CLK_SEL_POS)
#define MM_GLB_REG_H264_CLK_SEL_UMSK (~(((1U << MM_GLB_REG_H264_CLK_SEL_LEN) - 1) << MM_GLB_REG_H264_CLK_SEL_POS))
#define MM_GLB_REG_H264_CLK_DIV MM_GLB_REG_H264_CLK_DIV
#define MM_GLB_REG_H264_CLK_DIV_POS (12U)
#define MM_GLB_REG_H264_CLK_DIV_LEN (3U)
#define MM_GLB_REG_H264_CLK_DIV_MSK (((1U << MM_GLB_REG_H264_CLK_DIV_LEN) - 1) << MM_GLB_REG_H264_CLK_DIV_POS)
#define MM_GLB_REG_H264_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_H264_CLK_DIV_LEN) - 1) << MM_GLB_REG_H264_CLK_DIV_POS))
/* 0x10 : mm_clk_ctrl_peri */
#define MM_GLB_MM_CLK_CTRL_PERI_OFFSET (0x10)
#define MM_GLB_REG_I2C0_CLK_DIV MM_GLB_REG_I2C0_CLK_DIV
#define MM_GLB_REG_I2C0_CLK_DIV_POS (0U)
#define MM_GLB_REG_I2C0_CLK_DIV_LEN (8U)
#define MM_GLB_REG_I2C0_CLK_DIV_MSK (((1U << MM_GLB_REG_I2C0_CLK_DIV_LEN) - 1) << MM_GLB_REG_I2C0_CLK_DIV_POS)
#define MM_GLB_REG_I2C0_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_I2C0_CLK_DIV_LEN) - 1) << MM_GLB_REG_I2C0_CLK_DIV_POS))
#define MM_GLB_REG_I2C0_CLK_DIV_EN MM_GLB_REG_I2C0_CLK_DIV_EN
#define MM_GLB_REG_I2C0_CLK_DIV_EN_POS (8U)
#define MM_GLB_REG_I2C0_CLK_DIV_EN_LEN (1U)
#define MM_GLB_REG_I2C0_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_I2C0_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_I2C0_CLK_DIV_EN_POS)
#define MM_GLB_REG_I2C0_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_I2C0_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_I2C0_CLK_DIV_EN_POS))
#define MM_GLB_REG_I2C0_CLK_EN MM_GLB_REG_I2C0_CLK_EN
#define MM_GLB_REG_I2C0_CLK_EN_POS (9U)
#define MM_GLB_REG_I2C0_CLK_EN_LEN (1U)
#define MM_GLB_REG_I2C0_CLK_EN_MSK (((1U << MM_GLB_REG_I2C0_CLK_EN_LEN) - 1) << MM_GLB_REG_I2C0_CLK_EN_POS)
#define MM_GLB_REG_I2C0_CLK_EN_UMSK (~(((1U << MM_GLB_REG_I2C0_CLK_EN_LEN) - 1) << MM_GLB_REG_I2C0_CLK_EN_POS))
#define MM_GLB_REG_UART0_CLK_DIV_EN MM_GLB_REG_UART0_CLK_DIV_EN
#define MM_GLB_REG_UART0_CLK_DIV_EN_POS (16U)
#define MM_GLB_REG_UART0_CLK_DIV_EN_LEN (1U)
#define MM_GLB_REG_UART0_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_UART0_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_UART0_CLK_DIV_EN_POS)
#define MM_GLB_REG_UART0_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_UART0_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_UART0_CLK_DIV_EN_POS))
#define MM_GLB_REG_UART0_CLK_DIV MM_GLB_REG_UART0_CLK_DIV
#define MM_GLB_REG_UART0_CLK_DIV_POS (17U)
#define MM_GLB_REG_UART0_CLK_DIV_LEN (3U)
#define MM_GLB_REG_UART0_CLK_DIV_MSK (((1U << MM_GLB_REG_UART0_CLK_DIV_LEN) - 1) << MM_GLB_REG_UART0_CLK_DIV_POS)
#define MM_GLB_REG_UART0_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_UART0_CLK_DIV_LEN) - 1) << MM_GLB_REG_UART0_CLK_DIV_POS))
#define MM_GLB_REG_SPI_CLK_DIV_EN MM_GLB_REG_SPI_CLK_DIV_EN
#define MM_GLB_REG_SPI_CLK_DIV_EN_POS (23U)
#define MM_GLB_REG_SPI_CLK_DIV_EN_LEN (1U)
#define MM_GLB_REG_SPI_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_SPI_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_SPI_CLK_DIV_EN_POS)
#define MM_GLB_REG_SPI_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_SPI_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_SPI_CLK_DIV_EN_POS))
#define MM_GLB_REG_SPI_CLK_DIV MM_GLB_REG_SPI_CLK_DIV
#define MM_GLB_REG_SPI_CLK_DIV_POS (24U)
#define MM_GLB_REG_SPI_CLK_DIV_LEN (8U)
#define MM_GLB_REG_SPI_CLK_DIV_MSK (((1U << MM_GLB_REG_SPI_CLK_DIV_LEN) - 1) << MM_GLB_REG_SPI_CLK_DIV_POS)
#define MM_GLB_REG_SPI_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_SPI_CLK_DIV_LEN) - 1) << MM_GLB_REG_SPI_CLK_DIV_POS))
/* 0x18 : mm_clk_ctrl_peri3 */
#define MM_GLB_MM_CLK_CTRL_PERI3_OFFSET (0x18)
#define MM_GLB_REG_I2C1_CLK_DIV MM_GLB_REG_I2C1_CLK_DIV
#define MM_GLB_REG_I2C1_CLK_DIV_POS (0U)
#define MM_GLB_REG_I2C1_CLK_DIV_LEN (8U)
#define MM_GLB_REG_I2C1_CLK_DIV_MSK (((1U << MM_GLB_REG_I2C1_CLK_DIV_LEN) - 1) << MM_GLB_REG_I2C1_CLK_DIV_POS)
#define MM_GLB_REG_I2C1_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_I2C1_CLK_DIV_LEN) - 1) << MM_GLB_REG_I2C1_CLK_DIV_POS))
#define MM_GLB_REG_I2C1_CLK_DIV_EN MM_GLB_REG_I2C1_CLK_DIV_EN
#define MM_GLB_REG_I2C1_CLK_DIV_EN_POS (8U)
#define MM_GLB_REG_I2C1_CLK_DIV_EN_LEN (1U)
#define MM_GLB_REG_I2C1_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_I2C1_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_I2C1_CLK_DIV_EN_POS)
#define MM_GLB_REG_I2C1_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_I2C1_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_I2C1_CLK_DIV_EN_POS))
#define MM_GLB_REG_I2C1_CLK_EN MM_GLB_REG_I2C1_CLK_EN
#define MM_GLB_REG_I2C1_CLK_EN_POS (9U)
#define MM_GLB_REG_I2C1_CLK_EN_LEN (1U)
#define MM_GLB_REG_I2C1_CLK_EN_MSK (((1U << MM_GLB_REG_I2C1_CLK_EN_LEN) - 1) << MM_GLB_REG_I2C1_CLK_EN_POS)
#define MM_GLB_REG_I2C1_CLK_EN_UMSK (~(((1U << MM_GLB_REG_I2C1_CLK_EN_LEN) - 1) << MM_GLB_REG_I2C1_CLK_EN_POS))
#define MM_GLB_REG_UART1_CLK_DIV_EN MM_GLB_REG_UART1_CLK_DIV_EN
#define MM_GLB_REG_UART1_CLK_DIV_EN_POS (16U)
#define MM_GLB_REG_UART1_CLK_DIV_EN_LEN (1U)
#define MM_GLB_REG_UART1_CLK_DIV_EN_MSK (((1U << MM_GLB_REG_UART1_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_UART1_CLK_DIV_EN_POS)
#define MM_GLB_REG_UART1_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_UART1_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_UART1_CLK_DIV_EN_POS))
#define MM_GLB_REG_UART1_CLK_DIV MM_GLB_REG_UART1_CLK_DIV
#define MM_GLB_REG_UART1_CLK_DIV_POS (17U)
#define MM_GLB_REG_UART1_CLK_DIV_LEN (3U)
#define MM_GLB_REG_UART1_CLK_DIV_MSK (((1U << MM_GLB_REG_UART1_CLK_DIV_LEN) - 1) << MM_GLB_REG_UART1_CLK_DIV_POS)
#define MM_GLB_REG_UART1_CLK_DIV_UMSK (~(((1U << MM_GLB_REG_UART1_CLK_DIV_LEN) - 1) << MM_GLB_REG_UART1_CLK_DIV_POS))
/* 0x40 : mm_sw_sys_reset */
#define MM_GLB_MM_SW_SYS_RESET_OFFSET (0x40)
#define MM_GLB_REG_CTRL_SYS_RESET MM_GLB_REG_CTRL_SYS_RESET
#define MM_GLB_REG_CTRL_SYS_RESET_POS (0U)
#define MM_GLB_REG_CTRL_SYS_RESET_LEN (1U)
#define MM_GLB_REG_CTRL_SYS_RESET_MSK (((1U << MM_GLB_REG_CTRL_SYS_RESET_LEN) - 1) << MM_GLB_REG_CTRL_SYS_RESET_POS)
#define MM_GLB_REG_CTRL_SYS_RESET_UMSK (~(((1U << MM_GLB_REG_CTRL_SYS_RESET_LEN) - 1) << MM_GLB_REG_CTRL_SYS_RESET_POS))
#define MM_GLB_REG_CTRL_PWRON_RST MM_GLB_REG_CTRL_PWRON_RST
#define MM_GLB_REG_CTRL_PWRON_RST_POS (2U)
#define MM_GLB_REG_CTRL_PWRON_RST_LEN (1U)
#define MM_GLB_REG_CTRL_PWRON_RST_MSK (((1U << MM_GLB_REG_CTRL_PWRON_RST_LEN) - 1) << MM_GLB_REG_CTRL_PWRON_RST_POS)
#define MM_GLB_REG_CTRL_PWRON_RST_UMSK (~(((1U << MM_GLB_REG_CTRL_PWRON_RST_LEN) - 1) << MM_GLB_REG_CTRL_PWRON_RST_POS))
#define MM_GLB_REG_CTRL_MMCPU0_RESET MM_GLB_REG_CTRL_MMCPU0_RESET
#define MM_GLB_REG_CTRL_MMCPU0_RESET_POS (8U)
#define MM_GLB_REG_CTRL_MMCPU0_RESET_LEN (1U)
#define MM_GLB_REG_CTRL_MMCPU0_RESET_MSK (((1U << MM_GLB_REG_CTRL_MMCPU0_RESET_LEN) - 1) << MM_GLB_REG_CTRL_MMCPU0_RESET_POS)
#define MM_GLB_REG_CTRL_MMCPU0_RESET_UMSK (~(((1U << MM_GLB_REG_CTRL_MMCPU0_RESET_LEN) - 1) << MM_GLB_REG_CTRL_MMCPU0_RESET_POS))
/* 0x44 : sw_reset_mm_peri */
#define MM_GLB_SW_RESET_MM_PERI_OFFSET (0x44)
#define MM_GLB_SWRST_MM_MISC MM_GLB_SWRST_MM_MISC
#define MM_GLB_SWRST_MM_MISC_POS (0U)
#define MM_GLB_SWRST_MM_MISC_LEN (1U)
#define MM_GLB_SWRST_MM_MISC_MSK (((1U << MM_GLB_SWRST_MM_MISC_LEN) - 1) << MM_GLB_SWRST_MM_MISC_POS)
#define MM_GLB_SWRST_MM_MISC_UMSK (~(((1U << MM_GLB_SWRST_MM_MISC_LEN) - 1) << MM_GLB_SWRST_MM_MISC_POS))
#define MM_GLB_SWRST_DMA MM_GLB_SWRST_DMA
#define MM_GLB_SWRST_DMA_POS (1U)
#define MM_GLB_SWRST_DMA_LEN (1U)
#define MM_GLB_SWRST_DMA_MSK (((1U << MM_GLB_SWRST_DMA_LEN) - 1) << MM_GLB_SWRST_DMA_POS)
#define MM_GLB_SWRST_DMA_UMSK (~(((1U << MM_GLB_SWRST_DMA_LEN) - 1) << MM_GLB_SWRST_DMA_POS))
#define MM_GLB_SWRST_UART0 MM_GLB_SWRST_UART0
#define MM_GLB_SWRST_UART0_POS (2U)
#define MM_GLB_SWRST_UART0_LEN (1U)
#define MM_GLB_SWRST_UART0_MSK (((1U << MM_GLB_SWRST_UART0_LEN) - 1) << MM_GLB_SWRST_UART0_POS)
#define MM_GLB_SWRST_UART0_UMSK (~(((1U << MM_GLB_SWRST_UART0_LEN) - 1) << MM_GLB_SWRST_UART0_POS))
#define MM_GLB_SWRST_I2C0 MM_GLB_SWRST_I2C0
#define MM_GLB_SWRST_I2C0_POS (3U)
#define MM_GLB_SWRST_I2C0_LEN (1U)
#define MM_GLB_SWRST_I2C0_MSK (((1U << MM_GLB_SWRST_I2C0_LEN) - 1) << MM_GLB_SWRST_I2C0_POS)
#define MM_GLB_SWRST_I2C0_UMSK (~(((1U << MM_GLB_SWRST_I2C0_LEN) - 1) << MM_GLB_SWRST_I2C0_POS))
#define MM_GLB_SWRST_I2C1 MM_GLB_SWRST_I2C1
#define MM_GLB_SWRST_I2C1_POS (4U)
#define MM_GLB_SWRST_I2C1_LEN (1U)
#define MM_GLB_SWRST_I2C1_MSK (((1U << MM_GLB_SWRST_I2C1_LEN) - 1) << MM_GLB_SWRST_I2C1_POS)
#define MM_GLB_SWRST_I2C1_UMSK (~(((1U << MM_GLB_SWRST_I2C1_LEN) - 1) << MM_GLB_SWRST_I2C1_POS))
#define MM_GLB_SWRST_IPC MM_GLB_SWRST_IPC
#define MM_GLB_SWRST_IPC_POS (5U)
#define MM_GLB_SWRST_IPC_LEN (1U)
#define MM_GLB_SWRST_IPC_MSK (((1U << MM_GLB_SWRST_IPC_LEN) - 1) << MM_GLB_SWRST_IPC_POS)
#define MM_GLB_SWRST_IPC_UMSK (~(((1U << MM_GLB_SWRST_IPC_LEN) - 1) << MM_GLB_SWRST_IPC_POS))
#define MM_GLB_SWRST_DMA2D MM_GLB_SWRST_DMA2D
#define MM_GLB_SWRST_DMA2D_POS (6U)
#define MM_GLB_SWRST_DMA2D_LEN (1U)
#define MM_GLB_SWRST_DMA2D_MSK (((1U << MM_GLB_SWRST_DMA2D_LEN) - 1) << MM_GLB_SWRST_DMA2D_POS)
#define MM_GLB_SWRST_DMA2D_UMSK (~(((1U << MM_GLB_SWRST_DMA2D_LEN) - 1) << MM_GLB_SWRST_DMA2D_POS))
#define MM_GLB_SWRST_SPI MM_GLB_SWRST_SPI
#define MM_GLB_SWRST_SPI_POS (8U)
#define MM_GLB_SWRST_SPI_LEN (1U)
#define MM_GLB_SWRST_SPI_MSK (((1U << MM_GLB_SWRST_SPI_LEN) - 1) << MM_GLB_SWRST_SPI_POS)
#define MM_GLB_SWRST_SPI_UMSK (~(((1U << MM_GLB_SWRST_SPI_LEN) - 1) << MM_GLB_SWRST_SPI_POS))
#define MM_GLB_SWRST_TIMER MM_GLB_SWRST_TIMER
#define MM_GLB_SWRST_TIMER_POS (9U)
#define MM_GLB_SWRST_TIMER_LEN (1U)
#define MM_GLB_SWRST_TIMER_MSK (((1U << MM_GLB_SWRST_TIMER_LEN) - 1) << MM_GLB_SWRST_TIMER_POS)
#define MM_GLB_SWRST_TIMER_UMSK (~(((1U << MM_GLB_SWRST_TIMER_LEN) - 1) << MM_GLB_SWRST_TIMER_POS))
#define MM_GLB_SWRST_I2S0 MM_GLB_SWRST_I2S0
#define MM_GLB_SWRST_I2S0_POS (10U)
#define MM_GLB_SWRST_I2S0_LEN (1U)
#define MM_GLB_SWRST_I2S0_MSK (((1U << MM_GLB_SWRST_I2S0_LEN) - 1) << MM_GLB_SWRST_I2S0_POS)
#define MM_GLB_SWRST_I2S0_UMSK (~(((1U << MM_GLB_SWRST_I2S0_LEN) - 1) << MM_GLB_SWRST_I2S0_POS))
#define MM_GLB_SWRST_I2S1 MM_GLB_SWRST_I2S1
#define MM_GLB_SWRST_I2S1_POS (11U)
#define MM_GLB_SWRST_I2S1_LEN (1U)
#define MM_GLB_SWRST_I2S1_MSK (((1U << MM_GLB_SWRST_I2S1_LEN) - 1) << MM_GLB_SWRST_I2S1_POS)
#define MM_GLB_SWRST_I2S1_UMSK (~(((1U << MM_GLB_SWRST_I2S1_LEN) - 1) << MM_GLB_SWRST_I2S1_POS))
#define MM_GLB_SWRST_PDM0 MM_GLB_SWRST_PDM0
#define MM_GLB_SWRST_PDM0_POS (12U)
#define MM_GLB_SWRST_PDM0_LEN (1U)
#define MM_GLB_SWRST_PDM0_MSK (((1U << MM_GLB_SWRST_PDM0_LEN) - 1) << MM_GLB_SWRST_PDM0_POS)
#define MM_GLB_SWRST_PDM0_UMSK (~(((1U << MM_GLB_SWRST_PDM0_LEN) - 1) << MM_GLB_SWRST_PDM0_POS))
#define MM_GLB_SWRST_PDM1 MM_GLB_SWRST_PDM1
#define MM_GLB_SWRST_PDM1_POS (13U)
#define MM_GLB_SWRST_PDM1_LEN (1U)
#define MM_GLB_SWRST_PDM1_MSK (((1U << MM_GLB_SWRST_PDM1_LEN) - 1) << MM_GLB_SWRST_PDM1_POS)
#define MM_GLB_SWRST_PDM1_UMSK (~(((1U << MM_GLB_SWRST_PDM1_LEN) - 1) << MM_GLB_SWRST_PDM1_POS))
#define MM_GLB_SWRST_UART1 MM_GLB_SWRST_UART1
#define MM_GLB_SWRST_UART1_POS (14U)
#define MM_GLB_SWRST_UART1_LEN (1U)
#define MM_GLB_SWRST_UART1_MSK (((1U << MM_GLB_SWRST_UART1_LEN) - 1) << MM_GLB_SWRST_UART1_POS)
#define MM_GLB_SWRST_UART1_UMSK (~(((1U << MM_GLB_SWRST_UART1_LEN) - 1) << MM_GLB_SWRST_UART1_POS))
#define MM_GLB_SWRST_PUHS MM_GLB_SWRST_PUHS
#define MM_GLB_SWRST_PUHS_POS (15U)
#define MM_GLB_SWRST_PUHS_LEN (1U)
#define MM_GLB_SWRST_PUHS_MSK (((1U << MM_GLB_SWRST_PUHS_LEN) - 1) << MM_GLB_SWRST_PUHS_POS)
#define MM_GLB_SWRST_PUHS_UMSK (~(((1U << MM_GLB_SWRST_PUHS_LEN) - 1) << MM_GLB_SWRST_PUHS_POS))
/* 0x48 : sw_reset_sub */
#define MM_GLB_SW_RESET_SUB_OFFSET (0x48)
#define MM_GLB_SWRST_MISC MM_GLB_SWRST_MISC
#define MM_GLB_SWRST_MISC_POS (0U)
#define MM_GLB_SWRST_MISC_LEN (1U)
#define MM_GLB_SWRST_MISC_MSK (((1U << MM_GLB_SWRST_MISC_LEN) - 1) << MM_GLB_SWRST_MISC_POS)
#define MM_GLB_SWRST_MISC_UMSK (~(((1U << MM_GLB_SWRST_MISC_LEN) - 1) << MM_GLB_SWRST_MISC_POS))
#define MM_GLB_SWRST_MAIN MM_GLB_SWRST_MAIN
#define MM_GLB_SWRST_MAIN_POS (1U)
#define MM_GLB_SWRST_MAIN_LEN (1U)
#define MM_GLB_SWRST_MAIN_MSK (((1U << MM_GLB_SWRST_MAIN_LEN) - 1) << MM_GLB_SWRST_MAIN_POS)
#define MM_GLB_SWRST_MAIN_UMSK (~(((1U << MM_GLB_SWRST_MAIN_LEN) - 1) << MM_GLB_SWRST_MAIN_POS))
#define MM_GLB_SWRST_TSRC MM_GLB_SWRST_TSRC
#define MM_GLB_SWRST_TSRC_POS (2U)
#define MM_GLB_SWRST_TSRC_LEN (1U)
#define MM_GLB_SWRST_TSRC_MSK (((1U << MM_GLB_SWRST_TSRC_LEN) - 1) << MM_GLB_SWRST_TSRC_POS)
#define MM_GLB_SWRST_TSRC_UMSK (~(((1U << MM_GLB_SWRST_TSRC_LEN) - 1) << MM_GLB_SWRST_TSRC_POS))
#define MM_GLB_SWRST_DP_TSRC MM_GLB_SWRST_DP_TSRC
#define MM_GLB_SWRST_DP_TSRC_POS (3U)
#define MM_GLB_SWRST_DP_TSRC_LEN (1U)
#define MM_GLB_SWRST_DP_TSRC_MSK (((1U << MM_GLB_SWRST_DP_TSRC_LEN) - 1) << MM_GLB_SWRST_DP_TSRC_POS)
#define MM_GLB_SWRST_DP_TSRC_UMSK (~(((1U << MM_GLB_SWRST_DP_TSRC_LEN) - 1) << MM_GLB_SWRST_DP_TSRC_POS))
#define MM_GLB_SWRST_NR3D_CTRL MM_GLB_SWRST_NR3D_CTRL
#define MM_GLB_SWRST_NR3D_CTRL_POS (4U)
#define MM_GLB_SWRST_NR3D_CTRL_LEN (1U)
#define MM_GLB_SWRST_NR3D_CTRL_MSK (((1U << MM_GLB_SWRST_NR3D_CTRL_LEN) - 1) << MM_GLB_SWRST_NR3D_CTRL_POS)
#define MM_GLB_SWRST_NR3D_CTRL_UMSK (~(((1U << MM_GLB_SWRST_NR3D_CTRL_LEN) - 1) << MM_GLB_SWRST_NR3D_CTRL_POS))
#define MM_GLB_SWRST_DVP2BUSA MM_GLB_SWRST_DVP2BUSA
#define MM_GLB_SWRST_DVP2BUSA_POS (5U)
#define MM_GLB_SWRST_DVP2BUSA_LEN (1U)
#define MM_GLB_SWRST_DVP2BUSA_MSK (((1U << MM_GLB_SWRST_DVP2BUSA_LEN) - 1) << MM_GLB_SWRST_DVP2BUSA_POS)
#define MM_GLB_SWRST_DVP2BUSA_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSA_LEN) - 1) << MM_GLB_SWRST_DVP2BUSA_POS))
#define MM_GLB_SWRST_DVP2BUSB MM_GLB_SWRST_DVP2BUSB
#define MM_GLB_SWRST_DVP2BUSB_POS (6U)
#define MM_GLB_SWRST_DVP2BUSB_LEN (1U)
#define MM_GLB_SWRST_DVP2BUSB_MSK (((1U << MM_GLB_SWRST_DVP2BUSB_LEN) - 1) << MM_GLB_SWRST_DVP2BUSB_POS)
#define MM_GLB_SWRST_DVP2BUSB_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSB_LEN) - 1) << MM_GLB_SWRST_DVP2BUSB_POS))
#define MM_GLB_SWRST_DVP2BUSC MM_GLB_SWRST_DVP2BUSC
#define MM_GLB_SWRST_DVP2BUSC_POS (7U)
#define MM_GLB_SWRST_DVP2BUSC_LEN (1U)
#define MM_GLB_SWRST_DVP2BUSC_MSK (((1U << MM_GLB_SWRST_DVP2BUSC_LEN) - 1) << MM_GLB_SWRST_DVP2BUSC_POS)
#define MM_GLB_SWRST_DVP2BUSC_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSC_LEN) - 1) << MM_GLB_SWRST_DVP2BUSC_POS))
#define MM_GLB_SWRST_DVP2BUSD MM_GLB_SWRST_DVP2BUSD
#define MM_GLB_SWRST_DVP2BUSD_POS (8U)
#define MM_GLB_SWRST_DVP2BUSD_LEN (1U)
#define MM_GLB_SWRST_DVP2BUSD_MSK (((1U << MM_GLB_SWRST_DVP2BUSD_LEN) - 1) << MM_GLB_SWRST_DVP2BUSD_POS)
#define MM_GLB_SWRST_DVP2BUSD_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSD_LEN) - 1) << MM_GLB_SWRST_DVP2BUSD_POS))
#define MM_GLB_SWRST_MIPI MM_GLB_SWRST_MIPI
#define MM_GLB_SWRST_MIPI_POS (9U)
#define MM_GLB_SWRST_MIPI_LEN (1U)
#define MM_GLB_SWRST_MIPI_MSK (((1U << MM_GLB_SWRST_MIPI_LEN) - 1) << MM_GLB_SWRST_MIPI_POS)
#define MM_GLB_SWRST_MIPI_UMSK (~(((1U << MM_GLB_SWRST_MIPI_LEN) - 1) << MM_GLB_SWRST_MIPI_POS))
#define MM_GLB_SWRST_DVP2BUSE MM_GLB_SWRST_DVP2BUSE
#define MM_GLB_SWRST_DVP2BUSE_POS (17U)
#define MM_GLB_SWRST_DVP2BUSE_LEN (1U)
#define MM_GLB_SWRST_DVP2BUSE_MSK (((1U << MM_GLB_SWRST_DVP2BUSE_LEN) - 1) << MM_GLB_SWRST_DVP2BUSE_POS)
#define MM_GLB_SWRST_DVP2BUSE_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSE_LEN) - 1) << MM_GLB_SWRST_DVP2BUSE_POS))
#define MM_GLB_SWRST_DVP2BUSF MM_GLB_SWRST_DVP2BUSF
#define MM_GLB_SWRST_DVP2BUSF_POS (18U)
#define MM_GLB_SWRST_DVP2BUSF_LEN (1U)
#define MM_GLB_SWRST_DVP2BUSF_MSK (((1U << MM_GLB_SWRST_DVP2BUSF_LEN) - 1) << MM_GLB_SWRST_DVP2BUSF_POS)
#define MM_GLB_SWRST_DVP2BUSF_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSF_LEN) - 1) << MM_GLB_SWRST_DVP2BUSF_POS))
#define MM_GLB_SWRST_DVP2BUSG MM_GLB_SWRST_DVP2BUSG
#define MM_GLB_SWRST_DVP2BUSG_POS (19U)
#define MM_GLB_SWRST_DVP2BUSG_LEN (1U)
#define MM_GLB_SWRST_DVP2BUSG_MSK (((1U << MM_GLB_SWRST_DVP2BUSG_LEN) - 1) << MM_GLB_SWRST_DVP2BUSG_POS)
#define MM_GLB_SWRST_DVP2BUSG_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSG_LEN) - 1) << MM_GLB_SWRST_DVP2BUSG_POS))
#define MM_GLB_SWRST_DVP2BUSH MM_GLB_SWRST_DVP2BUSH
#define MM_GLB_SWRST_DVP2BUSH_POS (20U)
#define MM_GLB_SWRST_DVP2BUSH_LEN (1U)
#define MM_GLB_SWRST_DVP2BUSH_MSK (((1U << MM_GLB_SWRST_DVP2BUSH_LEN) - 1) << MM_GLB_SWRST_DVP2BUSH_POS)
#define MM_GLB_SWRST_DVP2BUSH_UMSK (~(((1U << MM_GLB_SWRST_DVP2BUSH_LEN) - 1) << MM_GLB_SWRST_DVP2BUSH_POS))
/* 0x4C : sw_reset_codec_sub */
#define MM_GLB_SW_RESET_CODEC_SUB_OFFSET (0x4C)
#define MM_GLB_SWRST_CODEC_MISC MM_GLB_SWRST_CODEC_MISC
#define MM_GLB_SWRST_CODEC_MISC_POS (0U)
#define MM_GLB_SWRST_CODEC_MISC_LEN (1U)
#define MM_GLB_SWRST_CODEC_MISC_MSK (((1U << MM_GLB_SWRST_CODEC_MISC_LEN) - 1) << MM_GLB_SWRST_CODEC_MISC_POS)
#define MM_GLB_SWRST_CODEC_MISC_UMSK (~(((1U << MM_GLB_SWRST_CODEC_MISC_LEN) - 1) << MM_GLB_SWRST_CODEC_MISC_POS))
#define MM_GLB_SWRST_MJPEG MM_GLB_SWRST_MJPEG
#define MM_GLB_SWRST_MJPEG_POS (1U)
#define MM_GLB_SWRST_MJPEG_LEN (1U)
#define MM_GLB_SWRST_MJPEG_MSK (((1U << MM_GLB_SWRST_MJPEG_LEN) - 1) << MM_GLB_SWRST_MJPEG_POS)
#define MM_GLB_SWRST_MJPEG_UMSK (~(((1U << MM_GLB_SWRST_MJPEG_LEN) - 1) << MM_GLB_SWRST_MJPEG_POS))
#define MM_GLB_SWRST_H264 MM_GLB_SWRST_H264
#define MM_GLB_SWRST_H264_POS (2U)
#define MM_GLB_SWRST_H264_LEN (1U)
#define MM_GLB_SWRST_H264_MSK (((1U << MM_GLB_SWRST_H264_LEN) - 1) << MM_GLB_SWRST_H264_POS)
#define MM_GLB_SWRST_H264_UMSK (~(((1U << MM_GLB_SWRST_H264_LEN) - 1) << MM_GLB_SWRST_H264_POS))
#define MM_GLB_SWRST_MJPEG_DEC MM_GLB_SWRST_MJPEG_DEC
#define MM_GLB_SWRST_MJPEG_DEC_POS (3U)
#define MM_GLB_SWRST_MJPEG_DEC_LEN (1U)
#define MM_GLB_SWRST_MJPEG_DEC_MSK (((1U << MM_GLB_SWRST_MJPEG_DEC_LEN) - 1) << MM_GLB_SWRST_MJPEG_DEC_POS)
#define MM_GLB_SWRST_MJPEG_DEC_UMSK (~(((1U << MM_GLB_SWRST_MJPEG_DEC_LEN) - 1) << MM_GLB_SWRST_MJPEG_DEC_POS))
#define MM_GLB_SWRST_CNN MM_GLB_SWRST_CNN
#define MM_GLB_SWRST_CNN_POS (4U)
#define MM_GLB_SWRST_CNN_LEN (1U)
#define MM_GLB_SWRST_CNN_MSK (((1U << MM_GLB_SWRST_CNN_LEN) - 1) << MM_GLB_SWRST_CNN_POS)
#define MM_GLB_SWRST_CNN_UMSK (~(((1U << MM_GLB_SWRST_CNN_LEN) - 1) << MM_GLB_SWRST_CNN_POS))
#define MM_GLB_SWRST_VRAM MM_GLB_SWRST_VRAM
#define MM_GLB_SWRST_VRAM_POS (16U)
#define MM_GLB_SWRST_VRAM_LEN (1U)
#define MM_GLB_SWRST_VRAM_MSK (((1U << MM_GLB_SWRST_VRAM_LEN) - 1) << MM_GLB_SWRST_VRAM_POS)
#define MM_GLB_SWRST_VRAM_UMSK (~(((1U << MM_GLB_SWRST_VRAM_LEN) - 1) << MM_GLB_SWRST_VRAM_POS))
/* 0x50 : image_sensor_ctrl */
#define MM_GLB_IMAGE_SENSOR_CTRL_OFFSET (0x50)
#define MM_GLB_RG_IS_RST_N MM_GLB_RG_IS_RST_N
#define MM_GLB_RG_IS_RST_N_POS (0U)
#define MM_GLB_RG_IS_RST_N_LEN (1U)
#define MM_GLB_RG_IS_RST_N_MSK (((1U << MM_GLB_RG_IS_RST_N_LEN) - 1) << MM_GLB_RG_IS_RST_N_POS)
#define MM_GLB_RG_IS_RST_N_UMSK (~(((1U << MM_GLB_RG_IS_RST_N_LEN) - 1) << MM_GLB_RG_IS_RST_N_POS))
/* 0x60 : tz_mm_clkrst */
#define MM_GLB_TZ_MM_CLKRST_OFFSET (0x60)
#define MM_GLB_TZC_MM_SWRST_LOCK MM_GLB_TZC_MM_SWRST_LOCK
#define MM_GLB_TZC_MM_SWRST_LOCK_POS (0U)
#define MM_GLB_TZC_MM_SWRST_LOCK_LEN (1U)
#define MM_GLB_TZC_MM_SWRST_LOCK_MSK (((1U << MM_GLB_TZC_MM_SWRST_LOCK_LEN) - 1) << MM_GLB_TZC_MM_SWRST_LOCK_POS)
#define MM_GLB_TZC_MM_SWRST_LOCK_UMSK (~(((1U << MM_GLB_TZC_MM_SWRST_LOCK_LEN) - 1) << MM_GLB_TZC_MM_SWRST_LOCK_POS))
#define MM_GLB_TZC_MM_SYS_RESET_LOCK MM_GLB_TZC_MM_SYS_RESET_LOCK
#define MM_GLB_TZC_MM_SYS_RESET_LOCK_POS (1U)
#define MM_GLB_TZC_MM_SYS_RESET_LOCK_LEN (1U)
#define MM_GLB_TZC_MM_SYS_RESET_LOCK_MSK (((1U << MM_GLB_TZC_MM_SYS_RESET_LOCK_LEN) - 1) << MM_GLB_TZC_MM_SYS_RESET_LOCK_POS)
#define MM_GLB_TZC_MM_SYS_RESET_LOCK_UMSK (~(((1U << MM_GLB_TZC_MM_SYS_RESET_LOCK_LEN) - 1) << MM_GLB_TZC_MM_SYS_RESET_LOCK_POS))
#define MM_GLB_TZC_MM_PWRON_RST_LOCK MM_GLB_TZC_MM_PWRON_RST_LOCK
#define MM_GLB_TZC_MM_PWRON_RST_LOCK_POS (2U)
#define MM_GLB_TZC_MM_PWRON_RST_LOCK_LEN (1U)
#define MM_GLB_TZC_MM_PWRON_RST_LOCK_MSK (((1U << MM_GLB_TZC_MM_PWRON_RST_LOCK_LEN) - 1) << MM_GLB_TZC_MM_PWRON_RST_LOCK_POS)
#define MM_GLB_TZC_MM_PWRON_RST_LOCK_UMSK (~(((1U << MM_GLB_TZC_MM_PWRON_RST_LOCK_LEN) - 1) << MM_GLB_TZC_MM_PWRON_RST_LOCK_POS))
#define MM_GLB_TZC_MM_CPU0_RESET_LOCK MM_GLB_TZC_MM_CPU0_RESET_LOCK
#define MM_GLB_TZC_MM_CPU0_RESET_LOCK_POS (3U)
#define MM_GLB_TZC_MM_CPU0_RESET_LOCK_LEN (1U)
#define MM_GLB_TZC_MM_CPU0_RESET_LOCK_MSK (((1U << MM_GLB_TZC_MM_CPU0_RESET_LOCK_LEN) - 1) << MM_GLB_TZC_MM_CPU0_RESET_LOCK_POS)
#define MM_GLB_TZC_MM_CPU0_RESET_LOCK_UMSK (~(((1U << MM_GLB_TZC_MM_CPU0_RESET_LOCK_LEN) - 1) << MM_GLB_TZC_MM_CPU0_RESET_LOCK_POS))
#define MM_GLB_TZC_MM_CLK_LOCK MM_GLB_TZC_MM_CLK_LOCK
#define MM_GLB_TZC_MM_CLK_LOCK_POS (4U)
#define MM_GLB_TZC_MM_CLK_LOCK_LEN (1U)
#define MM_GLB_TZC_MM_CLK_LOCK_MSK (((1U << MM_GLB_TZC_MM_CLK_LOCK_LEN) - 1) << MM_GLB_TZC_MM_CLK_LOCK_POS)
#define MM_GLB_TZC_MM_CLK_LOCK_UMSK (~(((1U << MM_GLB_TZC_MM_CLK_LOCK_LEN) - 1) << MM_GLB_TZC_MM_CLK_LOCK_POS))
struct mm_glb_reg {
/* 0x0 : mm_clk_ctrl_cpu */
union {
struct {
uint32_t reg_pll_en : 1; /* [ 0], r/w, 0x1 */
uint32_t reg_cpu_clk_en : 1; /* [ 1], r/w, 0x1 */
uint32_t reg_bclk_en : 1; /* [ 2], r/w, 0x1 */
uint32_t reg_mm_cpu_clk_en : 1; /* [ 3], r/w, 0x1 */
uint32_t reg_uart_clk_sel : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t reg_i2c_clk_sel : 1; /* [ 6], r/w, 0x0 */
uint32_t reg_spi_clk_sel : 1; /* [ 7], r/w, 0x0 */
uint32_t reg_cpu_clk_sel : 2; /* [ 9: 8], r/w, 0x0 */
uint32_t reg_xclk_clk_sel : 1; /* [ 10], r/w, 0x0 */
uint32_t reg_cpu_root_clk_sel : 1; /* [ 11], r/w, 0x0 */
uint32_t reg_mmcpu0_clk_en : 1; /* [ 12], r/w, 0x0 */
uint32_t reg_bclk1x_sel : 2; /* [14:13], r/w, 0x0 */
uint32_t reserved_15_17 : 3; /* [17:15], rsvd, 0x0 */
uint32_t reg_bclk2x_div_act_pulse : 1; /* [ 18], w1p, 0x0 */
uint32_t reg_bclk2x_div_bypass : 1; /* [ 19], r/w, 0x0 */
uint32_t sts_bclk2x_prot_done : 1; /* [ 20], r, 0x1 */
uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */
uint32_t reg_bclk2x_sw_done_cnt : 4; /* [27:24], r/w, 0x5 */
uint32_t cpu_clk_sw_state : 3; /* [30:28], r, 0x0 */
uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
} BF;
uint32_t WORD;
} mm_clk_ctrl_cpu;
/* 0x4 : mm_clk_cpu */
union {
struct {
uint32_t reg_cpu_clk_div : 8; /* [ 7: 0], r/w, 0x0 */
uint32_t reg_cnn_clk_div_en : 1; /* [ 8], r/w, 0x1 */
uint32_t reg_cnn_clk_sel : 2; /* [10: 9], r/w, 0x0 */
uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
uint32_t reg_cnn_clk_div : 3; /* [14:12], r/w, 0x0 */
uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
uint32_t reg_bclk2x_div : 8; /* [23:16], r/w, 0x0 */
uint32_t reg_bclk1x_div : 8; /* [31:24], r/w, 0x0 */
} BF;
uint32_t WORD;
} mm_clk_cpu;
/* 0x8 : dp_clk */
union {
struct {
uint32_t reserved_0_15 : 16; /* [15: 0], rsvd, 0x0 */
uint32_t reg_dp_clk_div_en : 1; /* [ 16], r/w, 0x1 */
uint32_t reg_dp_clk_sel : 1; /* [ 17], r/w, 0x0 */
uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */
uint32_t reg_dp_clk_div : 4; /* [23:20], r/w, 0x0 */
uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
} BF;
uint32_t WORD;
} dp_clk;
/* 0xC : codec_clk */
union {
struct {
uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */
uint32_t reg_h264_clk_div_en : 1; /* [ 8], r/w, 0x1 */
uint32_t reg_h264_clk_sel : 2; /* [10: 9], r/w, 0x0 */
uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
uint32_t reg_h264_clk_div : 3; /* [14:12], r/w, 0x0 */
uint32_t reserved_15_31 : 17; /* [31:15], rsvd, 0x0 */
} BF;
uint32_t WORD;
} codec_clk;
/* 0x10 : mm_clk_ctrl_peri */
union {
struct {
uint32_t reg_i2c0_clk_div : 8; /* [ 7: 0], r/w, 0x0 */
uint32_t reg_i2c0_clk_div_en : 1; /* [ 8], r/w, 0x1 */
uint32_t reg_i2c0_clk_en : 1; /* [ 9], r/w, 0x1 */
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
uint32_t reg_uart0_clk_div_en : 1; /* [ 16], r/w, 0x1 */
uint32_t reg_uart0_clk_div : 3; /* [19:17], r/w, 0x0 */
uint32_t reserved_20_22 : 3; /* [22:20], rsvd, 0x0 */
uint32_t reg_spi_clk_div_en : 1; /* [ 23], r/w, 0x1 */
uint32_t reg_spi_clk_div : 8; /* [31:24], r/w, 0x0 */
} BF;
uint32_t WORD;
} mm_clk_ctrl_peri;
/* 0x14 reserved */
uint8_t RESERVED0x14[4];
/* 0x18 : mm_clk_ctrl_peri3 */
union {
struct {
uint32_t reg_i2c1_clk_div : 8; /* [ 7: 0], r/w, 0x0 */
uint32_t reg_i2c1_clk_div_en : 1; /* [ 8], r/w, 0x1 */
uint32_t reg_i2c1_clk_en : 1; /* [ 9], r/w, 0x1 */
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
uint32_t reg_uart1_clk_div_en : 1; /* [ 16], r/w, 0x1 */
uint32_t reg_uart1_clk_div : 3; /* [19:17], r/w, 0x0 */
uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */
} BF;
uint32_t WORD;
} mm_clk_ctrl_peri3;
/* 0x1c reserved */
uint8_t RESERVED0x1c[36];
/* 0x40 : mm_sw_sys_reset */
union {
struct {
uint32_t reg_ctrl_sys_reset : 1; /* [ 0], r/w, 0x0 */
uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
uint32_t reg_ctrl_pwron_rst : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */
uint32_t reg_ctrl_mmcpu0_reset : 1; /* [ 8], r/w, 0x1 */
uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
} BF;
uint32_t WORD;
} mm_sw_sys_reset;
/* 0x44 : sw_reset_mm_peri */
union {
struct {
uint32_t swrst_mm_misc : 1; /* [ 0], r/w, 0x0 */
uint32_t swrst_dma : 1; /* [ 1], r/w, 0x0 */
uint32_t swrst_uart0 : 1; /* [ 2], r/w, 0x0 */
uint32_t swrst_i2c0 : 1; /* [ 3], r/w, 0x0 */
uint32_t swrst_i2c1 : 1; /* [ 4], r/w, 0x0 */
uint32_t swrst_ipc : 1; /* [ 5], r/w, 0x0 */
uint32_t swrst_dma2d : 1; /* [ 6], r/w, 0x0 */
uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t swrst_spi : 1; /* [ 8], r/w, 0x0 */
uint32_t swrst_timer : 1; /* [ 9], r/w, 0x0 */
uint32_t swrst_i2s0 : 1; /* [ 10], r/w, 0x0 */
uint32_t swrst_i2s1 : 1; /* [ 11], r/w, 0x0 */
uint32_t swrst_pdm0 : 1; /* [ 12], r/w, 0x0 */
uint32_t swrst_pdm1 : 1; /* [ 13], r/w, 0x0 */
uint32_t swrst_uart1 : 1; /* [ 14], r/w, 0x0 */
uint32_t swrst_pUHS : 1; /* [ 15], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} sw_reset_mm_peri;
/* 0x48 : sw_reset_sub */
union {
struct {
uint32_t swrst_misc : 1; /* [ 0], r/w, 0x0 */
uint32_t swrst_main : 1; /* [ 1], r/w, 0x0 */
uint32_t swrst_tsrc : 1; /* [ 2], r/w, 0x0 */
uint32_t swrst_dp_tsrc : 1; /* [ 3], r/w, 0x0 */
uint32_t swrst_nr3d_ctrl : 1; /* [ 4], r/w, 0x0 */
uint32_t swrst_dvp2busA : 1; /* [ 5], r/w, 0x0 */
uint32_t swrst_dvp2busB : 1; /* [ 6], r/w, 0x0 */
uint32_t swrst_dvp2busC : 1; /* [ 7], r/w, 0x0 */
uint32_t swrst_dvp2busD : 1; /* [ 8], r/w, 0x0 */
uint32_t swrst_mipi : 1; /* [ 9], r/w, 0x0 */
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
uint32_t swrst_reg : 1; /* [ 16], r/w, 0x0 */
uint32_t swrst_dvp2busE : 1; /* [ 17], r/w, 0x0 */
uint32_t swrst_dvp2busF : 1; /* [ 18], r/w, 0x0 */
uint32_t swrst_dvp2busG : 1; /* [ 19], r/w, 0x0 */
uint32_t swrst_dvp2busH : 1; /* [ 20], r/w, 0x0 */
uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */
} BF;
uint32_t WORD;
} sw_reset_sub;
/* 0x4C : sw_reset_codec_sub */
union {
struct {
uint32_t swrst_codec_misc : 1; /* [ 0], r/w, 0x0 */
uint32_t swrst_mjpeg : 1; /* [ 1], r/w, 0x0 */
uint32_t swrst_h264 : 1; /* [ 2], r/w, 0x0 */
uint32_t swrst_mjpeg_dec : 1; /* [ 3], r/w, 0x0 */
uint32_t swrst_cnn : 1; /* [ 4], r/w, 0x0 */
uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */
uint32_t swrst_vram : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
} BF;
uint32_t WORD;
} sw_reset_codec_sub;
/* 0x50 : image_sensor_ctrl */
union {
struct {
uint32_t rg_is_rst_n : 1; /* [ 0], r/w, 0x1 */
uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
} BF;
uint32_t WORD;
} image_sensor_ctrl;
/* 0x54 reserved */
uint8_t RESERVED0x54[12];
/* 0x60 : tz_mm_clkrst */
union {
struct {
uint32_t tzc_mm_swrst_lock : 1; /* [ 0], r, 0x0 */
uint32_t tzc_mm_sys_reset_lock : 1; /* [ 1], r, 0x0 */
uint32_t tzc_mm_pwron_rst_lock : 1; /* [ 2], r, 0x0 */
uint32_t tzc_mm_cpu0_reset_lock : 1; /* [ 3], r, 0x0 */
uint32_t tzc_mm_clk_lock : 1; /* [ 4], r, 0x0 */
uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */
} BF;
uint32_t WORD;
} tz_mm_clkrst;
};
#endif /* __MM_GLB_REG_H__ */

971
include/bl808/mm_misc_reg.h Normal file
View File

@ -0,0 +1,971 @@
/**
******************************************************************************
* @file mm_misc_reg.h
* @version V1.0
* @date 2021-07-12
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __MM_MISC_REG_H__
#define __MM_MISC_REG_H__
#include <linux/types.h>
/* 0x0 : CPU0_Boot */
#define MM_MISC_CPU0_BOOT_OFFSET (0x0)
#define MM_MISC_REG_CPU0_RVBA MM_MISC_REG_CPU0_RVBA
#define MM_MISC_REG_CPU0_RVBA_POS (0U)
#define MM_MISC_REG_CPU0_RVBA_LEN (32U)
#define MM_MISC_REG_CPU0_RVBA_MSK (((1U << MM_MISC_REG_CPU0_RVBA_LEN) - 1) << MM_MISC_REG_CPU0_RVBA_POS)
#define MM_MISC_REG_CPU0_RVBA_UMSK (~(((1U << MM_MISC_REG_CPU0_RVBA_LEN) - 1) << MM_MISC_REG_CPU0_RVBA_POS))
/* 0x8 : CPU_cfg */
#define MM_MISC_CPU_CFG_OFFSET (0x8)
#define MM_MISC_REG_CPU0_APB_BASE MM_MISC_REG_CPU0_APB_BASE
#define MM_MISC_REG_CPU0_APB_BASE_POS (0U)
#define MM_MISC_REG_CPU0_APB_BASE_LEN (13U)
#define MM_MISC_REG_CPU0_APB_BASE_MSK (((1U << MM_MISC_REG_CPU0_APB_BASE_LEN) - 1) << MM_MISC_REG_CPU0_APB_BASE_POS)
#define MM_MISC_REG_CPU0_APB_BASE_UMSK (~(((1U << MM_MISC_REG_CPU0_APB_BASE_LEN) - 1) << MM_MISC_REG_CPU0_APB_BASE_POS))
#define MM_MISC_CPU0_NDM_RSTN_EN MM_MISC_CPU0_NDM_RSTN_EN
#define MM_MISC_CPU0_NDM_RSTN_EN_POS (28U)
#define MM_MISC_CPU0_NDM_RSTN_EN_LEN (1U)
#define MM_MISC_CPU0_NDM_RSTN_EN_MSK (((1U << MM_MISC_CPU0_NDM_RSTN_EN_LEN) - 1) << MM_MISC_CPU0_NDM_RSTN_EN_POS)
#define MM_MISC_CPU0_NDM_RSTN_EN_UMSK (~(((1U << MM_MISC_CPU0_NDM_RSTN_EN_LEN) - 1) << MM_MISC_CPU0_NDM_RSTN_EN_POS))
#define MM_MISC_CPU0_HART_RSTN_EN MM_MISC_CPU0_HART_RSTN_EN
#define MM_MISC_CPU0_HART_RSTN_EN_POS (29U)
#define MM_MISC_CPU0_HART_RSTN_EN_LEN (1U)
#define MM_MISC_CPU0_HART_RSTN_EN_MSK (((1U << MM_MISC_CPU0_HART_RSTN_EN_LEN) - 1) << MM_MISC_CPU0_HART_RSTN_EN_POS)
#define MM_MISC_CPU0_HART_RSTN_EN_UMSK (~(((1U << MM_MISC_CPU0_HART_RSTN_EN_LEN) - 1) << MM_MISC_CPU0_HART_RSTN_EN_POS))
/* 0xC : CPU_sts1 */
#define MM_MISC_CPU_STS1_OFFSET (0xC)
#define MM_MISC_CPU0_LPMD_B MM_MISC_CPU0_LPMD_B
#define MM_MISC_CPU0_LPMD_B_POS (4U)
#define MM_MISC_CPU0_LPMD_B_LEN (2U)
#define MM_MISC_CPU0_LPMD_B_MSK (((1U << MM_MISC_CPU0_LPMD_B_LEN) - 1) << MM_MISC_CPU0_LPMD_B_POS)
#define MM_MISC_CPU0_LPMD_B_UMSK (~(((1U << MM_MISC_CPU0_LPMD_B_LEN) - 1) << MM_MISC_CPU0_LPMD_B_POS))
#define MM_MISC_CPU0_RETIRE_PC_39_32 MM_MISC_CPU0_RETIRE_PC_39_32
#define MM_MISC_CPU0_RETIRE_PC_39_32_POS (16U)
#define MM_MISC_CPU0_RETIRE_PC_39_32_LEN (8U)
#define MM_MISC_CPU0_RETIRE_PC_39_32_MSK (((1U << MM_MISC_CPU0_RETIRE_PC_39_32_LEN) - 1) << MM_MISC_CPU0_RETIRE_PC_39_32_POS)
#define MM_MISC_CPU0_RETIRE_PC_39_32_UMSK (~(((1U << MM_MISC_CPU0_RETIRE_PC_39_32_LEN) - 1) << MM_MISC_CPU0_RETIRE_PC_39_32_POS))
#define MM_MISC_CPU0_RETIRE MM_MISC_CPU0_RETIRE
#define MM_MISC_CPU0_RETIRE_POS (24U)
#define MM_MISC_CPU0_RETIRE_LEN (1U)
#define MM_MISC_CPU0_RETIRE_MSK (((1U << MM_MISC_CPU0_RETIRE_LEN) - 1) << MM_MISC_CPU0_RETIRE_POS)
#define MM_MISC_CPU0_RETIRE_UMSK (~(((1U << MM_MISC_CPU0_RETIRE_LEN) - 1) << MM_MISC_CPU0_RETIRE_POS))
#define MM_MISC_CPU0_PAD_HALTED MM_MISC_CPU0_PAD_HALTED
#define MM_MISC_CPU0_PAD_HALTED_POS (25U)
#define MM_MISC_CPU0_PAD_HALTED_LEN (1U)
#define MM_MISC_CPU0_PAD_HALTED_MSK (((1U << MM_MISC_CPU0_PAD_HALTED_LEN) - 1) << MM_MISC_CPU0_PAD_HALTED_POS)
#define MM_MISC_CPU0_PAD_HALTED_UMSK (~(((1U << MM_MISC_CPU0_PAD_HALTED_LEN) - 1) << MM_MISC_CPU0_PAD_HALTED_POS))
#define MM_MISC_CPU0_NDM_RSTN_REQ MM_MISC_CPU0_NDM_RSTN_REQ
#define MM_MISC_CPU0_NDM_RSTN_REQ_POS (28U)
#define MM_MISC_CPU0_NDM_RSTN_REQ_LEN (1U)
#define MM_MISC_CPU0_NDM_RSTN_REQ_MSK (((1U << MM_MISC_CPU0_NDM_RSTN_REQ_LEN) - 1) << MM_MISC_CPU0_NDM_RSTN_REQ_POS)
#define MM_MISC_CPU0_NDM_RSTN_REQ_UMSK (~(((1U << MM_MISC_CPU0_NDM_RSTN_REQ_LEN) - 1) << MM_MISC_CPU0_NDM_RSTN_REQ_POS))
#define MM_MISC_CPU0_HART_RSTN_REQ MM_MISC_CPU0_HART_RSTN_REQ
#define MM_MISC_CPU0_HART_RSTN_REQ_POS (29U)
#define MM_MISC_CPU0_HART_RSTN_REQ_LEN (1U)
#define MM_MISC_CPU0_HART_RSTN_REQ_MSK (((1U << MM_MISC_CPU0_HART_RSTN_REQ_LEN) - 1) << MM_MISC_CPU0_HART_RSTN_REQ_POS)
#define MM_MISC_CPU0_HART_RSTN_REQ_UMSK (~(((1U << MM_MISC_CPU0_HART_RSTN_REQ_LEN) - 1) << MM_MISC_CPU0_HART_RSTN_REQ_POS))
/* 0x10 : CPU_sts2 */
#define MM_MISC_CPU_STS2_OFFSET (0x10)
#define MM_MISC_CPU0_RETIRE_PC_31_0 MM_MISC_CPU0_RETIRE_PC_31_0
#define MM_MISC_CPU0_RETIRE_PC_31_0_POS (0U)
#define MM_MISC_CPU0_RETIRE_PC_31_0_LEN (32U)
#define MM_MISC_CPU0_RETIRE_PC_31_0_MSK (((1U << MM_MISC_CPU0_RETIRE_PC_31_0_LEN) - 1) << MM_MISC_CPU0_RETIRE_PC_31_0_POS)
#define MM_MISC_CPU0_RETIRE_PC_31_0_UMSK (~(((1U << MM_MISC_CPU0_RETIRE_PC_31_0_LEN) - 1) << MM_MISC_CPU0_RETIRE_PC_31_0_POS))
/* 0x18 : CPU_RTC */
#define MM_MISC_CPU_RTC_OFFSET (0x18)
#define MM_MISC_C906_RTC_DIV MM_MISC_C906_RTC_DIV
#define MM_MISC_C906_RTC_DIV_POS (0U)
#define MM_MISC_C906_RTC_DIV_LEN (10U)
#define MM_MISC_C906_RTC_DIV_MSK (((1U << MM_MISC_C906_RTC_DIV_LEN) - 1) << MM_MISC_C906_RTC_DIV_POS)
#define MM_MISC_C906_RTC_DIV_UMSK (~(((1U << MM_MISC_C906_RTC_DIV_LEN) - 1) << MM_MISC_C906_RTC_DIV_POS))
#define MM_MISC_C906_RTC_RST MM_MISC_C906_RTC_RST
#define MM_MISC_C906_RTC_RST_POS (30U)
#define MM_MISC_C906_RTC_RST_LEN (1U)
#define MM_MISC_C906_RTC_RST_MSK (((1U << MM_MISC_C906_RTC_RST_LEN) - 1) << MM_MISC_C906_RTC_RST_POS)
#define MM_MISC_C906_RTC_RST_UMSK (~(((1U << MM_MISC_C906_RTC_RST_LEN) - 1) << MM_MISC_C906_RTC_RST_POS))
#define MM_MISC_C906_RTC_EN MM_MISC_C906_RTC_EN
#define MM_MISC_C906_RTC_EN_POS (31U)
#define MM_MISC_C906_RTC_EN_LEN (1U)
#define MM_MISC_C906_RTC_EN_MSK (((1U << MM_MISC_C906_RTC_EN_LEN) - 1) << MM_MISC_C906_RTC_EN_POS)
#define MM_MISC_C906_RTC_EN_UMSK (~(((1U << MM_MISC_C906_RTC_EN_LEN) - 1) << MM_MISC_C906_RTC_EN_POS))
/* 0x1C : tzc_mmsys_misc */
#define MM_MISC_TZC_MMSYS_MISC_OFFSET (0x1C)
#define MM_MISC_TZC_MM_CPU0_LOCK MM_MISC_TZC_MM_CPU0_LOCK
#define MM_MISC_TZC_MM_CPU0_LOCK_POS (0U)
#define MM_MISC_TZC_MM_CPU0_LOCK_LEN (1U)
#define MM_MISC_TZC_MM_CPU0_LOCK_MSK (((1U << MM_MISC_TZC_MM_CPU0_LOCK_LEN) - 1) << MM_MISC_TZC_MM_CPU0_LOCK_POS)
#define MM_MISC_TZC_MM_CPU0_LOCK_UMSK (~(((1U << MM_MISC_TZC_MM_CPU0_LOCK_LEN) - 1) << MM_MISC_TZC_MM_CPU0_LOCK_POS))
#define MM_MISC_TZC_MM_SRAM_LOCK MM_MISC_TZC_MM_SRAM_LOCK
#define MM_MISC_TZC_MM_SRAM_LOCK_POS (2U)
#define MM_MISC_TZC_MM_SRAM_LOCK_LEN (1U)
#define MM_MISC_TZC_MM_SRAM_LOCK_MSK (((1U << MM_MISC_TZC_MM_SRAM_LOCK_LEN) - 1) << MM_MISC_TZC_MM_SRAM_LOCK_POS)
#define MM_MISC_TZC_MM_SRAM_LOCK_UMSK (~(((1U << MM_MISC_TZC_MM_SRAM_LOCK_LEN) - 1) << MM_MISC_TZC_MM_SRAM_LOCK_POS))
/* 0x20 : peri_apb_ctrl */
#define MM_MISC_PERI_APB_CTRL_OFFSET (0x20)
#define MM_MISC_REG_MMINFRA_BERR_INT_EN MM_MISC_REG_MMINFRA_BERR_INT_EN
#define MM_MISC_REG_MMINFRA_BERR_INT_EN_POS (0U)
#define MM_MISC_REG_MMINFRA_BERR_INT_EN_LEN (1U)
#define MM_MISC_REG_MMINFRA_BERR_INT_EN_MSK (((1U << MM_MISC_REG_MMINFRA_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_INT_EN_POS)
#define MM_MISC_REG_MMINFRA_BERR_INT_EN_UMSK (~(((1U << MM_MISC_REG_MMINFRA_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_INT_EN_POS))
#define MM_MISC_REG_BERR_INT_EN MM_MISC_REG_BERR_INT_EN
#define MM_MISC_REG_BERR_INT_EN_POS (1U)
#define MM_MISC_REG_BERR_INT_EN_LEN (1U)
#define MM_MISC_REG_BERR_INT_EN_MSK (((1U << MM_MISC_REG_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_BERR_INT_EN_POS)
#define MM_MISC_REG_BERR_INT_EN_UMSK (~(((1U << MM_MISC_REG_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_BERR_INT_EN_POS))
#define MM_MISC_REG_CODEC_BERR_INT_EN MM_MISC_REG_CODEC_BERR_INT_EN
#define MM_MISC_REG_CODEC_BERR_INT_EN_POS (2U)
#define MM_MISC_REG_CODEC_BERR_INT_EN_LEN (1U)
#define MM_MISC_REG_CODEC_BERR_INT_EN_MSK (((1U << MM_MISC_REG_CODEC_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_CODEC_BERR_INT_EN_POS)
#define MM_MISC_REG_CODEC_BERR_INT_EN_UMSK (~(((1U << MM_MISC_REG_CODEC_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_CODEC_BERR_INT_EN_POS))
#define MM_MISC_REG_MMCPU_BERR_INT_EN MM_MISC_REG_MMCPU_BERR_INT_EN
#define MM_MISC_REG_MMCPU_BERR_INT_EN_POS (3U)
#define MM_MISC_REG_MMCPU_BERR_INT_EN_LEN (1U)
#define MM_MISC_REG_MMCPU_BERR_INT_EN_MSK (((1U << MM_MISC_REG_MMCPU_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_INT_EN_POS)
#define MM_MISC_REG_MMCPU_BERR_INT_EN_UMSK (~(((1U << MM_MISC_REG_MMCPU_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_INT_EN_POS))
#define MM_MISC_REG_MM_X2HS_SP_BYPASS MM_MISC_REG_MM_X2HS_SP_BYPASS
#define MM_MISC_REG_MM_X2HS_SP_BYPASS_POS (8U)
#define MM_MISC_REG_MM_X2HS_SP_BYPASS_LEN (1U)
#define MM_MISC_REG_MM_X2HS_SP_BYPASS_MSK (((1U << MM_MISC_REG_MM_X2HS_SP_BYPASS_LEN) - 1) << MM_MISC_REG_MM_X2HS_SP_BYPASS_POS)
#define MM_MISC_REG_MM_X2HS_SP_BYPASS_UMSK (~(((1U << MM_MISC_REG_MM_X2HS_SP_BYPASS_LEN) - 1) << MM_MISC_REG_MM_X2HS_SP_BYPASS_POS))
#define MM_MISC_RG_PCLK_FORCE_ON MM_MISC_RG_PCLK_FORCE_ON
#define MM_MISC_RG_PCLK_FORCE_ON_POS (16U)
#define MM_MISC_RG_PCLK_FORCE_ON_LEN (16U)
#define MM_MISC_RG_PCLK_FORCE_ON_MSK (((1U << MM_MISC_RG_PCLK_FORCE_ON_LEN) - 1) << MM_MISC_RG_PCLK_FORCE_ON_POS)
#define MM_MISC_RG_PCLK_FORCE_ON_UMSK (~(((1U << MM_MISC_RG_PCLK_FORCE_ON_LEN) - 1) << MM_MISC_RG_PCLK_FORCE_ON_POS))
/* 0x2C : mm_infra_qos_ctrl */
#define MM_MISC_MM_INFRA_QOS_CTRL_OFFSET (0x2C)
#define MM_MISC_REG_MMCPU0_AWQOS MM_MISC_REG_MMCPU0_AWQOS
#define MM_MISC_REG_MMCPU0_AWQOS_POS (2U)
#define MM_MISC_REG_MMCPU0_AWQOS_LEN (1U)
#define MM_MISC_REG_MMCPU0_AWQOS_MSK (((1U << MM_MISC_REG_MMCPU0_AWQOS_LEN) - 1) << MM_MISC_REG_MMCPU0_AWQOS_POS)
#define MM_MISC_REG_MMCPU0_AWQOS_UMSK (~(((1U << MM_MISC_REG_MMCPU0_AWQOS_LEN) - 1) << MM_MISC_REG_MMCPU0_AWQOS_POS))
#define MM_MISC_REG_MMCPU0_ARQOS MM_MISC_REG_MMCPU0_ARQOS
#define MM_MISC_REG_MMCPU0_ARQOS_POS (3U)
#define MM_MISC_REG_MMCPU0_ARQOS_LEN (1U)
#define MM_MISC_REG_MMCPU0_ARQOS_MSK (((1U << MM_MISC_REG_MMCPU0_ARQOS_LEN) - 1) << MM_MISC_REG_MMCPU0_ARQOS_POS)
#define MM_MISC_REG_MMCPU0_ARQOS_UMSK (~(((1U << MM_MISC_REG_MMCPU0_ARQOS_LEN) - 1) << MM_MISC_REG_MMCPU0_ARQOS_POS))
#define MM_MISC_REG_H_WTHRE_MM2CONN MM_MISC_REG_H_WTHRE_MM2CONN
#define MM_MISC_REG_H_WTHRE_MM2CONN_POS (16U)
#define MM_MISC_REG_H_WTHRE_MM2CONN_LEN (2U)
#define MM_MISC_REG_H_WTHRE_MM2CONN_MSK (((1U << MM_MISC_REG_H_WTHRE_MM2CONN_LEN) - 1) << MM_MISC_REG_H_WTHRE_MM2CONN_POS)
#define MM_MISC_REG_H_WTHRE_MM2CONN_UMSK (~(((1U << MM_MISC_REG_H_WTHRE_MM2CONN_LEN) - 1) << MM_MISC_REG_H_WTHRE_MM2CONN_POS))
#define MM_MISC_REG_H_WTHRE_CONN2MM MM_MISC_REG_H_WTHRE_CONN2MM
#define MM_MISC_REG_H_WTHRE_CONN2MM_POS (18U)
#define MM_MISC_REG_H_WTHRE_CONN2MM_LEN (2U)
#define MM_MISC_REG_H_WTHRE_CONN2MM_MSK (((1U << MM_MISC_REG_H_WTHRE_CONN2MM_LEN) - 1) << MM_MISC_REG_H_WTHRE_CONN2MM_POS)
#define MM_MISC_REG_H_WTHRE_CONN2MM_UMSK (~(((1U << MM_MISC_REG_H_WTHRE_CONN2MM_LEN) - 1) << MM_MISC_REG_H_WTHRE_CONN2MM_POS))
#define MM_MISC_REG_X_WTHRE_MMHW2PA MM_MISC_REG_X_WTHRE_MMHW2PA
#define MM_MISC_REG_X_WTHRE_MMHW2PA_POS (20U)
#define MM_MISC_REG_X_WTHRE_MMHW2PA_LEN (2U)
#define MM_MISC_REG_X_WTHRE_MMHW2PA_MSK (((1U << MM_MISC_REG_X_WTHRE_MMHW2PA_LEN) - 1) << MM_MISC_REG_X_WTHRE_MMHW2PA_POS)
#define MM_MISC_REG_X_WTHRE_MMHW2PA_UMSK (~(((1U << MM_MISC_REG_X_WTHRE_MMHW2PA_LEN) - 1) << MM_MISC_REG_X_WTHRE_MMHW2PA_POS))
#define MM_MISC_REG_X_WTHRE_MMHW2EXT MM_MISC_REG_X_WTHRE_MMHW2EXT
#define MM_MISC_REG_X_WTHRE_MMHW2EXT_POS (22U)
#define MM_MISC_REG_X_WTHRE_MMHW2EXT_LEN (2U)
#define MM_MISC_REG_X_WTHRE_MMHW2EXT_MSK (((1U << MM_MISC_REG_X_WTHRE_MMHW2EXT_LEN) - 1) << MM_MISC_REG_X_WTHRE_MMHW2EXT_POS)
#define MM_MISC_REG_X_WTHRE_MMHW2EXT_UMSK (~(((1U << MM_MISC_REG_X_WTHRE_MMHW2EXT_LEN) - 1) << MM_MISC_REG_X_WTHRE_MMHW2EXT_POS))
#define MM_MISC_REG_X_WTHRE_PUHS MM_MISC_REG_X_WTHRE_PUHS
#define MM_MISC_REG_X_WTHRE_PUHS_POS (24U)
#define MM_MISC_REG_X_WTHRE_PUHS_LEN (2U)
#define MM_MISC_REG_X_WTHRE_PUHS_MSK (((1U << MM_MISC_REG_X_WTHRE_PUHS_LEN) - 1) << MM_MISC_REG_X_WTHRE_PUHS_POS)
#define MM_MISC_REG_X_WTHRE_PUHS_UMSK (~(((1U << MM_MISC_REG_X_WTHRE_PUHS_LEN) - 1) << MM_MISC_REG_X_WTHRE_PUHS_POS))
/* 0x40 : dma_clk_ctrl */
#define MM_MISC_DMA_CLK_CTRL_OFFSET (0x40)
#define MM_MISC_DMA_CLK_EN MM_MISC_DMA_CLK_EN
#define MM_MISC_DMA_CLK_EN_POS (0U)
#define MM_MISC_DMA_CLK_EN_LEN (8U)
#define MM_MISC_DMA_CLK_EN_MSK (((1U << MM_MISC_DMA_CLK_EN_LEN) - 1) << MM_MISC_DMA_CLK_EN_POS)
#define MM_MISC_DMA_CLK_EN_UMSK (~(((1U << MM_MISC_DMA_CLK_EN_LEN) - 1) << MM_MISC_DMA_CLK_EN_POS))
/* 0x50 : vram_ctrl */
#define MM_MISC_VRAM_CTRL_OFFSET (0x50)
#define MM_MISC_REG_SYSRAM_SET MM_MISC_REG_SYSRAM_SET
#define MM_MISC_REG_SYSRAM_SET_POS (0U)
#define MM_MISC_REG_SYSRAM_SET_LEN (1U)
#define MM_MISC_REG_SYSRAM_SET_MSK (((1U << MM_MISC_REG_SYSRAM_SET_LEN) - 1) << MM_MISC_REG_SYSRAM_SET_POS)
#define MM_MISC_REG_SYSRAM_SET_UMSK (~(((1U << MM_MISC_REG_SYSRAM_SET_LEN) - 1) << MM_MISC_REG_SYSRAM_SET_POS))
#define MM_MISC_REG_H2PF_SRAM_REL MM_MISC_REG_H2PF_SRAM_REL
#define MM_MISC_REG_H2PF_SRAM_REL_POS (1U)
#define MM_MISC_REG_H2PF_SRAM_REL_LEN (2U)
#define MM_MISC_REG_H2PF_SRAM_REL_MSK (((1U << MM_MISC_REG_H2PF_SRAM_REL_LEN) - 1) << MM_MISC_REG_H2PF_SRAM_REL_POS)
#define MM_MISC_REG_H2PF_SRAM_REL_UMSK (~(((1U << MM_MISC_REG_H2PF_SRAM_REL_LEN) - 1) << MM_MISC_REG_H2PF_SRAM_REL_POS))
#define MM_MISC_REG_VRAM_SRAM_REL MM_MISC_REG_VRAM_SRAM_REL
#define MM_MISC_REG_VRAM_SRAM_REL_POS (4U)
#define MM_MISC_REG_VRAM_SRAM_REL_LEN (1U)
#define MM_MISC_REG_VRAM_SRAM_REL_MSK (((1U << MM_MISC_REG_VRAM_SRAM_REL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_REL_POS)
#define MM_MISC_REG_VRAM_SRAM_REL_UMSK (~(((1U << MM_MISC_REG_VRAM_SRAM_REL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_REL_POS))
#define MM_MISC_REG_SUB_SRAM_REL MM_MISC_REG_SUB_SRAM_REL
#define MM_MISC_REG_SUB_SRAM_REL_POS (6U)
#define MM_MISC_REG_SUB_SRAM_REL_LEN (1U)
#define MM_MISC_REG_SUB_SRAM_REL_MSK (((1U << MM_MISC_REG_SUB_SRAM_REL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_REL_POS)
#define MM_MISC_REG_SUB_SRAM_REL_UMSK (~(((1U << MM_MISC_REG_SUB_SRAM_REL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_REL_POS))
#define MM_MISC_REG_BLAI_SRAM_REL MM_MISC_REG_BLAI_SRAM_REL
#define MM_MISC_REG_BLAI_SRAM_REL_POS (7U)
#define MM_MISC_REG_BLAI_SRAM_REL_LEN (1U)
#define MM_MISC_REG_BLAI_SRAM_REL_MSK (((1U << MM_MISC_REG_BLAI_SRAM_REL_LEN) - 1) << MM_MISC_REG_BLAI_SRAM_REL_POS)
#define MM_MISC_REG_BLAI_SRAM_REL_UMSK (~(((1U << MM_MISC_REG_BLAI_SRAM_REL_LEN) - 1) << MM_MISC_REG_BLAI_SRAM_REL_POS))
#define MM_MISC_REG_H2PF_SRAM_SEL MM_MISC_REG_H2PF_SRAM_SEL
#define MM_MISC_REG_H2PF_SRAM_SEL_POS (8U)
#define MM_MISC_REG_H2PF_SRAM_SEL_LEN (3U)
#define MM_MISC_REG_H2PF_SRAM_SEL_MSK (((1U << MM_MISC_REG_H2PF_SRAM_SEL_LEN) - 1) << MM_MISC_REG_H2PF_SRAM_SEL_POS)
#define MM_MISC_REG_H2PF_SRAM_SEL_UMSK (~(((1U << MM_MISC_REG_H2PF_SRAM_SEL_LEN) - 1) << MM_MISC_REG_H2PF_SRAM_SEL_POS))
#define MM_MISC_REG_VRAM_SRAM_SEL MM_MISC_REG_VRAM_SRAM_SEL
#define MM_MISC_REG_VRAM_SRAM_SEL_POS (12U)
#define MM_MISC_REG_VRAM_SRAM_SEL_LEN (1U)
#define MM_MISC_REG_VRAM_SRAM_SEL_MSK (((1U << MM_MISC_REG_VRAM_SRAM_SEL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_SEL_POS)
#define MM_MISC_REG_VRAM_SRAM_SEL_UMSK (~(((1U << MM_MISC_REG_VRAM_SRAM_SEL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_SEL_POS))
#define MM_MISC_REG_SUB_SRAM_SEL MM_MISC_REG_SUB_SRAM_SEL
#define MM_MISC_REG_SUB_SRAM_SEL_POS (14U)
#define MM_MISC_REG_SUB_SRAM_SEL_LEN (1U)
#define MM_MISC_REG_SUB_SRAM_SEL_MSK (((1U << MM_MISC_REG_SUB_SRAM_SEL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_SEL_POS)
#define MM_MISC_REG_SUB_SRAM_SEL_UMSK (~(((1U << MM_MISC_REG_SUB_SRAM_SEL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_SEL_POS))
#define MM_MISC_REG_BLAI_SRAM_SEL MM_MISC_REG_BLAI_SRAM_SEL
#define MM_MISC_REG_BLAI_SRAM_SEL_POS (15U)
#define MM_MISC_REG_BLAI_SRAM_SEL_LEN (1U)
#define MM_MISC_REG_BLAI_SRAM_SEL_MSK (((1U << MM_MISC_REG_BLAI_SRAM_SEL_LEN) - 1) << MM_MISC_REG_BLAI_SRAM_SEL_POS)
#define MM_MISC_REG_BLAI_SRAM_SEL_UMSK (~(((1U << MM_MISC_REG_BLAI_SRAM_SEL_LEN) - 1) << MM_MISC_REG_BLAI_SRAM_SEL_POS))
/* 0x60 : sram_parm */
#define MM_MISC_SRAM_PARM_OFFSET (0x60)
#define MM_MISC_REG_SRAM_CPU_RAM_DVS MM_MISC_REG_SRAM_CPU_RAM_DVS
#define MM_MISC_REG_SRAM_CPU_RAM_DVS_POS (0U)
#define MM_MISC_REG_SRAM_CPU_RAM_DVS_LEN (4U)
#define MM_MISC_REG_SRAM_CPU_RAM_DVS_MSK (((1U << MM_MISC_REG_SRAM_CPU_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_DVS_POS)
#define MM_MISC_REG_SRAM_CPU_RAM_DVS_UMSK (~(((1U << MM_MISC_REG_SRAM_CPU_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_DVS_POS))
#define MM_MISC_REG_SRAM_CPU_RAM_DVSE MM_MISC_REG_SRAM_CPU_RAM_DVSE
#define MM_MISC_REG_SRAM_CPU_RAM_DVSE_POS (4U)
#define MM_MISC_REG_SRAM_CPU_RAM_DVSE_LEN (1U)
#define MM_MISC_REG_SRAM_CPU_RAM_DVSE_MSK (((1U << MM_MISC_REG_SRAM_CPU_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_DVSE_POS)
#define MM_MISC_REG_SRAM_CPU_RAM_DVSE_UMSK (~(((1U << MM_MISC_REG_SRAM_CPU_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_DVSE_POS))
#define MM_MISC_REG_SRAM_CPU_RAM_NAP MM_MISC_REG_SRAM_CPU_RAM_NAP
#define MM_MISC_REG_SRAM_CPU_RAM_NAP_POS (5U)
#define MM_MISC_REG_SRAM_CPU_RAM_NAP_LEN (1U)
#define MM_MISC_REG_SRAM_CPU_RAM_NAP_MSK (((1U << MM_MISC_REG_SRAM_CPU_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_NAP_POS)
#define MM_MISC_REG_SRAM_CPU_RAM_NAP_UMSK (~(((1U << MM_MISC_REG_SRAM_CPU_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_CPU_RAM_NAP_POS))
#define MM_MISC_REG_SRAM_L2RAM_DVS MM_MISC_REG_SRAM_L2RAM_DVS
#define MM_MISC_REG_SRAM_L2RAM_DVS_POS (8U)
#define MM_MISC_REG_SRAM_L2RAM_DVS_LEN (4U)
#define MM_MISC_REG_SRAM_L2RAM_DVS_MSK (((1U << MM_MISC_REG_SRAM_L2RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_DVS_POS)
#define MM_MISC_REG_SRAM_L2RAM_DVS_UMSK (~(((1U << MM_MISC_REG_SRAM_L2RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_DVS_POS))
#define MM_MISC_REG_SRAM_L2RAM_DVSE MM_MISC_REG_SRAM_L2RAM_DVSE
#define MM_MISC_REG_SRAM_L2RAM_DVSE_POS (12U)
#define MM_MISC_REG_SRAM_L2RAM_DVSE_LEN (1U)
#define MM_MISC_REG_SRAM_L2RAM_DVSE_MSK (((1U << MM_MISC_REG_SRAM_L2RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_DVSE_POS)
#define MM_MISC_REG_SRAM_L2RAM_DVSE_UMSK (~(((1U << MM_MISC_REG_SRAM_L2RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_DVSE_POS))
#define MM_MISC_REG_SRAM_L2RAM_NAP MM_MISC_REG_SRAM_L2RAM_NAP
#define MM_MISC_REG_SRAM_L2RAM_NAP_POS (13U)
#define MM_MISC_REG_SRAM_L2RAM_NAP_LEN (1U)
#define MM_MISC_REG_SRAM_L2RAM_NAP_MSK (((1U << MM_MISC_REG_SRAM_L2RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_NAP_POS)
#define MM_MISC_REG_SRAM_L2RAM_NAP_UMSK (~(((1U << MM_MISC_REG_SRAM_L2RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_L2RAM_NAP_POS))
#define MM_MISC_REG_SRAM_CDC_RAM_DVS MM_MISC_REG_SRAM_CDC_RAM_DVS
#define MM_MISC_REG_SRAM_CDC_RAM_DVS_POS (16U)
#define MM_MISC_REG_SRAM_CDC_RAM_DVS_LEN (4U)
#define MM_MISC_REG_SRAM_CDC_RAM_DVS_MSK (((1U << MM_MISC_REG_SRAM_CDC_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_DVS_POS)
#define MM_MISC_REG_SRAM_CDC_RAM_DVS_UMSK (~(((1U << MM_MISC_REG_SRAM_CDC_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_DVS_POS))
#define MM_MISC_REG_SRAM_CDC_RAM_DVSE MM_MISC_REG_SRAM_CDC_RAM_DVSE
#define MM_MISC_REG_SRAM_CDC_RAM_DVSE_POS (20U)
#define MM_MISC_REG_SRAM_CDC_RAM_DVSE_LEN (1U)
#define MM_MISC_REG_SRAM_CDC_RAM_DVSE_MSK (((1U << MM_MISC_REG_SRAM_CDC_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_DVSE_POS)
#define MM_MISC_REG_SRAM_CDC_RAM_DVSE_UMSK (~(((1U << MM_MISC_REG_SRAM_CDC_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_DVSE_POS))
#define MM_MISC_REG_SRAM_CDC_RAM_NAP MM_MISC_REG_SRAM_CDC_RAM_NAP
#define MM_MISC_REG_SRAM_CDC_RAM_NAP_POS (21U)
#define MM_MISC_REG_SRAM_CDC_RAM_NAP_LEN (1U)
#define MM_MISC_REG_SRAM_CDC_RAM_NAP_MSK (((1U << MM_MISC_REG_SRAM_CDC_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_NAP_POS)
#define MM_MISC_REG_SRAM_CDC_RAM_NAP_UMSK (~(((1U << MM_MISC_REG_SRAM_CDC_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_NAP_POS))
#define MM_MISC_REG_SRAM_SUB_RAM_DVS MM_MISC_REG_SRAM_SUB_RAM_DVS
#define MM_MISC_REG_SRAM_SUB_RAM_DVS_POS (24U)
#define MM_MISC_REG_SRAM_SUB_RAM_DVS_LEN (4U)
#define MM_MISC_REG_SRAM_SUB_RAM_DVS_MSK (((1U << MM_MISC_REG_SRAM_SUB_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVS_POS)
#define MM_MISC_REG_SRAM_SUB_RAM_DVS_UMSK (~(((1U << MM_MISC_REG_SRAM_SUB_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVS_POS))
#define MM_MISC_REG_SRAM_SUB_RAM_DVSE MM_MISC_REG_SRAM_SUB_RAM_DVSE
#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_POS (28U)
#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_LEN (1U)
#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_MSK (((1U << MM_MISC_REG_SRAM_SUB_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVSE_POS)
#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_UMSK (~(((1U << MM_MISC_REG_SRAM_SUB_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVSE_POS))
#define MM_MISC_REG_SRAM_SUB_RAM_NAP MM_MISC_REG_SRAM_SUB_RAM_NAP
#define MM_MISC_REG_SRAM_SUB_RAM_NAP_POS (29U)
#define MM_MISC_REG_SRAM_SUB_RAM_NAP_LEN (1U)
#define MM_MISC_REG_SRAM_SUB_RAM_NAP_MSK (((1U << MM_MISC_REG_SRAM_SUB_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_NAP_POS)
#define MM_MISC_REG_SRAM_SUB_RAM_NAP_UMSK (~(((1U << MM_MISC_REG_SRAM_SUB_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_NAP_POS))
/* 0xA0 : MM_INT_STA0 */
#define MM_MISC_MM_INT_STA0_OFFSET (0xA0)
#define MM_MISC_MM_INT_STA0 MM_MISC_MM_INT_STA0
#define MM_MISC_MM_INT_STA0_POS (0U)
#define MM_MISC_MM_INT_STA0_LEN (32U)
#define MM_MISC_MM_INT_STA0_MSK (((1U << MM_MISC_MM_INT_STA0_LEN) - 1) << MM_MISC_MM_INT_STA0_POS)
#define MM_MISC_MM_INT_STA0_UMSK (~(((1U << MM_MISC_MM_INT_STA0_LEN) - 1) << MM_MISC_MM_INT_STA0_POS))
/* 0xA4 : MM_INT_MASK0 */
#define MM_MISC_MM_INT_MASK0_OFFSET (0xA4)
#define MM_MISC_MM_INT_MASK0 MM_MISC_MM_INT_MASK0
#define MM_MISC_MM_INT_MASK0_POS (0U)
#define MM_MISC_MM_INT_MASK0_LEN (32U)
#define MM_MISC_MM_INT_MASK0_MSK (((1U << MM_MISC_MM_INT_MASK0_LEN) - 1) << MM_MISC_MM_INT_MASK0_POS)
#define MM_MISC_MM_INT_MASK0_UMSK (~(((1U << MM_MISC_MM_INT_MASK0_LEN) - 1) << MM_MISC_MM_INT_MASK0_POS))
/* 0xA8 : MM_INT_CLR_0 */
#define MM_MISC_MM_INT_CLR_0_OFFSET (0xA8)
#define MM_MISC_MM_INT_CLR0 MM_MISC_MM_INT_CLR0
#define MM_MISC_MM_INT_CLR0_POS (0U)
#define MM_MISC_MM_INT_CLR0_LEN (32U)
#define MM_MISC_MM_INT_CLR0_MSK (((1U << MM_MISC_MM_INT_CLR0_LEN) - 1) << MM_MISC_MM_INT_CLR0_POS)
#define MM_MISC_MM_INT_CLR0_UMSK (~(((1U << MM_MISC_MM_INT_CLR0_LEN) - 1) << MM_MISC_MM_INT_CLR0_POS))
/* 0xAC : MM_INT_STA1 */
#define MM_MISC_MM_INT_STA1_OFFSET (0xAC)
#define MM_MISC_MM_INT_STA1 MM_MISC_MM_INT_STA1
#define MM_MISC_MM_INT_STA1_POS (0U)
#define MM_MISC_MM_INT_STA1_LEN (32U)
#define MM_MISC_MM_INT_STA1_MSK (((1U << MM_MISC_MM_INT_STA1_LEN) - 1) << MM_MISC_MM_INT_STA1_POS)
#define MM_MISC_MM_INT_STA1_UMSK (~(((1U << MM_MISC_MM_INT_STA1_LEN) - 1) << MM_MISC_MM_INT_STA1_POS))
/* 0xB0 : MM_INT_MASK1 */
#define MM_MISC_MM_INT_MASK1_OFFSET (0xB0)
#define MM_MISC_MM_INT_MASK1 MM_MISC_MM_INT_MASK1
#define MM_MISC_MM_INT_MASK1_POS (0U)
#define MM_MISC_MM_INT_MASK1_LEN (32U)
#define MM_MISC_MM_INT_MASK1_MSK (((1U << MM_MISC_MM_INT_MASK1_LEN) - 1) << MM_MISC_MM_INT_MASK1_POS)
#define MM_MISC_MM_INT_MASK1_UMSK (~(((1U << MM_MISC_MM_INT_MASK1_LEN) - 1) << MM_MISC_MM_INT_MASK1_POS))
/* 0xB4 : MM_INT_CLR_1 */
#define MM_MISC_MM_INT_CLR_1_OFFSET (0xB4)
#define MM_MISC_MM_INT_CLR1 MM_MISC_MM_INT_CLR1
#define MM_MISC_MM_INT_CLR1_POS (0U)
#define MM_MISC_MM_INT_CLR1_LEN (32U)
#define MM_MISC_MM_INT_CLR1_MSK (((1U << MM_MISC_MM_INT_CLR1_LEN) - 1) << MM_MISC_MM_INT_CLR1_POS)
#define MM_MISC_MM_INT_CLR1_UMSK (~(((1U << MM_MISC_MM_INT_CLR1_LEN) - 1) << MM_MISC_MM_INT_CLR1_POS))
/* 0xF0 : mmsys_debug_sel */
#define MM_MISC_MMSYS_DEBUG_SEL_OFFSET (0xF0)
#define MM_MISC_MMSYS_DEBUG_SEL MM_MISC_MMSYS_DEBUG_SEL
#define MM_MISC_MMSYS_DEBUG_SEL_POS (0U)
#define MM_MISC_MMSYS_DEBUG_SEL_LEN (4U)
#define MM_MISC_MMSYS_DEBUG_SEL_MSK (((1U << MM_MISC_MMSYS_DEBUG_SEL_LEN) - 1) << MM_MISC_MMSYS_DEBUG_SEL_POS)
#define MM_MISC_MMSYS_DEBUG_SEL_UMSK (~(((1U << MM_MISC_MMSYS_DEBUG_SEL_LEN) - 1) << MM_MISC_MMSYS_DEBUG_SEL_POS))
/* 0xFC : mmsys_misc_dummy */
#define MM_MISC_MMSYS_MISC_DUMMY_OFFSET (0xFC)
#define MM_MISC_PIR_CTRL_O MM_MISC_PIR_CTRL_O
#define MM_MISC_PIR_CTRL_O_POS (0U)
#define MM_MISC_PIR_CTRL_O_LEN (1U)
#define MM_MISC_PIR_CTRL_O_MSK (((1U << MM_MISC_PIR_CTRL_O_LEN) - 1) << MM_MISC_PIR_CTRL_O_POS)
#define MM_MISC_PIR_CTRL_O_UMSK (~(((1U << MM_MISC_PIR_CTRL_O_LEN) - 1) << MM_MISC_PIR_CTRL_O_POS))
#define MM_MISC_LIGHT_SENSOR_CTRL_O MM_MISC_LIGHT_SENSOR_CTRL_O
#define MM_MISC_LIGHT_SENSOR_CTRL_O_POS (1U)
#define MM_MISC_LIGHT_SENSOR_CTRL_O_LEN (1U)
#define MM_MISC_LIGHT_SENSOR_CTRL_O_MSK (((1U << MM_MISC_LIGHT_SENSOR_CTRL_O_LEN) - 1) << MM_MISC_LIGHT_SENSOR_CTRL_O_POS)
#define MM_MISC_LIGHT_SENSOR_CTRL_O_UMSK (~(((1U << MM_MISC_LIGHT_SENSOR_CTRL_O_LEN) - 1) << MM_MISC_LIGHT_SENSOR_CTRL_O_POS))
#define MM_MISC_IR_CUT_CTRL_O MM_MISC_IR_CUT_CTRL_O
#define MM_MISC_IR_CUT_CTRL_O_POS (2U)
#define MM_MISC_IR_CUT_CTRL_O_LEN (1U)
#define MM_MISC_IR_CUT_CTRL_O_MSK (((1U << MM_MISC_IR_CUT_CTRL_O_LEN) - 1) << MM_MISC_IR_CUT_CTRL_O_POS)
#define MM_MISC_IR_CUT_CTRL_O_UMSK (~(((1U << MM_MISC_IR_CUT_CTRL_O_LEN) - 1) << MM_MISC_IR_CUT_CTRL_O_POS))
#define MM_MISC_DVP_SENSOR_PWDN MM_MISC_DVP_SENSOR_PWDN
#define MM_MISC_DVP_SENSOR_PWDN_POS (3U)
#define MM_MISC_DVP_SENSOR_PWDN_LEN (1U)
#define MM_MISC_DVP_SENSOR_PWDN_MSK (((1U << MM_MISC_DVP_SENSOR_PWDN_LEN) - 1) << MM_MISC_DVP_SENSOR_PWDN_POS)
#define MM_MISC_DVP_SENSOR_PWDN_UMSK (~(((1U << MM_MISC_DVP_SENSOR_PWDN_LEN) - 1) << MM_MISC_DVP_SENSOR_PWDN_POS))
#define MM_MISC_DUMMY_REG MM_MISC_DUMMY_REG
#define MM_MISC_DUMMY_REG_POS (4U)
#define MM_MISC_DUMMY_REG_LEN (28U)
#define MM_MISC_DUMMY_REG_MSK (((1U << MM_MISC_DUMMY_REG_LEN) - 1) << MM_MISC_DUMMY_REG_POS)
#define MM_MISC_DUMMY_REG_UMSK (~(((1U << MM_MISC_DUMMY_REG_LEN) - 1) << MM_MISC_DUMMY_REG_POS))
/* 0x100 : DDR_debug */
#define MM_MISC_DDR_DEBUG_OFFSET (0x100)
#define MM_MISC_DDR_CALIB_DONE MM_MISC_DDR_CALIB_DONE
#define MM_MISC_DDR_CALIB_DONE_POS (0U)
#define MM_MISC_DDR_CALIB_DONE_LEN (1U)
#define MM_MISC_DDR_CALIB_DONE_MSK (((1U << MM_MISC_DDR_CALIB_DONE_LEN) - 1) << MM_MISC_DDR_CALIB_DONE_POS)
#define MM_MISC_DDR_CALIB_DONE_UMSK (~(((1U << MM_MISC_DDR_CALIB_DONE_LEN) - 1) << MM_MISC_DDR_CALIB_DONE_POS))
/* 0x140 : mm_berr_cfg0 */
#define MM_MISC_MM_BERR_CFG0_OFFSET (0x140)
#define MM_MISC_REG_BERR_EN MM_MISC_REG_BERR_EN
#define MM_MISC_REG_BERR_EN_POS (0U)
#define MM_MISC_REG_BERR_EN_LEN (3U)
#define MM_MISC_REG_BERR_EN_MSK (((1U << MM_MISC_REG_BERR_EN_LEN) - 1) << MM_MISC_REG_BERR_EN_POS)
#define MM_MISC_REG_BERR_EN_UMSK (~(((1U << MM_MISC_REG_BERR_EN_LEN) - 1) << MM_MISC_REG_BERR_EN_POS))
#define MM_MISC_REG_CODEC_BERR_EN MM_MISC_REG_CODEC_BERR_EN
#define MM_MISC_REG_CODEC_BERR_EN_POS (8U)
#define MM_MISC_REG_CODEC_BERR_EN_LEN (3U)
#define MM_MISC_REG_CODEC_BERR_EN_MSK (((1U << MM_MISC_REG_CODEC_BERR_EN_LEN) - 1) << MM_MISC_REG_CODEC_BERR_EN_POS)
#define MM_MISC_REG_CODEC_BERR_EN_UMSK (~(((1U << MM_MISC_REG_CODEC_BERR_EN_LEN) - 1) << MM_MISC_REG_CODEC_BERR_EN_POS))
#define MM_MISC_REG_MMCPU_BERR_EN MM_MISC_REG_MMCPU_BERR_EN
#define MM_MISC_REG_MMCPU_BERR_EN_POS (16U)
#define MM_MISC_REG_MMCPU_BERR_EN_LEN (1U)
#define MM_MISC_REG_MMCPU_BERR_EN_MSK (((1U << MM_MISC_REG_MMCPU_BERR_EN_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_EN_POS)
#define MM_MISC_REG_MMCPU_BERR_EN_UMSK (~(((1U << MM_MISC_REG_MMCPU_BERR_EN_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_EN_POS))
#define MM_MISC_REG_MMINFRA_BERR_EN MM_MISC_REG_MMINFRA_BERR_EN
#define MM_MISC_REG_MMINFRA_BERR_EN_POS (24U)
#define MM_MISC_REG_MMINFRA_BERR_EN_LEN (5U)
#define MM_MISC_REG_MMINFRA_BERR_EN_MSK (((1U << MM_MISC_REG_MMINFRA_BERR_EN_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_EN_POS)
#define MM_MISC_REG_MMINFRA_BERR_EN_UMSK (~(((1U << MM_MISC_REG_MMINFRA_BERR_EN_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_EN_POS))
/* 0x144 : mm_berr_cfg1 */
#define MM_MISC_MM_BERR_CFG1_OFFSET (0x144)
#define MM_MISC_REG_BERR_CLR MM_MISC_REG_BERR_CLR
#define MM_MISC_REG_BERR_CLR_POS (0U)
#define MM_MISC_REG_BERR_CLR_LEN (1U)
#define MM_MISC_REG_BERR_CLR_MSK (((1U << MM_MISC_REG_BERR_CLR_LEN) - 1) << MM_MISC_REG_BERR_CLR_POS)
#define MM_MISC_REG_BERR_CLR_UMSK (~(((1U << MM_MISC_REG_BERR_CLR_LEN) - 1) << MM_MISC_REG_BERR_CLR_POS))
#define MM_MISC_REG_CODEC_BERR_CLR MM_MISC_REG_CODEC_BERR_CLR
#define MM_MISC_REG_CODEC_BERR_CLR_POS (1U)
#define MM_MISC_REG_CODEC_BERR_CLR_LEN (1U)
#define MM_MISC_REG_CODEC_BERR_CLR_MSK (((1U << MM_MISC_REG_CODEC_BERR_CLR_LEN) - 1) << MM_MISC_REG_CODEC_BERR_CLR_POS)
#define MM_MISC_REG_CODEC_BERR_CLR_UMSK (~(((1U << MM_MISC_REG_CODEC_BERR_CLR_LEN) - 1) << MM_MISC_REG_CODEC_BERR_CLR_POS))
#define MM_MISC_REG_MMCPU_BERR_CLR MM_MISC_REG_MMCPU_BERR_CLR
#define MM_MISC_REG_MMCPU_BERR_CLR_POS (2U)
#define MM_MISC_REG_MMCPU_BERR_CLR_LEN (1U)
#define MM_MISC_REG_MMCPU_BERR_CLR_MSK (((1U << MM_MISC_REG_MMCPU_BERR_CLR_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_CLR_POS)
#define MM_MISC_REG_MMCPU_BERR_CLR_UMSK (~(((1U << MM_MISC_REG_MMCPU_BERR_CLR_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_CLR_POS))
#define MM_MISC_REG_MMINFRA_BERR_CLR MM_MISC_REG_MMINFRA_BERR_CLR
#define MM_MISC_REG_MMINFRA_BERR_CLR_POS (3U)
#define MM_MISC_REG_MMINFRA_BERR_CLR_LEN (1U)
#define MM_MISC_REG_MMINFRA_BERR_CLR_MSK (((1U << MM_MISC_REG_MMINFRA_BERR_CLR_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_CLR_POS)
#define MM_MISC_REG_MMINFRA_BERR_CLR_UMSK (~(((1U << MM_MISC_REG_MMINFRA_BERR_CLR_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_CLR_POS))
#define MM_MISC_REG_BERR_LAST MM_MISC_REG_BERR_LAST
#define MM_MISC_REG_BERR_LAST_POS (8U)
#define MM_MISC_REG_BERR_LAST_LEN (1U)
#define MM_MISC_REG_BERR_LAST_MSK (((1U << MM_MISC_REG_BERR_LAST_LEN) - 1) << MM_MISC_REG_BERR_LAST_POS)
#define MM_MISC_REG_BERR_LAST_UMSK (~(((1U << MM_MISC_REG_BERR_LAST_LEN) - 1) << MM_MISC_REG_BERR_LAST_POS))
#define MM_MISC_REG_CODEC_BERR_LAST MM_MISC_REG_CODEC_BERR_LAST
#define MM_MISC_REG_CODEC_BERR_LAST_POS (9U)
#define MM_MISC_REG_CODEC_BERR_LAST_LEN (1U)
#define MM_MISC_REG_CODEC_BERR_LAST_MSK (((1U << MM_MISC_REG_CODEC_BERR_LAST_LEN) - 1) << MM_MISC_REG_CODEC_BERR_LAST_POS)
#define MM_MISC_REG_CODEC_BERR_LAST_UMSK (~(((1U << MM_MISC_REG_CODEC_BERR_LAST_LEN) - 1) << MM_MISC_REG_CODEC_BERR_LAST_POS))
#define MM_MISC_REG_MMCPU_BERR_LAST MM_MISC_REG_MMCPU_BERR_LAST
#define MM_MISC_REG_MMCPU_BERR_LAST_POS (10U)
#define MM_MISC_REG_MMCPU_BERR_LAST_LEN (1U)
#define MM_MISC_REG_MMCPU_BERR_LAST_MSK (((1U << MM_MISC_REG_MMCPU_BERR_LAST_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_LAST_POS)
#define MM_MISC_REG_MMCPU_BERR_LAST_UMSK (~(((1U << MM_MISC_REG_MMCPU_BERR_LAST_LEN) - 1) << MM_MISC_REG_MMCPU_BERR_LAST_POS))
#define MM_MISC_REG_MMINFRA_BERR_LAST MM_MISC_REG_MMINFRA_BERR_LAST
#define MM_MISC_REG_MMINFRA_BERR_LAST_POS (11U)
#define MM_MISC_REG_MMINFRA_BERR_LAST_LEN (1U)
#define MM_MISC_REG_MMINFRA_BERR_LAST_MSK (((1U << MM_MISC_REG_MMINFRA_BERR_LAST_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_LAST_POS)
#define MM_MISC_REG_MMINFRA_BERR_LAST_UMSK (~(((1U << MM_MISC_REG_MMINFRA_BERR_LAST_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_LAST_POS))
#define MM_MISC_STS_BERR MM_MISC_STS_BERR
#define MM_MISC_STS_BERR_POS (16U)
#define MM_MISC_STS_BERR_LEN (1U)
#define MM_MISC_STS_BERR_MSK (((1U << MM_MISC_STS_BERR_LEN) - 1) << MM_MISC_STS_BERR_POS)
#define MM_MISC_STS_BERR_UMSK (~(((1U << MM_MISC_STS_BERR_LEN) - 1) << MM_MISC_STS_BERR_POS))
#define MM_MISC_STS_CODEC_BERR MM_MISC_STS_CODEC_BERR
#define MM_MISC_STS_CODEC_BERR_POS (17U)
#define MM_MISC_STS_CODEC_BERR_LEN (1U)
#define MM_MISC_STS_CODEC_BERR_MSK (((1U << MM_MISC_STS_CODEC_BERR_LEN) - 1) << MM_MISC_STS_CODEC_BERR_POS)
#define MM_MISC_STS_CODEC_BERR_UMSK (~(((1U << MM_MISC_STS_CODEC_BERR_LEN) - 1) << MM_MISC_STS_CODEC_BERR_POS))
#define MM_MISC_STS_MMCPU_BERR MM_MISC_STS_MMCPU_BERR
#define MM_MISC_STS_MMCPU_BERR_POS (18U)
#define MM_MISC_STS_MMCPU_BERR_LEN (1U)
#define MM_MISC_STS_MMCPU_BERR_MSK (((1U << MM_MISC_STS_MMCPU_BERR_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_POS)
#define MM_MISC_STS_MMCPU_BERR_UMSK (~(((1U << MM_MISC_STS_MMCPU_BERR_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_POS))
#define MM_MISC_STS_MMINFRA_BERR MM_MISC_STS_MMINFRA_BERR
#define MM_MISC_STS_MMINFRA_BERR_POS (19U)
#define MM_MISC_STS_MMINFRA_BERR_LEN (1U)
#define MM_MISC_STS_MMINFRA_BERR_MSK (((1U << MM_MISC_STS_MMINFRA_BERR_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_POS)
#define MM_MISC_STS_MMINFRA_BERR_UMSK (~(((1U << MM_MISC_STS_MMINFRA_BERR_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_POS))
#define MM_MISC_STS_BERR_WRITE MM_MISC_STS_BERR_WRITE
#define MM_MISC_STS_BERR_WRITE_POS (24U)
#define MM_MISC_STS_BERR_WRITE_LEN (1U)
#define MM_MISC_STS_BERR_WRITE_MSK (((1U << MM_MISC_STS_BERR_WRITE_LEN) - 1) << MM_MISC_STS_BERR_WRITE_POS)
#define MM_MISC_STS_BERR_WRITE_UMSK (~(((1U << MM_MISC_STS_BERR_WRITE_LEN) - 1) << MM_MISC_STS_BERR_WRITE_POS))
#define MM_MISC_STS_CODEC_BERR_WRITE MM_MISC_STS_CODEC_BERR_WRITE
#define MM_MISC_STS_CODEC_BERR_WRITE_POS (25U)
#define MM_MISC_STS_CODEC_BERR_WRITE_LEN (1U)
#define MM_MISC_STS_CODEC_BERR_WRITE_MSK (((1U << MM_MISC_STS_CODEC_BERR_WRITE_LEN) - 1) << MM_MISC_STS_CODEC_BERR_WRITE_POS)
#define MM_MISC_STS_CODEC_BERR_WRITE_UMSK (~(((1U << MM_MISC_STS_CODEC_BERR_WRITE_LEN) - 1) << MM_MISC_STS_CODEC_BERR_WRITE_POS))
#define MM_MISC_STS_MMCPU_BERR_WRITE MM_MISC_STS_MMCPU_BERR_WRITE
#define MM_MISC_STS_MMCPU_BERR_WRITE_POS (26U)
#define MM_MISC_STS_MMCPU_BERR_WRITE_LEN (1U)
#define MM_MISC_STS_MMCPU_BERR_WRITE_MSK (((1U << MM_MISC_STS_MMCPU_BERR_WRITE_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_WRITE_POS)
#define MM_MISC_STS_MMCPU_BERR_WRITE_UMSK (~(((1U << MM_MISC_STS_MMCPU_BERR_WRITE_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_WRITE_POS))
#define MM_MISC_STS_MMINFRA_BERR_WRITE MM_MISC_STS_MMINFRA_BERR_WRITE
#define MM_MISC_STS_MMINFRA_BERR_WRITE_POS (27U)
#define MM_MISC_STS_MMINFRA_BERR_WRITE_LEN (1U)
#define MM_MISC_STS_MMINFRA_BERR_WRITE_MSK (((1U << MM_MISC_STS_MMINFRA_BERR_WRITE_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_WRITE_POS)
#define MM_MISC_STS_MMINFRA_BERR_WRITE_UMSK (~(((1U << MM_MISC_STS_MMINFRA_BERR_WRITE_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_WRITE_POS))
/* 0x148 : mm_berr_cfg2 */
#define MM_MISC_MM_BERR_CFG2_OFFSET (0x148)
#define MM_MISC_STS_BERR_SRC MM_MISC_STS_BERR_SRC
#define MM_MISC_STS_BERR_SRC_POS (0U)
#define MM_MISC_STS_BERR_SRC_LEN (3U)
#define MM_MISC_STS_BERR_SRC_MSK (((1U << MM_MISC_STS_BERR_SRC_LEN) - 1) << MM_MISC_STS_BERR_SRC_POS)
#define MM_MISC_STS_BERR_SRC_UMSK (~(((1U << MM_MISC_STS_BERR_SRC_LEN) - 1) << MM_MISC_STS_BERR_SRC_POS))
#define MM_MISC_STS_BERR_ID MM_MISC_STS_BERR_ID
#define MM_MISC_STS_BERR_ID_POS (8U)
#define MM_MISC_STS_BERR_ID_LEN (4U)
#define MM_MISC_STS_BERR_ID_MSK (((1U << MM_MISC_STS_BERR_ID_LEN) - 1) << MM_MISC_STS_BERR_ID_POS)
#define MM_MISC_STS_BERR_ID_UMSK (~(((1U << MM_MISC_STS_BERR_ID_LEN) - 1) << MM_MISC_STS_BERR_ID_POS))
#define MM_MISC_STS_CODEC_BERR_SRC MM_MISC_STS_CODEC_BERR_SRC
#define MM_MISC_STS_CODEC_BERR_SRC_POS (16U)
#define MM_MISC_STS_CODEC_BERR_SRC_LEN (3U)
#define MM_MISC_STS_CODEC_BERR_SRC_MSK (((1U << MM_MISC_STS_CODEC_BERR_SRC_LEN) - 1) << MM_MISC_STS_CODEC_BERR_SRC_POS)
#define MM_MISC_STS_CODEC_BERR_SRC_UMSK (~(((1U << MM_MISC_STS_CODEC_BERR_SRC_LEN) - 1) << MM_MISC_STS_CODEC_BERR_SRC_POS))
#define MM_MISC_STS_CODEC_BERR_ID MM_MISC_STS_CODEC_BERR_ID
#define MM_MISC_STS_CODEC_BERR_ID_POS (24U)
#define MM_MISC_STS_CODEC_BERR_ID_LEN (1U)
#define MM_MISC_STS_CODEC_BERR_ID_MSK (((1U << MM_MISC_STS_CODEC_BERR_ID_LEN) - 1) << MM_MISC_STS_CODEC_BERR_ID_POS)
#define MM_MISC_STS_CODEC_BERR_ID_UMSK (~(((1U << MM_MISC_STS_CODEC_BERR_ID_LEN) - 1) << MM_MISC_STS_CODEC_BERR_ID_POS))
/* 0x14C : mm_berr_cfg3 */
#define MM_MISC_MM_BERR_CFG3_OFFSET (0x14C)
#define MM_MISC_STS_MMCPU_BERR_SRC MM_MISC_STS_MMCPU_BERR_SRC
#define MM_MISC_STS_MMCPU_BERR_SRC_POS (0U)
#define MM_MISC_STS_MMCPU_BERR_SRC_LEN (1U)
#define MM_MISC_STS_MMCPU_BERR_SRC_MSK (((1U << MM_MISC_STS_MMCPU_BERR_SRC_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_SRC_POS)
#define MM_MISC_STS_MMCPU_BERR_SRC_UMSK (~(((1U << MM_MISC_STS_MMCPU_BERR_SRC_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_SRC_POS))
#define MM_MISC_STS_MMCPU_BERR_ID MM_MISC_STS_MMCPU_BERR_ID
#define MM_MISC_STS_MMCPU_BERR_ID_POS (8U)
#define MM_MISC_STS_MMCPU_BERR_ID_LEN (4U)
#define MM_MISC_STS_MMCPU_BERR_ID_MSK (((1U << MM_MISC_STS_MMCPU_BERR_ID_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_ID_POS)
#define MM_MISC_STS_MMCPU_BERR_ID_UMSK (~(((1U << MM_MISC_STS_MMCPU_BERR_ID_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_ID_POS))
#define MM_MISC_STS_MMINFRA_BERR_SRC MM_MISC_STS_MMINFRA_BERR_SRC
#define MM_MISC_STS_MMINFRA_BERR_SRC_POS (16U)
#define MM_MISC_STS_MMINFRA_BERR_SRC_LEN (5U)
#define MM_MISC_STS_MMINFRA_BERR_SRC_MSK (((1U << MM_MISC_STS_MMINFRA_BERR_SRC_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_SRC_POS)
#define MM_MISC_STS_MMINFRA_BERR_SRC_UMSK (~(((1U << MM_MISC_STS_MMINFRA_BERR_SRC_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_SRC_POS))
#define MM_MISC_STS_MMINFRA_BERR_ID MM_MISC_STS_MMINFRA_BERR_ID
#define MM_MISC_STS_MMINFRA_BERR_ID_POS (24U)
#define MM_MISC_STS_MMINFRA_BERR_ID_LEN (6U)
#define MM_MISC_STS_MMINFRA_BERR_ID_MSK (((1U << MM_MISC_STS_MMINFRA_BERR_ID_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_ID_POS)
#define MM_MISC_STS_MMINFRA_BERR_ID_UMSK (~(((1U << MM_MISC_STS_MMINFRA_BERR_ID_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_ID_POS))
/* 0x150 : mm_berr_cfg4 */
#define MM_MISC_MM_BERR_CFG4_OFFSET (0x150)
#define MM_MISC_STS_BERR_ADDR MM_MISC_STS_BERR_ADDR
#define MM_MISC_STS_BERR_ADDR_POS (0U)
#define MM_MISC_STS_BERR_ADDR_LEN (32U)
#define MM_MISC_STS_BERR_ADDR_MSK (((1U << MM_MISC_STS_BERR_ADDR_LEN) - 1) << MM_MISC_STS_BERR_ADDR_POS)
#define MM_MISC_STS_BERR_ADDR_UMSK (~(((1U << MM_MISC_STS_BERR_ADDR_LEN) - 1) << MM_MISC_STS_BERR_ADDR_POS))
/* 0x154 : mm_berr_cfg5 */
#define MM_MISC_MM_BERR_CFG5_OFFSET (0x154)
#define MM_MISC_STS_CODEC_BERR_ADDR MM_MISC_STS_CODEC_BERR_ADDR
#define MM_MISC_STS_CODEC_BERR_ADDR_POS (0U)
#define MM_MISC_STS_CODEC_BERR_ADDR_LEN (32U)
#define MM_MISC_STS_CODEC_BERR_ADDR_MSK (((1U << MM_MISC_STS_CODEC_BERR_ADDR_LEN) - 1) << MM_MISC_STS_CODEC_BERR_ADDR_POS)
#define MM_MISC_STS_CODEC_BERR_ADDR_UMSK (~(((1U << MM_MISC_STS_CODEC_BERR_ADDR_LEN) - 1) << MM_MISC_STS_CODEC_BERR_ADDR_POS))
/* 0x158 : mm_berr_cfg6 */
#define MM_MISC_MM_BERR_CFG6_OFFSET (0x158)
#define MM_MISC_STS_MMCPU_BERR_ADDR MM_MISC_STS_MMCPU_BERR_ADDR
#define MM_MISC_STS_MMCPU_BERR_ADDR_POS (0U)
#define MM_MISC_STS_MMCPU_BERR_ADDR_LEN (32U)
#define MM_MISC_STS_MMCPU_BERR_ADDR_MSK (((1U << MM_MISC_STS_MMCPU_BERR_ADDR_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_ADDR_POS)
#define MM_MISC_STS_MMCPU_BERR_ADDR_UMSK (~(((1U << MM_MISC_STS_MMCPU_BERR_ADDR_LEN) - 1) << MM_MISC_STS_MMCPU_BERR_ADDR_POS))
/* 0x15C : mm_berr_cfg7 */
#define MM_MISC_MM_BERR_CFG7_OFFSET (0x15C)
#define MM_MISC_STS_MMINFRA_BERR_ADDR MM_MISC_STS_MMINFRA_BERR_ADDR
#define MM_MISC_STS_MMINFRA_BERR_ADDR_POS (0U)
#define MM_MISC_STS_MMINFRA_BERR_ADDR_LEN (32U)
#define MM_MISC_STS_MMINFRA_BERR_ADDR_MSK (((1U << MM_MISC_STS_MMINFRA_BERR_ADDR_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_ADDR_POS)
#define MM_MISC_STS_MMINFRA_BERR_ADDR_UMSK (~(((1U << MM_MISC_STS_MMINFRA_BERR_ADDR_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_ADDR_POS))
struct mm_misc_reg {
/* 0x0 : CPU0_Boot */
union {
struct {
uint32_t reg_cpu0_rvba : 32; /* [31: 0], r/w, 0x3eff0000 */
} BF;
uint32_t WORD;
} CPU0_Boot;
/* 0x4 reserved */
uint8_t RESERVED0x4[4];
/* 0x8 : CPU_cfg */
union {
struct {
uint32_t reg_cpu0_apb_base : 13; /* [12: 0], r/w, 0x1c */
uint32_t reserved_13_27 : 15; /* [27:13], rsvd, 0x0 */
uint32_t cpu0_ndm_rstn_en : 1; /* [ 28], r/w, 0x0 */
uint32_t cpu0_hart_rstn_en : 1; /* [ 29], r/w, 0x0 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
} BF;
uint32_t WORD;
} CPU_cfg;
/* 0xC : CPU_sts1 */
union {
struct {
uint32_t reserved_0_3 : 4; /* [ 3: 0], rsvd, 0x0 */
uint32_t cpu0_lpmd_b : 2; /* [ 5: 4], r, 0x0 */
uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
uint32_t cpu0_retire_pc_39_32 : 8; /* [23:16], r, 0x0 */
uint32_t cpu0_retire : 1; /* [ 24], r, 0x0 */
uint32_t cpu0_pad_halted : 1; /* [ 25], r, 0x0 */
uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */
uint32_t cpu0_ndm_rstn_req : 1; /* [ 28], r, 0x0 */
uint32_t cpu0_hart_rstn_req : 1; /* [ 29], r, 0x0 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
} BF;
uint32_t WORD;
} CPU_sts1;
/* 0x10 : CPU_sts2 */
union {
struct {
uint32_t cpu0_retire_pc_31_0 : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} CPU_sts2;
/* 0x14 reserved */
uint8_t RESERVED0x14[4];
/* 0x18 : CPU_RTC */
union {
struct {
uint32_t c906_rtc_div : 10; /* [ 9: 0], r/w, 0xa */
uint32_t reserved_10_29 : 20; /* [29:10], rsvd, 0x0 */
uint32_t c906_rtc_rst : 1; /* [ 30], r/w, 0x0 */
uint32_t c906_rtc_en : 1; /* [ 31], r/w, 0x0 */
} BF;
uint32_t WORD;
} CPU_RTC;
/* 0x1C : tzc_mmsys_misc */
union {
struct {
uint32_t tzc_mm_cpu0_lock : 1; /* [ 0], r, 0x0 */
uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
uint32_t tzc_mm_sram_lock : 1; /* [ 2], r, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
} BF;
uint32_t WORD;
} tzc_mmsys_misc;
/* 0x20 : peri_apb_ctrl */
union {
struct {
uint32_t reg_mminfra_berr_int_en : 1; /* [ 0], r/w, 0x0 */
uint32_t reg_berr_int_en : 1; /* [ 1], r/w, 0x0 */
uint32_t reg_codec_berr_int_en : 1; /* [ 2], r/w, 0x0 */
uint32_t reg_mmcpu_berr_int_en : 1; /* [ 3], r/w, 0x0 */
uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
uint32_t reg_mm_x2hs_sp_bypass : 1; /* [ 8], r/w, 0x0 */
uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */
uint32_t rg_pclk_force_on : 16; /* [31:16], r/w, 0x0 */
} BF;
uint32_t WORD;
} peri_apb_ctrl;
/* 0x24 reserved */
uint8_t RESERVED0x24[8];
/* 0x2C : mm_infra_qos_ctrl */
union {
struct {
uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
uint32_t reg_mmcpu0_awqos : 1; /* [ 2], r/w, 0x0 */
uint32_t reg_mmcpu0_arqos : 1; /* [ 3], r/w, 0x0 */
uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */
uint32_t reg_h_wthre_mm2conn : 2; /* [17:16], r/w, 0x0 */
uint32_t reg_h_wthre_conn2mm : 2; /* [19:18], r/w, 0x0 */
uint32_t reg_x_wthre_mmhw2pA : 2; /* [21:20], r/w, 0x0 */
uint32_t reg_x_wthre_mmhw2ext : 2; /* [23:22], r/w, 0x0 */
uint32_t reg_x_wthre_pUHS : 2; /* [25:24], r/w, 0x0 */
uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
} BF;
uint32_t WORD;
} mm_infra_qos_ctrl;
/* 0x30 reserved */
uint8_t RESERVED0x30[16];
/* 0x40 : dma_clk_ctrl */
union {
struct {
uint32_t dma_clk_en : 8; /* [ 7: 0], r/w, 0xff */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
} BF;
uint32_t WORD;
} dma_clk_ctrl;
/* 0x44 reserved */
uint8_t RESERVED0x44[12];
/* 0x50 : vram_ctrl */
union {
struct {
uint32_t reg_sysram_set : 1; /* [ 0], w1p, 0x0 */
uint32_t reg_h2pf_sram_rel : 2; /* [ 2: 1], r/w, 0x0 */
uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
uint32_t reg_vram_sram_rel : 1; /* [ 4], r/w, 0x0 */
uint32_t reserved_5 : 1; /* [ 5], rsvd, 0x0 */
uint32_t reg_sub_sram_rel : 1; /* [ 6], r/w, 0x0 */
uint32_t reg_blai_sram_rel : 1; /* [ 7], r/w, 0x0 */
uint32_t reg_h2pf_sram_sel : 3; /* [10: 8], r, 0x0 */
uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
uint32_t reg_vram_sram_sel : 1; /* [ 12], r, 0x0 */
uint32_t reserved_13 : 1; /* [ 13], rsvd, 0x0 */
uint32_t reg_sub_sram_sel : 1; /* [ 14], r, 0x0 */
uint32_t reg_blai_sram_sel : 1; /* [ 15], r, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
} BF;
uint32_t WORD;
} vram_ctrl;
/* 0x54 reserved */
uint8_t RESERVED0x54[12];
/* 0x60 : sram_parm */
union {
struct {
uint32_t reg_sram_cpu_ram_dvs : 4; /* [ 3: 0], r/w, 0xc */
uint32_t reg_sram_cpu_ram_dvse : 1; /* [ 4], r/w, 0x0 */
uint32_t reg_sram_cpu_ram_nap : 1; /* [ 5], r/w, 0x0 */
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
uint32_t reg_sram_l2ram_dvs : 4; /* [11: 8], r/w, 0xc */
uint32_t reg_sram_l2ram_dvse : 1; /* [ 12], r/w, 0x0 */
uint32_t reg_sram_l2ram_nap : 1; /* [ 13], r/w, 0x0 */
uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
uint32_t reg_sram_cdc_ram_dvs : 4; /* [19:16], r/w, 0xc */
uint32_t reg_sram_cdc_ram_dvse : 1; /* [ 20], r/w, 0x0 */
uint32_t reg_sram_cdc_ram_nap : 1; /* [ 21], r/w, 0x0 */
uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
uint32_t reg_sram_sub_ram_dvs : 4; /* [27:24], r/w, 0xc */
uint32_t reg_sram_sub_ram_dvse : 1; /* [ 28], r/w, 0x0 */
uint32_t reg_sram_sub_ram_nap : 1; /* [ 29], r/w, 0x0 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
} BF;
uint32_t WORD;
} sram_parm;
/* 0x64 reserved */
uint8_t RESERVED0x64[60];
/* 0xA0 : MM_INT_STA0 */
union {
struct {
uint32_t mm_int_sta0 : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} MM_INT_STA0;
/* 0xA4 : MM_INT_MASK0 */
union {
struct {
uint32_t mm_int_mask0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} MM_INT_MASK0;
/* 0xA8 : MM_INT_CLR_0 */
union {
struct {
uint32_t mm_int_clr0 : 32; /* [31: 0], w1p, 0x0 */
} BF;
uint32_t WORD;
} MM_INT_CLR_0;
/* 0xAC : MM_INT_STA1 */
union {
struct {
uint32_t mm_int_sta1 : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} MM_INT_STA1;
/* 0xB0 : MM_INT_MASK1 */
union {
struct {
uint32_t mm_int_mask1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} MM_INT_MASK1;
/* 0xB4 : MM_INT_CLR_1 */
union {
struct {
uint32_t mm_int_clr1 : 32; /* [31: 0], w1p, 0x0 */
} BF;
uint32_t WORD;
} MM_INT_CLR_1;
/* 0xb8 reserved */
uint8_t RESERVED0xb8[56];
/* 0xF0 : mmsys_debug_sel */
union {
struct {
uint32_t mmsys_debug_sel : 4; /* [ 3: 0], r/w, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
} BF;
uint32_t WORD;
} mmsys_debug_sel;
/* 0xf4 reserved */
uint8_t RESERVED0xf4[8];
/* 0xFC : mmsys_misc_dummy */
union {
struct {
uint32_t PIR_ctrl_o : 1; /* [ 0], r/w, 0x0 */
uint32_t Light_sensor_ctrl_o : 1; /* [ 1], r/w, 0x0 */
uint32_t IR_cut_ctrl_o : 1; /* [ 2], r/w, 0x0 */
uint32_t dvp_sensor_pwdn : 1; /* [ 3], r/w, 0x0 */
uint32_t dummy_reg : 28; /* [31: 4], r/w, 0xfff0000 */
} BF;
uint32_t WORD;
} mmsys_misc_dummy;
/* 0x100 : DDR_debug */
union {
struct {
uint32_t ddr_calib_done : 1; /* [ 0], r, 0x0 */
uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
} BF;
uint32_t WORD;
} DDR_debug;
/* 0x104 reserved */
uint8_t RESERVED0x104[60];
/* 0x140 : mm_berr_cfg0 */
union {
struct {
uint32_t reg_berr_en : 3; /* [ 2: 0], r/w, 0x7 */
uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */
uint32_t reg_codec_berr_en : 3; /* [10: 8], r/w, 0x7 */
uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */
uint32_t reg_mmcpu_berr_en : 1; /* [ 16], r/w, 0x1 */
uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */
uint32_t reg_mminfra_berr_en : 5; /* [28:24], r/w, 0x1f */
uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */
} BF;
uint32_t WORD;
} mm_berr_cfg0;
/* 0x144 : mm_berr_cfg1 */
union {
struct {
uint32_t reg_berr_clr : 1; /* [ 0], r/w, 0x0 */
uint32_t reg_codec_berr_clr : 1; /* [ 1], r/w, 0x0 */
uint32_t reg_mmcpu_berr_clr : 1; /* [ 2], r/w, 0x0 */
uint32_t reg_mminfra_berr_clr : 1; /* [ 3], r/w, 0x0 */
uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
uint32_t reg_berr_last : 1; /* [ 8], r/w, 0x0 */
uint32_t reg_codec_berr_last : 1; /* [ 9], r/w, 0x0 */
uint32_t reg_mmcpu_berr_last : 1; /* [ 10], r/w, 0x0 */
uint32_t reg_mminfra_berr_last : 1; /* [ 11], r/w, 0x0 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t sts_berr : 1; /* [ 16], r, 0x0 */
uint32_t sts_codec_berr : 1; /* [ 17], r, 0x0 */
uint32_t sts_mmcpu_berr : 1; /* [ 18], r, 0x0 */
uint32_t sts_mminfra_berr : 1; /* [ 19], r, 0x0 */
uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */
uint32_t sts_berr_write : 1; /* [ 24], r, 0x0 */
uint32_t sts_codec_berr_write : 1; /* [ 25], r, 0x0 */
uint32_t sts_mmcpu_berr_write : 1; /* [ 26], r, 0x0 */
uint32_t sts_mminfra_berr_write : 1; /* [ 27], r, 0x0 */
uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
} BF;
uint32_t WORD;
} mm_berr_cfg1;
/* 0x148 : mm_berr_cfg2 */
union {
struct {
uint32_t sts_berr_src : 3; /* [ 2: 0], r, 0x0 */
uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */
uint32_t sts_berr_id : 4; /* [11: 8], r, 0x0 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t sts_codec_berr_src : 3; /* [18:16], r, 0x0 */
uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */
uint32_t sts_codec_berr_id : 1; /* [ 24], r, 0x0 */
uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
} BF;
uint32_t WORD;
} mm_berr_cfg2;
/* 0x14C : mm_berr_cfg3 */
union {
struct {
uint32_t sts_mmcpu_berr_src : 1; /* [ 0], r, 0x0 */
uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */
uint32_t sts_mmcpu_berr_id : 4; /* [11: 8], r, 0x0 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t sts_mminfra_berr_src : 5; /* [20:16], r, 0x0 */
uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */
uint32_t sts_mminfra_berr_id : 6; /* [29:24], r, 0x0 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
} BF;
uint32_t WORD;
} mm_berr_cfg3;
/* 0x150 : mm_berr_cfg4 */
union {
struct {
uint32_t sts_berr_addr : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} mm_berr_cfg4;
/* 0x154 : mm_berr_cfg5 */
union {
struct {
uint32_t sts_codec_berr_addr : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} mm_berr_cfg5;
/* 0x158 : mm_berr_cfg6 */
union {
struct {
uint32_t sts_mmcpu_berr_addr : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} mm_berr_cfg6;
/* 0x15C : mm_berr_cfg7 */
union {
struct {
uint32_t sts_mminfra_berr_addr : 32; /* [31: 0], r, 0x0 */
} BF;
uint32_t WORD;
} mm_berr_cfg7;
};
#endif /* __MM_MISC_REG_H__ */

2626
include/bl808/pds_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

1549
include/bl808/psram_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

1566
include/bl808/psram_uhs_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

208
include/bl808/pwm_v2_reg.h Normal file
View File

@ -0,0 +1,208 @@
/**
******************************************************************************
* @file pwm_reg.h
* @version V1.0
* @date 2022-08-15
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_PWM_V2_H__
#define __HARDWARE_PWM_V2_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define PWM_INT_CONFIG_OFFSET (0x0) /* pwm_int_config */
#define PWM_MC0_CONFIG0_OFFSET (0x40) /* pwm_mc0_config0 */
#define PWM_MC0_CONFIG1_OFFSET (0x44) /* pwm_mc0_config1 */
#define PWM_MC0_PERIOD_OFFSET (0x48) /* pwm_mc0_period */
#define PWM_MC0_DEAD_TIME_OFFSET (0x4C) /* pwm_mc0_dead_time */
#define PWM_MC0_CH0_THRE_OFFSET (0x50) /* pwm_mc0_ch0_thre */
#define PWM_MC0_CH1_THRE_OFFSET (0x54) /* pwm_mc0_ch1_thre */
#define PWM_MC0_CH2_THRE_OFFSET (0x58) /* pwm_mc0_ch2_thre */
#define PWM_MC0_CH3_THRE_OFFSET (0x5C) /* pwm_mc0_ch3_thre */
#define PWM_MC0_INT_STS_OFFSET (0x60) /* pwm_mc0_int_sts */
#define PWM_MC0_INT_MASK_OFFSET (0x64) /* pwm_mc0_int_mask */
#define PWM_MC0_INT_CLEAR_OFFSET (0x68) /* pwm_mc0_int_clear */
#define PWM_MC0_INT_EN_OFFSET (0x6C) /* pwm_mc0_int_en */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : pwm_int_config */
#define PWM0_INT_STS (1 << 0U)
#define PWM1_INT_STS (1 << 1U)
#define PWM0_INT_CLR (1 << 8U)
#define PWM1_INT_CLR (1 << 9U)
/* 0x40 : pwm_mc0_config0 */
#define PWM_CLK_DIV_SHIFT (0U)
#define PWM_CLK_DIV_MASK (0xffff << PWM_CLK_DIV_SHIFT)
#define PWM_STOP_ON_REPT (1 << 19U)
#define PWM_ADC_TRG_SRC_SHIFT (20U)
#define PWM_ADC_TRG_SRC_MASK (0xf << PWM_ADC_TRG_SRC_SHIFT)
#define PWM_SW_BREAK_EN (1 << 24U)
#define PWM_EXT_BREAK_EN (1 << 25U)
#define PWM_EXT_BREAK_PL (1 << 26U)
#define PWM_STOP_EN (1 << 27U)
#define PWM_STOP_MODE (1 << 28U)
#define PWM_STS_STOP (1 << 29U)
#define PWM_REG_CLK_SEL_SHIFT (30U)
#define PWM_REG_CLK_SEL_MASK (0x3 << PWM_REG_CLK_SEL_SHIFT)
/* 0x44 : pwm_mc0_config1 */
#define PWM_CH0_PEN (1 << 0U)
#define PWM_CH0_PSI (1 << 1U)
#define PWM_CH0_NEN (1 << 2U)
#define PWM_CH0_NSI (1 << 3U)
#define PWM_CH1_PEN (1 << 4U)
#define PWM_CH1_PSI (1 << 5U)
#define PWM_CH1_NEN (1 << 6U)
#define PWM_CH1_NSI (1 << 7U)
#define PWM_CH2_PEN (1 << 8U)
#define PWM_CH2_PSI (1 << 9U)
#define PWM_CH2_NEN (1 << 10U)
#define PWM_CH2_NSI (1 << 11U)
#define PWM_CH3_PEN (1 << 12U)
#define PWM_CH3_PSI (1 << 13U)
#define PWM_CH3_NEN (1 << 14U)
#define PWM_CH3_NSI (1 << 15U)
#define PWM_CH0_PPL (1 << 16U)
#define PWM_CH0_NPL (1 << 17U)
#define PWM_CH1_PPL (1 << 18U)
#define PWM_CH1_NPL (1 << 19U)
#define PWM_CH2_PPL (1 << 20U)
#define PWM_CH2_NPL (1 << 21U)
#define PWM_CH3_PPL (1 << 22U)
#define PWM_CH3_NPL (1 << 23U)
#define PWM_CH0_PBS (1 << 24U)
#define PWM_CH0_NBS (1 << 25U)
#define PWM_CH1_PBS (1 << 26U)
#define PWM_CH1_NBS (1 << 27U)
#define PWM_CH2_PBS (1 << 28U)
#define PWM_CH2_NBS (1 << 29U)
#define PWM_CH3_PBS (1 << 30U)
#define PWM_CH3_NBS (1 << 31U)
/* 0x48 : pwm_mc0_period */
#define PWM_PERIOD_SHIFT (0U)
#define PWM_PERIOD_MASK (0xffff << PWM_PERIOD_SHIFT)
#define PWM_INT_PERIOD_CNT_SHIFT (16U)
#define PWM_INT_PERIOD_CNT_MASK (0xffff << PWM_INT_PERIOD_CNT_SHIFT)
/* 0x4C : pwm_mc0_dead_time */
#define PWM_CH0_DTG_SHIFT (0U)
#define PWM_CH0_DTG_MASK (0xff << PWM_CH0_DTG_SHIFT)
#define PWM_CH1_DTG_SHIFT (8U)
#define PWM_CH1_DTG_MASK (0xff << PWM_CH1_DTG_SHIFT)
#define PWM_CH2_DTG_SHIFT (16U)
#define PWM_CH2_DTG_MASK (0xff << PWM_CH2_DTG_SHIFT)
#define PWM_CH3_DTG_SHIFT (24U)
#define PWM_CH3_DTG_MASK (0xff << PWM_CH3_DTG_SHIFT)
/* 0x50 : pwm_mc0_ch0_thre */
#define PWM_CH0_THREL_SHIFT (0U)
#define PWM_CH0_THREL_MASK (0xffff << PWM_CH0_THREL_SHIFT)
#define PWM_CH0_THREH_SHIFT (16U)
#define PWM_CH0_THREH_MASK (0xffff << PWM_CH0_THREH_SHIFT)
/* 0x54 : pwm_mc0_ch1_thre */
#define PWM_CH1_THREL_SHIFT (0U)
#define PWM_CH1_THREL_MASK (0xffff << PWM_CH1_THREL_SHIFT)
#define PWM_CH1_THREH_SHIFT (16U)
#define PWM_CH1_THREH_MASK (0xffff << PWM_CH1_THREH_SHIFT)
/* 0x58 : pwm_mc0_ch2_thre */
#define PWM_CH2_THREL_SHIFT (0U)
#define PWM_CH2_THREL_MASK (0xffff << PWM_CH2_THREL_SHIFT)
#define PWM_CH2_THREH_SHIFT (16U)
#define PWM_CH2_THREH_MASK (0xffff << PWM_CH2_THREH_SHIFT)
/* 0x5C : pwm_mc0_ch3_thre */
#define PWM_CH3_THREL_SHIFT (0U)
#define PWM_CH3_THREL_MASK (0xffff << PWM_CH3_THREL_SHIFT)
#define PWM_CH3_THREH_SHIFT (16U)
#define PWM_CH3_THREH_MASK (0xffff << PWM_CH3_THREH_SHIFT)
/* 0x60 : pwm_mc0_int_sts */
#define PWM_CH0L_INT (1 << 0U)
#define PWM_CH0H_INT (1 << 1U)
#define PWM_CH1L_INT (1 << 2U)
#define PWM_CH1H_INT (1 << 3U)
#define PWM_CH2L_INT (1 << 4U)
#define PWM_CH2H_INT (1 << 5U)
#define PWM_CH3L_INT (1 << 6U)
#define PWM_CH3H_INT (1 << 7U)
#define PWM_PRDE_INT (1 << 8U)
#define PWM_BRK_INT (1 << 9U)
#define PWM_REPT_INT (1 << 10U)
/* 0x64 : pwm_mc0_int_mask */
#define PWM_CR_PWM_CH0L_MASK (1 << 0U)
#define PWM_CR_PWM_CH0H_MASK (1 << 1U)
#define PWM_CR_PWM_CH1L_MASK (1 << 2U)
#define PWM_CR_PWM_CH1H_MASK (1 << 3U)
#define PWM_CR_PWM_CH2L_MASK (1 << 4U)
#define PWM_CR_PWM_CH2H_MASK (1 << 5U)
#define PWM_CR_PWM_CH3L_MASK (1 << 6U)
#define PWM_CR_PWM_CH3H_MASK (1 << 7U)
#define PWM_CR_PWM_PRDE_MASK (1 << 8U)
#define PWM_CR_PWM_BRK_MASK (1 << 9U)
#define PWM_CR_PWM_REPT_MASK (1 << 10U)
/* 0x68 : pwm_mc0_int_clear */
#define PWM_CR_PWM_CH0L_CLR (1 << 0U)
#define PWM_CR_PWM_CH0H_CLR (1 << 1U)
#define PWM_CR_PWM_CH1L_CLR (1 << 2U)
#define PWM_CR_PWM_CH1H_CLR (1 << 3U)
#define PWM_CR_PWM_CH2L_CLR (1 << 4U)
#define PWM_CR_PWM_CH2H_CLR (1 << 5U)
#define PWM_CR_PWM_CH3L_CLR (1 << 6U)
#define PWM_CR_PWM_CH3H_CLR (1 << 7U)
#define PWM_CR_PWM_PRDE_CLR (1 << 8U)
#define PWM_CR_PWM_BRK_CLR (1 << 9U)
#define PWM_CR_PWM_REPT_CLR (1 << 10U)
/* 0x6C : pwm_mc0_int_en */
#define PWM_CR_PWM_CH0L_EN (1 << 0U)
#define PWM_CR_PWM_CH0H_EN (1 << 1U)
#define PWM_CR_PWM_CH1L_EN (1 << 2U)
#define PWM_CR_PWM_CH1H_EN (1 << 3U)
#define PWM_CR_PWM_CH2L_EN (1 << 4U)
#define PWM_CR_PWM_CH2H_EN (1 << 5U)
#define PWM_CR_PWM_CH3L_EN (1 << 6U)
#define PWM_CR_PWM_CH3H_EN (1 << 7U)
#define PWM_CR_PWM_PRDE_EN (1 << 8U)
#define PWM_CR_PWM_BRK_EN (1 << 9U)
#define PWM_CR_PWM_REPT_EN (1 << 10U)
#endif /* __HARDWARE_PWM_V2_H__ */

92
include/bl808/rtc_reg.h Normal file
View File

@ -0,0 +1,92 @@
/**
******************************************************************************
* @file rtc_reg.h
* @version V1.0
* @date 2022-08-05
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_RTC_H__
#define __HARDWARE_RTC_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define HBN_CTL_OFFSET (0x0) /* HBN_CTL */
#define HBN_TIME_L_OFFSET (0x4) /* HBN_TIME_L */
#define HBN_TIME_H_OFFSET (0x8) /* HBN_TIME_H */
#define HBN_RTC_TIME_L_OFFSET (0xC) /* RTC_TIME_L */
#define HBN_RTC_TIME_H_OFFSET (0x10) /* RTC_TIME_H */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : HBN_CTL */
#define HBN_RTC_CTL_SHIFT (0U)
#define HBN_RTC_CTL_MASK (0x7f << HBN_RTC_CTL_SHIFT)
#define HBN_MODE (1 << 7U)
#define HBN_TRAP_MODE (1 << 8U)
#define HBN_PWRDN_HBN_CORE (1 << 9U)
#define HBN_PWRDN_HBN_RTC (1 << 11U)
#define HBN_SW_RST (1 << 12U)
#define HBN_DIS_PWR_OFF_LDO11 (1 << 13U)
#define HBN_DIS_PWR_OFF_LDO11_RT (1 << 14U)
#define HBN_LDO11_RT_VOUT_SEL_SHIFT (15U)
#define HBN_LDO11_RT_VOUT_SEL_MASK (0xf << HBN_LDO11_RT_VOUT_SEL_SHIFT)
#define HBN_LDO11_AON_VOUT_SEL_SHIFT (19U)
#define HBN_LDO11_AON_VOUT_SEL_MASK (0xf << HBN_LDO11_AON_VOUT_SEL_SHIFT)
#define HBN_PU_DCDC18_AON (1 << 23U)
#define HBN_RTC_DLY_OPTION (1 << 24U)
#define HBN_PWR_ON_OPTION (1 << 25U)
#define HBN_SRAM_SLP_OPTION (1 << 26U)
#define HBN_SRAM_SLP (1 << 27U)
#define HBN_STATE_SHIFT (28U)
#define HBN_STATE_MASK (0xf << HBN_STATE_SHIFT)
/* 0x4 : HBN_TIME_L */
#define HBN_TIME_L_SHIFT (0U)
#define HBN_TIME_L_MASK (0xffffffff << HBN_TIME_L_SHIFT)
/* 0x8 : HBN_TIME_H */
#define HBN_TIME_H_SHIFT (0U)
#define HBN_TIME_H_MASK (0xff << HBN_TIME_H_SHIFT)
/* 0xC : RTC_TIME_L */
#define HBN_RTC_TIME_LATCH_L_SHIFT (0U)
#define HBN_RTC_TIME_LATCH_L_MASK (0xffffffff << HBN_RTC_TIME_LATCH_L_SHIFT)
/* 0x10 : RTC_TIME_H */
#define HBN_RTC_TIME_LATCH_H_SHIFT (0U)
#define HBN_RTC_TIME_LATCH_H_MASK (0xff << HBN_RTC_TIME_LATCH_H_SHIFT)
#define HBN_RTC_TIME_LATCH (1 << 31U)
#endif /* __HARDWARE_RTC_H__ */

2730
include/bl808/sdh_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

558
include/bl808/sec_eng_reg.h Normal file
View File

@ -0,0 +1,558 @@
/**
******************************************************************************
* @file sec_eng_reg.h
* @version V1.0
* @date 2022-08-15
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_SEC_ENG_H__
#define __HARDWARE_SEC_ENG_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define SEC_ENG_SE_SHA_0_CTRL_OFFSET (0x0) /* se_sha_0_ctrl */
#define SEC_ENG_SE_SHA_0_MSA_OFFSET (0x4) /* se_sha_0_msa */
#define SEC_ENG_SE_SHA_0_STATUS_OFFSET (0x8) /* se_sha_0_status */
#define SEC_ENG_SE_SHA_0_ENDIAN_OFFSET (0xC) /* se_sha_0_endian */
#define SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET (0x10) /* se_sha_0_hash_l_0 */
#define SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET (0x14) /* se_sha_0_hash_l_1 */
#define SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET (0x18) /* se_sha_0_hash_l_2 */
#define SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET (0x1C) /* se_sha_0_hash_l_3 */
#define SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET (0x20) /* se_sha_0_hash_l_4 */
#define SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET (0x24) /* se_sha_0_hash_l_5 */
#define SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET (0x28) /* se_sha_0_hash_l_6 */
#define SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET (0x2C) /* se_sha_0_hash_l_7 */
#define SEC_ENG_SE_SHA_0_HASH_H_0_OFFSET (0x30) /* se_sha_0_hash_h_0 */
#define SEC_ENG_SE_SHA_0_HASH_H_1_OFFSET (0x34) /* se_sha_0_hash_h_1 */
#define SEC_ENG_SE_SHA_0_HASH_H_2_OFFSET (0x38) /* se_sha_0_hash_h_2 */
#define SEC_ENG_SE_SHA_0_HASH_H_3_OFFSET (0x3C) /* se_sha_0_hash_h_3 */
#define SEC_ENG_SE_SHA_0_HASH_H_4_OFFSET (0x40) /* se_sha_0_hash_h_4 */
#define SEC_ENG_SE_SHA_0_HASH_H_5_OFFSET (0x44) /* se_sha_0_hash_h_5 */
#define SEC_ENG_SE_SHA_0_HASH_H_6_OFFSET (0x48) /* se_sha_0_hash_h_6 */
#define SEC_ENG_SE_SHA_0_HASH_H_7_OFFSET (0x4C) /* se_sha_0_hash_h_7 */
#define SEC_ENG_SE_SHA_0_LINK_OFFSET (0x50) /* se_sha_0_link */
#define SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET (0xFC) /* se_sha_0_ctrl_prot */
#define SEC_ENG_SE_AES_0_CTRL_OFFSET (0x100) /* se_aes_0_ctrl */
#define SEC_ENG_SE_AES_0_MSA_OFFSET (0x104) /* se_aes_0_msa */
#define SEC_ENG_SE_AES_0_MDA_OFFSET (0x108) /* se_aes_0_mda */
#define SEC_ENG_SE_AES_0_STATUS_OFFSET (0x10C) /* se_aes_0_status */
#define SEC_ENG_SE_AES_0_IV_0_OFFSET (0x110) /* se_aes_0_iv_0 */
#define SEC_ENG_SE_AES_0_IV_1_OFFSET (0x114) /* se_aes_0_iv_1 */
#define SEC_ENG_SE_AES_0_IV_2_OFFSET (0x118) /* se_aes_0_iv_2 */
#define SEC_ENG_SE_AES_0_IV_3_OFFSET (0x11C) /* se_aes_0_iv_3 */
#define SEC_ENG_SE_AES_0_KEY_0_OFFSET (0x120) /* se_aes_0_key_0 */
#define SEC_ENG_SE_AES_0_KEY_1_OFFSET (0x124) /* se_aes_0_key_1 */
#define SEC_ENG_SE_AES_0_KEY_2_OFFSET (0x128) /* se_aes_0_key_2 */
#define SEC_ENG_SE_AES_0_KEY_3_OFFSET (0x12C) /* se_aes_0_key_3 */
#define SEC_ENG_SE_AES_0_KEY_4_OFFSET (0x130) /* se_aes_0_key_4 */
#define SEC_ENG_SE_AES_0_KEY_5_OFFSET (0x134) /* se_aes_0_key_5 */
#define SEC_ENG_SE_AES_0_KEY_6_OFFSET (0x138) /* se_aes_0_key_6 */
#define SEC_ENG_SE_AES_0_KEY_7_OFFSET (0x13C) /* se_aes_0_key_7 */
#define SEC_ENG_SE_AES_0_KEY_SEL_OFFSET (0x140) /* se_aes_0_key_sel */
#define SEC_ENG_SE_AES_1_KEY_SEL_OFFSET (0x144) /* se_aes_1_key_sel */
#define SEC_ENG_SE_AES_0_ENDIAN_OFFSET (0x148) /* se_aes_0_endian */
#define SEC_ENG_SE_AES_0_SBOOT_OFFSET (0x14C) /* se_aes_0_sboot */
#define SEC_ENG_SE_AES_0_LINK_OFFSET (0x150) /* se_aes_0_link */
#define SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET (0x1FC) /* se_aes_0_ctrl_prot */
#define SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET (0x200) /* se_trng_0_ctrl_0 */
#define SEC_ENG_SE_TRNG_0_STATUS_OFFSET (0x204) /* se_trng_0_status */
#define SEC_ENG_SE_TRNG_0_DOUT_0_OFFSET (0x208) /* se_trng_0_dout_0 */
#define SEC_ENG_SE_TRNG_0_DOUT_1_OFFSET (0x20C) /* se_trng_0_dout_1 */
#define SEC_ENG_SE_TRNG_0_DOUT_2_OFFSET (0x210) /* se_trng_0_dout_2 */
#define SEC_ENG_SE_TRNG_0_DOUT_3_OFFSET (0x214) /* se_trng_0_dout_3 */
#define SEC_ENG_SE_TRNG_0_DOUT_4_OFFSET (0x218) /* se_trng_0_dout_4 */
#define SEC_ENG_SE_TRNG_0_DOUT_5_OFFSET (0x21C) /* se_trng_0_dout_5 */
#define SEC_ENG_SE_TRNG_0_DOUT_6_OFFSET (0x220) /* se_trng_0_dout_6 */
#define SEC_ENG_SE_TRNG_0_DOUT_7_OFFSET (0x224) /* se_trng_0_dout_7 */
#define SEC_ENG_SE_TRNG_0_TEST_OFFSET (0x228) /* se_trng_0_test */
#define SEC_ENG_SE_TRNG_0_CTRL_1_OFFSET (0x22C) /* se_trng_0_ctrl_1 */
#define SEC_ENG_SE_TRNG_0_CTRL_2_OFFSET (0x230) /* se_trng_0_ctrl_2 */
#define SEC_ENG_SE_TRNG_0_CTRL_3_OFFSET (0x234) /* se_trng_0_ctrl_3 */
#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_OFFSET (0x240) /* se_trng_0_test_out_0 */
#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_OFFSET (0x244) /* se_trng_0_test_out_1 */
#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_OFFSET (0x248) /* se_trng_0_test_out_2 */
#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_OFFSET (0x24C) /* se_trng_0_test_out_3 */
#define SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET (0x2FC) /* se_trng_0_ctrl_prot */
#define SEC_ENG_SE_PKA_0_CTRL_0_OFFSET (0x300) /* se_pka_0_ctrl_0 */
#define SEC_ENG_SE_PKA_0_SEED_OFFSET (0x30C) /* se_pka_0_seed */
#define SEC_ENG_SE_PKA_0_CTRL_1_OFFSET (0x310) /* se_pka_0_ctrl_1 */
#define SEC_ENG_SE_PKA_0_RW_OFFSET (0x340) /* se_pka_0_rw */
#define SEC_ENG_SE_PKA_0_RW_BURST_OFFSET (0x360) /* se_pka_0_rw_burst */
#define SEC_ENG_SE_PKA_0_CTRL_PROT_OFFSET (0x3FC) /* se_pka_0_ctrl_prot */
#define SEC_ENG_SE_CDET_0_CTRL_0_OFFSET (0x400) /* se_cdet_0_ctrl_0 */
#define SEC_ENG_SE_CDET_0_CTRL_1_OFFSET (0x404) /* se_cdet_0_ctrl_1 */
#define SEC_ENG_SE_CDET_0_CTRL_2_OFFSET (0x408) /* se_cdet_0_ctrl_2 */
#define SEC_ENG_SE_CDET_0_CTRL_3_OFFSET (0x40C) /* se_cdet_0_ctrl_3 */
#define SEC_ENG_SE_CDET_0_CTRL_PROT_OFFSET (0x4FC) /* se_cdet_0_ctrl_prot */
#define SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET (0x500) /* se_gmac_0_ctrl_0 */
#define SEC_ENG_SE_GMAC_0_LCA_OFFSET (0x504) /* se_gmac_0_lca */
#define SEC_ENG_SE_GMAC_0_STATUS_OFFSET (0x508) /* se_gmac_0_status */
#define SEC_ENG_SE_GMAC_0_CTRL_PROT_OFFSET (0x5FC) /* se_gmac_0_ctrl_prot */
#define SEC_ENG_SE_CTRL_PROT_RD_OFFSET (0xF00) /* se_ctrl_prot_rd */
#define SEC_ENG_SE_CTRL_RESERVED_0_OFFSET (0xF04) /* se_ctrl_reserved_0 */
#define SEC_ENG_SE_CTRL_RESERVED_1_OFFSET (0xF08) /* se_ctrl_reserved_1 */
#define SEC_ENG_SE_CTRL_RESERVED_2_OFFSET (0xF0C) /* se_ctrl_reserved_2 */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : se_sha_0_ctrl */
#define SEC_ENG_SE_SHA_0_BUSY (1 << 0U)
#define SEC_ENG_SE_SHA_0_TRIG_1T (1 << 1U)
#define SEC_ENG_SE_SHA_0_MODE_SHIFT (2U)
#define SEC_ENG_SE_SHA_0_MODE_MASK (0x7 << SEC_ENG_SE_SHA_0_MODE_SHIFT)
#define SEC_ENG_SE_SHA_0_EN (1 << 5U)
#define SEC_ENG_SE_SHA_0_HASH_SEL (1 << 6U)
#define SEC_ENG_SE_SHA_0_INT (1 << 8U)
#define SEC_ENG_SE_SHA_0_INT_CLR_1T (1 << 9U)
#define SEC_ENG_SE_SHA_0_INT_SET_1T (1 << 10U)
#define SEC_ENG_SE_SHA_0_INT_MASK (1 << 11U)
#define SEC_ENG_SE_SHA_0_MODE_EXT_SHIFT (12U)
#define SEC_ENG_SE_SHA_0_MODE_EXT_MASK (0x3 << SEC_ENG_SE_SHA_0_MODE_EXT_SHIFT)
#define SEC_ENG_SE_SHA_0_LINK_MODE (1 << 15U)
#define SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT (16U)
#define SEC_ENG_SE_SHA_0_MSG_LEN_MASK (0xffff << SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT)
/* 0x4 : se_sha_0_msa */
#define SEC_ENG_SE_SHA_0_MSA_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_MSA_MASK (0xffffffff << SEC_ENG_SE_SHA_0_MSA_SHIFT)
/* 0x8 : se_sha_0_status */
#define SEC_ENG_SE_SHA_0_STATUS_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_STATUS_MASK (0xffffffff << SEC_ENG_SE_SHA_0_STATUS_SHIFT)
/* 0xC : se_sha_0_endian */
#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN (1 << 0U)
/* 0x10 : se_sha_0_hash_l_0 */
#define SEC_ENG_SE_SHA_0_HASH_L_0_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_0_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_0_SHIFT)
/* 0x14 : se_sha_0_hash_l_1 */
#define SEC_ENG_SE_SHA_0_HASH_L_1_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_1_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_1_SHIFT)
/* 0x18 : se_sha_0_hash_l_2 */
#define SEC_ENG_SE_SHA_0_HASH_L_2_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_2_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_2_SHIFT)
/* 0x1C : se_sha_0_hash_l_3 */
#define SEC_ENG_SE_SHA_0_HASH_L_3_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_3_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_3_SHIFT)
/* 0x20 : se_sha_0_hash_l_4 */
#define SEC_ENG_SE_SHA_0_HASH_L_4_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_4_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_4_SHIFT)
/* 0x24 : se_sha_0_hash_l_5 */
#define SEC_ENG_SE_SHA_0_HASH_L_5_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_5_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_5_SHIFT)
/* 0x28 : se_sha_0_hash_l_6 */
#define SEC_ENG_SE_SHA_0_HASH_L_6_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_6_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_6_SHIFT)
/* 0x2C : se_sha_0_hash_l_7 */
#define SEC_ENG_SE_SHA_0_HASH_L_7_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_7_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_7_SHIFT)
/* 0x30 : se_sha_0_hash_h_0 */
#define SEC_ENG_SE_SHA_0_HASH_H_0_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_0_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_0_SHIFT)
/* 0x34 : se_sha_0_hash_h_1 */
#define SEC_ENG_SE_SHA_0_HASH_H_1_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_1_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_1_SHIFT)
/* 0x38 : se_sha_0_hash_h_2 */
#define SEC_ENG_SE_SHA_0_HASH_H_2_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_2_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_2_SHIFT)
/* 0x3C : se_sha_0_hash_h_3 */
#define SEC_ENG_SE_SHA_0_HASH_H_3_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_3_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_3_SHIFT)
/* 0x40 : se_sha_0_hash_h_4 */
#define SEC_ENG_SE_SHA_0_HASH_H_4_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_4_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_4_SHIFT)
/* 0x44 : se_sha_0_hash_h_5 */
#define SEC_ENG_SE_SHA_0_HASH_H_5_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_5_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_5_SHIFT)
/* 0x48 : se_sha_0_hash_h_6 */
#define SEC_ENG_SE_SHA_0_HASH_H_6_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_6_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_6_SHIFT)
/* 0x4C : se_sha_0_hash_h_7 */
#define SEC_ENG_SE_SHA_0_HASH_H_7_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_7_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_7_SHIFT)
/* 0x50 : se_sha_0_link */
#define SEC_ENG_SE_SHA_0_LCA_SHIFT (0U)
#define SEC_ENG_SE_SHA_0_LCA_MASK (0xffffffff << SEC_ENG_SE_SHA_0_LCA_SHIFT)
/* 0xFC : se_sha_0_ctrl_prot */
#define SEC_ENG_SE_SHA_ID0_EN (1 << 1U)
#define SEC_ENG_SE_SHA_ID1_EN (1 << 2U)
/* 0x100 : se_aes_0_ctrl */
#define SEC_ENG_SE_AES_0_BUSY (1 << 0U)
#define SEC_ENG_SE_AES_0_TRIG_1T (1 << 1U)
#define SEC_ENG_SE_AES_0_EN (1 << 2U)
#define SEC_ENG_SE_AES_0_MODE_SHIFT (3U)
#define SEC_ENG_SE_AES_0_MODE_MASK (0x3 << SEC_ENG_SE_AES_0_MODE_SHIFT)
#define SEC_ENG_SE_AES_0_DEC_EN (1 << 5U)
#define SEC_ENG_SE_AES_0_DEC_KEY_SEL (1 << 6U)
#define SEC_ENG_SE_AES_0_HW_KEY_EN (1 << 7U)
#define SEC_ENG_SE_AES_0_INT (1 << 8U)
#define SEC_ENG_SE_AES_0_INT_CLR_1T (1 << 9U)
#define SEC_ENG_SE_AES_0_INT_SET_1T (1 << 10U)
#define SEC_ENG_SE_AES_0_INT_MASK (1 << 11U)
#define SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT (12U)
#define SEC_ENG_SE_AES_0_BLOCK_MODE_MASK (0x3 << SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT)
#define SEC_ENG_SE_AES_0_IV_SEL (1 << 14U)
#define SEC_ENG_SE_AES_0_LINK_MODE (1 << 15U)
#define SEC_ENG_SE_AES_0_MSG_LEN_SHIFT (16U)
#define SEC_ENG_SE_AES_0_MSG_LEN_MASK (0xffff << SEC_ENG_SE_AES_0_MSG_LEN_SHIFT)
/* 0x104 : se_aes_0_msa */
#define SEC_ENG_SE_AES_0_MSA_SHIFT (0U)
#define SEC_ENG_SE_AES_0_MSA_MASK (0xffffffff << SEC_ENG_SE_AES_0_MSA_SHIFT)
/* 0x108 : se_aes_0_mda */
#define SEC_ENG_SE_AES_0_MDA_SHIFT (0U)
#define SEC_ENG_SE_AES_0_MDA_MASK (0xffffffff << SEC_ENG_SE_AES_0_MDA_SHIFT)
/* 0x10C : se_aes_0_status */
#define SEC_ENG_SE_AES_0_STATUS_SHIFT (0U)
#define SEC_ENG_SE_AES_0_STATUS_MASK (0xffffffff << SEC_ENG_SE_AES_0_STATUS_SHIFT)
/* 0x110 : se_aes_0_iv_0 */
#define SEC_ENG_SE_AES_0_IV_0_SHIFT (0U)
#define SEC_ENG_SE_AES_0_IV_0_MASK (0xffffffff << SEC_ENG_SE_AES_0_IV_0_SHIFT)
/* 0x114 : se_aes_0_iv_1 */
#define SEC_ENG_SE_AES_0_IV_1_SHIFT (0U)
#define SEC_ENG_SE_AES_0_IV_1_MASK (0xffffffff << SEC_ENG_SE_AES_0_IV_1_SHIFT)
/* 0x118 : se_aes_0_iv_2 */
#define SEC_ENG_SE_AES_0_IV_2_SHIFT (0U)
#define SEC_ENG_SE_AES_0_IV_2_MASK (0xffffffff << SEC_ENG_SE_AES_0_IV_2_SHIFT)
/* 0x11C : se_aes_0_iv_3 */
#define SEC_ENG_SE_AES_0_IV_3_SHIFT (0U)
#define SEC_ENG_SE_AES_0_IV_3_MASK (0xffffffff << SEC_ENG_SE_AES_0_IV_3_SHIFT)
/* 0x120 : se_aes_0_key_0 */
#define SEC_ENG_SE_AES_0_KEY_0_SHIFT (0U)
#define SEC_ENG_SE_AES_0_KEY_0_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_0_SHIFT)
/* 0x124 : se_aes_0_key_1 */
#define SEC_ENG_SE_AES_0_KEY_1_SHIFT (0U)
#define SEC_ENG_SE_AES_0_KEY_1_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_1_SHIFT)
/* 0x128 : se_aes_0_key_2 */
#define SEC_ENG_SE_AES_0_KEY_2_SHIFT (0U)
#define SEC_ENG_SE_AES_0_KEY_2_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_2_SHIFT)
/* 0x12C : se_aes_0_key_3 */
#define SEC_ENG_SE_AES_0_KEY_3_SHIFT (0U)
#define SEC_ENG_SE_AES_0_KEY_3_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_3_SHIFT)
/* 0x130 : se_aes_0_key_4 */
#define SEC_ENG_SE_AES_0_KEY_4_SHIFT (0U)
#define SEC_ENG_SE_AES_0_KEY_4_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_4_SHIFT)
/* 0x134 : se_aes_0_key_5 */
#define SEC_ENG_SE_AES_0_KEY_5_SHIFT (0U)
#define SEC_ENG_SE_AES_0_KEY_5_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_5_SHIFT)
/* 0x138 : se_aes_0_key_6 */
#define SEC_ENG_SE_AES_0_KEY_6_SHIFT (0U)
#define SEC_ENG_SE_AES_0_KEY_6_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_6_SHIFT)
/* 0x13C : se_aes_0_key_7 */
#define SEC_ENG_SE_AES_0_KEY_7_SHIFT (0U)
#define SEC_ENG_SE_AES_0_KEY_7_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_7_SHIFT)
/* 0x140 : se_aes_0_key_sel */
#define SEC_ENG_SE_AES_0_KEY_SEL_SHIFT (0U)
#define SEC_ENG_SE_AES_0_KEY_SEL_MASK (0x3 << SEC_ENG_SE_AES_0_KEY_SEL_SHIFT)
/* 0x144 : se_aes_1_key_sel */
#define SEC_ENG_SE_AES_1_KEY_SEL_SHIFT (0U)
#define SEC_ENG_SE_AES_1_KEY_SEL_MASK (0x3 << SEC_ENG_SE_AES_1_KEY_SEL_SHIFT)
/* 0x148 : se_aes_0_endian */
#define SEC_ENG_SE_AES_0_DOUT_ENDIAN (1 << 0U)
#define SEC_ENG_SE_AES_0_DIN_ENDIAN (1 << 1U)
#define SEC_ENG_SE_AES_0_KEY_ENDIAN (1 << 2U)
#define SEC_ENG_SE_AES_0_IV_ENDIAN (1 << 3U)
#define SEC_ENG_SE_AES_0_TWK_ENDIAN (1 << 4U)
#define SEC_ENG_SE_AES_0_CTR_LEN_SHIFT (30U)
#define SEC_ENG_SE_AES_0_CTR_LEN_MASK (0x3 << SEC_ENG_SE_AES_0_CTR_LEN_SHIFT)
/* 0x14C : se_aes_sboot */
#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL (1 << 0U)
#define SEC_ENG_SE_AES_0_XTS_MODE (1 << 15U)
#define SEC_ENG_SE_AES_0_UNI_LEN_SHIFT (16U)
#define SEC_ENG_SE_AES_0_UNI_LEN_MASK (0xffff << SEC_ENG_SE_AES_0_UNI_LEN_SHIFT)
/* 0x150 : se_aes_0_link */
#define SEC_ENG_SE_AES_0_LCA_SHIFT (0U)
#define SEC_ENG_SE_AES_0_LCA_MASK (0xffffffff << SEC_ENG_SE_AES_0_LCA_SHIFT)
/* 0x1FC : se_aes_0_ctrl_prot */
#define SEC_ENG_SE_AES_ID0_EN (1 << 1U)
#define SEC_ENG_SE_AES_ID1_EN (1 << 2U)
/* 0x200 : se_trng_0_ctrl_0 */
#define SEC_ENG_SE_TRNG_0_BUSY (1 << 0U)
#define SEC_ENG_SE_TRNG_0_TRIG_1T (1 << 1U)
#define SEC_ENG_SE_TRNG_0_EN (1 << 2U)
#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T (1 << 3U)
#define SEC_ENG_SE_TRNG_0_HT_ERROR (1 << 4U)
#define SEC_ENG_SE_TRNG_0_INT (1 << 8U)
#define SEC_ENG_SE_TRNG_0_INT_CLR_1T (1 << 9U)
#define SEC_ENG_SE_TRNG_0_INT_SET_1T (1 << 10U)
#define SEC_ENG_SE_TRNG_0_INT_MASK (1 << 11U)
#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL (1 << 13U)
#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED (1 << 14U)
#define SEC_ENG_SE_TRNG_0_MANUAL_EN (1 << 15U)
/* 0x204 : se_trng_0_status */
#define SEC_ENG_SE_TRNG_0_STATUS_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_STATUS_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_STATUS_SHIFT)
/* 0x208 : se_trng_0_dout_0 */
#define SEC_ENG_SE_TRNG_0_DOUT_0_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_0_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_0_SHIFT)
/* 0x20C : se_trng_0_dout_1 */
#define SEC_ENG_SE_TRNG_0_DOUT_1_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_1_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_1_SHIFT)
/* 0x210 : se_trng_0_dout_2 */
#define SEC_ENG_SE_TRNG_0_DOUT_2_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_2_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_2_SHIFT)
/* 0x214 : se_trng_0_dout_3 */
#define SEC_ENG_SE_TRNG_0_DOUT_3_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_3_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_3_SHIFT)
/* 0x218 : se_trng_0_dout_4 */
#define SEC_ENG_SE_TRNG_0_DOUT_4_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_4_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_4_SHIFT)
/* 0x21C : se_trng_0_dout_5 */
#define SEC_ENG_SE_TRNG_0_DOUT_5_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_5_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_5_SHIFT)
/* 0x220 : se_trng_0_dout_6 */
#define SEC_ENG_SE_TRNG_0_DOUT_6_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_6_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_6_SHIFT)
/* 0x224 : se_trng_0_dout_7 */
#define SEC_ENG_SE_TRNG_0_DOUT_7_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_7_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_7_SHIFT)
/* 0x228 : se_trng_0_test */
#define SEC_ENG_SE_TRNG_0_TEST_EN (1 << 0U)
#define SEC_ENG_SE_TRNG_0_CP_TEST_EN (1 << 1U)
#define SEC_ENG_SE_TRNG_0_CP_BYPASS (1 << 2U)
#define SEC_ENG_SE_TRNG_0_HT_DIS (1 << 3U)
#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_SHIFT (4U)
#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_MASK (0xff << SEC_ENG_SE_TRNG_0_HT_ALARM_N_SHIFT)
/* 0x22C : se_trng_0_ctrl_1 */
#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_SHIFT)
/* 0x230 : se_trng_0_ctrl_2 */
#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_MASK (0xffff << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_SHIFT)
/* 0x234 : se_trng_0_ctrl_3 */
#define SEC_ENG_SE_TRNG_0_CP_RATIO_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_CP_RATIO_MASK (0xff << SEC_ENG_SE_TRNG_0_CP_RATIO_SHIFT)
#define SEC_ENG_SE_TRNG_0_HT_RCT_C_SHIFT (8U)
#define SEC_ENG_SE_TRNG_0_HT_RCT_C_MASK (0xff << SEC_ENG_SE_TRNG_0_HT_RCT_C_SHIFT)
#define SEC_ENG_SE_TRNG_0_HT_APT_C_SHIFT (16U)
#define SEC_ENG_SE_TRNG_0_HT_APT_C_MASK (0x3ff << SEC_ENG_SE_TRNG_0_HT_APT_C_SHIFT)
#define SEC_ENG_SE_TRNG_0_HT_OD_EN (1 << 26U)
#define SEC_ENG_SE_TRNG_0_ROSC_EN (1 << 31U)
/* 0x240 : se_trng_0_test_out_0 */
#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_0_SHIFT)
/* 0x244 : se_trng_0_test_out_1 */
#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_1_SHIFT)
/* 0x248 : se_trng_0_test_out_2 */
#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_2_SHIFT)
/* 0x24C : se_trng_0_test_out_3 */
#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_SHIFT (0U)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_3_SHIFT)
/* 0x2FC : se_trng_0_ctrl_prot */
#define SEC_ENG_SE_TRNG_ID0_EN (1 << 1U)
#define SEC_ENG_SE_TRNG_ID1_EN (1 << 2U)
/* 0x300 : se_pka_0_ctrl_0 */
#define SEC_ENG_SE_PKA_0_DONE (1 << 0U)
#define SEC_ENG_SE_PKA_0_DONE_CLR_1T (1 << 1U)
#define SEC_ENG_SE_PKA_0_BUSY (1 << 2U)
#define SEC_ENG_SE_PKA_0_EN (1 << 3U)
#define SEC_ENG_SE_PKA_0_PROT_MD_SHIFT (4U)
#define SEC_ENG_SE_PKA_0_PROT_MD_MASK (0xf << SEC_ENG_SE_PKA_0_PROT_MD_SHIFT)
#define SEC_ENG_SE_PKA_0_INT (1 << 8U)
#define SEC_ENG_SE_PKA_0_INT_CLR_1T (1 << 9U)
#define SEC_ENG_SE_PKA_0_INT_SET (1 << 10U)
#define SEC_ENG_SE_PKA_0_INT_MASK (1 << 11U)
#define SEC_ENG_SE_PKA_0_ENDIAN (1 << 12U)
#define SEC_ENG_SE_PKA_0_RAM_CLR_MD (1 << 13U)
#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T (1 << 15U)
#define SEC_ENG_SE_PKA_0_STATUS_SHIFT (16U)
#define SEC_ENG_SE_PKA_0_STATUS_MASK (0xffff << SEC_ENG_SE_PKA_0_STATUS_SHIFT)
/* 0x30C : se_pka_0_seed */
#define SEC_ENG_SE_PKA_0_SEED_SHIFT (0U)
#define SEC_ENG_SE_PKA_0_SEED_MASK (0xffffffff << SEC_ENG_SE_PKA_0_SEED_SHIFT)
/* 0x310 : se_pka_0_ctrl_1 */
#define SEC_ENG_SE_PKA_0_HBURST_SHIFT (0U)
#define SEC_ENG_SE_PKA_0_HBURST_MASK (0x7 << SEC_ENG_SE_PKA_0_HBURST_SHIFT)
#define SEC_ENG_SE_PKA_0_HBYPASS (1 << 3U)
/* 0x340 : se_pka_0_rw */
/* 0x360 : se_pka_0_rw_burst */
/* 0x3FC : se_pka_0_ctrl_prot */
#define SEC_ENG_SE_PKA_ID0_EN (1 << 1U)
#define SEC_ENG_SE_PKA_ID1_EN (1 << 2U)
/* 0x400 : se_cdet_0_ctrl_0 */
#define SEC_ENG_SE_CDET_0_EN (1 << 0U)
#define SEC_ENG_SE_CDET_0_BUSY (1 << 1U)
#define SEC_ENG_SE_CDET_0_STATUS_SHIFT (3U)
#define SEC_ENG_SE_CDET_0_STATUS_MASK (0x1f << SEC_ENG_SE_CDET_0_STATUS_SHIFT)
#define SEC_ENG_SE_CDET_0_INT (1 << 8U)
#define SEC_ENG_SE_CDET_0_INT_CLR (1 << 9U)
#define SEC_ENG_SE_CDET_0_INT_SET (1 << 10U)
#define SEC_ENG_SE_CDET_0_INT_MASK (1 << 11U)
#define SEC_ENG_SE_CDET_0_MODE (1 << 12U)
/* 0x404 : se_cdet_0_ctrl_1 */
#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_SHIFT (0U)
#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_MASK (0xffff << SEC_ENG_SE_CDET_0_G_LOOP_MAX_SHIFT)
#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_SHIFT (16U)
#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_MASK (0xffff << SEC_ENG_SE_CDET_0_G_LOOP_MIN_SHIFT)
/* 0x408 : se_cdet_0_ctrl_2 */
#define SEC_ENG_SE_CDET_0_T_LOOP_N_SHIFT (0U)
#define SEC_ENG_SE_CDET_0_T_LOOP_N_MASK (0xffff << SEC_ENG_SE_CDET_0_T_LOOP_N_SHIFT)
#define SEC_ENG_SE_CDET_0_T_DLY_N_SHIFT (16U)
#define SEC_ENG_SE_CDET_0_T_DLY_N_MASK (0xff << SEC_ENG_SE_CDET_0_T_DLY_N_SHIFT)
#define SEC_ENG_SE_CDET_0_G_SLP_N_SHIFT (24U)
#define SEC_ENG_SE_CDET_0_G_SLP_N_MASK (0xff << SEC_ENG_SE_CDET_0_G_SLP_N_SHIFT)
/* 0x40C : se_cdet_0_ctrl_3 */
#define SEC_ENG_SE_CDET_0_T_COUNT_SHIFT (0U)
#define SEC_ENG_SE_CDET_0_T_COUNT_MASK (0xffff << SEC_ENG_SE_CDET_0_T_COUNT_SHIFT)
#define SEC_ENG_SE_CDET_0_G_COUNT_SHIFT (16U)
#define SEC_ENG_SE_CDET_0_G_COUNT_MASK (0xffff << SEC_ENG_SE_CDET_0_G_COUNT_SHIFT)
/* 0x4FC : se_cdet_0_ctrl_prot */
#define SEC_ENG_SE_CDET_PROT_EN (1 << 0U)
#define SEC_ENG_SE_CDET_ID0_EN (1 << 1U)
#define SEC_ENG_SE_CDET_ID1_EN (1 << 2U)
/* 0x500 : se_gmac_0_ctrl_0 */
#define SEC_ENG_SE_GMAC_0_BUSY (1 << 0U)
#define SEC_ENG_SE_GMAC_0_TRIG_1T (1 << 1U)
#define SEC_ENG_SE_GMAC_0_EN (1 << 2U)
#define SEC_ENG_SE_GMAC_0_INT (1 << 8U)
#define SEC_ENG_SE_GMAC_0_INT_CLR_1T (1 << 9U)
#define SEC_ENG_SE_GMAC_0_INT_SET_1T (1 << 10U)
#define SEC_ENG_SE_GMAC_0_INT_MASK (1 << 11U)
#define SEC_ENG_SE_GMAC_0_T_ENDIAN (1 << 12U)
#define SEC_ENG_SE_GMAC_0_H_ENDIAN (1 << 13U)
#define SEC_ENG_SE_GMAC_0_X_ENDIAN (1 << 14U)
/* 0x504 : se_gmac_0_lca */
#define SEC_ENG_SE_GMAC_0_LCA_SHIFT (0U)
#define SEC_ENG_SE_GMAC_0_LCA_MASK (0xffffffff << SEC_ENG_SE_GMAC_0_LCA_SHIFT)
/* 0x508 : se_gmac_0_status */
#define SEC_ENG_SE_GMAC_0_STATUS_SHIFT (0U)
#define SEC_ENG_SE_GMAC_0_STATUS_MASK (0xffffffff << SEC_ENG_SE_GMAC_0_STATUS_SHIFT)
/* 0x5FC : se_gmac_0_ctrl_prot */
#define SEC_ENG_SE_GMAC_ID0_EN (1 << 1U)
#define SEC_ENG_SE_GMAC_ID1_EN (1 << 2U)
/* 0xF00 : se_ctrl_prot_rd */
#define SEC_ENG_SE_SHA_ID0_EN_RD (1 << 0U)
#define SEC_ENG_SE_SHA_ID1_EN_RD (1 << 1U)
#define SEC_ENG_SE_AES_ID0_EN_RD (1 << 2U)
#define SEC_ENG_SE_AES_ID1_EN_RD (1 << 3U)
#define SEC_ENG_SE_TRNG_ID0_EN_RD (1 << 4U)
#define SEC_ENG_SE_TRNG_ID1_EN_RD (1 << 5U)
#define SEC_ENG_SE_PKA_ID0_EN_RD (1 << 6U)
#define SEC_ENG_SE_PKA_ID1_EN_RD (1 << 7U)
#define SEC_ENG_SE_CDET_ID0_EN_RD (1 << 8U)
#define SEC_ENG_SE_CDET_ID1_EN_RD (1 << 9U)
#define SEC_ENG_SE_GMAC_ID0_EN_RD (1 << 10U)
#define SEC_ENG_SE_GMAC_ID1_EN_RD (1 << 11U)
#define SEC_ENG_SE_DBG_DIS (1 << 31U)
/* 0xF04 : se_ctrl_reserved_0 */
#define SEC_ENG_SE_CTRL_RESERVED_0_SHIFT (0U)
#define SEC_ENG_SE_CTRL_RESERVED_0_MASK (0xffffffff << SEC_ENG_SE_CTRL_RESERVED_0_SHIFT)
/* 0xF08 : se_ctrl_reserved_1 */
#define SEC_ENG_SE_CTRL_RESERVED_1_SHIFT (0U)
#define SEC_ENG_SE_CTRL_RESERVED_1_MASK (0xffffffff << SEC_ENG_SE_CTRL_RESERVED_1_SHIFT)
/* 0xF0C : se_ctrl_reserved_2 */
#define SEC_ENG_SE_CTRL_RESERVED_2_SHIFT (0U)
#define SEC_ENG_SE_CTRL_RESERVED_2_MASK (0xffffffff << SEC_ENG_SE_CTRL_RESERVED_2_SHIFT)
#endif /* __HARDWARE_SEC_ENG_H__ */

3351
include/bl808/sf_ctrl_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

156
include/bl808/spi_reg.h Normal file
View File

@ -0,0 +1,156 @@
/**
******************************************************************************
* @file spi_reg.h
* @version V1.0
* @date 2022-06-20
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_SPI_H__
#define __HARDWARE_SPI_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define SPI_CONFIG_OFFSET (0x0) /* spi_config */
#define SPI_INT_STS_OFFSET (0x4) /* spi_int_sts */
#define SPI_BUS_BUSY_OFFSET (0x8) /* spi_bus_busy */
#define SPI_PRD_0_OFFSET (0x10) /* spi_prd_0 */
#define SPI_PRD_1_OFFSET (0x14) /* spi_prd_1 */
#define SPI_RXD_IGNR_OFFSET (0x18) /* spi_rxd_ignr */
#define SPI_STO_VALUE_OFFSET (0x1C) /* spi_sto_value */
#define SPI_FIFO_CONFIG_0_OFFSET (0x80) /* spi_fifo_config_0 */
#define SPI_FIFO_CONFIG_1_OFFSET (0x84) /* spi_fifo_config_1 */
#define SPI_FIFO_WDATA_OFFSET (0x88) /* spi_fifo_wdata */
#define SPI_FIFO_RDATA_OFFSET (0x8C) /* spi_fifo_rdata */
#define SPI_BACKUP_IO_EN_OFFSET (0xFC) /* backup_io_en */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : spi_config */
#define SPI_CR_SPI_M_EN (1 << 0U)
#define SPI_CR_SPI_S_EN (1 << 1U)
#define SPI_CR_SPI_FRAME_SIZE_SHIFT (2U)
#define SPI_CR_SPI_FRAME_SIZE_MASK (0x3 << SPI_CR_SPI_FRAME_SIZE_SHIFT)
#define SPI_CR_SPI_SCLK_POL (1 << 4U)
#define SPI_CR_SPI_SCLK_PH (1 << 5U)
#define SPI_CR_SPI_BIT_INV (1 << 6U)
#define SPI_CR_SPI_BYTE_INV (1 << 7U)
#define SPI_CR_SPI_RXD_IGNR_EN (1 << 8U)
#define SPI_CR_SPI_M_CONT_EN (1 << 9U)
#define SPI_CR_SPI_S_3PIN_MODE (1 << 10U)
#define SPI_CR_SPI_DEG_EN (1 << 11U)
#define SPI_CR_SPI_DEG_CNT_SHIFT (12U)
#define SPI_CR_SPI_DEG_CNT_MASK (0xf << SPI_CR_SPI_DEG_CNT_SHIFT)
/* 0x4 : spi_int_sts */
#define SPI_END_INT (1 << 0U)
#define SPI_TXF_INT (1 << 1U)
#define SPI_RXF_INT (1 << 2U)
#define SPI_STO_INT (1 << 3U)
#define SPI_TXU_INT (1 << 4U)
#define SPI_FER_INT (1 << 5U)
#define SPI_CR_SPI_END_MASK (1 << 8U)
#define SPI_CR_SPI_TXF_MASK (1 << 9U)
#define SPI_CR_SPI_RXF_MASK (1 << 10U)
#define SPI_CR_SPI_STO_MASK (1 << 11U)
#define SPI_CR_SPI_TXU_MASK (1 << 12U)
#define SPI_CR_SPI_FER_MASK (1 << 13U)
#define SPI_CR_SPI_END_CLR (1 << 16U)
#define SPI_CR_SPI_STO_CLR (1 << 19U)
#define SPI_CR_SPI_TXU_CLR (1 << 20U)
#define SPI_CR_SPI_END_EN (1 << 24U)
#define SPI_CR_SPI_TXF_EN (1 << 25U)
#define SPI_CR_SPI_RXF_EN (1 << 26U)
#define SPI_CR_SPI_STO_EN (1 << 27U)
#define SPI_CR_SPI_TXU_EN (1 << 28U)
#define SPI_CR_SPI_FER_EN (1 << 29U)
/* 0x8 : spi_bus_busy */
#define SPI_STS_SPI_BUS_BUSY (1 << 0U)
/* 0x10 : spi_prd_0 */
#define SPI_CR_SPI_PRD_S_SHIFT (0U)
#define SPI_CR_SPI_PRD_S_MASK (0xff << SPI_CR_SPI_PRD_S_SHIFT)
#define SPI_CR_SPI_PRD_P_SHIFT (8U)
#define SPI_CR_SPI_PRD_P_MASK (0xff << SPI_CR_SPI_PRD_P_SHIFT)
#define SPI_CR_SPI_PRD_D_PH_0_SHIFT (16U)
#define SPI_CR_SPI_PRD_D_PH_0_MASK (0xff << SPI_CR_SPI_PRD_D_PH_0_SHIFT)
#define SPI_CR_SPI_PRD_D_PH_1_SHIFT (24U)
#define SPI_CR_SPI_PRD_D_PH_1_MASK (0xff << SPI_CR_SPI_PRD_D_PH_1_SHIFT)
/* 0x14 : spi_prd_1 */
#define SPI_CR_SPI_PRD_I_SHIFT (0U)
#define SPI_CR_SPI_PRD_I_MASK (0xff << SPI_CR_SPI_PRD_I_SHIFT)
/* 0x18 : spi_rxd_ignr */
#define SPI_CR_SPI_RXD_IGNR_P_SHIFT (0U)
#define SPI_CR_SPI_RXD_IGNR_P_MASK (0x1f << SPI_CR_SPI_RXD_IGNR_P_SHIFT)
#define SPI_CR_SPI_RXD_IGNR_S_SHIFT (16U)
#define SPI_CR_SPI_RXD_IGNR_S_MASK (0x1f << SPI_CR_SPI_RXD_IGNR_S_SHIFT)
/* 0x1C : spi_sto_value */
#define SPI_CR_SPI_STO_VALUE_SHIFT (0U)
#define SPI_CR_SPI_STO_VALUE_MASK (0xfff << SPI_CR_SPI_STO_VALUE_SHIFT)
/* 0x80 : spi_fifo_config_0 */
#define SPI_DMA_TX_EN (1 << 0U)
#define SPI_DMA_RX_EN (1 << 1U)
#define SPI_TX_FIFO_CLR (1 << 2U)
#define SPI_RX_FIFO_CLR (1 << 3U)
#define SPI_TX_FIFO_OVERFLOW (1 << 4U)
#define SPI_TX_FIFO_UNDERFLOW (1 << 5U)
#define SPI_RX_FIFO_OVERFLOW (1 << 6U)
#define SPI_RX_FIFO_UNDERFLOW (1 << 7U)
/* 0x84 : spi_fifo_config_1 */
#define SPI_TX_FIFO_CNT_SHIFT (0U)
#define SPI_TX_FIFO_CNT_MASK (0x3f << SPI_TX_FIFO_CNT_SHIFT)
#define SPI_RX_FIFO_CNT_SHIFT (8U)
#define SPI_RX_FIFO_CNT_MASK (0x3f << SPI_RX_FIFO_CNT_SHIFT)
#define SPI_TX_FIFO_TH_SHIFT (16U)
#define SPI_TX_FIFO_TH_MASK (0x1f << SPI_TX_FIFO_TH_SHIFT)
#define SPI_RX_FIFO_TH_SHIFT (24U)
#define SPI_RX_FIFO_TH_MASK (0x1f << SPI_RX_FIFO_TH_SHIFT)
/* 0x88 : spi_fifo_wdata */
#define SPI_FIFO_WDATA_SHIFT (0U)
#define SPI_FIFO_WDATA_MASK (0xffffffff << SPI_FIFO_WDATA_SHIFT)
/* 0x8C : spi_fifo_rdata */
#define SPI_FIFO_RDATA_SHIFT (0U)
#define SPI_FIFO_RDATA_MASK (0xffffffff << SPI_FIFO_RDATA_SHIFT)
/* 0xFC : backup_io_en */
#define SPI_BACKUP_IO_EN (1 << 0U)
#endif /* __HARDWARE_SPI_H__ */

272
include/bl808/timer_reg.h Normal file
View File

@ -0,0 +1,272 @@
/**
******************************************************************************
* @file timer_reg.h
* @version V1.0
* @date 2022-08-03
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_TIMER_H__
#define __HARDWARE_TIMER_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define TIMER_TCCR_OFFSET (0x0) /* Timer Clock Source */
#define TIMER_TMR0_0_OFFSET (0x10) /* Timer0 Match Value 0 */
#define TIMER_TMR0_1_OFFSET (0x14) /* Timer0 Match Value 1 */
#define TIMER_TMR0_2_OFFSET (0x18) /* Timer0 Match Value 2 */
#define TIMER_TMR1_0_OFFSET (0x1C) /* Timer1 Match Value 0 */
#define TIMER_TMR1_1_OFFSET (0x20) /* Timer1 Match Value 1 */
#define TIMER_TMR1_2_OFFSET (0x24) /* Timer1 Match Value 2 */
#define TIMER_TCR0_OFFSET (0x2C) /* Timer0 Counter Value */
#define TIMER_TCR1_OFFSET (0x30) /* Timer1 Counter Value */
#define TIMER_TSR0_OFFSET (0x38) /* Timer0 Match Status */
#define TIMER_TSR1_OFFSET (0x3C) /* Timer1 Match Status */
#define TIMER_TIER0_OFFSET (0x44) /* Timer0 Match Interrupt Enable */
#define TIMER_TIER1_OFFSET (0x48) /* Timer1 Match Interrupt Enable */
#define TIMER_TPLVR0_OFFSET (0x50) /* Timer0 Pre-Load Value */
#define TIMER_TPLVR1_OFFSET (0x54) /* Timer1 Pre-Load Value */
#define TIMER_TPLCR0_OFFSET (0x5C) /* Timer0 Pre-Load Control */
#define TIMER_TPLCR1_OFFSET (0x60) /* Timer1 Pre-Load Control */
#define TIMER_WMER_OFFSET (0x64) /* Watch-dog reset/interrupt Mode */
#define TIMER_WMR_OFFSET (0x68) /* Watch-dog Match Value */
#define TIMER_WVR_OFFSET (0x6C) /* Watch-dog Counter Value */
#define TIMER_WSR_OFFSET (0x70) /* Watch-dog Reset Status */
#define TIMER_TICR0_OFFSET (0x78) /* Timer0 Interrupt Clear */
#define TIMER_TICR1_OFFSET (0x7C) /* Timer1 Interrupt Clear */
#define TIMER_WICR_OFFSET (0x80) /* WDT Interrupt Clear */
#define TIMER_TCER_OFFSET (0x84) /* Timer Counter Enable/Clear */
#define TIMER_TCMR_OFFSET (0x88) /* Timer Counter Mode */
#define TIMER_TILR0_OFFSET (0x90) /* Timer0 Match Interrupt Mode */
#define TIMER_TILR1_OFFSET (0x94) /* Timer1 Match Interrupt Mode */
#define TIMER_WCR_OFFSET (0x98) /* WDT Counter Reset */
#define TIMER_WFAR_OFFSET (0x9C) /* WDT Access Key1 */
#define TIMER_WSAR_OFFSET (0xA0) /* WDT Access Key2 */
#define TIMER_TCVWR0_OFFSET (0xA8) /* Timer0 Counter Latch Value */
#define TIMER_TCVWR1_OFFSET (0xAC) /* Timer1 Counter Latch Value */
#define TIMER_TCVSYN0_OFFSET (0xB4) /* Timer0 Counter Sync Value */
#define TIMER_TCVSYN1_OFFSET (0xB8) /* Timer1 Counter Sync Value */
#define TIMER_TCDR_OFFSET (0xBC) /* Timer Division */
#define TIMER_GPIO_OFFSET (0xC0) /* GPIO Mode */
#define TIMER_GPIO_LAT1_OFFSET (0xC4) /* GPIO Latch Value1 */
#define TIMER_GPIO_LAT2_OFFSET (0xC8) /* GPIO Latch Value2 */
#define TIMER_TCDR_FORCE_OFFSET (0xCC) /* Timer Division Force */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : Timer Clock Source */
#define TIMER_CS_0_SHIFT (0U)
#define TIMER_CS_0_MASK (0xf << TIMER_CS_0_SHIFT)
#define TIMER_CS_1_SHIFT (4U)
#define TIMER_CS_1_MASK (0xf << TIMER_CS_1_SHIFT)
#define TIMER_CS_WDT_SHIFT (8U)
#define TIMER_CS_WDT_MASK (0xf << TIMER_CS_WDT_SHIFT)
#define TIMER_ID_SHIFT (24U)
#define TIMER_ID_MASK (0xff << TIMER_ID_SHIFT)
/* 0x10 : Timer0 Match Value 0 */
#define TIMER_TMR0_0_SHIFT (0U)
#define TIMER_TMR0_0_MASK (0xffffffff << TIMER_TMR0_0_SHIFT)
/* 0x14 : Timer0 Match Value 1 */
#define TIMER_TMR0_1_SHIFT (0U)
#define TIMER_TMR0_1_MASK (0xffffffff << TIMER_TMR0_1_SHIFT)
/* 0x18 : Timer0 Match Value 2 */
#define TIMER_TMR0_2_SHIFT (0U)
#define TIMER_TMR0_2_MASK (0xffffffff << TIMER_TMR0_2_SHIFT)
/* 0x1C : Timer1 Match Value 0 */
#define TIMER_TMR1_0_SHIFT (0U)
#define TIMER_TMR1_0_MASK (0xffffffff << TIMER_TMR1_0_SHIFT)
/* 0x20 : Timer1 Match Value 1 */
#define TIMER_TMR1_1_SHIFT (0U)
#define TIMER_TMR1_1_MASK (0xffffffff << TIMER_TMR1_1_SHIFT)
/* 0x24 : Timer1 Match Value 2 */
#define TIMER_TMR1_2_SHIFT (0U)
#define TIMER_TMR1_2_MASK (0xffffffff << TIMER_TMR1_2_SHIFT)
/* 0x2C : Timer0 Counter Value */
#define TIMER_TCR0_CNT_SHIFT (0U)
#define TIMER_TCR0_CNT_MASK (0xffffffff << TIMER_TCR0_CNT_SHIFT)
/* 0x30 : Timer1 Counter Value */
#define TIMER_TCR1_CNT_SHIFT (0U)
#define TIMER_TCR1_CNT_MASK (0xffffffff << TIMER_TCR1_CNT_SHIFT)
/* 0x38 : Timer0 Match Status */
#define TIMER_TSR0_0 (1 << 0U)
#define TIMER_TSR0_1 (1 << 1U)
#define TIMER_TSR0_2 (1 << 2U)
/* 0x3C : Timer1 Match Status */
#define TIMER_TSR1_0 (1 << 0U)
#define TIMER_TSR1_1 (1 << 1U)
#define TIMER_TSR1_2 (1 << 2U)
/* 0x44 : Timer0 Match Interrupt Enable */
#define TIMER_TIER0_0 (1 << 0U)
#define TIMER_TIER0_1 (1 << 1U)
#define TIMER_TIER0_2 (1 << 2U)
/* 0x48 : Timer1 Match Interrupt Enable */
#define TIMER_TIER1_0 (1 << 0U)
#define TIMER_TIER1_1 (1 << 1U)
#define TIMER_TIER1_2 (1 << 2U)
/* 0x50 : Timer0 Pre-Load Value */
#define TIMER_TPLVR0_SHIFT (0U)
#define TIMER_TPLVR0_MASK (0xffffffff << TIMER_TPLVR0_SHIFT)
/* 0x54 : Timer1 Pre-Load Value */
#define TIMER_TPLVR1_SHIFT (0U)
#define TIMER_TPLVR1_MASK (0xffffffff << TIMER_TPLVR1_SHIFT)
/* 0x5C : Timer0 Pre-Load Control */
#define TIMER_TPLCR0_SHIFT (0U)
#define TIMER_TPLCR0_MASK (0x3 << TIMER_TPLCR0_SHIFT)
/* 0x60 : Timer1 Pre-Load Control */
#define TIMER_TPLCR1_SHIFT (0U)
#define TIMER_TPLCR1_MASK (0x3 << TIMER_TPLCR1_SHIFT)
/* 0x64 : Watch-dog reset/interrupt Mode */
#define TIMER_WE (1 << 0U)
#define TIMER_WRIE (1 << 1U)
/* 0x68 : Watch-dog Match Value */
#define TIMER_WMR_SHIFT (0U)
#define TIMER_WMR_MASK (0xffff << TIMER_WMR_SHIFT)
#define TIMER_WDT_ALIGN (1 << 16U)
/* 0x6C : Watch-dog Counter Value */
#define TIMER_WDT_CNT_SHIFT (0U)
#define TIMER_WDT_CNT_MASK (0xffff << TIMER_WDT_CNT_SHIFT)
/* 0x70 : Watch-dog Reset Status */
#define TIMER_WTS (1 << 0U)
/* 0x78 : Timer0 Interrupt Clear */
#define TIMER_TCLR0_0 (1 << 0U)
#define TIMER_TCLR0_1 (1 << 1U)
#define TIMER_TCLR0_2 (1 << 2U)
/* 0x7C : Timer1 Interrupt Clear */
#define TIMER_TCLR1_0 (1 << 0U)
#define TIMER_TCLR1_1 (1 << 1U)
#define TIMER_TCLR1_2 (1 << 2U)
/* 0x80 : WDT Interrupt Clear */
#define TIMER_WICLR (1 << 0U)
/* 0x84 : Timer Counter Enable/Clear */
#define TIMER0_EN (1 << 1U)
#define TIMER1_EN (1 << 2U)
#define TIMER_TCR0_CNT_CLR (1 << 5U)
#define TIMER_TCR1_CNT_CLR (1 << 6U)
/* 0x88 : Timer Counter Mode */
#define TIMER0_MODE (1 << 1U)
#define TIMER1_MODE (1 << 2U)
#define TIMER0_ALIGN (1 << 5U)
#define TIMER1_ALIGN (1 << 6U)
/* 0x90 : Timer0 Match Interrupt Mode */
#define TIMER_TILR0_0 (1 << 0U)
#define TIMER_TILR0_1 (1 << 1U)
#define TIMER_TILR0_2 (1 << 2U)
/* 0x94 : Timer1 Match Interrupt Mode */
#define TIMER_TILR1_0 (1 << 0U)
#define TIMER_TILR1_1 (1 << 1U)
#define TIMER_TILR1_2 (1 << 2U)
/* 0x98 : WDT Counter Reset */
#define TIMER_WCR (1 << 0U)
/* 0x9C : WDT Access Key1 */
#define TIMER_WFAR_SHIFT (0U)
#define TIMER_WFAR_MASK (0xffff << TIMER_WFAR_SHIFT)
/* 0xA0 : WDT Access Key2 */
#define TIMER_WSAR_SHIFT (0U)
#define TIMER_WSAR_MASK (0xffff << TIMER_WSAR_SHIFT)
/* 0xA8 : Timer0 Counter Latch Value */
#define TIMER_TCR0_CNT_LAT_SHIFT (0U)
#define TIMER_TCR0_CNT_LAT_MASK (0xffffffff << TIMER_TCR0_CNT_LAT_SHIFT)
/* 0xAC : Timer1 Counter Latch Value */
#define TIMER_TCR1_CNT_LAT_SHIFT (0U)
#define TIMER_TCR1_CNT_LAT_MASK (0xffffffff << TIMER_TCR1_CNT_LAT_SHIFT)
/* 0xB4 : Timer0 Counter Sync Value */
#define TIMER_TCR0_CNT_SYNC_SHIFT (0U)
#define TIMER_TCR0_CNT_SYNC_MASK (0xffffffff << TIMER_TCR0_CNT_SYNC_SHIFT)
/* 0xB8 : Timer1 Counter Sync Value */
#define TIMER_TCR1_CNT_SYNC_SHIFT (0U)
#define TIMER_TCR1_CNT_SYNC_MASK (0xffffffff << TIMER_TCR1_CNT_SYNC_SHIFT)
/* 0xBC : Timer Division */
#define TIMER_TCDR0_SHIFT (8U)
#define TIMER_TCDR0_MASK (0xff << TIMER_TCDR0_SHIFT)
#define TIMER_TCDR1_SHIFT (16U)
#define TIMER_TCDR1_MASK (0xff << TIMER_TCDR1_SHIFT)
#define TIMER_WCDR_SHIFT (24U)
#define TIMER_WCDR_MASK (0xff << TIMER_WCDR_SHIFT)
/* 0xC0 : GPIO Mode */
#define TIMER0_GPIO_EN (1 << 1U)
#define TIMER0_GPIO_INV (1 << 5U)
#define TIMER1_GPIO_INV (1 << 6U)
#define TIMER_WDT_GPIO_INV (1 << 7U)
#define TIMER_GPIO_LAT_OK (1 << 31U)
/* 0xC4 : GPIO Latch Value1 */
#define TIMER_GPIO_LAT1_SHIFT (0U)
#define TIMER_GPIO_LAT1_MASK (0xffffffff << TIMER_GPIO_LAT1_SHIFT)
/* 0xC8 : GPIO Latch Value2 */
#define TIMER_GPIO_LAT2_SHIFT (0U)
#define TIMER_GPIO_LAT2_MASK (0xffffffff << TIMER_GPIO_LAT2_SHIFT)
/* 0xCC : Timer Division Force */
#define TIMER_TCDR0_FORCE (1 << 1U)
#define TIMER_TCDR1_FORCE (1 << 2U)
#define TIMER_WCDR_FORCE (1 << 4U)
#endif /* __HARDWARE_TIMER_H__ */

3801
include/bl808/tzc_nsec_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

3801
include/bl808/tzc_sec_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

264
include/bl808/uart_reg.h Normal file
View File

@ -0,0 +1,264 @@
/**
******************************************************************************
* @file uart_reg.h
* @version V1.0
* @date 2022-06-10
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_UART_H__
#define __HARDWARE_UART_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define UART_UTX_CONFIG_OFFSET (0x0) /* utx_config */
#define UART_URX_CONFIG_OFFSET (0x4) /* urx_config */
#define UART_BIT_PRD_OFFSET (0x8) /* uart_bit_prd */
#define UART_DATA_CONFIG_OFFSET (0xC) /* data_config */
#define UART_UTX_IR_POSITION_OFFSET (0x10) /* utx_ir_position */
#define UART_URX_IR_POSITION_OFFSET (0x14) /* urx_ir_position */
#define UART_URX_RTO_TIMER_OFFSET (0x18) /* urx_rto_timer */
#define UART_SW_MODE_OFFSET (0x1C) /* uart_sw_mode */
#define UART_INT_STS_OFFSET (0x20) /* UART interrupt status */
#define UART_INT_MASK_OFFSET (0x24) /* UART interrupt mask */
#define UART_INT_CLEAR_OFFSET (0x28) /* UART interrupt clear */
#define UART_INT_EN_OFFSET (0x2C) /* UART interrupt enable */
#define UART_STATUS_OFFSET (0x30) /* uart_status */
#define UART_STS_URX_ABR_PRD_OFFSET (0x34) /* sts_urx_abr_prd */
#define UART_URX_ABR_PRD_B01_OFFSET (0x38) /* urx_abr_prd_b01 */
#define UART_URX_ABR_PRD_B23_OFFSET (0x3C) /* urx_abr_prd_b23 */
#define UART_URX_ABR_PRD_B45_OFFSET (0x40) /* urx_abr_prd_b45 */
#define UART_URX_ABR_PRD_B67_OFFSET (0x44) /* urx_abr_prd_b67 */
#define UART_URX_ABR_PW_TOL_OFFSET (0x48) /* urx_abr_pw_tol */
#define UART_URX_BCR_INT_CFG_OFFSET (0x50) /* urx_bcr_int_cfg */
#define UART_UTX_RS485_CFG_OFFSET (0x54) /* utx_rs485_cfg */
#define UART_FIFO_CONFIG_0_OFFSET (0x80) /* uart_fifo_config_0 */
#define UART_FIFO_CONFIG_1_OFFSET (0x84) /* uart_fifo_config_1 */
#define UART_FIFO_WDATA_OFFSET (0x88) /* uart_fifo_wdata */
#define UART_FIFO_RDATA_OFFSET (0x8C) /* uart_fifo_rdata */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : utx_config */
#define UART_CR_UTX_EN (1 << 0U)
#define UART_CR_UTX_CTS_EN (1 << 1U)
#define UART_CR_UTX_FRM_EN (1 << 2U)
#define UART_CR_UTX_LIN_EN (1 << 3U)
#define UART_CR_UTX_PRT_EN (1 << 4U)
#define UART_CR_UTX_PRT_SEL (1 << 5U)
#define UART_CR_UTX_IR_EN (1 << 6U)
#define UART_CR_UTX_IR_INV (1 << 7U)
#define UART_CR_UTX_BIT_CNT_D_SHIFT (8U)
#define UART_CR_UTX_BIT_CNT_D_MASK (0x7 << UART_CR_UTX_BIT_CNT_D_SHIFT)
#define UART_CR_UTX_BIT_CNT_P_SHIFT (11U)
#define UART_CR_UTX_BIT_CNT_P_MASK (0x3 << UART_CR_UTX_BIT_CNT_P_SHIFT)
#define UART_CR_UTX_BIT_CNT_B_SHIFT (13U)
#define UART_CR_UTX_BIT_CNT_B_MASK (0x7 << UART_CR_UTX_BIT_CNT_B_SHIFT)
#define UART_CR_UTX_LEN_SHIFT (16U)
#define UART_CR_UTX_LEN_MASK (0xffff << UART_CR_UTX_LEN_SHIFT)
/* 0x4 : urx_config */
#define UART_CR_URX_EN (1 << 0U)
#define UART_CR_URX_ABR_EN (1 << 1U)
#define UART_CR_URX_LIN_EN (1 << 3U)
#define UART_CR_URX_PRT_EN (1 << 4U)
#define UART_CR_URX_PRT_SEL (1 << 5U)
#define UART_CR_URX_IR_EN (1 << 6U)
#define UART_CR_URX_IR_INV (1 << 7U)
#define UART_CR_URX_BIT_CNT_D_SHIFT (8U)
#define UART_CR_URX_BIT_CNT_D_MASK (0x7 << UART_CR_URX_BIT_CNT_D_SHIFT)
#define UART_CR_URX_DEG_EN (1 << 11U)
#define UART_CR_URX_DEG_CNT_SHIFT (12U)
#define UART_CR_URX_DEG_CNT_MASK (0xf << UART_CR_URX_DEG_CNT_SHIFT)
#define UART_CR_URX_LEN_SHIFT (16U)
#define UART_CR_URX_LEN_MASK (0xffff << UART_CR_URX_LEN_SHIFT)
/* 0x8 : uart_bit_prd */
#define UART_CR_UTX_BIT_PRD_SHIFT (0U)
#define UART_CR_UTX_BIT_PRD_MASK (0xffff << UART_CR_UTX_BIT_PRD_SHIFT)
#define UART_CR_URX_BIT_PRD_SHIFT (16U)
#define UART_CR_URX_BIT_PRD_MASK (0xffff << UART_CR_URX_BIT_PRD_SHIFT)
/* 0xC : data_config */
#define UART_CR_UART_BIT_INV (1 << 0U)
/* 0x10 : utx_ir_position */
#define UART_CR_UTX_IR_POS_S_SHIFT (0U)
#define UART_CR_UTX_IR_POS_S_MASK (0xffff << UART_CR_UTX_IR_POS_S_SHIFT)
#define UART_CR_UTX_IR_POS_P_SHIFT (16U)
#define UART_CR_UTX_IR_POS_P_MASK (0xffff << UART_CR_UTX_IR_POS_P_SHIFT)
/* 0x14 : urx_ir_position */
#define UART_CR_URX_IR_POS_S_SHIFT (0U)
#define UART_CR_URX_IR_POS_S_MASK (0xffff << UART_CR_URX_IR_POS_S_SHIFT)
/* 0x18 : urx_rto_timer */
#define UART_CR_URX_RTO_VALUE_SHIFT (0U)
#define UART_CR_URX_RTO_VALUE_MASK (0xff << UART_CR_URX_RTO_VALUE_SHIFT)
/* 0x1C : uart_sw_mode */
#define UART_CR_UTX_TXD_SW_MODE (1 << 0U)
#define UART_CR_UTX_TXD_SW_VAL (1 << 1U)
#define UART_CR_URX_RTS_SW_MODE (1 << 2U)
#define UART_CR_URX_RTS_SW_VAL (1 << 3U)
/* 0x20 : UART interrupt status */
#define UART_UTX_END_INT (1 << 0U)
#define UART_URX_END_INT (1 << 1U)
#define UART_UTX_FIFO_INT (1 << 2U)
#define UART_URX_FIFO_INT (1 << 3U)
#define UART_URX_RTO_INT (1 << 4U)
#define UART_URX_PCE_INT (1 << 5U)
#define UART_UTX_FER_INT (1 << 6U)
#define UART_URX_FER_INT (1 << 7U)
#define UART_URX_LSE_INT (1 << 8U)
#define UART_URX_BCR_INT (1 << 9U)
#define UART_URX_ADS_INT (1 << 10U)
#define UART_URX_AD5_INT (1 << 11U)
/* 0x24 : UART interrupt mask */
#define UART_CR_UTX_END_MASK (1 << 0U)
#define UART_CR_URX_END_MASK (1 << 1U)
#define UART_CR_UTX_FIFO_MASK (1 << 2U)
#define UART_CR_URX_FIFO_MASK (1 << 3U)
#define UART_CR_URX_RTO_MASK (1 << 4U)
#define UART_CR_URX_PCE_MASK (1 << 5U)
#define UART_CR_UTX_FER_MASK (1 << 6U)
#define UART_CR_URX_FER_MASK (1 << 7U)
#define UART_CR_URX_LSE_MASK (1 << 8U)
#define UART_CR_URX_BCR_MASK (1 << 9U)
#define UART_CR_URX_ADS_MASK (1 << 10U)
#define UART_CR_URX_AD5_MASK (1 << 11U)
/* 0x28 : UART interrupt clear */
#define UART_CR_UTX_END_CLR (1 << 0U)
#define UART_CR_URX_END_CLR (1 << 1U)
#define UART_CR_URX_RTO_CLR (1 << 4U)
#define UART_CR_URX_PCE_CLR (1 << 5U)
#define UART_CR_URX_LSE_CLR (1 << 8U)
#define UART_CR_URX_BCR_CLR (1 << 9U)
#define UART_CR_URX_ADS_CLR (1 << 10U)
#define UART_CR_URX_AD5_CLR (1 << 11U)
/* 0x2C : UART interrupt enable */
#define UART_CR_UTX_END_EN (1 << 0U)
#define UART_CR_URX_END_EN (1 << 1U)
#define UART_CR_UTX_FIFO_EN (1 << 2U)
#define UART_CR_URX_FIFO_EN (1 << 3U)
#define UART_CR_URX_RTO_EN (1 << 4U)
#define UART_CR_URX_PCE_EN (1 << 5U)
#define UART_CR_UTX_FER_EN (1 << 6U)
#define UART_CR_URX_FER_EN (1 << 7U)
#define UART_CR_URX_LSE_EN (1 << 8U)
#define UART_CR_URX_BCR_EN (1 << 9U)
#define UART_CR_URX_ADS_EN (1 << 10U)
#define UART_CR_URX_AD5_EN (1 << 11U)
/* 0x30 : uart_status */
#define UART_STS_UTX_BUS_BUSY (1 << 0U)
#define UART_STS_URX_BUS_BUSY (1 << 1U)
/* 0x34 : sts_urx_abr_prd */
#define UART_STS_URX_ABR_PRD_START_SHIFT (0U)
#define UART_STS_URX_ABR_PRD_START_MASK (0xffff << UART_STS_URX_ABR_PRD_START_SHIFT)
#define UART_STS_URX_ABR_PRD_0X55_SHIFT (16U)
#define UART_STS_URX_ABR_PRD_0X55_MASK (0xffff << UART_STS_URX_ABR_PRD_0X55_SHIFT)
/* 0x38 : urx_abr_prd_b01 */
#define UART_STS_URX_ABR_PRD_BIT0_SHIFT (0U)
#define UART_STS_URX_ABR_PRD_BIT0_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT0_SHIFT)
#define UART_STS_URX_ABR_PRD_BIT1_SHIFT (16U)
#define UART_STS_URX_ABR_PRD_BIT1_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT1_SHIFT)
/* 0x3C : urx_abr_prd_b23 */
#define UART_STS_URX_ABR_PRD_BIT2_SHIFT (0U)
#define UART_STS_URX_ABR_PRD_BIT2_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT2_SHIFT)
#define UART_STS_URX_ABR_PRD_BIT3_SHIFT (16U)
#define UART_STS_URX_ABR_PRD_BIT3_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT3_SHIFT)
/* 0x40 : urx_abr_prd_b45 */
#define UART_STS_URX_ABR_PRD_BIT4_SHIFT (0U)
#define UART_STS_URX_ABR_PRD_BIT4_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT4_SHIFT)
#define UART_STS_URX_ABR_PRD_BIT5_SHIFT (16U)
#define UART_STS_URX_ABR_PRD_BIT5_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT5_SHIFT)
/* 0x44 : urx_abr_prd_b67 */
#define UART_STS_URX_ABR_PRD_BIT6_SHIFT (0U)
#define UART_STS_URX_ABR_PRD_BIT6_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT6_SHIFT)
#define UART_STS_URX_ABR_PRD_BIT7_SHIFT (16U)
#define UART_STS_URX_ABR_PRD_BIT7_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT7_SHIFT)
/* 0x48 : urx_abr_pw_tol */
#define UART_CR_URX_ABR_PW_TOL_SHIFT (0U)
#define UART_CR_URX_ABR_PW_TOL_MASK (0xff << UART_CR_URX_ABR_PW_TOL_SHIFT)
/* 0x50 : urx_bcr_int_cfg */
#define UART_CR_URX_BCR_VALUE_SHIFT (0U)
#define UART_CR_URX_BCR_VALUE_MASK (0xffff << UART_CR_URX_BCR_VALUE_SHIFT)
#define UART_STS_URX_BCR_COUNT_SHIFT (16U)
#define UART_STS_URX_BCR_COUNT_MASK (0xffff << UART_STS_URX_BCR_COUNT_SHIFT)
/* 0x54 : utx_rs485_cfg */
#define UART_CR_UTX_RS485_EN (1 << 0U)
#define UART_CR_UTX_RS485_POL (1 << 1U)
/* 0x80 : uart_fifo_config_0 */
#define UART_DMA_TX_EN (1 << 0U)
#define UART_DMA_RX_EN (1 << 1U)
#define UART_TX_FIFO_CLR (1 << 2U)
#define UART_RX_FIFO_CLR (1 << 3U)
#define UART_TX_FIFO_OVERFLOW (1 << 4U)
#define UART_TX_FIFO_UNDERFLOW (1 << 5U)
#define UART_RX_FIFO_OVERFLOW (1 << 6U)
#define UART_RX_FIFO_UNDERFLOW (1 << 7U)
/* 0x84 : uart_fifo_config_1 */
#define UART_TX_FIFO_CNT_SHIFT (0U)
#define UART_TX_FIFO_CNT_MASK (0x3f << UART_TX_FIFO_CNT_SHIFT)
#define UART_RX_FIFO_CNT_SHIFT (8U)
#define UART_RX_FIFO_CNT_MASK (0x3f << UART_RX_FIFO_CNT_SHIFT)
#define UART_TX_FIFO_TH_SHIFT (16U)
#define UART_TX_FIFO_TH_MASK (0x1f << UART_TX_FIFO_TH_SHIFT)
#define UART_RX_FIFO_TH_SHIFT (24U)
#define UART_RX_FIFO_TH_MASK (0x1f << UART_RX_FIFO_TH_SHIFT)
/* 0x88 : uart_fifo_wdata */
#define UART_FIFO_WDATA_SHIFT (0U)
#define UART_FIFO_WDATA_MASK (0xff << UART_FIFO_WDATA_SHIFT)
/* 0x8C : uart_fifo_rdata */
#define UART_FIFO_RDATA_SHIFT (0U)
#define UART_FIFO_RDATA_MASK (0xff << UART_FIFO_RDATA_SHIFT)
#endif /* __HARDWARE_UART_H__ */

734
include/bl808/usb_v2_reg.h Normal file
View File

@ -0,0 +1,734 @@
/**
******************************************************************************
* @file usb_v2_reg.h
* @version V1.0
* @date 2022-08-15
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_USB_V2_H__
#define __HARDWARE_USB_V2_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define USB_HCCAP_OFFSET (0x0) /* HCCAP */
#define USB_HCSPARAMS_OFFSET (0x4) /* HCSPARAMS */
#define USB_HCCPARAMS_OFFSET (0x8) /* HCCPARAMS */
#define USBCMD_OFFSET (0x10) /* USBCMD */
#define USBSTS_OFFSET (0x14) /* USBSTS */
#define USBINTR_OFFSET (0x18) /* USBINTR */
#define USB_FRINDEX_OFFSET (0x1C) /* FRINDEX */
#define USB_PERIODICLISTBASE_OFFSET (0x24) /* PERIODICLISTBASE */
#define USB_ASYNCLISTADDR_OFFSET (0x28) /* ASYNCLISTADDR */
#define USB_PORTSC_OFFSET (0x30) /* PORTSC */
#define USB_HCMISC_OFFSET (0x40) /* HCMISC */
#define USB_FS_EOF_OFFSET (0x44) /* FS_EOF */
#define USB_HS_EOF_OFFSET (0x48) /* HS_EOF */
#define USB_OTG_CSR_OFFSET (0x80) /* OTG_CSR */
#define USB_OTG_ISR_OFFSET (0x84) /* OTG_ISR */
#define USB_OTG_IER_OFFSET (0x88) /* OTG_IER */
#define USB_GLB_ISR_OFFSET (0xC0) /* GLB_ISR */
#define USB_GLB_INT_OFFSET (0xC4) /* GLB_INT */
#define USB_REVISION_OFFSET (0xE0) /* REVISION */
#define USB_FEATURE_OFFSET (0xE4) /* FEATURE */
#define USB_AXI_CR_OFFSET (0xE8) /* AXI_CR */
#define USB_DEV_CTL_OFFSET (0x100) /* DEV_CTL */
#define USB_DEV_ADR_OFFSET (0x104) /* DEV_ADR */
#define USB_DEV_TST_OFFSET (0x108) /* DEV_TST */
#define USB_DEV_SFN_OFFSET (0x10C) /* DEV_SFN */
#define USB_DEV_SMT_OFFSET (0x110) /* DEV_SMT */
#define USB_PHY_TST_OFFSET (0x114) /* PHY_TST */
#define USB_DEV_VCTL_OFFSET (0x118) /* DEV_VCTL */
#define USB_DEV_CXCFG_OFFSET (0x11C) /* DEV_CXCFG */
#define USB_DEV_CXCFE_OFFSET (0x120) /* DEV_CXCFE */
#define USB_DEV_ICR_OFFSET (0x124) /* DEV_ICR */
#define USB_DEV_MIGR_OFFSET (0x130) /* DEV_MIGR */
#define USB_DEV_MISG0_OFFSET (0x134) /* DEV_MISG0 */
#define USB_DEV_MISG1_OFFSET (0x138) /* DEV_MISG1 */
#define USB_DEV_MISG2_OFFSET (0x13C) /* DEV_MISG2 */
#define USB_DEV_IGR_OFFSET (0x140) /* DEV_IGR */
#define USB_DEV_ISG0_OFFSET (0x144) /* DEV_ISG0 */
#define USB_DEV_ISG1_OFFSET (0x148) /* DEV_ISG1 */
#define USB_DEV_ISG2_OFFSET (0x14C) /* DEV_ISG2 */
#define USB_DEV_RXZ_OFFSET (0x150) /* DEV_RXZ */
#define USB_DEV_TXZ_OFFSET (0x154) /* DEV_TXZ */
#define USB_DEV_ISE_OFFSET (0x158) /* DEV_ISE */
#define USB_DEV_INMPS1_OFFSET (0x160) /* DEV_INMPS1 */
#define USB_DEV_INMPS2_OFFSET (0x164) /* DEV_INMPS2 */
#define USB_DEV_INMPS3_OFFSET (0x168) /* DEV_INMPS3 */
#define USB_DEV_INMPS4_OFFSET (0x16C) /* DEV_INMPS4 */
#define USB_DEV_INMPS5_OFFSET (0x170) /* DEV_INMPS5 */
#define USB_DEV_INMPS6_OFFSET (0x174) /* DEV_INMPS6 */
#define USB_DEV_INMPS7_OFFSET (0x178) /* DEV_INMPS7 */
#define USB_DEV_INMPS8_OFFSET (0x17C) /* DEV_INMPS8 */
#define USB_DEV_OUTMPS1_OFFSET (0x180) /* DEV_OUTMPS1 */
#define USB_DEV_OUTMPS2_OFFSET (0x184) /* DEV_OUTMPS2 */
#define USB_DEV_OUTMPS3_OFFSET (0x188) /* DEV_OUTMPS3 */
#define USB_DEV_OUTMPS4_OFFSET (0x18C) /* DEV_OUTMPS4 */
#define USB_DEV_OUTMPS5_OFFSET (0x190) /* DEV_OUTMPS5 */
#define USB_DEV_OUTMPS6_OFFSET (0x194) /* DEV_OUTMPS6 */
#define USB_DEV_OUTMPS7_OFFSET (0x198) /* DEV_OUTMPS7 */
#define USB_DEV_OUTMPS8_OFFSET (0x19C) /* DEV_OUTMPS8 */
#define USB_DEV_EPMAP0_OFFSET (0x1A0) /* DEV_EPMAP0 */
#define USB_DEV_EPMAP1_OFFSET (0x1A4) /* DEV_EPMAP1 */
#define USB_DEV_FMAP_OFFSET (0x1A8) /* DEV_FMAP */
#define USB_DEV_FCFG_OFFSET (0x1AC) /* DEV_FCFG */
#define USB_DEV_FIBC0_OFFSET (0x1B0) /* DEV_FIBC0 */
#define USB_DEV_FIBC1_OFFSET (0x1B4) /* DEV_FIBC1 */
#define USB_DEV_FIBC2_OFFSET (0x1B8) /* DEV_FIBC2 */
#define USB_DEV_FIBC3_OFFSET (0x1BC) /* DEV_FIBC3 */
#define USB_DMA_TFN_OFFSET (0x1C0) /* DMA_TFN */
#define USB_DMA_CPS0_OFFSET (0x1C4) /* DMA_CPS0 */
#define USB_DMA_CPS1_OFFSET (0x1C8) /* DMA_CPS1 */
#define USB_DMA_CPS2_OFFSET (0x1CC) /* DMA_CPS2 */
#define USB_DMA_CPS3_OFFSET (0x1D0) /* DMA_CPS3 */
#define USB_DMA_CPS4_OFFSET (0x1D4) /* DMA_CPS4 */
#define USB_DEV_FMAP2_OFFSET (0x1D8) /* DEV_FMAP2 */
#define USB_DEV_FCFG2_OFFSET (0x1DC) /* DEV_FCFG2 */
#define USB_DEV_FMAP3_OFFSET (0x1E0) /* DEV_FMAP3 */
#define USB_DEV_FCFG3_OFFSET (0x1E4) /* DEV_FCFG3 */
#define USB_DEV_FMAP4_OFFSET (0x1E8) /* DEV_FMAP4 */
#define USB_DEV_FCFG4_OFFSET (0x1EC) /* DEV_FCFG4 */
#define USB_DEV_FIBC4_OFFSET (0x1F0) /* DEV_FIBC4 */
#define USB_DEV_FIBC5_OFFSET (0x1F4) /* DEV_FIBC5 */
#define USB_DEV_FIBC6_OFFSET (0x1F8) /* DEV_FIBC6 */
#define USB_DEV_FIBC7_OFFSET (0x1FC) /* DEV_FIBC7 */
#define USB_VDMA_CXFPS1_OFFSET (0x300) /* VDMA_CXFPS1 */
#define USB_VDMA_CXFPS2_OFFSET (0x304) /* VDMA_CXFPS2 */
#define USB_VDMA_F0PS1_OFFSET (0x308) /* VDMA_F0PS1 */
#define USB_VDMA_F0PS2_OFFSET (0x30C) /* VDMA_F0PS2 */
#define USB_VDMA_F1PS1_OFFSET (0x310) /* VDMA_F1PS1 */
#define USB_VDMA_F1PS2_OFFSET (0x314) /* VDMA_F1PS2 */
#define USB_VDMA_F2PS1_OFFSET (0x318) /* VDMA_F2PS1 */
#define USB_VDMA_F2PS2_OFFSET (0x31C) /* VDMA_F2PS2 */
#define USB_VDMA_F3PS1_OFFSET (0x320) /* VDMA_F3PS1 */
#define USB_VDMA_F3PS2_OFFSET (0x324) /* VDMA_F3PS2 */
#define USB_DEV_ISG3_OFFSET (0x328) /* DEV_ISG3 */
#define USB_DEV_MISG3_OFFSET (0x32C) /* DEV_MISG3 */
#define USB_VDMA_CTRL_OFFSET (0x330) /* VDMA_CTRL */
#define USB_LPM_CAP_OFFSET (0x334) /* LPM_CAP */
#define USB_DEV_ISG4_OFFSET (0x338) /* DEV_ISG4 */
#define USB_DEV_MISG4_OFFSET (0x33C) /* DEV_MISG4 */
#define USB_VDMA_FNPS1_OFFSET (0x350) /* VDMA_FNPS1 */
#define USB_VDMA_FNPS2_OFFSET (0x354) /* VDMA_FNPS2 */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : HCCAP */
#define USB_CAPLENGTH_SHIFT (0U)
#define USB_CAPLENGTH_MASK (0xff << USB_CAPLENGTH_SHIFT)
#define USB_HCIVERSION_SHIFT (16U)
#define USB_HCIVERSION_MASK (0xffff << USB_HCIVERSION_SHIFT)
/* 0x4 : HCSPARAMS */
#define USB_N_PORTS_SHIFT (0U)
#define USB_N_PORTS_MASK (0xf << USB_N_PORTS_SHIFT)
/* 0x8 : HCCPARAMS */
#define USB_PROG_FR_LIST_FLAG (1 << 1U)
#define USB_ASYN_SCH_PARK_CAP (1 << 2U)
/* 0x10 : USBCMD */
#define USB_RS (1 << 0U)
#define USB_HC_RESET (1 << 1U)
#define USB_FRL_SIZE_SHIFT (2U)
#define USB_FRL_SIZE_MASK (0x3 << USB_FRL_SIZE_SHIFT)
#define USB_PSCH_EN (1 << 4U)
#define USB_ASCH_EN (1 << 5U)
#define USB_INT_OAAD (1 << 6U)
#define USB_ASYN_PK_CNT_SHIFT (8U)
#define USB_ASYN_PK_CNT_MASK (0x3 << USB_ASYN_PK_CNT_SHIFT)
#define USB_ASYN_PK_EN (1 << 11U)
#define USB_INT_THRC_SHIFT (16U)
#define USB_INT_THRC_MASK (0xff << USB_INT_THRC_SHIFT)
/* 0x14 : USBSTS */
#define USB_INT (1 << 0U)
#define USBERR_INT (1 << 1U)
#define USB_PO_CHG_DET (1 << 2U)
#define USB_FRL_ROL (1 << 3U)
#define USB_H_SYSERR (1 << 4U)
#define USB_INT_OAA (1 << 5U)
#define USB_HCHALTED (1 << 12U)
#define USB_RECLAMATION (1 << 13U)
#define USB_PSCH_STS (1 << 14U)
#define USB_ASCH_STS (1 << 15U)
/* 0x18 : USBINTR */
#define USB_INT_EN (1 << 0U)
#define USBERR_INT_EN (1 << 1U)
#define USB_PO_CHG_INT_EN (1 << 2U)
#define USB_FRL_ROL_EN (1 << 3U)
#define USB_H_SYSERR_EN (1 << 4U)
#define USB_INT_OAA_EN (1 << 5U)
/* 0x1C : FRINDEX */
#define USB_FRINDEX_SHIFT (0U)
#define USB_FRINDEX_MASK (0x3fff << USB_FRINDEX_SHIFT)
/* 0x24 : PERIODICLISTBASE */
#define USB_PERI_BASADR_SHIFT (12U)
#define USB_PERI_BASADR_MASK (0xfffff << USB_PERI_BASADR_SHIFT)
/* 0x28 : ASYNCLISTADDR */
#define USB_ASYNC_LADR_SHIFT (5U)
#define USB_ASYNC_LADR_MASK (0x7fffff << USB_ASYNC_LADR_SHIFT)
/* 0x30 : PORTSC */
#define USB_CONN_STS (1 << 0U)
#define USB_CONN_CHG (1 << 1U)
#define USB_PO_EN (1 << 2U)
#define USB_PO_EN_CHG (1 << 3U)
#define USB_F_PO_RESM (1 << 6U)
#define USB_PO_SUSP (1 << 7U)
#define USB_PO_RESET (1 << 8U)
#define USB_LINE_STS_SHIFT (10U)
#define USB_LINE_STS_MASK (0x3 << USB_LINE_STS_SHIFT)
#define USB_PORT_TEST_SHIFT (16U)
#define USB_PORT_TEST_MASK (0xf << USB_PORT_TEST_SHIFT)
#define USB_HC_TST_PKDONE (1 << 20U)
/* 0x40 : HCMISC */
#define USB_ASYN_SCH_SLPT_SHIFT (0U)
#define USB_ASYN_SCH_SLPT_MASK (0x3 << USB_ASYN_SCH_SLPT_SHIFT)
#define USB_EOF1_TIME_SHIFT (2U)
#define USB_EOF1_TIME_MASK (0x3 << USB_EOF1_TIME_SHIFT)
#define USB_EOF2_TIME_SHIFT (4U)
#define USB_EOF2_TIME_MASK (0x3 << USB_EOF2_TIME_SHIFT)
#define USB_HOSTPHY_SUSPEND (1 << 6U)
#define USB_HC_WKP_DET_EN (1 << 8U)
#define USB_HC_CONN_DET_EN (1 << 9U)
/* 0x44 : FS_EOF */
#define USB_FS_EOF1_TIME_SHIFT (0U)
#define USB_FS_EOF1_TIME_MASK (0xfff << USB_FS_EOF1_TIME_SHIFT)
#define USB_FS_EOF1_TIME_125US_SHIFT (12U)
#define USB_FS_EOF1_TIME_125US_MASK (0x7 << USB_FS_EOF1_TIME_125US_SHIFT)
#define USB_ITDDMASM_SHIFT (16U)
#define USB_ITDDMASM_MASK (0xf << USB_ITDDMASM_SHIFT)
#define USB_ITDTRAVSM_SHIFT (20U)
#define USB_ITDTRAVSM_MASK (0x3 << USB_ITDTRAVSM_SHIFT)
#define USB_DMADMSM_SHIFT (22U)
#define USB_DMADMSM_MASK (0xf << USB_DMADMSM_SHIFT)
#define USB_QHTTRSM_SHIFT (26U)
#define USB_QHTTRSM_MASK (0x7 << USB_QHTTRSM_SHIFT)
#define USB_QHTRAVSM_SHIFT (29U)
#define USB_QHTRAVSM_MASK (0x7 << USB_QHTRAVSM_SHIFT)
/* 0x48 : HS_EOF */
#define USB_HS_EOF1_TIME_SHIFT (0U)
#define USB_HS_EOF1_TIME_MASK (0xfff << USB_HS_EOF1_TIME_SHIFT)
#define USB_FS_EOF1_TIME_125US_SHIFT (12U)
#define USB_FS_EOF1_TIME_125US_MASK (0x7 << USB_FS_EOF1_TIME_125US_SHIFT)
#define USB_SITDDMASM_SHIFT (16U)
#define USB_SITDDMASM_MASK (0xf << USB_SITDDMASM_SHIFT)
#define USB_SITDTRAVSM_SHIFT (20U)
#define USB_SITDTRAVSM_MASK (0x3 << USB_SITDTRAVSM_SHIFT)
/* 0x80 : OTG_CSR */
#define USB_B_BUS_REQ (1 << 0U)
#define USB_B_HNP_EN (1 << 1U)
#define USB_B_DSCHRG_VBUS (1 << 2U)
#define USB_A_BUS_REQ_HOV (1 << 4U)
#define USB_A_BUS_DROP_HOV (1 << 5U)
#define USB_A_SET_B_HNP_EN (1 << 6U)
#define USB_A_SRP_DET_EN (1 << 7U)
#define USB_A_SRP_RESP_TYP (1 << 8U)
#define USB_ID_FLT_SEL (1 << 9U)
#define USB_VBUS_FLT_SEL_HOV_POV (1 << 10U)
#define USB_HDISCON_FLT_SEL_HOV (1 << 11U)
#define USB_IDPULUP_HOV_POV (1 << 13U)
#define USB_B_SESS_END_POV (1 << 16U)
#define USB_B_SESS_VLD_POV (1 << 17U)
#define USB_A_SESS_VLD (1 << 18U)
#define USB_VBUS_VLD_HOV (1 << 19U)
#define USB_CROLE_HOV_POV (1 << 20U)
#define USB_ID_HOV_POV (1 << 21U)
#define USB_SPD_TYP_HOV_POV_SHIFT (22U)
#define USB_SPD_TYP_HOV_POV_MASK (0x3 << USB_SPD_TYP_HOV_POV_SHIFT)
/* 0x84 : OTG_ISR */
#define USB_B_SRP_DN (1 << 0U)
#define USB_A_SRP_DET (1 << 4U)
#define USB_A_VBUS_ERR_HOV (1 << 5U)
#define USB_B_SESS_END_INT_POV (1 << 6U)
#define USB_RLCHG (1 << 8U)
#define USB_IDCHG (1 << 9U)
#define USB_OVC_HOV (1 << 10U)
#define USB_A_WAIT_CON_HOV (1 << 11U)
#define USB_APLGRMV (1 << 12U)
/* 0x88 : OTG_IER */
#define USB_B_SRP_DN_EN (1 << 0U)
#define USB_A_SRP_DET_INT_EN (1 << 4U)
#define USB_A_VBUS_ERR_EN_HOV (1 << 5U)
#define USB_B_SESS_END_EN_POV (1 << 6U)
#define USB_RLCHG_EN (1 << 8U)
#define USB_IDCHG_EN (1 << 9U)
#define USB_OVC_EN_HOV (1 << 10U)
#define USB_A_WAIT_CON_EN_HOV (1 << 11U)
#define USB_APLGRMV_EN (1 << 12U)
/* 0xC0 : GLB_ISR */
#define USB_DEV_INT (1 << 0U)
#define USB_OTG_INT (1 << 1U)
#define USB_HC_INT (1 << 2U)
/* 0xC4 : GLB_INT */
#define USB_MDEV_INT (1 << 0U)
#define USB_MOTG_INT (1 << 1U)
#define USB_MHC_INT (1 << 2U)
/* 0xE0 : REVISION */
#define USB_REVISION_SHIFT (0U)
#define USB_REVISION_MASK (0xffffffff << USB_REVISION_SHIFT)
/* 0xE4 : FEATURE */
#define USB_DMABUFSIZE_SHIFT (0U)
#define USB_DMABUFSIZE_MASK (0x1f << USB_DMABUFSIZE_SHIFT)
#define USB_FIFO_NUM_SHIFT (5U)
#define USB_FIFO_NUM_MASK (0x1f << USB_FIFO_NUM_SHIFT)
#define USB_EP_NUM_SHIFT (10U)
#define USB_EP_NUM_MASK (0x1f << USB_EP_NUM_SHIFT)
#define USB_DEV_ONLY (1 << 15U)
#define USB_HOST_ONLY (1 << 16U)
/* 0xE8 : AXI_CR */
#define USB_AXI_SGLBST (1 << 0U)
/* 0x100 : DEV_CTL */
#define USB_CAP_RMWAKUP (1 << 0U)
#define USB_HALF_SPEED_HOV (1 << 1U)
#define USB_GLINT_EN_HOV (1 << 2U)
#define USB_GOSUSP (1 << 3U)
#define USB_SFRST_HOV (1 << 4U)
#define USB_CHIP_EN_HOV (1 << 5U)
#define USB_HS_EN_HOV (1 << 6U)
#define USB_SYSBUS_WIDTH_HOV (1 << 7U)
#define USB_FORCE_FS (1 << 9U)
#define USB_IDLE_DEGLITCH_HOV (1 << 10U)
#define USB_LPM_BESL_MAX_SHIFT (12U)
#define USB_LPM_BESL_MAX_MASK (0xf << USB_LPM_BESL_MAX_SHIFT)
#define USB_LPM_BESL_MIN_SHIFT (16U)
#define USB_LPM_BESL_MIN_MASK (0xf << USB_LPM_BESL_MIN_SHIFT)
#define USB_LPM_BESL_SHIFT (20U)
#define USB_LPM_BESL_MASK (0xf << USB_LPM_BESL_SHIFT)
#define USB_LPM_EN (1 << 25U)
#define USB_LPM_ACCEPT (1 << 26U)
/* 0x104 : DEV_ADR */
#define USB_DEVADR_SHIFT (0U)
#define USB_DEVADR_MASK (0x7f << USB_DEVADR_SHIFT)
#define USB_AFT_CONF (1 << 7U)
/* 0x108 : DEV_TST */
#define USB_TST_CLRFF_HOV (1 << 0U)
#define USB_TST_LPCX (1 << 1U)
#define USB_TST_CLREA (1 << 2U)
#define USB_TST_DISTO_HOV (1 << 4U)
#define USB_TST_MOD_HOV (1 << 5U)
#define USB_DISGENSOF (1 << 6U)
#define USB_TST_MOD_TYP_HOV (1 << 7U)
/* 0x10C : DEV_SFN */
#define USB_SOFN_SHIFT (0U)
#define USB_SOFN_MASK (0x7ff << USB_SOFN_SHIFT)
#define USB_USOFN_SHIFT (11U)
#define USB_USOFN_MASK (0x7 << USB_USOFN_SHIFT)
/* 0x110 : DEV_SMT */
#define USB_SOFMT_SHIFT (0U)
#define USB_SOFMT_MASK (0xffff << USB_SOFMT_SHIFT)
/* 0x114 : PHY_TST */
#define USB_UNPLUG (1 << 0U)
#define USB_TST_JSTA (1 << 1U)
#define USB_TST_KSTA (1 << 2U)
#define USB_TST_SE0NAK (1 << 3U)
#define USB_TST_PKT (1 << 4U)
/* 0x11C : DEV_CXCFG */
#define USB_VSTA_HOV_SHIFT (0U)
#define USB_VSTA_HOV_MASK (0xff << USB_VSTA_HOV_SHIFT)
/* 0x120 : DEV_CXCFE */
#define USB_CX_DONE (1 << 0U)
#define USB_TST_PKDONE (1 << 1U)
#define USB_CX_STL (1 << 2U)
#define USB_CX_CLR (1 << 3U)
#define USB_CX_FUL (1 << 4U)
#define USB_CX_EMP (1 << 5U)
#define USB_F0_EMP (1 << 8U)
#define USB_F1_EMP (1 << 9U)
#define USB_F2_EMP (1 << 10U)
#define USB_F3_EMP (1 << 11U)
/* 0x124 : DEV_ICR */
#define USB_IDLE_CNT_SHIFT (0U)
#define USB_IDLE_CNT_MASK (0x7 << USB_IDLE_CNT_SHIFT)
/* 0x130 : DEV_MIGR */
#define USB_MINT_G0 (1 << 0U)
#define USB_MINT_G1 (1 << 1U)
#define USB_MINT_G2 (1 << 2U)
#define USB_MINT_G3 (1 << 3U)
#define USB_MINT_G4 (1 << 4U)
/* 0x134 : DEV_MISG0 */
#define USB_MCX_SETUP_INT (1 << 0U)
#define USB_MCX_IN_INT (1 << 1U)
#define USB_MCX_OUT_INT (1 << 2U)
#define USB_MCX_COMFAIL_INT (1 << 4U)
#define USB_MCX_COMABORT_INT (1 << 5U)
/* 0x138 : DEV_MISG1 */
#define USB_MF0_OUT_INT (1 << 0U)
#define USB_MF0_SPK_INT (1 << 1U)
#define USB_MF1_OUT_INT (1 << 2U)
#define USB_MF1_SPK_INT (1 << 3U)
#define USB_MF2_OUT_INT (1 << 4U)
#define USB_MF2_SPK_INT (1 << 5U)
#define USB_MF3_OUT_INT (1 << 6U)
#define USB_MF3_SPK_INT (1 << 7U)
#define USB_MF0_IN_INT (1 << 16U)
#define USB_MF1_IN_INT (1 << 17U)
#define USB_MF2_IN_INT (1 << 18U)
#define USB_MF3_IN_INT (1 << 19U)
/* 0x13C : DEV_MISG2 */
#define USB_MUSBRST_INT (1 << 0U)
#define USB_MSUSP_INT (1 << 1U)
#define USB_MRESM_INT (1 << 2U)
#define USB_MSEQ_ERR_INT (1 << 3U)
#define USB_MSEQ_ABORT_INT (1 << 4U)
#define USB_MTX0BYTE_INT (1 << 5U)
#define USB_MRX0BYTE_INT (1 << 6U)
#define USB_MDMA_CMPLT_HOV (1 << 7U)
#define USB_MDMA_ERROR_HOV (1 << 8U)
#define USB_MDEV_IDLE_HOV (1 << 9U)
#define USB_MDEV_WAKEUP_BYVBUS (1 << 10U)
/* 0x140 : DEV_IGR */
#define USB_INT_G0 (1 << 0U)
#define USB_INT_G1 (1 << 1U)
#define USB_INT_G2 (1 << 2U)
#define USB_INT_G3 (1 << 3U)
#define USB_INT_G4 (1 << 4U)
/* 0x144 : DEV_ISG0 */
#define USB_CX_SETUP_INT (1 << 0U)
#define USB_CX_IN_INT (1 << 1U)
#define USB_CX_OUT_INT (1 << 2U)
#define USB_CX_COMFAIL_INT (1 << 4U)
#define USB_CX_COMABT_INT (1 << 5U)
/* 0x148 : DEV_ISG1 */
#define USB_F0_OUT_INT (1 << 0U)
#define USB_F0_SPK_INT (1 << 1U)
#define USB_F1_OUT_INT (1 << 2U)
#define USB_F1_SPK_INT (1 << 3U)
#define USB_F2_OUT_INT (1 << 4U)
#define USB_F2_SPK_INT (1 << 5U)
#define USB_F3_OUT_INT (1 << 6U)
#define USB_F3_SPK_INT (1 << 7U)
#define USB_F0_IN_INT (1 << 16U)
#define USB_F1_IN_INT (1 << 17U)
#define USB_F2_IN_INT (1 << 18U)
#define USB_F3_IN_INT (1 << 19U)
/* 0x14C : DEV_ISG2 */
#define USBRST_INT (1 << 0U)
#define USB_SUSP_INT (1 << 1U)
#define USB_RESM_INT (1 << 2U)
#define USB_ISO_SEQ_ERR_INT (1 << 3U)
#define USB_ISO_SEQ_ABORT_INT (1 << 4U)
#define USB_TX0BYTE_INT (1 << 5U)
#define USB_RX0BYTE_INT (1 << 6U)
#define USB_DMA_CMPLT_HOV (1 << 7U)
#define USB_DMA_ERROR_HOV (1 << 8U)
#define USB_DEV_IDLE_HOV (1 << 9U)
#define USB_DEV_WAKEUP_BYVBUS (1 << 10U)
/* 0x150 : DEV_RXZ */
#define USB_RX0BYTE_EP1 (1 << 0U)
#define USB_RX0BYTE_EP2 (1 << 1U)
#define USB_RX0BYTE_EP3 (1 << 2U)
#define USB_RX0BYTE_EP4 (1 << 3U)
/* 0x154 : DEV_TXZ */
#define USB_TX0BYTE_EP1 (1 << 0U)
#define USB_TX0BYTE_EP2 (1 << 1U)
#define USB_TX0BYTE_EP3 (1 << 2U)
#define USB_TX0BYTE_EP4 (1 << 3U)
/* 0x158 : DEV_ISE */
#define USB_ISO_ABT_ERR_EP1 (1 << 0U)
#define USB_ISO_ABT_ERR_EP2 (1 << 1U)
#define USB_ISO_ABT_ERR_EP3 (1 << 2U)
#define USB_ISO_ABT_ERR_EP4 (1 << 3U)
#define USB_ISO_SEQ_ERR_EP1 (1 << 16U)
#define USB_ISO_SEQ_ERR_EP2 (1 << 17U)
#define USB_ISO_SEQ_ERR_EP3 (1 << 18U)
#define USB_ISO_SEQ_ERR_EP4 (1 << 19U)
/* 0x160 : DEV_INMPS1 */
#define USB_MAXPS_IEP1_SHIFT (0U)
#define USB_MAXPS_IEP1_MASK (0x7ff << USB_MAXPS_IEP1_SHIFT)
#define USB_STL_IEP1 (1 << 11U)
#define USB_RSTG_IEP1 (1 << 12U)
#define USB_TX_NUM_HBW_IEP1_SHIFT (13U)
#define USB_TX_NUM_HBW_IEP1_MASK (0x3 << USB_TX_NUM_HBW_IEP1_SHIFT)
#define USB_TX0BYTE_IEP1 (1 << 15U)
/* 0x164 : DEV_INMPS2 */
/* 0x168 : DEV_INMPS3 */
/* 0x16C : DEV_INMPS4 */
/* 0x170 : DEV_INMPS5 */
/* 0x174 : DEV_INMPS6 */
/* 0x178 : DEV_INMPS7 */
/* 0x17C : DEV_INMPS8 */
/* 0x180 : DEV_OUTMPS1 */
#define USB_MAXPS_OEP1_SHIFT (0U)
#define USB_MAXPS_OEP1_MASK (0x7ff << USB_MAXPS_OEP1_SHIFT)
#define USB_STL_OEP1 (1 << 11U)
#define USB_RSTG_OEP1 (1 << 12U)
/* 0x184 : DEV_OUTMPS2 */
/* 0x188 : DEV_OUTMPS3 */
/* 0x18C : DEV_OUTMPS4 */
/* 0x190 : DEV_OUTMPS5 */
/* 0x194 : DEV_OUTMPS6 */
/* 0x198 : DEV_OUTMPS7 */
/* 0x19C : DEV_OUTMPS8 */
/* 0x1A0 : DEV_EPMAP0 */
#define USB_FNO_IEP1_SHIFT (0U)
#define USB_FNO_IEP1_MASK (0xf << USB_FNO_IEP1_SHIFT)
#define USB_FNO_OEP1_SHIFT (4U)
#define USB_FNO_OEP1_MASK (0xf << USB_FNO_OEP1_SHIFT)
#define USB_FNO_IEP2_SHIFT (8U)
#define USB_FNO_IEP2_MASK (0xf << USB_FNO_IEP2_SHIFT)
#define USB_FNO_OEP2_SHIFT (12U)
#define USB_FNO_OEP2_MASK (0xf << USB_FNO_OEP2_SHIFT)
#define USB_FNO_IEP3_SHIFT (16U)
#define USB_FNO_IEP3_MASK (0xf << USB_FNO_IEP3_SHIFT)
#define USB_FNO_OEP3_SHIFT (20U)
#define USB_FNO_OEP3_MASK (0xf << USB_FNO_OEP3_SHIFT)
#define USB_FNO_IEP4_SHIFT (24U)
#define USB_FNO_IEP4_MASK (0xf << USB_FNO_IEP4_SHIFT)
#define USB_FNO_OEP4_SHIFT (28U)
#define USB_FNO_OEP4_MASK (0xf << USB_FNO_OEP4_SHIFT)
/* 0x1A4 : DEV_EPMAP1 */
/* 0x1A8 : DEV_FMAP */
#define USB_EPNO_FIFO0_SHIFT (0U)
#define USB_EPNO_FIFO0_MASK (0xf << USB_EPNO_FIFO0_SHIFT)
#define USB_DIR_FIFO0_SHIFT (4U)
#define USB_DIR_FIFO0_MASK (0x3 << USB_DIR_FIFO0_SHIFT)
#define USB_EPNO_FIFO1_SHIFT (8U)
#define USB_EPNO_FIFO1_MASK (0xf << USB_EPNO_FIFO1_SHIFT)
#define USB_DIR_FIFO1_SHIFT (12U)
#define USB_DIR_FIFO1_MASK (0x3 << USB_DIR_FIFO1_SHIFT)
#define USB_EPNO_FIFO2_SHIFT (16U)
#define USB_EPNO_FIFO2_MASK (0xf << USB_EPNO_FIFO2_SHIFT)
#define USB_DIR_FIFO2_SHIFT (20U)
#define USB_DIR_FIFO2_MASK (0x3 << USB_DIR_FIFO2_SHIFT)
#define USB_EPNO_FIFO3_SHIFT (24U)
#define USB_EPNO_FIFO3_MASK (0xf << USB_EPNO_FIFO3_SHIFT)
#define USB_DIR_FIFO3_SHIFT (28U)
#define USB_DIR_FIFO3_MASK (0x3 << USB_DIR_FIFO3_SHIFT)
/* 0x1AC : DEV_FCFG */
#define USB_BLK_TYP_F0_SHIFT (0U)
#define USB_BLK_TYP_F0_MASK (0x3 << USB_BLK_TYP_F0_SHIFT)
#define USB_BLKNO_F0_SHIFT (2U)
#define USB_BLKNO_F0_MASK (0x3 << USB_BLKNO_F0_SHIFT)
#define USB_BLKSZ_F0 (1 << 4U)
#define USB_EN_F0 (1 << 5U)
#define USB_BLK_TYP_F1_SHIFT (8U)
#define USB_BLK_TYP_F1_MASK (0x3 << USB_BLK_TYP_F1_SHIFT)
#define USB_BLKNO_F1_SHIFT (10U)
#define USB_BLKNO_F1_MASK (0x3 << USB_BLKNO_F1_SHIFT)
#define USB_BLKSZ_F1 (1 << 12U)
#define USB_EN_F1 (1 << 13U)
#define USB_BLK_TYP_F2_SHIFT (16U)
#define USB_BLK_TYP_F2_MASK (0x3 << USB_BLK_TYP_F2_SHIFT)
#define USB_BLKNO_F2_SHIFT (18U)
#define USB_BLKNO_F2_MASK (0x3 << USB_BLKNO_F2_SHIFT)
#define USB_BLKSZ_F2 (1 << 20U)
#define USB_EN_F2 (1 << 21U)
#define USB_BLK_TYP_F3_SHIFT (24U)
#define USB_BLK_TYP_F3_MASK (0x3 << USB_BLK_TYP_F3_SHIFT)
#define USB_BLKNO_F3_SHIFT (26U)
#define USB_BLKNO_F3_MASK (0x3 << USB_BLKNO_F3_SHIFT)
#define USB_BLKSZ_F3 (1 << 28U)
#define USB_EN_F3 (1 << 29U)
/* 0x1B0 : DEV_FIBC0 */
#define USB_BC_F0_SHIFT (0U)
#define USB_BC_F0_MASK (0x7ff << USB_BC_F0_SHIFT)
#define USB_FFRST0_HOV (1 << 12U)
/* 0x1B4 : DEV_FIBC1 */
/* 0x1B8 : DEV_FIBC2 */
/* 0x1BC : DEV_FIBC3 */
/* 0x1C0 : DMA_TFN */
#define USB_ACC_F0_HOV (1 << 0U)
#define USB_ACC_F1_HOV (1 << 1U)
#define USB_ACC_F2_HOV (1 << 2U)
#define USB_ACC_F3_HOV (1 << 3U)
#define USB_ACC_CXF_HOV (1 << 4U)
/* 0x1C4 : DMA_CPS0 */
#define USB_AWCHACHE_HOV_SHIFT (0U)
#define USB_AWCHACHE_HOV_MASK (0xf << USB_AWCHACHE_HOV_SHIFT)
#define USB_AWPORT_HOV_SHIFT (4U)
#define USB_AWPORT_HOV_MASK (0x7 << USB_AWPORT_HOV_SHIFT)
#define USB_AWLOCK_HOV_SHIFT (7U)
#define USB_AWLOCK_HOV_MASK (0x3 << USB_AWLOCK_HOV_SHIFT)
#define USB_ARCACHE_HOV_SHIFT (9U)
#define USB_ARCACHE_HOV_MASK (0xf << USB_ARCACHE_HOV_SHIFT)
#define USB_ARPORT_HOV_SHIFT (13U)
#define USB_ARPORT_HOV_MASK (0x7 << USB_ARPORT_HOV_SHIFT)
#define USB_ARLOCK_HOV_SHIFT (16U)
#define USB_ARLOCK_HOV_MASK (0x3 << USB_ARLOCK_HOV_SHIFT)
#define USB_BUF_LD_EN_HOV (1 << 18U)
#define USB_DST_WD_HOV (1 << 19U)
/* 0x1C8 : DMA_CPS1 */
#define USB_DMA_START_HOV (1 << 0U)
#define USB_DMA_TYPE_HOV (1 << 1U)
#define USB_DMA_IO_HOV (1 << 2U)
#define USB_DMA_ABORT_HOV (1 << 3U)
#define USB_CLRFIFO_DMAABORT_HOV (1 << 4U)
#define USB_DMA_LEN_HOV_SHIFT (8U)
#define USB_DMA_LEN_HOV_MASK (0x1ffff << USB_DMA_LEN_HOV_SHIFT)
#define USB_R_HPORT_HOV_SHIFT (25U)
#define USB_R_HPORT_HOV_MASK (0xf << USB_R_HPORT_HOV_SHIFT)
#define USB_UNDEF_LEN_BURST_HOV (1 << 29U)
#define USB_L1_WAKEUP (1 << 30U)
#define USB_DEVPHY_SUSPEND_HOV (1 << 31U)
/* 0x1CC : DMA_CPS2 */
#define USB_DMA_MADDR_HOV_SHIFT (0U)
#define USB_DMA_MADDR_HOV_MASK (0xffffffff << USB_DMA_MADDR_HOV_SHIFT)
/* 0x1D0 : DMA_CPS3 */
#define USB_SETUP_CMD_RPORT_SHIFT (0U)
#define USB_SETUP_CMD_RPORT_MASK (0xffffffff << USB_SETUP_CMD_RPORT_SHIFT)
/* 0x1D4 : DMA_CPS4 */
/* 0x1D8 : DEV_FMAP2 */
/* 0x1DC : DEV_FCFG2 */
/* 0x1E0 : DEV_FMAP3 */
/* 0x1E4 : DEV_FCFG3 */
/* 0x1E8 : DEV_FMAP4 */
/* 0x1EC : DEV_FCFG4 */
/* 0x1F0 : DEV_FIBC4 */
/* 0x1F4 : DEV_FIBC5 */
/* 0x1F8 : DEV_FIBC6 */
/* 0x1FC : DEV_FIBC7 */
/* 0x300 : VDMA_CXFPS1 */
#define USB_VDMA_START_CXF (1 << 0U)
#define USB_VDMA_TYPE_CXF (1 << 1U)
#define USB_VDMA_IO_CXF (1 << 2U)
#define USB_VDMA_LEN_CXF_SHIFT (8U)
#define USB_VDMA_LEN_CXF_MASK (0x1ffff << USB_VDMA_LEN_CXF_SHIFT)
/* 0x304 : VDMA_CXFPS2 */
#define USB_VDMA_MADDR_CXF_SHIFT (8U)
#define USB_VDMA_MADDR_CXF_MASK (0x1ffff << USB_VDMA_MADDR_CXF_SHIFT)
/* 0x308 : VDMA_F0PS1 */
#define USB_VDMA_START_F0 (1 << 0U)
#define USB_VDMA_TYPE_F0 (1 << 1U)
#define USB_VDMA_IO_F0 (1 << 2U)
#define USB_VDMA_LEN_F0_SHIFT (8U)
#define USB_VDMA_LEN_F0_MASK (0x1ffff << USB_VDMA_LEN_F0_SHIFT)
/* 0x30c : VDMA_F0PS2 */
#define USB_VDMA_MADDR_F0_SHIFT (8U)
#define USB_VDMA_MADDR_F0_MASK (0x1ffff << USB_VDMA_MADDR_F0_SHIFT)
/* 0x310 : VDMA_F1PS1 */
/* 0x314 : VDMA_F1PS2 */
/* 0x318 : VDMA_F2PS1 */
/* 0x31C : VDMA_F2PS2 */
/* 0x320 : VDMA_F3PS1 */
/* 0x324 : VDMA_F3PS2 */
/* 0x328 : DEV_ISG3 */
#define USB_VDMA_CMPLT_CXF (1 << 0U)
#define USB_VDMA_CMPLT_F0 (1 << 1U)
#define USB_VDMA_CMPLT_F1 (1 << 2U)
#define USB_VDMA_CMPLT_F2 (1 << 3U)
#define USB_VDMA_CMPLT_F3 (1 << 4U)
#define USB_VDMA_ERROR_CXF (1 << 16U)
#define USB_VDMA_ERROR_F0 (1 << 17U)
#define USB_VDMA_ERROR_F1 (1 << 18U)
#define USB_VDMA_ERROR_F2 (1 << 19U)
#define USB_VDMA_ERROR_F3 (1 << 20U)
/* 0x32C : DEV_MISG3 */
#define USB_MVDMA_CMPLT_CXF (1 << 0U)
#define USB_MVDMA_CMPLT_F0 (1 << 1U)
#define USB_MVDMA_CMPLT_F1 (1 << 2U)
#define USB_MVDMA_CMPLT_F2 (1 << 3U)
#define USB_MVDMA_CMPLT_F3 (1 << 4U)
#define USB_MVDMA_ERROR_CXF (1 << 16U)
#define USB_MVDMA_ERROR_F0 (1 << 17U)
#define USB_MVDMA_ERROR_F1 (1 << 18U)
#define USB_MVDMA_ERROR_F2 (1 << 19U)
#define USB_MVDMA_ERROR_F3 (1 << 20U)
/* 0x330 : VDMA_CTRL */
#define USB_VDMA_EN (1 << 0U)
/* 0x334 : LPM_CAP */
#define USB_LPM_WAKEUP_EN (1 << 0U)
/* 0x338 : DEV_ISG4 */
#define USB_L1_INT (1 << 0U)
/* 0x33C : DEV_MISG4 */
#define USB_ML1_INT (1 << 0U)
/* 0x350 : VDMA_FnPS1 */
/* 0x354 : VDMA_FnPS2 */
#endif /* __HARDWARE_USB_V2_H__ */