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3 Commits

Author SHA1 Message Date
Claudiu Beznea
c05be59ca8 clk: at91: clk-master: split master clock in pres and divider 
Split master clock in 2 controlling block: one for prescaler one for
divider. This will allow referencing correctly the CPU clock and
master clock in device trees.

Reported-by: Eugen Hristev <eugen.hristev@microchip.com>
Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with
CCF")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 2021-09-21 10:05:37 +03:00
Eugen Hristev
dc470834a1 clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics 
This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 2020-10-19 09:19:53 +03:00
Claudiu Beznea
6a6fe3ed4d clk: at91: sama7g5: add clock support 
Add clock support for SAMA7G5.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 2020-09-22 11:27:18 +03:00