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4 Commits

Author SHA1 Message Date
Samuel Holland
0636e3e95b riscv: cpu: thead: Add CPU-specific cache operations 
Use the vendor CSRs for enabling/disabling the caches, and the ISA
extension for cache maintenance.

Signed-off-by: Samuel Holland <samuel@sholland.org>
 2023-02-05 14:15:31 -06:00
Samuel Holland
88065c42f7 riscv: cpu: thead: Initialize extension CSRs 
Enable the T-HEAD ISA extensions, as these are required to use the cache
maintenance instructions. Enable the branch predictor and BTB to improve
performance. Some bits are only available on specific CPU models, so
provide Kconfig symbols for selecting the right model.

Signed-off-by: Samuel Holland <samuel@sholland.org>
 2023-02-05 12:05:24 -06:00
Samuel Holland
8ac224a247 riscv: cpu: thead: Add extension CSR definitions 
T-HEAD C9xx and E9xx CPUs contain some extra CSRs which control the
branch predictor and cache-related functionality.

Signed-off-by: Samuel Holland <samuel@sholland.org>
 2023-02-05 12:05:24 -06:00
Samuel Holland
722832d48b riscv: cpu: Add skeleton for T-HEAD CPUs 
This is a direct copy of the existing generic CPU code.

Signed-off-by: Samuel Holland <samuel@sholland.org>
 2023-02-05 12:05:24 -06:00