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2 Commits

Author SHA1 Message Date
Samuel Holland
0636e3e95b riscv: cpu: thead: Add CPU-specific cache operations 
Use the vendor CSRs for enabling/disabling the caches, and the ISA
extension for cache maintenance.

Signed-off-by: Samuel Holland <samuel@sholland.org>
 2023-02-05 14:15:31 -06:00
Samuel Holland
722832d48b riscv: cpu: Add skeleton for T-HEAD CPUs 
This is a direct copy of the existing generic CPU code.

Signed-off-by: Samuel Holland <samuel@sholland.org>
 2023-02-05 12:05:24 -06:00