random-mirrors/smaeul-u-boot
1
0
Fork 0
mirror of https://github.com/smaeul/u-boot.git synced 2025-09-14 14:06:02 +01:00
Code Issues Packages Projects Releases Wiki Activity
84,361 Commits 30 Branches 324 Tags
Commit Graph

1 Commits

Author SHA1 Message Date
Samuel Holland
0636e3e95b riscv: cpu: thead: Add CPU-specific cache operations 
Use the vendor CSRs for enabling/disabling the caches, and the ISA
extension for cache maintenance.

Signed-off-by: Samuel Holland <samuel@sholland.org>
 2023-02-05 14:15:31 -06:00