A few boards have shown to be required to properly configure pinctrl
for the fixed regulator gpio pin used by sdmmc before being able to read
from SD-cards.
Include the related gpio, regulator and pinctrl nodes and enable related
Kconfig options so that pinctrl can be configured in SPL for boards that
may be affected by such issue.
Also change to imply SPL_DM_SEQ_ALIAS for all boards because it must be
enabled for working gpio usage in SPL after a future DT sync.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
When RK3399 boards run SPL from eMMC and fail to load FIT from eMMC due
to it being missing or checksum validation fails there can be a fallback
to read FIT from SD-card. However, without proper pinctrl configuration
reading FIT from SD-card may fail:
U-Boot SPL 2024.04-rc4 (Mar 17 2024 - 22:54:45 +0000)
Trying to boot from MMC2
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC2
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC1
Card did not respond to voltage select! : -110
mmc_init: -95, time 12
spl: mmc init failed with error: -95
SPL: failed to boot from all boot devices (err=-6)
### ERROR ### Please RESET the board ###
Fix this by tagging related sdhci, sdmmc and spi flash pinctrl nodes
with bootph props. Also move bootph for common nodes shared by all
boards to the SoC u-boot.dtsi.
eMMC, SD-Card and SPI flash nodes are also changed to only be tagged
with bootph props for SPL and U-Boot pre-reloc phases.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Remove superfluous bootph-all props already inherited from main soc
u-boot.dtsi file.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
A lot of RK3399 boards use a u-boot,spl-boot-order of "same-as-spl",
&sdhci and &sdmmc.
Move this to rk3399-u-boot.dtsi and make this default for boards
currently missing a u-boot,spl-boot-order prop.
Before commit a7e69952eb6d ("rockchip: spl: Cache boot source id for
later use") it was required to include the SPI flash node in the
u-boot,spl-boot-order prop to successfully load FIT from SPI flash.
The SPI flash node reference has been dropped from spl-boot-order from
pinebook-pro, roc-pc and rockpro64 now that "same-as-spl" also gets
resolved to the SPI flash node and loading FIT from SPI flash works
without having the node explicitly referenced in spl-boot-order prop.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is
loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only
reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for
TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB
Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows
for a payload of 3168 KB before env offset start to overlap.
Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash
image, u-boot-rockchip-spi.bin.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The i2c locks up when initialized before relocation, and it stays broken
in Linux as well breaking the ability to boot Linux.
The i2c bus and pmic was not actually used in pre-reloc before
commit ad607512f575 ("power: pmic: rk8xx: Support sysreset shutdown method")
The cause is not known.
This is board-specific, other boards that do not add the option to
include the i2c bus in pre-reloc DT are not affected.
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
- uboot rockchip edp code is looking for a rockchip,panel property
for the edp dts node, so add it.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
The rng is embedded in the SoC so enable it in the device tree
universally, the use of it can be controlled by enabling/disabling
at the device config level.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
SPI flash on this machine is located on bus 1, default to using bus 1
for SPI flash and stop aliasing it to bus 0.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob")
Some minor fixes for SPI flash on the Pinebook Pro and also
default to saving environment to the SPI flash as it's
guaranteed to be on board.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(applied with make savedefconfig)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Enable the rng so UEFI can provide entropy for KASLR
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
