Detect RAM size via EEPROM and adjust DDR size and banks accordingly.
Include necessary fixups to handle ECC-enabled configurations.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: Daniel Schultz <d.schultz@phytec.de>
Call 'phytec_ft_board_fixup' in the common K3 board code
to expose the product name and part number to Linux.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
ft_board_setup inside the board code allows to alter
device-tree during the boot process.
Introduce a new function for the PHYTEC SOM detection
to read the product name and part number from the EEPROM
content and include both into the device-tree as
* phytec,som-part-number
* phytec,som-product-name
This function can be called from the board code when those
values should be exposed to Linux.
This patch also updates the phytec_print_som_info
function and changes the output.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
We set the boot source as environment variable 'boot'.
Also include 'uart' and 'usbdfu' as possible boot sources.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
With commit 22ce56a3ebdb ("ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc()
to solve 'calculations restricted to 32 bits' issue") we need to provide the
detected RAM size in the device tree node prio to K3 DDRSS driver probe.
This is done by calling fdt_fixup_memory_banks() in do_board_detect().
After probing, call into k3-ddrss driver to fixup device tree and resize
the available amount of DDR if ECC is enabled.
A third fixup is required from A53 SPL to take the fixup
as done from R5 SPL and apply it to DT passed to A53 U-boot,
which in turn passes this to the OS.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Add instructions on how to build and package OP-TEE for the
phycore-imx8mm based boards. The build instructions are identical for
phyGATE-Tauri-L and phyBOARD-Polis.
Also fix missig '-' for TF-A build instructions.
Signed-off-by: Yannic Moog <y.moog@phytec.de>
Garrett Giordano <ggiordano@phytec.com> says:
This patch set adds the phyCORE AM62Ax board support and documenation to
u-boot.
The phyCORE-AM62Ax is a SoM (System on Module) featuring TI's AM62Ax SoC. It can
be used in combination with different carrier boards. This module can come
with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs
from the AM62x family.
A development Kit, called phyBOARD-Lyra is used as a carrier board reference
design around the AM62x SoM.
This series depends on the following two patches:
- [PATCH v2] arm: mach-k3: am62a7: Provide a way to obtain boot device for non SPL
https://lists.denx.de/pipermail/u-boot/2024-October/570156.html
- [PATCH] board: phytec: common: Introduce CONFIG_PHYTEC_K3_DDR_PATCH
https://lists.denx.de/pipermail/u-boot/2024-November/571543.html
Link: https://lore.kernel.org/r/20241118231606.3161665-1-ggiordano@phytec.com
[trini: Fix warning in board/phytec/common/k3/board.c when
CONFIG_EFI_HAVE_CAPSULE_SUPPORT is not enabled]
Signed-off-by: Tom Rini <trini@konsulko.com>
Wadim Egorov <w.egorov@phytec.de> says:
This implements capsule updates for all our K3 SoMs for
eMMC, OSPI NOR and uSD cards.
We can use capsule updates to update the bootloader on all our
supported flash devices.
Link: https://lore.kernel.org/r/20241127121736.1525948-1-w.egorov@phytec.de
Move the environment into the board directory and convert header to a
txt file. In addition, this patch also applies following changes:
- Change default nfsroot path to /srv/nfs due to compliance with Linux
FHS 3.0.
- Rename specific variables as stated in the bootstd documentation.
Renamed variables:
fdt_addr => fdt_addr_r
fdt_file => fdtfile
Signed-off-by: Yunus Bas <y.bas@phytec.de>
Introduce CONFIG_PHYTEC_K3_DDR_PATCH to make DDR timing patch code
optional for PHYTEC K3 boards. This allows better control over which
boards receive DDR timing patches, rather than compiling the code for
all boards with K3_DDRSS enabled.
Also enable the feature by default for PHYCORE_AM62X_R5.
Signed-off-by: Garrett Giordano <ggiordano@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
The phyCORE-i.MX 93 is available in various variants (e.g. different ram
sizes, eMMC HS400 yes/no). Enable hardware introspection for the
imx93-phyboard-segin_defconfig, so that during startup the SOM module
variant can be detected, and the hardware can be configured accordingly.
The resulting SPL and u-boot binary shall able to boot each
phyCORE-i.MX 93 module variant on each carrier board. Finally rename
imx93-phyboard-segin_defconfig to imx93-phycore_defconfig, to highlight
its SOM scope.
Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Yannic Moog <y.moog@phytec.de>
The phyCORE-i.MX 93 is available in various variants. Relevant variant
options for the spl/u-boot are:
- with or without HS400 support for the eMMC
- with 1GB ram chip, or 2GB ram chip
The phyCORE's eeprom contains all information about the existing variant
options. Add evaluation of the eeprom data to the spl/u-boot to
enable/disable HS400 and to select the appropriate ram configuration at
startup.
Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Yannic Moog <y.moog@phytec.de>
Tested-by: Primoz Fiser <primoz.fiser@norik.com>
The phyCORE-i.MX 93 is available with a 1GB ram chip or a 2GB ram chip.
Add the ram timings for the 2GB chip, in form of a diff compared
to the existing LPDDR4X 1GB timings. With that, the SPL can select the
appropriate timings at startup.
Update also the 1GB ram timings with new version of the DDR Tool.
Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de>
Tested-by: Primoz Fiser <primoz.fiser@norik.com>
Our SoMs are available in multiple configurations, managed via device
tree overlays. To determine the specific variant in use, we read the
EEPROM and apply the appropriate overlays during boot to the device tree
used by the OS.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Neha Malcom Francis <n-francis@ti.com>
Since we use SPEED GRADE fuse to set A55 frequency, remove the
set_arm_core_low_drive_clk function which has hard coded frequency.
And adjust clock_init called sequence and split it to early and late
functions.
Set the authen register in early function, because CCF driver checks
NS bit.
Set bus and core clock in late function, because the fuse read and
SoC type/rev depend on ELE.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Daniel Schultz <d.schultz@phytec.de> says:
This patch stack extends the phyCORE-AM62x/AM64x U-Boot by following boot
sources:
- Load U-Boot with USB DFU
- Load a Linux and initramfs from OSPI/QSPI NOR flash
- Load a Linux and rootfs from Network
Moreover, it adds required changes to the environment to boot an A/B
system with RAUC and includes some minor fixes.
Include the boot logic to boot via Network or from a OSPI/QSPI
NOR flash. Moreover, set all required variables to both boot
methods to the environment.
Note: The phyBOARD-Electra AM64x is not able to load the U-Boot
via Network. However, it's still possible to load the kernel.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Include the boot logic to boot via Network or from a OSPI/QSPI
NOR flash. Moreover, set all required variables to both boot
methods to the environment.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Depending on if a SPI-NOR flash is populated add the mtd partition
table to the device tree. For this we have to also probe the
flash before booting.
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
Added m7 core support in uboot for imx8mp by adding
the boot variable prepare_mcore.
Based on commit 0ed32cc8568a ("LF-6555 imx8m[m/n/p/q]_evk: add
bootargs to support mcore")
Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de>
Use our common environment file to implement MMC boot.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Rename existing environment variables according to the bootstd doc.
Renamed variables are fdto_addr, bootenv_addr, fdt_addr and
fdt_file.
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Include the common overlays env file for phycore_imx93.
The common overlays env file supports disabling loading overlays by
setting the no_overlays variable.
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Add support for loading bootenv.txt as well as loading and applying
overlays during boot from mmc and net.
${no_bootenv}: Prevent loading external bootenv.txt environment. Use
${overlays} variable directly from u-boot environment.
${no_overlay}: Do not load overlays defined in ${overlays} variable.
Overlays loaded over the extension command are still
being applied.
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
By moving the earlycon definition into a dedicated variable, it's
easier to change these values in case the kernel should print on
a different serial interface.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
By moving the earlycon definition into a dedicated variable, it's
easier to change these values in case the kernel should print on
a different serial interface.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Add and use the correct number of ddr phy registers to update the
corresponding settings.
Fixes: cbf5c99ef317 ("board: phytec: common: Introduce a method to inject DDR timings deltas")
Signed-off-by: Dominik Haller <d.haller@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
There is no need to reread the EEPROM multiple times in different stages
to detect the RAM size. We can do this once at an early stage and let
higher stages decode memory nodes using fdtdec.
Make sure to pass fixup memory nodes before passing to u-boot stage.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
Pull in ti/k3_dfu.env for dfu_alt_info_ram in SPL stage.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
Copy fixed-partitions nodes from U-Boot device tree to OS device tree.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
Wadim Egorov <w.egorov@phytec.de> says:
Changes in v2:
- Reabse to current next
- Add Tested-by: John Ma <jma@phytec.com>
- Add Kconfig option to select RAM size statically
- Make board/phytec/common/k3 always compile for CONFIG_ARCH_K3
v1: https://lists.denx.de/pipermail/u-boot/2024-May/553057.html
Use content of EEPROM to detect the actual RAM size and adjust
DDR timings, size and banks accordingly.
Also enable the SoM detection per default in the defconfigs.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: John Ma <jma@phytec.com>
Introduce fdt_apply_ddrss_timings_patch() to allow board code to
override DDR settings in the device tree prior to DDRSS driver probing.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: John Ma <jma@phytec.com>
Functions are declared as phytec_am6* and not phytec_am62*.
Update the definitions to match the declarations.
Fixes: 9d152c23279c ("board: phytec: Add SOM detection for AM6x")
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: John Ma <jma@phytec.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
SoM detection is using I2C driver model functions.
Let's depend on I2C.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: John Ma <jma@phytec.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Daniel Schultz <d.schultz@phytec.de> says:
This patch series adds support for the EEPROM v3 API.
V3 is backwards compatible to V2 and therefore, the V2 image still
exists at the beginning. Only the API version changed from 2 to 3.
V3 is a block-based memory layout organized as singled-linked list
with different types of blocks. This is a more flexible approach and
allows us to extend it by more block types in the future.
The V3 data starts with a 8-byte large header which defines the
block count (u8), V3 subversion (u8) and data payload length (u16).
Additionally the header contains a CRC8 checksum a 3 reserved bytes.
Each block starts with a 4-byte large header which defined the
block type (u8), the absolute address of the next block (u16) and a
CRC8 checksum. The content itself is defined via the block type and
we currently have 2 different types:
1) MAC: Contains the Ethernet interface number (u8), MAC address
(6 x u8) and a CRC8 checksum.
Read the EEPROM API v3 content and set all available
MAC-Addresses to the environment.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
This API is based on a block structure with a 8 Byte large
API v3 header and various of different blocks following. It extends
our current API v2, which is always 32 Byte large, and is located
directly after v2.
Add the MAC block as first block type. It contains the physical
Ehternet interface number, a MAC address and a CRC checksum over the
MAC payload.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Move the entire initialization code for API v2 into a dedicated
function. This rework will allow to easily integrate the API v3
as next step during init.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
The EEPROM image length for API v2 is fixed to 32 bytes. No need
to use sizeof while this value won't change. This value is
also be required for API v3 to know where the API v3 header starts.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
