So far all sunxi boards programming the DCDC1 power rail on the AXP PMIC
also set the DCDC5 rail, so we could handle both with the same DCDC1
guard.
Some boards using the AXP313 will need to set DCDC1 now as well, and
since the AXP313 only has three buck converters, there will be no DCDC5,
so this trick is not going to work anymore.
Don't try to be too clever, and just protect programming the two DCDC
rails with two separate guards.
This has the interesting side effect of fixing operation on A80 boards,
using the AXP809 PMIC. Apparently programming DCDC5 right after DCDC1,
but before the other three rails caused some glitch, which made the board
hang during Linux boot, during the PSCI handler in U-Boot. Just keeping
the old setup order (DCDC1,2,3,4,5) will make those boards boot to the
Linux prompt again.
Fixes: ffb02942fab024d4a9b6a ("sunxi: board: simplify early PMIC setup conditions")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Add defconfig & devicetree for IBM SBP1 board BMC based on AST2600 SoC.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Include k3_rproc.env to access rproc boot commands and specify rproc
firmware names for adding remoteproc support in J722S SoCs.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Add instructions on how to build and package OP-TEE for the
phycore-imx8mm based boards. The build instructions are identical for
phyGATE-Tauri-L and phyBOARD-Polis.
Also fix missig '-' for TF-A build instructions.
Signed-off-by: Yannic Moog <y.moog@phytec.de>
Enable dynamic settings to mmcdev and mmcroot for i.MX8MQ-EVK
Since we are here, clean up the including headers
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add support for K230 CanMV board with serial console and usb otg
support. It can boot via vendor's u-boot-spl and boot into Linux
via tftp through the onboard RTL8152.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
As there are few redundant functions in board/ti/*/evm.c files, pull
them to a common location of access to reuse and include the common file
to access the functions.
Call k3-ddrss driver through fixup_ddr_driver_for_ecc() to fixup the
device tree and resize the available amount of DDR, if ECC is enabled.
Otherwise, fixup the device tree using the regular
fdt_fixup_memory_banks().
Also call dram_init_banksize() after every call to
fixup_ddr_driver_for_ecc() is made so that gd->bd is populated
correctly.
Ensure that fixup_ddr_driver_for_ecc() is agnostic to the number of DDR
controllers present.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
This releases the DP configuration from reset early on during the boot process
for K26 SOM. It will also avoid the boot hang situation should any attempt be
made to configure the DP registers while it is still in reset.
Fixes the same issue as described by the commit 8b81010a2fe3 ("video:
zynqmp: Add support for reset").
Signed-off-by: Neal Frager <neal.frager@amd.com>
Link: https://lore.kernel.org/r/20241218130129.687650-1-neal.frager@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
USB hub initialization is done by driver introduced by commit 09f557e106ef
("usb: onboard-hub: Add i2c initialization for usb5744 hub") that's why
there is no need to do initialization via variables.
Reported-by: Love Kumar <love.kumar@amd.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/96e9c80aeeed4e9664858bf236476997d17a9914.1734522042.git.michal.simek@amd.com
The main reason for this change is that upstream QEMU has no multiboot
register implemented that's why access to it fails which ends up in CI
failure for our target.
That's why in JTAG bootmode returns 0 which is correct behaviour because
multiboot register is not used in this mode and value should be ignored and
as a side effect it is also fixing CI/Qemu issue.
Also move versal_get_bootmode() to avoid function declaration.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/484b9cafc45e72308a1a29a3ab772020f96784cc.1736155238.git.michal.simek@amd.com
Use generic is_cortex_a() functions instead of open-coded midr_el1 read.
No functional change.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
The commit 7cec3e701940 ("rockchip: rk3588-nanopc-t6: Add support for
NanoPC-T6 LTS") added support for the LTS variant of NanoPC T6. However,
a board specific -u-boot.dtsi file was never added.
Due to the missing -u-boot.dtsi file the LTS fdt included in the FIT is
never tagged with bootph props.
When ENV_IS_IN_SPI_FLASH is enabled, not enabled in defconfig, the env
can successfully load from SPI flash on the non-LTS variant, something
that does not work on the LTS variant due to missing bootph-some-ram
props in the LTS fdt.
Fix this by adding a LTS -u-boot.dtsi file that just include the non-LTS
-u-boot.dtsi file.
Reported-by: Ricardo Pardini <ricardo@pardini.net>
Fixes: 7cec3e701940 ("rockchip: rk3588-nanopc-t6: Add support for NanoPC-T6 LTS")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Radxa ROCK 5C[1] is a Rockchip RK3588S2 based single board computer.
[1] https://radxa.com/products/rock5/5c
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
Ethernet ports designed and developed by FriendlyElec for IoT
applications.
Specification:
- Rockchip RK3566
- 2GB LPDDR4X RAM
- optional 32GB eMMC module
- SD card slot
- 2x 1000 Base-T
- 3x LEDs (POWER, LAN, WAN)
- 2x Buttons (Reset, MaskROM)
- 1x USB 3.0 Port
- Type-C 5V 2A Power
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The device tree for Firefly-RK3288 in dts/upstream can be used as-is by
U-Boot, migrate board to use OF_UPSTREAM.
Add chosen stdout-path prop to board u-boot.dtsi as it is missing in DT
from dts/upstream. Also change to use the upstream power_led symbol.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The firefly-rk3288_defconfig build target does not enable the SPL_LED
Kconfig option.
Drop the unused SPL_LED related code and replace it with a default-state
prop to ensure the LED driver enable the LED at U-Boot proper phase.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Khadas Edge2 is a Rockchip RK3588S based SBC (Single Board Computer)
by Khadas.
There are tree variants depending on the DRAM size : 8G and 16G.
Specification:
Rockchip RK3588S SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
8/16GB memory LPDDR4x
Mali G610MP4 GPU
3x MIPI CSI 4x lanes
2x MIPI-DSI DPHY 4x lanes
32/64GB eMMC
1x USB 2.0, 1x USB 3.0, 2x USB-Type-C
1x HDMI 2.1 output, 1x DP 1.4 output
USB PD over USB Type-C
Kernel commit:
04d552993522 ("arm64: dts: rockchip: Add Khadas edge2 board")
Signed-off-by: Jacobe Zang <jacobe.zang@wesion.com>
The device tree for mqmaker MiQi in dts/upstream can be used as-is by
U-Boot, migrate board to OF_UPSTREAM.
The change to use DT from dts/upstream will include minor changes and
fixes related to work led and usb otg.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The device tree for ASUS Tinker Board and S variant in dts/upstream can
be used as-is by U-Boot, migrate board to OF_UPSTREAM.
The change to use DT from dts/upstream will include minor changes and
fixes related to leds and regulators.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable MISC_INIT_R and ROCKCHIP_EFUSE to read cpuid from efuse and set
the cpuid# and serial# env vars.
Change to read mac address from eeprom in rockchip_early_misc_init_r()
to ensure the ethaddr env var is set before rockchip_setup_macaddr() try
to set ethaddr based on cpuid.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add myself as a reviewer for Tinker Board and S variant so that I can
help with review and testing of defconfig and device tree changes.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for building U-Boot SPL for Renesas R-Car Gen4 R8A779G0 V4H SoC.
The SPL initializes the DBSC5 DRAM controller, RT-VRAM and loads and starts
U-Boot proper on the Cortex-A76 core.
The SoC BootROM can not boot the CA76 core directly, instead the SPL starts
on the CR52 core which immediately brings up the CA76 core, which in turn
starts executing the actual SPL. This is achieved by placing a tiny bit of
precompiled Aarch32 code at the very beginning of the SPL. The code consists
of some 32 instructions, uses APMU to configure CA76 start address to offset
0x80 Bytes from start of the SPL, and uses APMU to start the CA76 core. The
code parts the CR52 core in an endless loop once the CA76 core got started.
The 32 instructions are completely arbitrary number, so is the offset 0x80
Bytes from start of SPL, because 0x80 = 128 decimal and 128 / 4 bytes per
instruction is 32 instructions. The 32 instructions turned out to be enough
to started the CA76 and 0x80 is nicely aligned.
Once the SPL completes hardware initialization, the SPL loads U-Boot proper.
The u-boot.itb proper fitImage contains 64bit build on u-boot-nodtb.bin and
a DT for R8A779G0 V4H White Hawk board and is generated by binman. The
u-boot.itb is loaded from SPI NOR offset 0x80000.
In order to install this setup on an existing R8A779G0 V4H White Hawk board,
build using r8a779g0_whitehawk_defconfig, generate SPI NOR image flash.bin
and write flash.bin to SPI NOR offset 0x0 . Finally, configure board MD pin
switches according to the R8A779G0 V4H White Hawk board documentation for
40 MHz SPI NOR boot using DMA and restart the board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
In case U-Boot runs in EL3, which is the highest privilege level on ARM64,
there can be no firmware running that would restrict access to the bottom
128 MiB of DRAM. In fact, it is likely that U-Boot would have to load that
firmware into those bottom 128 MiB of DRAM and start that firmware.
Make those bottom 128 MiB of DRAM available in case U-Boot runs in EL3 to
allow loading the firmware to that area.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Split common board code for R-Car Gen3 and Gen4 into separate files.
The R-Car Gen3 board code contains fixups specific to TFA which are
no longer required on R-Car Gen4, keep those fixups in its own file
so they would not interfere with Gen4.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
All R-Car Gen4 board files are copies of one another at this point.
Deduplicate them into single board/renesas/rcar-common/gen4-common.c
and remove all the duplicates. The one exception is R-Car V3U Falcon
board, which enables RWDT reset in board_init(), conditionally build
RWDT enablement in board_init() in the new common code for V3U.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
