96315 Commits

Author SHA1 Message Date
Vasileios Amoiridis
159dfef261 drivers: bootcount: Add ZynqMP specific bootcount support
Add native support of the bootcount mechanism in the ZynqMP by
utilising internal PMU registers. The Persistent Global Storage
Registers of the Platform Management Unit can keep their value
during reboot cycles unless there is a POR reset, making them
appropriate for the bootcount mechanism.

Signed-off-by: Vasileios Amoiridis <vasileios.amoiridis@cern.ch>
Reviewed-by: Heiko Schocher <hs@denx.de>
Link: https://lore.kernel.org/r/20241105132744.1572759-2-vassilisamir@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-11-15 14:32:47 +01:00
Peter Korsgaard
4bd7222c6b boot/image-board.c: boot_get_fpga(): pass compatible flag to fpga_load()
For E.G. signed FPGA bitstreams, similar to how it is done for the FPGA
loading from SPL since commit 71f1a5392aad ("spl: fit: pass real compatible
flags to fpga_load()").

Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Link: https://lore.kernel.org/r/20241105162136.839633-1-peter@korsgaard.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-11-15 14:32:47 +01:00
Michal Simek
064c8978b4 arm64: versal: Enable capsule update (SD)
Enable capsule update in SD boot mode. For getting it work there is a need
to generate or setup dfu_alt_info and enable sysreset with DFU_MMC.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/cede513de764b99560dc3737457dbc8a5cc71d21.1729857366.git.michal.simek@amd.com
2024-11-15 14:32:47 +01:00
Michal Simek
cf3aa7b52c arm64: versal: Do not define do_reset() if sysreset is enabled
If sysreset is enabled reset_cpu is defined in sysreset uclass that's why
it can't be in platform/board code.
The same change was done by commit f1bc214b0024 ("arm64: zynqmp: Do not
define do_reset() if sysreset is enabled").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8c1a5d6148c5e6c46790b725e8148a4e12d393ba.1729857366.git.michal.simek@amd.com
2024-11-15 14:32:47 +01:00
Padmarao Begari
b872583df1 arm64: zynqmp: Fix r5 mode for cpu release command
The cpu release command for r5 mode (lockstep/split) argument
accepts only string. But the zynqmp tcminit command accepts
string or number for r5 mode (lockstep/split or 0/1) argument.
To fix the r5 mode argument, the common argument (lockstep/split
or 0/1) is used across different u-boot commands. Use the strcmp()
instead of strncmp() to make uniform the r5 mode (lockstep/split
or 0/1) for the zynqmp tcminit and cpu release command.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20241104122750.96251-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-11-15 14:32:47 +01:00
Michal Simek
6f7ff73fba arm64: xilinx: Rename SPI_ADVANCE to SPI_STACKED_PARALLEL
Align defconfigs with the latest Kconfig layout.

Fixes: f896aa656774 ("mtd: spi-nor: Rename SPI_ADVANCE to SPI_STACKED_PARALLEL")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fe05a0e542d6117c10956e4a104123e46f956793.1730450241.git.michal.simek@amd.com
2024-11-15 14:32:47 +01:00
Sughosh Ganu
62fbddf7c8 xilinx: use get_mem_top() to compute ram_top
Use the get_mem_top function to compute the value of ram_top. This was
earlier done through LMB API's, which are no longer available till
after relocation. Use get_mem_top() instead to compute the ram_top
value.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20241025172724.195093-3-sughosh.ganu@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-11-15 14:32:47 +01:00
Sughosh Ganu
feb423a3a3 common: memtop: add logic to detect ram_top
Add generic logic to determine the ram_top value for boards. Earlier,
this was achieved in an indirect manner through a set of LMB API's.
That has since changed so that the LMB code is available only after
relocation. Replace those LMB calls with a single call to
get_mem_top() to determine the value of ram_top.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20241025172724.195093-2-sughosh.ganu@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-11-15 14:32:02 +01:00
Saeed Nowshadi
7aeed221db arm64: zynqmp: Fix pwm-fan polarity
In previous version of pwm driver, the polarity of pwm were implemented
in reverse.  In recent release, that issue in the driver is fixed,
therefore, correctly set the polarity in the device tree.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3e8e38b77101335f86bca0f05b3988877bb12993.1729766551.git.michal.simek@amd.com
2024-11-12 09:01:46 +01:00
Michal Simek
4de127a44a arm64: zynqmp: Configure SoC RTC on SOM
Use RTC available in HW on Kria SOM without using emulation that's why
configure it properly and disable emulated one.
Power on reset value of RTC Calibration register without battery backup is
not matching with crystal frequency which leads to RTC time drift. That's
why write CALIB_WRITE register with crystal frequency (0x7FFF). There is
also an option to write zero so that Linux will set default value (0x7FFF)
in driver probe but calibration 0 is not permited by DT schema.

Co-developed-by: Srinivas Goud <srinivas.goud@amd.com>
Signed-off-by: Srinivas Goud <srinivas.goud@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9b684faeec85381b9b8fe796aaebc2ee79f17b8e.1729663761.git.michal.simek@amd.com
2024-11-12 09:01:46 +01:00
Tom Rini
cca05617a8 Prepare v2025.01-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-11-11 10:07:36 -06:00
Tom Rini
48fd7e9699 Merge patch series "Fix IOVA allocation in Apple dart iommu after global LMB mem map changes"
Janne Grunau <j@jannau.net> says:

The changes in "Make LMB memory map global and persistent" [1] break
mapping DMA memory in the USB xHCI driver when using the apple_dart
iommu present on Apple silicon systems.

The IOVA space used by the u-boot driver (low 4GB) and physical memory
do not overlap. The physical memory on this systems starts depending on
the SoC either at 0x10_0000_0000 or 0x100_0000_0000. It make no sense to
manage these distinct regions in a single LMB map. In addition every
device has its own iommu and IO address space so sharing a single memory
map between all iommu instances is not necessary.

To fix this issue restore the used subset (add, alloc and free) of the
previous pointer based LMB interface with "io_" as prefix.

To ensure that low level lmb functions do not use the global LMB
variable reorder lib/lmb.c so that the variable is not visible.

Tested with patches from my "Fix device removal order for Apple dart
iommu" series [2] to fix a separate issue.

The cosmetic commit has two checkpatch warnings in existing code which I
ignored.

[1] https://lore.kernel.org/u-boot/20240826115940.3233167-1-sughosh.ganu@linaro.org/
[2] https://lore.kernel.org/u-boot/20241031-iommu_apple_dart_ordering-v1-0-8a6877946d6b@jannau.net/

Link: https://lore.kernel.org/r/20241111-io_lmb_apple_dart_iommu-v3-0-32c05da51d72@jannau.net
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-11-11 09:11:55 -06:00
Janne Grunau
f642f34434 iommu: apple: Manage IOVA separately from global LMB mem map
There is no overlap between the IOVA space managed by the iommu (here
the 32-bit address space) and physical RAM on Apple silicon systems. The
RAM starts at 0x10_0000_0000 or 0x100_0000_0000 so it's not possible to
manage the IOVA with the global memory LMB and use 1:1 translation.
In addition each device has its own iommu and does not need to share the
address space with all other devices. This should not be problem for
u-boot's limited use and hardware support.
Restore the private per instance LMB IOVA map.

Fixes: ed17a33fed2 ("lmb: make LMB memory map persistent and global")
Signed-off-by: Janne Grunau <j@jannau.net>
2024-11-11 07:26:44 -06:00
Janne Grunau
f6999cb554 lmb: Add basic io_lmb functionality
These functions can be used with struct lmb pointers and will be used to
manage IOVA space in the apple_dart iommu driver. This restores part of
the pointer base struct lmb API from before commit ed17a33fed29 ("lmb:
make LMB memory map persistent and global").
io_lmb_add() and io_lmb_free() can trivially reuse exisiting lmb
functions. io_lmb_setup() is separate for unique error log messages.
io_lmb_alloc() is a simplified copy of _lmb_alloc_base() since the
later has unused features and internal use of the global LMB memory map.

Signed-off-by: Janne Grunau <j@jannau.net>
2024-11-11 07:26:44 -06:00
Janne Grunau
174f53d2f2 lmb: cosmetic: reorder functions and global LMB variable
Low lovel LMB functionality will be used to manage IOVA space in the
Apple dart iommu driver. This reordering ensures that those function
can not access the global LMB memory map variable.

Signed-off-by: Janne Grunau <j@jannau.net>
2024-11-11 07:26:44 -06:00
Janne Grunau
408b4ae8e3 lmb: Do not use global LMB variable in _lmb_free()
It will be re-used with a lmb list pointer as argument for IOVA
allocations in the apple_dart iommu driver.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Janne Grunau <j@jannau.net>
2024-11-11 07:26:44 -06:00
Tom Rini
fdcf06d58d Merge tag 'u-boot-rockchip-20241111' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/23280

- Add board:
        rk3328: FriendlyElec NanoPi R2S Plus
        rk3568: Qnap TS433
        rk3588: Cool Pi CM5 GenBook
- Move rk3399_force_power_on_reset to TPL for puma board;
2024-11-11 07:25:25 -06:00
Quentin Schulz
0a17123ded rockchip: rk3399: move sysreset-gpio logic to TPL
If TPL_GPIO and TPL_PINCTRL_ROCKCHIP are enabled and a sysreset-gpio is
provided in the TPL Device Tree, this will trigger a system reset
similar to what's currently been done in SPL whenever the RK3399 "warm"
boots. Because there's currently only one user of sysreset-gpio logic,
and TPL is enabled on that board, so let's migrate the logic and that
board to do it in TPL.

There are three reasons for moving this earlier:
- faster boot time as we don't need to reach SPL to be able to reset the
  system on a condition we know is already met in TPL,
- have less code to be impacted by the issue this system reset works
  around (that is, "unclean" SoC registers after a reboot),
- less confusion around the reason for restarting. Indeed when done from
  SPL, the following log can be observed:

"""
U-Boot TPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45)
Channel 0: DDR3, 666MHz
BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
Channel 1: DDR3, 666MHz
BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
256B stride
Trying to boot from BOOTROM
Returning to boot ROM...

U-Boot SPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45 +0100)
Trying to boot from MMC2

U-Boot TPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45)
"""

possibly hinting at an issue within the SPL when loading the fitImage
from MMC2 instead of the normal course of events (a system reset).

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Paul Kocialkowski <paulk@sys-base.io>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-11-11 15:14:15 +08:00
Quentin Schulz
7461d55ca7 rockchip: tpl: allow to call board/SoC-specific code before DRAM init
This defines a weak tpl_board_init function that can be used for running
board/SoC-specific code before the DRAM init happens, similarly to
spl_board_init() for SPL.

Reviewed-by: Paul Kocialkowski <paulk@sys-base.io>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-11-11 15:14:15 +08:00
Quentin Schulz
b21fd44c84 rockchip: rk3399: merge CRU check within rk3399_force_power_on_reset
To prepare to support forcing power on reset from TPL which would have
the exact same logic, just in an earlier stage, let's merge the CRU
check that triggers the power on reset with the rest of the logic.

Reviewed-by: Paul Kocialkowski <paulk@sys-base.io>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-11-11 15:14:14 +08:00
Quentin Schulz
5bc65f5cab pinctrl: rockchip: allow to build for TPL
A later commit will make use of the pinctrl driver in TPL so let's add
the ability to build the Rockchip pinctrl driver in TPL.

Reviewed-by: Paul Kocialkowski <paulk@sys-base.io>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-11-11 15:14:14 +08:00
Jonas Karlman
0bf38a8aa2 rockchip: rk35xx-generic: Disable late boardinfo
Disable DISPLAY_BOARDINFO_LATE as the early boardinfo print of Model
should be enough.

  U-Boot 2025.01-rc1 (Nov 02 2024 - 16:04:16 +0000)

  Model: Generic RK3566/RK3568
  DRAM:  8 GiB (effective 7.7 GiB)
  Core:  250 devices, 24 uclasses, devicetree: separate
  MMC:   mmc@fe2b0000: 1, mmc@fe310000: 0
  Loading Environment from nowhere... OK
  In:    serial@fe660000
  Out:   serial@fe660000
  Err:   serial@fe660000
  Model: Generic RK3566/RK3568
  Hit any key to stop autoboot:  0
  =>

Enable CMD_MISC to make it easier to inspect data in OTP.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-11-11 15:14:14 +08:00
Jonas Karlman
3133b7c645 board: rockchip: Add FriendlyElec NanoPi R2S Plus
The FriendlyElec NanoPi R2S Plus is a single-board computer based on
Rockchip RK3328 SoC. It features e.g. 1 GB DDR4 RAM, 32 GB eMMC,
SD-card, 2x GbE LAN, optional M.2 SDIO Wi-Fi and 2x USB 2.0 host.

Features tested on a NanoPi R2S Plus 2309:
- SD-card boot
- eMMC boot
- Ethernet
- USB gadget
- USB host

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-11-11 15:14:14 +08:00
Sergey Bostandzhyan
d6a55cc9e7 arm64: dts: rockchip: Add DTS for FriendlyARM NanoPi R2S Plus
The R2S Plus is basically an R2S with additional eMMC.

The eMMC configuration for the DTS has been extracted and copied from
rk3328-nanopi-r2.dts, v2017.09 branch from the friendlyarm/uboot-rockchip
repository.

Signed-off-by: Sergey Bostandzhyan <jin@mediatomb.cc>
Link: https://lore.kernel.org/r/20240814170048.23816-2-jin@mediatomb.cc
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: b8c02878292200ebb5b4a8cfc9dbf227327908bd ]

(cherry picked from commit c9bf98827964441f4dd16faa45bd4046f472e693)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-11-11 15:14:14 +08:00
Andy Yan
dfcd4afd4c board: rockchip: Add support for rk3588 GenBook
Add support for Cool Pi GenBook, it works as a carrier board
connect with CM5 SOM.

Specification:
- Rockchip RK3588
- LPDDR5X 8/32 GB
- eMMC 64 GB
- HDMI Type A out x 1
- USB 3.0 Host x 1
- USB-C 3.0 with DisplayPort AltMode
- PCIE M.2 E Key for RTL8852BE Wireless connection
- PCIE M.2 M Key for NVME connection
- eDP panel with 1920x1080

Tested by Armbian boot on USB disk.

Change-Id: I4d9b8572dc7c400077dde666633f3fea1b47dd03
Signed-off-by: Andy Yan <andyshrk@163.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-11-11 15:14:14 +08:00
Andy Yan
3126a63c8d rockchip: Make it possible to define per board boot_targets
Some board may want to have a different boot priority(a laptop
may want to usb has the highest boot priority for third-part
os installation). So let the board can define it's own
boot_targets.

Signed-off-by: Andy Yan <andyshrk@163.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-11-11 15:14:14 +08:00
Andy Yan
82f9074c43 arm64: dts: rockchip: Add support for rk3588 based Cool Pi CM5 GenBook
Cool Pi CM5 GenBook works as a carrier board connect with CM5 [0].

Specification:
- Rockchip RK3588
- LPDDR5X 8/32 GB
- eMMC 64 GB
- HDMI Type A out x 1
- USB 3.0 Host x 1
- USB-C 3.0 with DisplayPort AltMode
- PCIE M.2 E Key for RTL8852BE Wireless connection
- PCIE M.2 M Key for NVME connection
- eDP panel with 1920x1080

This patch add basic support to bringup eMMC/USB HOST/WiFi/TouchPad/
Battery/PCIE NVME, and can also drive a HDMI output with out of tree
hdmi patches.

[0] https://www.crowdsupply.com/shenzhen-tianmao-technology-co-ltd/genbook-rk3588

Signed-off-by: Andy Yan <andyshrk@163.com>
Link: https://lore.kernel.org/r/20240730102433.540260-3-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 4a8c1161b843c366776fc872a6fe45b743b2983e ]

(cherry picked from commit dc6316da23734d9321e09f8c8a7669f4b4cb9f75)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-11-11 15:14:14 +08:00
Heiko Stuebner
d3cacb79e7 board: rockchip: add support for Qnap TS433 devices
The Qnap TS433 is a 4-bay NAS based around the RK3568.

Two SATA bays are connected to the RK3568's own SATA controllers while
the other two are connected to a JMicron SATA controller living on the
PCIe bus.

It provides one 2.5Gb and one 1Gb ethernet port as well as 3 usb ports.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-11-11 15:14:14 +08:00
Tom Rini
446a30d2a0 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh 2024-11-10 20:22:39 -06:00
Marek Vasut
24b28ffc40 mtd: spi-nor: Fix integer overflow in stacked memories support
The 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
adds new SPI bus flags, but also introduces a completely new set of
SPI bus flags in another location. The existing flags field is type
u8, while the new separate flags are BIT(8) and higher. Use of those
new flags triggers integer overflow.

Drop the newly introduced flags which were never used anywhere in the
code. Move the one remaining flag which was used in the correct place
and change it from BIT(8) to BIT(6) so it fits the u8 flags.

Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Addresses-Coverity-ID: 510804 Extra high-order bits
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
2024-11-10 20:21:07 -06:00
Lad Prabhakar
5fb5ed2f78 board: hoperun: Switch to use complete DTS files from upstream DTS
For upstream Linux kernel we use below DTBs for HiHope boards:
- r8a774a1-hihope-rzg2m-ex.dtb
- r8a774e1-hihope-rzg2h-ex.dtb
- r8a774b1-hihope-rzg2n-ex.dtb

Update the CONFIG_OF_LIST to match the above. Now that we have switched
upstream DTS, drop deleting the nodes and also rename the
r8a774*-u-boot.dtsi files to r8a774*-ex-u-boot.dtsi to match the OF_LIST
files so that the `bootph-all` property gets applied to required nodes
in upstream DTS.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
2024-11-10 19:38:46 +01:00
Chris Paterson
34547a44da configs: hihope_rzg2: Set correct MMC device for U-Boot env
Currently we set CONFIG_SYS_MMC_ENV_DEV=1 which is wrong:
  Loading Environment from MMC... MMC: no card present
  *** Warning - No block device, using default environment

This issue was introduced when we switched to using upstream Linux device
trees for the hihope boards which named the MMC devices differently.

Correct to dev 0 so that the U-Boot environment can be loaded from the
correct storage device.

Fixes: 18fb23b13158 ("ARM: dts: renesas: Switch to using upstream DT on 64bit Renesas SoCs")

Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2024-11-10 19:38:46 +01:00
Paul Barker
9d81a9ff99 arm: renesas: Fix RZ/G2L GICR base address
When support for the Renesas RZ/G2L SoC was added, the GICR base address
for CPU1 was accidentally used. We should instead supply the GICR base
address for CPU0 so that interrupts are correctly configured for the
CPU core that U-Boot is actually using.

Fixes: 387d4275ab0e ("arm: rmobile: Add basic RZ/G2L family support")
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-11-10 19:36:54 +01:00
Paul Barker
2badc6529b dt-bindings: Drop unused RZ/G2L devicetree bindings
We are now using the dts/upstream subtree for the RZ/G2L SoC family so
we can drop unused dt-bindings headers.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-11-10 19:36:39 +01:00
Paul Barker
db3b17db5c ARM: dts: Drop unused RZ/G2L devicetrees
We are now using the dts/upstream subtree for the RZ/G2L SoC family so
we can drop unused devicetree files from arch/arm/dts.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-11-10 19:36:38 +01:00
Paul Barker
7edcc241f3 board: rzg2l: Update MAINTAINERS file to match dts/upstream paths
We are now using the dts/upstream subtree for the RZ/G2L SoC family, so
update the board MAINTAINERS file to match rz-smarc dtsi files in this
subtree.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-11-10 19:36:29 +01:00
Tom Rini
9c25cd5631 Merge tag 'u-boot-imx-master-20241105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/23262

- Improve imx9 boot medium autodection.
- Add possibility to skip DCD on i.MX8.
- Switch to using upstream DT on DH i.MX6 DHCOM.
- Add support for i.MX6DL DHCOM SoM on PDK2 carrier board.
- Handle FIELD_RETURN on i.MX HAB.
2024-11-09 11:26:14 -06:00
Tom Rini
f448c4517b Pull request efi-2025-01-rc2-2
Documentation:
 
 * correct title and author of rst2pdf generated pdf
 * describe CONFIG_DEBUG_SBI_CONSOLE
 * remove vile language
 
 UEFI
 
 * correct printf codes in mkeficapsule
 * add an EFI test app
 * move default filename to a function
 * move get_efi_pxe_arch() to efi_helper
 * allow reporting the host defaults in efidebug
 * drop sandbox PXE architecture
 
 Other:
 
 * do not reserve extra 16 KiB of stack in lmb
 * disable the sandbox virtio blk device
 * provide -N command line flag to control EFI default boot file name
   on the sandbox
 * provide a unit test for the efi bootmeth
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEK7wKXt3/btL6/yA+hO4vgnE3U0sFAmcvMKkACgkQhO4vgnE3
 U0ugEA/+O1SZITtLk77A00DPxf00/GXKY0PljKKx9UbEtEId6Bdc2Sm/Sq7lXy9S
 /G5kxqHSmzBLF/VFr0qMXH3eI8KC1wql00XQKkrcfBqXSRVc26xpEPEy9hJGYaG6
 dm5mQczSuaqa9+ZV+JppbHT75zhK6/1iDkNzB4v9dnUxijxjcj20CZyoIQponkoj
 GIMLw17j7ObOWuU+xhXVmcOfXzyp1jGGIQc48qj/3gzy0OWuqFM4zmZr4HKIpfTQ
 p0JBnCAnJpMNZ8JU3AQCh3OmnOff6a1Jfim0jQez9vu6EUTezWwC5MMgq3TBIdXA
 UlS9qKHXUVrov9sQV/SbcdwvBsk41E+lGNnt9aO+lAPfn7OzQFLdIOXMXVyKwPVD
 yU/VgchS0YAKBNiOM/i++SXogdWhElk+ySjT+gSr1YwOcXLBV+gGKvi7XB/uoVXS
 mNN561Ep3YcxZ+6kP81JKYZ9fmuR398XQYU1yjhl0PTRsiF8xK7evmHSvVY2HCg7
 fm/K0RFRTXO1A+4gG3Z4jeK6GJWve44Kh8TSM0m+4TOLK21QFhe70fpRUwz4BGCB
 vTo3LL7Zxh4GSI5zOS5ViIuZg71+z/NDcS7EMBB6AcHlaaDlDSE0ImhSBuv8YpLX
 61FYdwS8Z2eXKCnZNJImXCBp9T7PkyTjB3DH8ECx1LnvfwZQw9o=
 =8H9E
 -----END PGP SIGNATURE-----

Merge tag 'efi-2025-01-rc2-2' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request efi-2025-01-rc2-2

Documentation:

* correct title and author of rst2pdf generated pdf
* describe CONFIG_DEBUG_SBI_CONSOLE
* remove vile language

UEFI

* correct printf codes in mkeficapsule
* add an EFI test app
* move default filename to a function
* move get_efi_pxe_arch() to efi_helper
* allow reporting the host defaults in efidebug
* drop sandbox PXE architecture

Other:

* do not reserve extra 16 KiB of stack in lmb
* disable the sandbox virtio blk device
* provide -N command line flag to control EFI default boot file name
  on the sandbox
* provide a unit test for the efi bootmeth
2024-11-09 08:05:41 -06:00
Ian Ray
28958998f6 arm: mach-imx: imx8m: re-use SNVS init routine
Working with HAB on the i.MX8MP we've encountered a case where a board
that successfully authenticates u-boot when booting Linux subsequently
fails to properly bring up the RTC.

The RTC registers live in the low-power block of the Secure Non-Volatile
Storage (SNVS) block.

The root cause of the error has been traced to the HAB handing off the
SNVS-RTC in a state where HPCOMR::NPSWA_EN = 0 in other words where the
Non-Privileged Software Access Enable bit is zero.

Configure SNVS to allow unpriv access to SNVS LP for imx8m and imx8mp.

This commit generalizes 723f8359c1 ("imx: mx7: snvs: Add an SNVS init
routine") to also be used on i.MX8M SoCs, and was testeed on i.MX8MP.

Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
2024-11-09 08:55:04 -03:00
Ian Ray
d6893740c1 arm: mach-imx: move snvs module
Commit 723f8359c1 ("imx: mx7: snvs: Add an SNVS init routine") noted
that the init_snvs() call likely applies to other i.MX processors, and
this has been found to be true for i.MX8MP.

Move snvs module for future re-use.

Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
2024-11-09 08:55:04 -03:00
Marek Vasut
354e33d06c ARM: dts: imx: Switch to using upstream DT on DH i.MX6 DHCOM
Enable OF_UPSTREAM to use upstream DT and add nxp/imx/ prefix to the
DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/
including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory.

Signed-off-by: Marek Vasut <marex@denx.de>
2024-11-09 08:54:35 -03:00
Marek Vasut
c5c700ca63 ARM: dts: imx6dl: Add support for i.MX6DL DHCOM SoM on PDK2 carrier board
Add support for the DH electronics i.MX6DL DHCOM SoM and a PDK2 evaluation
board. The evaluation board features three serial ports, USB OTG, USB host
with an USB hub, Fast or Gigabit ethernet, eMMC, uSD, SD, analog audio,
PCIe and HDMI video output.

All of the aforementioned features except for mSATA are supported, mSATA
is not available on i.MX6DL and is only available on DHCOM populated with
i.MX6Q SoC which is already supported upstream.

Backport from linux-next commit
c3f5d76a6e03 ("ARM: dts: imx6dl: Add support for i.MX6DL DHCOM SoM on PDK2 carrier board")

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-11-09 08:54:35 -03:00
Heiko Schocher
254c00803b tools: imx8image: add possibility to skip dcd
Currently U-Boot always adds DCD Image to boot container.
On imx8qxp SoC it is possible to init RAM from within SCFW,
and adding a DCD image type to the boot container in this case
breaks booting (No debug output anymore from SCFW! Nor any
output from SPL), so we need to configure a dcd skip somehow.

This patch adds a new imx8image_cmd entry CMD_DCD_SKIP and a
new entry in imximage.cfg "DCD_SKIP". If set to "true"
no DCD image type will be added to the container.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2024-11-09 08:54:19 -03:00
Benjamin Szőke
6bc9d4407c imx9: Improve boot mode autodetection
Improve "mmcautodetect=yes" boot mode autodetection to able to use it
if CONFIG_ENV_IS_NOWHERE=y is used for i.MX9 SoCs and i.MX93 EVK board.

If both CONFIG_ENV_IS_IN_MMC=y and CONFIG_ENV_IS_NOWHERE=y are in the
defconfig, CONFIG_ENV_IS_IN_MMC=y will be overiden default
CONFIG_ENV_IS_NOWHERE settings.

Goal is in this patch to able to use the boot mode autodetection
if defconfig use only CONFIG_ENV_IS_NOWHERE=y option
(without CONFIG_ENV_IS_IN_MMC) for any i.MX9 SoC.

Signed-off-by: Benjamin Szőke <egyszeregy@freemail.hu>
2024-11-09 08:54:01 -03:00
Paul Geurts
0bf7d6b497 imx: hab: Make imx_hab_is_enabled dependent on FIELD_RETURN
The decision on whether HAB is enabled is solely based on the SEC_CONFIG
fuse. The HAB FIELD_RETURN feature is able to permanently disable HAB on
a CPU, after which it is able to boot unsigned firmware. U-Boot however
does not take into account the FIELD_RETURN mode, and refuses to boot
unsigned software when the feature is enabled.

Also take the FIELD_RETURN fuse into account when deciding whether HAB
is enabled. When The FIELD_RETURN fuse is blown, HAB is not enabled.

Tested on i.MX8M Mini, i.MX8M Plus, i.MX8M Nano and i.MX6ULL

Signed-off-by: Paul Geurts <paul.geurts@prodrive-technologies.com>
2024-11-09 08:53:36 -03:00
Paul Geurts
0a245862c2 imx: hab: rename imx_sec_config_fuse_t to imx_fuse
The imx_sec_config_fuse_t structure is not specific to the sec_config
fuse, but can be used for all fuse words.

Rename the structure to a more generic name to be reused for other
fuses.

Signed-off-by: Paul Geurts <paul.geurts@prodrive-technologies.com>
2024-11-09 08:53:36 -03:00
Simon Glass
70b78d5293 test: efi: boot: Add a test for the efi bootmeth
Add a simple test of booting with the EFI bootmeth, which runs the app
and checks that it can call 'exit boot-services' (to check that all the
device-removal code doesn't break anything) and then exit back to
U-Boot.

This uses a disk image containing the testapp, ready for execution by
sandbox when needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-09 10:01:47 +01:00
Simon Glass
79aed64f94 test: efi: boot: Set up an image suitable for EFI testing
Create a new disk for use with tests, which contains the new 'testapp'
EFI app specifically intended for testing the EFI loader.

Attach it to the USB device, since most testing is currently done with
mmc.

Initially this image will be used to test the EFI bootmeth.

Fix a stale comment in prep_mmc_bootdev() while we are here.

For now this uses sudo and a compressed fallback file, like all the
other bootstd tests. Once this series is in, the patch which moves
this to use user-space tools will be cleaned up and re-submitted.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-09 10:01:47 +01:00
Simon Glass
ade8b30039 sandbox: virtio: Disable the sandbox virtio blk device
This is not implemented so cannot actually be used to read blocks.
Disable it until it is implemented, to avoid causing a hang with EFI,
which probes every available BLK device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Issue: https://source.denx.de/u-boot/u-boot/-/issues/37
2024-11-09 10:01:47 +01:00
Simon Glass
16b5423eb3 efi_loader: Drop sandbox PXE architecture
Rather than returning 0, just return an error, since sandbox is not used
with PXE at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-09 10:01:47 +01:00