A few boards have shown to be required to properly configure pinctrl
for the fixed regulator gpio pin used by sdmmc before being able to read
from SD-cards.
Include the related gpio, regulator and pinctrl nodes and enable related
Kconfig options so that pinctrl can be configured in SPL for boards that
may be affected by such issue.
Also change to imply SPL_DM_SEQ_ALIAS for all boards because it must be
enabled for working gpio usage in SPL after a future DT sync.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
When RK3399 boards run SPL from eMMC and fail to load FIT from eMMC due
to it being missing or checksum validation fails there can be a fallback
to read FIT from SD-card. However, without proper pinctrl configuration
reading FIT from SD-card may fail:
U-Boot SPL 2024.04-rc4 (Mar 17 2024 - 22:54:45 +0000)
Trying to boot from MMC2
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC2
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC1
Card did not respond to voltage select! : -110
mmc_init: -95, time 12
spl: mmc init failed with error: -95
SPL: failed to boot from all boot devices (err=-6)
### ERROR ### Please RESET the board ###
Fix this by tagging related sdhci, sdmmc and spi flash pinctrl nodes
with bootph props. Also move bootph for common nodes shared by all
boards to the SoC u-boot.dtsi.
eMMC, SD-Card and SPI flash nodes are also changed to only be tagged
with bootph props for SPL and U-Boot pre-reloc phases.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The initial serial console UART iomux is typically configured in
board_debug_uart_init() at TPL stage on Rockchip platform.
Later stages typically use pinctrl driver to configure iomux UART once
again based on the control FDT.
Include uart related pinctrl nodes in TPL/SPL control FDT to make it
possible for pinctrl driver to configure UART iomux at TPL/SPL stage.
Following debug log message may also be seen at U-Boot pre-reloc stage:
ns16550_serial serial@ff1a0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
This can be resolved by including bootph prop for U-Bood pre-reloc
phase (bootph-some-ram or bootph-all). However, this has intentionally
been excluded due to including it unnecessarily slows down boot around
200-400 ms.
Also add the clock-frequency prop similar to what has been done for
other Rockchip SoCs.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rk3399-puma is the only supported board that use uart0 for serial
console, other RK3399 boards typically use uart2 for serial console
and may use uart0 for bluetooth.
Move setting bootph prop to board u-boot.dtsi to only include the uart0
node in TPL/SPL control FDT for the rk3399-puma target.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The vop nodes should not be included in TPL/SPL control FDT, it should
only be included at U-Boot proper pre-reloc phase.
Change to use bootph-some-ram prop to fix this.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sort nodes alphabetically by name, symbol or reg addr in RK3399 related
u-boot.dtsi files. Also remove one of the duplicated &pmu nodes.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Remove superfluous bootph-all props already inherited from main soc
u-boot.dtsi file.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
A lot of RK3399 boards use a u-boot,spl-boot-order of "same-as-spl",
&sdhci and &sdmmc.
Move this to rk3399-u-boot.dtsi and make this default for boards
currently missing a u-boot,spl-boot-order prop.
Before commit a7e69952eb6d ("rockchip: spl: Cache boot source id for
later use") it was required to include the SPI flash node in the
u-boot,spl-boot-order prop to successfully load FIT from SPI flash.
The SPI flash node reference has been dropped from spl-boot-order from
pinebook-pro, roc-pc and rockpro64 now that "same-as-spl" also gets
resolved to the SPI flash node and loading FIT from SPI flash works
without having the node explicitly referenced in spl-boot-order prop.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The TPL and/or SPL control FDT on RK3399 boards does not contain any
node with a compatible that is supported by driver/misc/ drivers.
Remove use of xPL_MISC_DRIVERS options to stop including e.g an unused
efuse driver in TPL and/or SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Imply OF_LIBFDT_OVERLAY Kconfig options to add device tree overlay
support on all RK3399 boards.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Imply support for GbE PHY status parsing and configuration when support
for onboard ethernet is enabled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
The RK3399 SoC contain a crypto engine block that can generate random
numbers.
Imply DM_RNG and RNG_ROCKCHIP Kconfig options to take advantage of the
random generator on all RK3399 boards. Also remove the unnecessary use
of a status = "okay" prop.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
The RK3399 SoC support the ARMv8 Cryptography Extensions, use of ARMv8
crypto can speed up FIT checksum validation in SPL.
Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto
extensions for SHA256 when validating checksum of FIT images.
Imply SPL_FIT_SIGNATURE and LEGACY_IMAGE_FORMAT to enable FIT checksum
validation to almost all RK3399 boards.
The following boards have been excluded:
- chromebook_bob: SPL max size limitation of 120 KiB
- chromebook_kevin: SPL max size limitation of 120 KiB
Also imply OF_LIVE to help speed up init of U-Boot proper and disable
CONFIG_SPL_RAW_IMAGE_SUPPORT on leez-rk3399 to ensure SPL does not try
to jump to code that failed checksum validation.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Remove <common.h> from this board vendor directory and when needed
add missing include files directly.
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
This follows the example of RISC-V where <asm/global_data.h> includes
<asm/u-boot.h> directly as "gd" includes a reference to bd_info already
and so the first must include the second anyhow. We then remove
<asm/u-boot.h> from all of the places which include references to "gd"
an so have <asm/global_data.h> already.
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from the remainder of the files under arch/arm and
when needed add missing include files directly.
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from all fsl-layerscape related files and when needed
add missing include files directly.
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from all mach-aspeed files and when needed add missing
include files directly.
Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from all mach-bcmbca, mach-bcm283x and bcm* CPU
directory files and when needed add missing include files directly.
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from all mach-imx, CPU specific sub-directories and
include/asm/arch-mx* files and when needed add missing include files
directly.
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from all mach-meson files and when needed add missing
include files directly.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from all mach-rockchip and include/asm/arch-rockchip
files and when needed add missing include files directly.
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from all mach-s5pc1xx and cpu/armv7/s5p-common files
and when needed add missing include files directly.
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from all mach-sunxi and board/sunxi files and when
needed add missing include files directly.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from all mach-stm32 and mach-stm32mp files and when
needed add missing include files directly.
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from all mach-tegra and include/asm/arch-tegra files
and when needed add missing include files directly.
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from all mach-u8500 files and when needed add missing
include files directly.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove <common.h> from all mach-versal-net, mach-versal, mach-zynq and
mach-zynqmp files and when needed add missing include files directly.
Signed-off-by: Tom Rini <trini@konsulko.com>
The phycore-rk3288 can be migrated to OF_UPSTREAM.
Drop redundant device tree files, update MAINTAINERS and
defconfig's DEFAULT_DEVICE_TREE for rockchip vendor prefix accordingly.
Move device tree nodes required for u-boot to rk3288-phycore-rdk-u-boot.dtsi
such as chosen, i2c_eeprom_id and it's alias.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
