Maintain backward compatibility with pre-binman u-boot file naming,
the U-Boot fitImage used to be named u-boot.itb before, restore the
file name after binman conversion.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Jerome Forissier <jerome.forissier@linaro.org> says:
Miscellaneous fixes made when developing the lwIP series [1]. They are
posted separately since they make sense on their own. Subsequent
versions of the lwIP series will contain a squashed version of this one.
[1] http://patchwork.ozlabs.org/project/uboot/list/?series=420712&state=%2A&archive=both
emac.c implements cpu_eth_init() so it needs to pull the corresponding
header file.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
The AT91-based platforms have a mem_init() function declared in
arch/arm/mach-at91/include/mach/at91_common.h and implemented in various
places. In preparation of the introduction of the lwIP networking library
which also has a global mem_init() function, rename the AT91 one to
at91_mem_init().
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Hari Prasath Gujulan Elango <hari.prasathge@microchip.com>
beagleboneai64 boot was broken after OF_UPSTREAM support for
J721E SOC.
So add bootph in chipid node similar to other boards of
this SOC.
Fixes: 46bb1405b461 ("arm: dts: k3-j721e: Move to OF_UPSTREAM")
Reported-by: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
fixed-clock can't be described on the bus because it is missing reg
property. Also remove additional compatible string for flash. Mini qspi
configuration is used with multiple different flashes that's why describing
only one is not correct but also not required based on DT schema.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0e4721eda8d0f23a9d9f0c15cf887f0bba639cd4.1726219714.git.michal.simek@amd.com
amba is not approved node name for simple-bus that's why use axi instead to
be aligned with other xilinx boards. Node reference is not changed that's
why there is no impact but also mini configuration will never gets to OS
that's why nothing should be affected from OS perspective (paths in /proc/
for example).
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1b18a69ae47bdcb1a0795af7621d13bfecfc9861.1726219714.git.michal.simek@amd.com
Generic understanding/consideration is that phy-mode as sgmi means that the
internal PCS(Physical Coding Sublayer) should be enabled by default.
Xilinx GEM implementation allows configuration GEM (gmii mode) + PL PCS PMA
(sgmii mode, Physical Medum Attachment) but in this case phy-mode should be
setup as gmii.
The reason for this assumption is that phy-mode should be described based
on GEM configuration not based on mode coming out of PHY.
Also Linux kernel automatically setting up PCSSEL bit when phy mode is
sgmii without a need to specified additional DT propety.
All our DTSes with sgmii phy mode have this flag enabled that's why there
is no need/reason to just duplicate information.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2ecdbcc4ce692e2f8b3e7054a2abab35f6c03a69.1726213052.git.michal.simek@amd.com
Remove device tree overlay (DTBO) entries for the ZynqMP target
from the Makefile. Add new device tree binaries (DTBs) for the
zynqmp-sm-k24-revA and zynqmp-smk-k24-revA configurations.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240906070808.1045991-3-prasad.kummari@amd.com
Linux commits:
15d16d6dadf6 kbuild: Add generic rule to apply fdtoverlay
44f87191d105 kbuild: parameterize the .o part of suffix-search
The Linux commit 15d16d6dadf6 adds a generic rule in Makefile.lib
to automatically apply fdtoverlay, so that each platform doesn't
need to include a complex rule. This also automatically appends
DTC_FLAGS_foo_base += -@ to all base files
The platform's Makefile only needs to have this now:
foo-dtbs := foo_base.dtb foo_overlay1.dtbo foo_overlay2.dtbo
dtb-y := foo.dtb
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240906070808.1045991-2-prasad.kummari@amd.com
Set NIDEN, enabling non-invasive debug for the CCI-400 PMU. Otherwise,
the PMU is effectively disabled.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240905171833.325548-3-sean.anderson@linux.dev
Signed-off-by: Michal Simek <michal.simek@amd.com>
To boot into the firmware recovery tool, the user currently
needs to press a button on the board while powering the
system up. To simplify this process, a U-Boot command
was added to allow booting directly into the recovery tool.
For example:
ZynqMP> zynqmp reboot <multiboot offset in hex>
Co-develop-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Co-develop-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240827115529.2931334-1-prasad.kummari@amd.com
Add support for the Comvetia i.MX6Q LXR2 board, which is
uses the Phytec PFLA02 SoM.
Based on the original work from Stefano Babic <sbabic@denx.de>.
The Phytec PFLA02 devicetrees are taken from kernel 6.11-rc7.
The imx6q-lxr.dts has been submitted upstream:
https://lore.kernel.org/linux-devicetree/20240913200906.1753458-3-festevam@gmail.com/
After it gets accepted in mainline (most likely in kernel 6.13),
the lxr2 board can then be switched to OF_UPSTREAM and these device trees
can be removed from U-Boot.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Remove unused CONFIG_IMX9_LOW_DRIVE_MODE kconfig and
imx93_11x11_evk_ld_defconfig.
Remove the ld timing file.
The LD mode support will be added back with runtime detection later.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add trdc_mbc_blk_num to get num blks in a MBC mem slot, then drop
the hardcoded value '40' for NIC OCRAM configuration.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8M and i.MX9 have duplicated fixup_thermal_trips, so move it
to arch/arm/mach-imx/fdt.c to avoid duplicated code.
The critial temperature point for i.MX9 set to "maxc - 5" back to give
some margin.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add support for iMX93 low performance parts 9302 and 9301 which
restrict to low drive voltage only.
The parts run A55 max speed at 900Mhz and M33 at 133Mhz, have NPU
and A55 core1 (9301) disabled.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
disable_cpu_nodes could be reused by i.MX9, so move disable_cpu_nodes
out from mach-imx/imx8m/soc.c to mach-imx/fdt.c and update
disable_cpu_nodes to make it easy to support different socs.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8M use PPI for PMU interrupts, there is no reason to update
interrupt-affinity for PMU even interrupt-affinity was wrongly added
to device tree before.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
To support 1.866GTS LPDDR4x timing script, need to add 233Mhz freq
to DDR PLL for second mission point at 933MTS. Otherwise DDR training
will fail.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Normally, the wdog will be used for trigger external PMIC reset
through the WDOG_ANY pin. If the PMIC chip has debounce logic for
the reset signal, in some corner case the wdog can NOT trigger
external PMIC reset if the SoC has been reset internal before the
PMIC captures the WDOG_ANY pin reset, so need to keep the WDOG3-5
reset masked in the SRC to let the PMIC to do the reset safely.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Since we use SPEED GRADE fuse to set A55 frequency, remove the
set_arm_core_low_drive_clk function which has hard coded frequency.
And adjust clock_init called sequence and split it to early and late
functions.
Set the authen register in early function, because CCF driver checks
NS bit.
Set bus and core clock in late function, because the fuse read and
SoC type/rev depend on ELE.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Replace the static CONFIG_IMX9_LOW_DRIVE_MODE with runtime target
voltage mode by checking the part's SPEED GRADE fuse.
SPL will configure to highest A55 speed which is indicated by the SPEED
fuse and select corresponding voltage mode.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The boot image includes Edgelock Enclave(ELE) Firmware. Print the
information out to let user know which version firmware is being used.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The second Ethernet MAC (eQOS) fuse layout is changed since i.MX93 A1
following other i.MX platforms, for example i.MX8MP.
Order for A0:
MAC1_ADDR[15:0]
MAC1_ADDR[31:16]
MAC1_ADDR[47:32]
MAC2_ADDR[47:32]
MAC2_ADDR[15:0]
MAC2_ADDR[31:16]
Order since A1:
MAC1_ADDR[15:0]
MAC1_ADDR[31:16]
MAC1_ADDR[47:32]
MAC2_ADDR[15:0]
MAC2_ADDR[31:16]
MAC2_ADDR[47:32]
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
To support OSCCA enabled part which has disabled FSB access from SOC,
change directly read from FSB to use fuse_read API.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Print UID in big endian format and as one buffer of bytes, so customer
can directly use it for EdgeLock 2GO.
Before:
UID: 0xf6c8ae93 0x0f46b326 0x10d61eb3 0x0583c2d2
Become:
UID: 93aec8f626b3460fb31ed610d2c28305
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
ROM use UID[0] and UID[1] as serial number with big endian when usb serial
download.
After update this, uuu(>1.6) can use below command to filter out devices
when multi boards connected.
uuu -ms <serial#> ...
[sudo] uuu -lsusb can list known devices with serial# informaiton.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
On OSCCA part, M33 TCM is used for ROM PATCH and protected by ELE ROM.
So after release TRDC, we need to configure TRDC for M33 TCM,
otherwise A55 can't access the TCM.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
SSAR handshake done means power on finished, not ISO done. so correct
the waiting mask.
Fixes: 0256577a83b ("imx: imx9: Add MIX power init")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Simon Glass <sjg@chromium.org> says:
This series includes the patches needed to make make the EFI 'boot' test
work. That test has now been split off into a separate series along with
the EFI patches.
This series fixes these problems:
- sandbox memory-mapping conflict with PCI
- the fix for that causes the mbr test to crash as it sets up pointers
instead of addresses for its 'mmc' commands
- the mmc and read commands which cast addresses to pointers
- a tricky bug to do with USB keyboard and stdio
- a few other minor things
An address may be mapped twice and unmapped twice. Delete the mapping
only when the last user unmaps it.
Fix a missing comment while here.
Signed-off-by: Simon Glass <sjg@chromium.org>
So far unmapping has not been implemented. This means that if one test
maps a pointer to an address with map_sysmem(), then a second test can
use that same pointer, by mapping the address back to a pointer with
map_to_sysmem(). This is not really desirable, even if it doesn't
cause any problems at the moment.
Implement unmapping, to clean this up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Sandbox keeps a table of addresses which map to pointers which are
outside its emulated DRAM. The current range from 10000000 conflicts
with the PCI range, meaning that if PCI mapping is on, that particular
address can be decoded by PCI instead of the table.
Fix this by moving the range up to the top of memory. Update the docs
while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
