78115 Commits

Author SHA1 Message Date
Samuel Holland
f92e2302b4 sunxi: Add a U-Boot port for the Lichee RV 86 Panel
Signed-off-by: Samuel Holland <samuel@sholland.org>
d1-2022-03-07
2022-03-07 19:07:10 -06:00
Jisheng Zhang
d717f61e5d sunxi: Add a U-Boot port for the Lichee RV and its dock
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
[Samuel: licheepi -> lichee; drop DRAM size; other changes]
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-28 23:37:51 -06:00
TekkamanV
750ee8f57a riscv64: update nezha_defconfig for development/testing
Signed-off-by: TekkamanV <tekkamanv@163.com>
[Samuel: Kept default prompt, trimmed things to stay under 1 MiB]
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-28 23:31:59 -06:00
TekkamanV
818efd944a sun20i: Add some variables to the default environment
Signed-off-by: TekkamanV <tekkamanv@163.com>
[Samuel: Only kept the non-Fedora-specific subset of changes]
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-28 23:31:59 -06:00
Samuel Holland
89f4e650eb sunxi: Add a U-Boot port for the Allwinner D1 Nezha
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-28 23:31:59 -06:00
Samuel Holland
6e97abfc25 sunxi: Convert some Kconfig defaults to implies
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:50 -06:00
Samuel Holland
cf3d771919 board: riscv: Sort target configs alphabetically
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:50 -06:00
Samuel Holland
48bdb12434 riscv: cpu: Add cache operations for T-HEAD CPUs
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:50 -06:00
Samuel Holland
61f46f2630 usb: musb-new: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:50 -06:00
Samuel Holland
295d64ece8 [BROKEN] spi: sunxi: Add support for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:50 -06:00
Samuel Holland
1d493ece7a spi: sunxi: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
d77264e31c pinctrl: sunxi: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
1ace90300d pinctrl: sunxi: Add support for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
ad156580ad phy: sun4i-usb: Add support for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
4f94eeccd4 phy: sun4i-usb: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Andre Przywara
3451f398ba phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling
As Icenowy pointed out, newer manuals (starting with H6) actually
document the register block at offset 0x800 as "HCI controller and PHY
interface", also describe the bits in our "PMU_UNK1" register.
Let's put proper names to those "unknown" variables and symbols.

While we are at it, generalise the existing code by allowing a bitmap
of bits to clear and set, to cover newer SoCs: The A100 and H616 use a
different bit for the SIDDQ control.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
e685e542b8 net: sun8i-emac: Downgrade printf in probe to debug
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
e5c5868348 net: sun8i_emac: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
c9588b157d mmc: sunxi: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
8548e47d40 gpio: sunxi: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
b6491e8175 clk: sunxi: Add support for D1 CCU
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
dc927ccf10 dt-bindings: leds: Update common binding
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
095688f2ab Merge branch 'patch/axp-gpio' into allwinner
# Conflicts:
#	arch/arm/mach-sunxi/Kconfig
2022-02-26 21:45:51 -06:00
Samuel Holland
e73ddaed44 Merge branch 'patch/axp-vbus' into allwinner
# Conflicts:
#	arch/arm/include/asm/arch-sunxi/gpio.h
2022-02-26 21:45:46 -06:00
Samuel Holland
a95f12e41d Merge branch 'patch/dm-i2c' into allwinner 2022-02-26 21:45:40 -06:00
Samuel Holland
c76c156861 Merge branch 'patch/dm-pinctrl' into allwinner 2022-02-26 21:45:38 -06:00
Samuel Holland
2ff0d92275 Merge branch 'patch/mkimage-toc1' into allwinner 2022-02-26 21:45:33 -06:00
Samuel Holland
77693293e1 Merge branch 'patch/mkimage-toc0' into allwinner 2022-02-26 21:45:31 -06:00
Samuel Holland
3078fe58c3 Merge branch 'patch/mkimage-riscv' into allwinner 2022-02-26 21:45:29 -06:00
Samuel Holland
b4dffc6a4a Merge branch 'patch/h6-dts' into allwinner 2022-02-26 21:45:26 -06:00
Samuel Holland
24e36b8177 Merge branch 'patch/h3-scp' into allwinner 2022-02-26 21:45:25 -06:00
Samuel Holland
0459d5e504 Merge branch 'patch/h3-fit' into allwinner 2022-02-26 21:45:22 -06:00
Samuel Holland
2315fe6cd7 Merge branch 'patch/dt-sync' into allwinner 2022-02-26 21:45:20 -06:00
Samuel Holland
e89dc4991a tools: mkimage: Add Allwinner TOC1 support
TOC1 is an container format used by Allwinner's boot0 that can hold
multiple images. It supports encryption and signatures, but that
functionality is not implemented, only the basic "non-secure" subset.

A config file is used to provide the list of data files to include. Its
path is passed as the argument to "-d". It contains sections of the
following form:

  [name]
  file = /path/to/file
  addr = 0x12345678

Specific well-known names, such as "dtb", "opensbi", and "u-boot", are
used by the bootloader to distinguish the items inside the image.

Cover-letter:
tools: mkimage: Add Allwinner TOC1 support

The SPL port for the Allwinner D1 RISC-V SoC will probably take a while
longer than porting U-Boot proper, as none of the relevant drivers are
set up for DM in SPL. In the meantime, we are using[1][2] a fork[3] of
Allwinner's boot0 loader, which they also call "spl" in their BSP. boot0
uses this TOC1 image format.

The vendor tools for generating TOC1 images require a binary config file
generated by their FEX compiler. Instead of trying to support that, I
made up a simple human-readable config file format. I didn't see any
existing platform-agnostic parser for multi-image containers in mkimage.

I am sending this as RFC because it is only of temporary/limited use.
It only works with one specific fork of boot0 which was modified to
"behave" (the the original vendor version monkey-patches a custom header
inside the U-Boot image during boot). So it will be obsolete once U-Boot
SPL is ported. And it is Yet Another Image Format. On the other hand, it
does work, and it is currently being used.

[1]: https://linux-sunxi.org/Allwinner_Nezha#U-Boot
[2]: https://fedoraproject.org/wiki/Architectures/RISC-V/Allwinner
[3]: https://github.com/smaeul/sun20i_d1_spl
END
Series-prefix: RFC
Series-to: sunxi
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:45:00 -06:00
Samuel Holland
a9a4131130 sunxi: Support building a SPL as a TOC0 image
Now that mkimage can generate TOC0 images, and the SPL can interpret
them, hook up the build infrastructure so the user can choose which
image type to build. Since the absolute load address is stored in the
TOC0 header, that information must be passed to mkimage.

Cover-letter:
sunxi: TOC0 image type support
This series adds support for the TOC0 image format used by the Allwinner
secure boot ROM (SBROM). This series has been tested on the following
SoCs/boards, with the eFuse burnt to enable secure mode:
 - A50: Ainol Q88 Tablet
 - A64: Pine A64 Plus
 - H5: Orange Pi Zero Plus
 - H6: Pine H64 Model B
 - H616: Orange Pi Zero 2

This time I also tested it on boards that are not switched to secure
mode (with A64, H3, and H5).

Due to both series changing Makefile.spl, the last patch depends on:
https://patchwork.ozlabs.org/project/uboot/list/?series=267136

Since this series no longer selects TOOLS_LIBCRYPTO anywhere, building
certain platforms/options may fail with an error like the following if
TOOLS_LIBCRYPTO is disabled:

    MKIMAGE spl/sunxi-spl.bin
  ./tools/mkimage: unsupported type Allwinner TOC0 Boot Image
  make[1]: *** [scripts/Makefile.spl:426: spl/sunxi-spl.bin] Error 1
  make: *** [Makefile:1982: spl/u-boot-spl] Error 2
END

Series-to: sunxi
Series-version: 4
Series-changes: 2
 - Rebase on top of Icenowy's RISC-V support series
 - Rename Kconfig symbols to include the full image type name

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:44:45 -06:00
Samuel Holland
aee968ef3d sunxi: Support SPL in both eGON and TOC0 images
SPL uses the image header to detect the boot device and to find the
offset of the next U-Boot stage. Since this information is stored
differently in the eGON and TOC0 image headers, add code to find the
correct value based on the image type currently in use.

Series-changes: 2
 - Moved SPL header signature checks out of sunxi_image.h
 - Refactored SPL header signature checks to use fewer casts

Series-changes: 3
 - Fixed offset of magic passed to memcmp
 - Refactored functions to not return pointers (fixes ambiguous NULL)

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:44:45 -06:00
Samuel Holland
8e3dfc7f12 spi: sun4i_spi: Remove non-DM pin setup
This is now handled automatically by the pinctrl driver.

Series-version: 2
Cover-letter:
sunxi: Add and use a pinctrl driver
This series resolves some longstanding TODOs by implementing a pinctrl
driver for sunxi platforms and converting DM drivers to use it.
END
Series-to: sunxi
Series-cc: sjg
Series-cc: Sean Anderson <seanga2@gmail.com>
Series-cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
a7644cdf90 pinctrl: sunxi: Add SPI0 pinmuxes
Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
2f45eef7b9 pwm: sunxi: Remove non-DM pin setup
This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
0031d5c2e4 pinctrl: sunxi: Add the A64 PWM pinmux
This is the only possible mux setting for the A64's PWM peripheral.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
8505d11974 sunxi: Remove non-DM MMC pin setup
This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
09e5cbacb4 pinctrl: sunxi: Add MMC pinmuxes
Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
70468f7ebe i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C
When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.

Clean up the code in the process: remove #ifdefs and recognize that the
pin configuration is the same for all sun8i/sun50i SoCs, not just those
which select CONFIG_MACH_SUN8I.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
728c6782d2 i2c: sun6i_p2wi: Only do non-DM pin setup for non-DM I2C
When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
70b6734d81 i2c: sun8i_rsb: Add support for DM clocks and resets
Currently, clock/reset setup for this device is handled by a
platform-specific function and is intermixed with non-DM pinctrl
setup. Use the devicetree to get clocks/resets, which disentagles
it from the pinctrl setup in preparation for moving to DM_PINCTRL.

This also has the added benefit of picking the right clock/reset
bits for H6 and new SoCs that have a rearranged PRCM MMIO space.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:28:46 -06:00
Samuel Holland
f3fddfae64 i2c: sun8i_rsb: Initialize chips in .child_pre_probe
Chips attached to the RSB bus require an initialization command before
they can be used. (Specifically, this command programs the chip's
runtime address.) The driver does this in its .probe_chip hook, under
the assumption that .probe_chip is called during child probe. This is
not the case; .probe_chip is only called by dm_i2c_probe, which is
intended for use by board-level code, not for chips with OF nodes.

Since this initialization command must be run before a child chip can be
used, do it before probing each child.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:28:46 -06:00
Samuel Holland
191fc15ebc i2c: sun6i_p2wi: Add support for DM clocks and resets
Currently, clock/reset setup for this device is handled by a
platform-specific function and is intermixed with non-DM pinctrl
setup. Use the devicetree to get clocks/resets, which disentagles
it from the pinctrl setup in preparation for moving to DM_PINCTRL.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:28:46 -06:00
Samuel Holland
967656994b i2c: sun6i_p2wi: Initialize chips in .child_pre_probe
Chips attached to the P2WI bus require an initialization command before
they can be used. (Specifically, this switches the chip from I2C mode
to P2WI mode.) The driver does this in its .probe_chip hook, under the
assumption that .probe_chip is called during child probe. This is not
the case; .probe_chip is only called by dm_i2c_probe, which is intended
for use by board-level code, not for chips with OF nodes.

Since this initialization command must be run before a child chip can be
used, do it before probing each child.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:26:15 -06:00
Samuel Holland
8db2b02cf8 gpio: axp: Add pull-down support for AXP22x/AXP8xx variant
The AXP221 and newer PMICs support a pull-down function on their GPIOs.
Add support for it.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:06 -06:00
Samuel Holland
ceab9469ee gpio: axp: Add support for getting the pin function
Implement the .get_function operation, so the gpio command can report
the current function. Since the GPIOF_FUNC (versus GPIOF_UNUSED) mux
values vary among the PMICs, report all non-GPIO mux values as UNKNOWN.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:06 -06:00