The clock and reset drivers use the exact same platform data. Simplify
them by sharing the object. This is safe because the parent device
(the clock device) always gets its driver model callbacks run first.
Series-to: sunxi
Series-cc: Lukasz Majewski <lukma@denx.de>
Series-cc: Sean Anderson <seanga2@gmail.com>
Series-version: 2
Cover-letter:
clk: sunxi: Out-of-bounds access fix and driver cleanup
This series fixes an issue with out-of-bounds access to the gate array
(patches 1-2), uses the rearranged array size information to remove a
bunch of duplicate code (patches 3-4), and then simplifies how the reset
driver is bound (patches 5-7).
The original motivation for these changes was adding a driver for the
legacy A31/A23/A33 PRCM binding (which I will send separately), and
trying to use OF_PLATDATA in SPL (which did not work out). But I think
at least some of the cleanup is worth applying on its own.
Patch 4 is generally the same change I made between v1 and v2 of the
pinctrl series, using some #ifdefs to share a U_BOOT_DRIVER. It's not
quite as clean as the pinctrl case, because here the SoC-specific parts
are in different files, so all of the CCU descriptors have to be global.
END
Acked-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
All of the driver private data should really be platform data since it
is determined statically (selected by the compatible string or extracted
from the devicetree). Move everything to platform data, so it can be
provided when binding the driver. This is useful for SPL, or for
instantiating the driver as part of an MFD.
Acked-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Now that all of the variants use the same bind/probe functions and ops,
there is no need to have a separate driver for each variant. Since most
SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit
of firmware size and RAM.
Acked-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
This allows all of the clock drivers to use a common bind function.
Acked-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
The reset array size is currently used for bounds checking in the reset
driver. The same bounds check should really be done in the clock driver.
Currently, the array size is provided to the reset driver separately
from the CCU descriptor, which is a bit strange. Let's do this the usual
way, with the array sizes next to the arrays themselves.
Acked-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Some devices enumerate various clocks in their DT, and many drivers
just blanketly try to enable all of them. This creates problems
since we only model a few gate clocks, and the clock driver outputs
a warning when a clock is not described:
=========
sunxi_set_gate: (CLK#3) unhandled
=========
Some clocks don't have an enable bit, or are already enabled in a
different way, so we might want to just ignore them.
Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define
a GATE_DUMMY macro that can be used in the clock description array.
Define a few clocks, used by some pinctrl devices, that way to suppress
the runtime warnings.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
The CCU header is only used by the DM drivers, not any platform code.
Its current location adds an artificial dependency on CONFIG_ARM and
ARCH_SUNXI, which will be problematic when adding the CCU driver for
a RISC-V sunxi platform.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
