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111 Commits

Author SHA1 Message Date
Samuel Holland
f92e2302b4 sunxi: Add a U-Boot port for the Lichee RV 86 Panel
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-03-07 19:07:10 -06:00
Jisheng Zhang
d717f61e5d sunxi: Add a U-Boot port for the Lichee RV and its dock
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
[Samuel: licheepi -> lichee; drop DRAM size; other changes]
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-28 23:37:51 -06:00
TekkamanV
750ee8f57a riscv64: update nezha_defconfig for development/testing
Signed-off-by: TekkamanV <tekkamanv@163.com>
[Samuel: Kept default prompt, trimmed things to stay under 1 MiB]
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-28 23:31:59 -06:00
TekkamanV
818efd944a sun20i: Add some variables to the default environment
Signed-off-by: TekkamanV <tekkamanv@163.com>
[Samuel: Only kept the non-Fedora-specific subset of changes]
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-28 23:31:59 -06:00
Samuel Holland
89f4e650eb sunxi: Add a U-Boot port for the Allwinner D1 Nezha
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-28 23:31:59 -06:00
Samuel Holland
6e97abfc25 sunxi: Convert some Kconfig defaults to implies
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:50 -06:00
Samuel Holland
cf3d771919 board: riscv: Sort target configs alphabetically
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:50 -06:00
Samuel Holland
48bdb12434 riscv: cpu: Add cache operations for T-HEAD CPUs
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:50 -06:00
Samuel Holland
61f46f2630 usb: musb-new: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:50 -06:00
Samuel Holland
295d64ece8 [BROKEN] spi: sunxi: Add support for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:50 -06:00
Samuel Holland
1d493ece7a spi: sunxi: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
d77264e31c pinctrl: sunxi: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
1ace90300d pinctrl: sunxi: Add support for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
ad156580ad phy: sun4i-usb: Add support for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
4f94eeccd4 phy: sun4i-usb: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Andre Przywara
3451f398ba phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling
As Icenowy pointed out, newer manuals (starting with H6) actually
document the register block at offset 0x800 as "HCI controller and PHY
interface", also describe the bits in our "PMU_UNK1" register.
Let's put proper names to those "unknown" variables and symbols.

While we are at it, generalise the existing code by allowing a bitmap
of bits to clear and set, to cover newer SoCs: The A100 and H616 use a
different bit for the SIDDQ control.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
e685e542b8 net: sun8i-emac: Downgrade printf in probe to debug
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
e5c5868348 net: sun8i_emac: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
c9588b157d mmc: sunxi: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
8548e47d40 gpio: sunxi: Hack up the driver for the D1
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
b6491e8175 clk: sunxi: Add support for D1 CCU
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
dc927ccf10 dt-bindings: leds: Update common binding
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:46:49 -06:00
Samuel Holland
095688f2ab Merge branch 'patch/axp-gpio' into allwinner
# Conflicts:
#	arch/arm/mach-sunxi/Kconfig
2022-02-26 21:45:51 -06:00
Samuel Holland
e73ddaed44 Merge branch 'patch/axp-vbus' into allwinner
# Conflicts:
#	arch/arm/include/asm/arch-sunxi/gpio.h
2022-02-26 21:45:46 -06:00
Samuel Holland
a95f12e41d Merge branch 'patch/dm-i2c' into allwinner 2022-02-26 21:45:40 -06:00
Samuel Holland
c76c156861 Merge branch 'patch/dm-pinctrl' into allwinner 2022-02-26 21:45:38 -06:00
Samuel Holland
2ff0d92275 Merge branch 'patch/mkimage-toc1' into allwinner 2022-02-26 21:45:33 -06:00
Samuel Holland
77693293e1 Merge branch 'patch/mkimage-toc0' into allwinner 2022-02-26 21:45:31 -06:00
Samuel Holland
3078fe58c3 Merge branch 'patch/mkimage-riscv' into allwinner 2022-02-26 21:45:29 -06:00
Samuel Holland
b4dffc6a4a Merge branch 'patch/h6-dts' into allwinner 2022-02-26 21:45:26 -06:00
Samuel Holland
24e36b8177 Merge branch 'patch/h3-scp' into allwinner 2022-02-26 21:45:25 -06:00
Samuel Holland
0459d5e504 Merge branch 'patch/h3-fit' into allwinner 2022-02-26 21:45:22 -06:00
Samuel Holland
2315fe6cd7 Merge branch 'patch/dt-sync' into allwinner 2022-02-26 21:45:20 -06:00
Samuel Holland
e89dc4991a tools: mkimage: Add Allwinner TOC1 support
TOC1 is an container format used by Allwinner's boot0 that can hold
multiple images. It supports encryption and signatures, but that
functionality is not implemented, only the basic "non-secure" subset.

A config file is used to provide the list of data files to include. Its
path is passed as the argument to "-d". It contains sections of the
following form:

  [name]
  file = /path/to/file
  addr = 0x12345678

Specific well-known names, such as "dtb", "opensbi", and "u-boot", are
used by the bootloader to distinguish the items inside the image.

Cover-letter:
tools: mkimage: Add Allwinner TOC1 support

The SPL port for the Allwinner D1 RISC-V SoC will probably take a while
longer than porting U-Boot proper, as none of the relevant drivers are
set up for DM in SPL. In the meantime, we are using[1][2] a fork[3] of
Allwinner's boot0 loader, which they also call "spl" in their BSP. boot0
uses this TOC1 image format.

The vendor tools for generating TOC1 images require a binary config file
generated by their FEX compiler. Instead of trying to support that, I
made up a simple human-readable config file format. I didn't see any
existing platform-agnostic parser for multi-image containers in mkimage.

I am sending this as RFC because it is only of temporary/limited use.
It only works with one specific fork of boot0 which was modified to
"behave" (the the original vendor version monkey-patches a custom header
inside the U-Boot image during boot). So it will be obsolete once U-Boot
SPL is ported. And it is Yet Another Image Format. On the other hand, it
does work, and it is currently being used.

[1]: https://linux-sunxi.org/Allwinner_Nezha#U-Boot
[2]: https://fedoraproject.org/wiki/Architectures/RISC-V/Allwinner
[3]: https://github.com/smaeul/sun20i_d1_spl
END
Series-prefix: RFC
Series-to: sunxi
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:45:00 -06:00
Samuel Holland
a9a4131130 sunxi: Support building a SPL as a TOC0 image
Now that mkimage can generate TOC0 images, and the SPL can interpret
them, hook up the build infrastructure so the user can choose which
image type to build. Since the absolute load address is stored in the
TOC0 header, that information must be passed to mkimage.

Cover-letter:
sunxi: TOC0 image type support
This series adds support for the TOC0 image format used by the Allwinner
secure boot ROM (SBROM). This series has been tested on the following
SoCs/boards, with the eFuse burnt to enable secure mode:
 - A50: Ainol Q88 Tablet
 - A64: Pine A64 Plus
 - H5: Orange Pi Zero Plus
 - H6: Pine H64 Model B
 - H616: Orange Pi Zero 2

This time I also tested it on boards that are not switched to secure
mode (with A64, H3, and H5).

Due to both series changing Makefile.spl, the last patch depends on:
https://patchwork.ozlabs.org/project/uboot/list/?series=267136

Since this series no longer selects TOOLS_LIBCRYPTO anywhere, building
certain platforms/options may fail with an error like the following if
TOOLS_LIBCRYPTO is disabled:

    MKIMAGE spl/sunxi-spl.bin
  ./tools/mkimage: unsupported type Allwinner TOC0 Boot Image
  make[1]: *** [scripts/Makefile.spl:426: spl/sunxi-spl.bin] Error 1
  make: *** [Makefile:1982: spl/u-boot-spl] Error 2
END

Series-to: sunxi
Series-version: 4
Series-changes: 2
 - Rebase on top of Icenowy's RISC-V support series
 - Rename Kconfig symbols to include the full image type name

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:44:45 -06:00
Samuel Holland
aee968ef3d sunxi: Support SPL in both eGON and TOC0 images
SPL uses the image header to detect the boot device and to find the
offset of the next U-Boot stage. Since this information is stored
differently in the eGON and TOC0 image headers, add code to find the
correct value based on the image type currently in use.

Series-changes: 2
 - Moved SPL header signature checks out of sunxi_image.h
 - Refactored SPL header signature checks to use fewer casts

Series-changes: 3
 - Fixed offset of magic passed to memcmp
 - Refactored functions to not return pointers (fixes ambiguous NULL)

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:44:45 -06:00
Samuel Holland
8e3dfc7f12 spi: sun4i_spi: Remove non-DM pin setup
This is now handled automatically by the pinctrl driver.

Series-version: 2
Cover-letter:
sunxi: Add and use a pinctrl driver
This series resolves some longstanding TODOs by implementing a pinctrl
driver for sunxi platforms and converting DM drivers to use it.
END
Series-to: sunxi
Series-cc: sjg
Series-cc: Sean Anderson <seanga2@gmail.com>
Series-cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
a7644cdf90 pinctrl: sunxi: Add SPI0 pinmuxes
Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
2f45eef7b9 pwm: sunxi: Remove non-DM pin setup
This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
0031d5c2e4 pinctrl: sunxi: Add the A64 PWM pinmux
This is the only possible mux setting for the A64's PWM peripheral.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
8505d11974 sunxi: Remove non-DM MMC pin setup
This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
09e5cbacb4 pinctrl: sunxi: Add MMC pinmuxes
Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
70468f7ebe i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C
When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.

Clean up the code in the process: remove #ifdefs and recognize that the
pin configuration is the same for all sun8i/sun50i SoCs, not just those
which select CONFIG_MACH_SUN8I.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
728c6782d2 i2c: sun6i_p2wi: Only do non-DM pin setup for non-DM I2C
When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:31:55 -06:00
Samuel Holland
70b6734d81 i2c: sun8i_rsb: Add support for DM clocks and resets
Currently, clock/reset setup for this device is handled by a
platform-specific function and is intermixed with non-DM pinctrl
setup. Use the devicetree to get clocks/resets, which disentagles
it from the pinctrl setup in preparation for moving to DM_PINCTRL.

This also has the added benefit of picking the right clock/reset
bits for H6 and new SoCs that have a rearranged PRCM MMIO space.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:28:46 -06:00
Samuel Holland
f3fddfae64 i2c: sun8i_rsb: Initialize chips in .child_pre_probe
Chips attached to the RSB bus require an initialization command before
they can be used. (Specifically, this command programs the chip's
runtime address.) The driver does this in its .probe_chip hook, under
the assumption that .probe_chip is called during child probe. This is
not the case; .probe_chip is only called by dm_i2c_probe, which is
intended for use by board-level code, not for chips with OF nodes.

Since this initialization command must be run before a child chip can be
used, do it before probing each child.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:28:46 -06:00
Samuel Holland
191fc15ebc i2c: sun6i_p2wi: Add support for DM clocks and resets
Currently, clock/reset setup for this device is handled by a
platform-specific function and is intermixed with non-DM pinctrl
setup. Use the devicetree to get clocks/resets, which disentagles
it from the pinctrl setup in preparation for moving to DM_PINCTRL.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:28:46 -06:00
Samuel Holland
967656994b i2c: sun6i_p2wi: Initialize chips in .child_pre_probe
Chips attached to the P2WI bus require an initialization command before
they can be used. (Specifically, this switches the chip from I2C mode
to P2WI mode.) The driver does this in its .probe_chip hook, under the
assumption that .probe_chip is called during child probe. This is not
the case; .probe_chip is only called by dm_i2c_probe, which is intended
for use by board-level code, not for chips with OF nodes.

Since this initialization command must be run before a child chip can be
used, do it before probing each child.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:26:15 -06:00
Samuel Holland
8db2b02cf8 gpio: axp: Add pull-down support for AXP22x/AXP8xx variant
The AXP221 and newer PMICs support a pull-down function on their GPIOs.
Add support for it.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:06 -06:00
Samuel Holland
ceab9469ee gpio: axp: Add support for getting the pin function
Implement the .get_function operation, so the gpio command can report
the current function. Since the GPIOF_FUNC (versus GPIOF_UNUSED) mux
values vary among the PMICs, report all non-GPIO mux values as UNKNOWN.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:06 -06:00
Samuel Holland
b821f5b943 gpio: axp: Select variant from compatible at runtime
There are three major variants of the AXP PMIC GPIO functionality (plus
PMICs with no GPIOs at all). Except for GPIO3 on the AXP209, which uses
a different register layout, it is straightforward to support all three
variants with a single driver. Do this, and in the process remove the
GPIO-related definitions from the PMIC-specific headers, and therefore
the dependency on AXP_PMIC_BUS.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:06 -06:00
Samuel Holland
6f32bc0481 gpio: axp: Use DM_PMIC functions for register access
Now that the PMIC driver implements the DM_PMIC uclass, those functions
can be used instead of the platform-specific "pmic_bus" functions.

Since the driver still uses the single set of register definitions from
axpXXX.h (as selected by AXPxxx_POWER), it still depends on one of those
choices, and therefore also AXP_PMIC_BUS.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:06 -06:00
Samuel Holland
405fb692ee gpio: axp: Bind via device tree
Now that the PMIC has a DM driver and binds device tree subnodes, the
GPIO device can be bound that way, instead of from inside board code.

Since the driver still uses the single set of register definitions from
axpXXX.h (as selected by AXPxxx_POWER), it does not differentiate among
the supported compatibles.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:06 -06:00
Samuel Holland
de2f12a075 gpio: axp: Consistently use the "axp_gpio" order
This is less confusing than half of the driver using "axp_gpio" and the
other half using "gpio_axp".

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:06 -06:00
Samuel Holland
e303018546 ARM: dts: sunxi: Add AXP221 and AXP809 GPIO nodes
These PMICs each have two GPIO pins, and are supported by the axp_gpio
driver. In order to convert the axp_gpio driver to probe using the
device tree, the corresponding device tree nodes must be present. Add
them, following the same binding as the AXP209 and AXP813.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:06 -06:00
Samuel Holland
8948fcc9da phy: sun4i-usb: Use DM_GPIO for id/vbus_det GPIOs
Now that the sunxi_gpio driver handles pull-up/down via the driver
model, we can switch to DM_GPIO for these pins with no loss in
functionality. Since the driver now gets its pin configuration from
the device tree, we can remove the Kconfig symbols.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:02 -06:00
Samuel Holland
8642395169 gpio: axp/sunxi: Remove virtual VBUS enable GPIO
Now that this functionality is modeled using the device tree and
regulator uclass, the named GPIO is not referenced anywhere. Remove
it, along with the rest of the support for AXP virtual GPIOs.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:02 -06:00
Samuel Holland
93de303221 sunxi: Remove obsolete USBx_VBUS_PIN Kconfig symbols
Now that the USB PHY driver uses the device tree to get VBUS supply
regulators, these Kconfig symbols are unused. Remove them.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:02 -06:00
Samuel Holland
1388a7072e phy: sun4i-usb: Control USB supplies via regulator uclass
The device tree binding for the PHY provides VBUS supplies as regulator
references. Now that all boards have the appropriate regulator uclass
drivers enabled, the PHY driver can switch to using them. This replaces
direct GPIO usage, which in some cases needed a special DM-incompatible
"virtual" GPIO from the PMIC.

The following boards provided a value for CONFIG_USB0_VBUS_PIN, but are
missing the "usb0_vbus-supply" property in their device tree. None of
them have the MUSB controller enabled in host or OTG mode, so they
should see no impact:
 - Ainol_AW1_defconfig / sun7i-a20-ainol-aw1
 - Ampe_A76_defconfig / sun5i-a13-ampe-a76
 - CHIP_pro_defconfig / sun5i-gr8-chip-pro
 - Cubieboard4_defconfig / sun9i-a80-cubieboard4
 - Merrii_A80_Optimus_defconfig / sun9i-a80-optimus
 - Sunchip_CX-A99_defconfig / sun9i-a80-cx-a99
 - Yones_Toptech_BD1078_defconfig / sun7i-a20-yones-toptech-bd1078
 - Yones_Toptech_BS1078_V2_defconfig /
   sun6i-a31s-yones-toptech-bs1078-v2
 - iNet_3F_defconfig / sun4i-a10-inet-3f
 - iNet_3W_defconfig / sun4i-a10-inet-3w
 - iNet_86VS_defconfig / sun5i-a13-inet-86vs
 - iNet_D978_rev2_defconfig / sun8i-a33-inet-d978-rev2
 - icnova-a20-swac_defconfig / sun7i-a20-icnova-swac
 - sun8i_a23_evb_defconfig / sun8i-a23-evb

Similarly, the following boards set CONFIG_USB1_VBUS_PIN, but do not
have "usb1_vbus-supply" in their device tree. Neither of them have USB
enabled at all, so again there should be no impact:
 - Cubieboard4_defconfig / sun9i-a80-cubieboard4 (also for USB3)
 - sun8i_a23_evb_defconfig / sun8i-a23-evb

The following boards use a different pin for USB1 VBUS between their
defconfig and their device tree. Depending on which is correct, they
may be broken:
 - Linksprite_pcDuino3_Nano_defconfig (PH11) /
   sun7i-a20-pcduino3-nano (PD2)
 - icnova-a20-swac_defconfig (PG10) / sun7i-a20-icnova-swac (PH6)

Finally, this board has conflicting pins given for its USB2 VBUS:
 - Lamobo_R1_defconfig (PH3) / sun7i-a20-lamobo-r1 (PH12)

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:02 -06:00
Samuel Holland
1c6fe3f007 sunxi: Enable fixed regulator support for USB supplies
On many boards, the USB ports are powered by a GPIO-controlled fixed
regulator. In preparation for switching the USB PHY driver to use the
regulator uclass instead of driving the GPIO directly, ensure these
boards have fixed regulator support enabled.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:02 -06:00
Samuel Holland
75946b0e8a sunxi: Enable PMIC drivevbus regulator support for USB supplies
On many boards, the USB ports are powered by the PMIC's "drivevbus"
regulator. In preparation for switching the USB PHY driver to use the
regulator uclass instead of a virtual GPIO pin, ensure these boards
have AXP PMIC regulator support enabled.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:02 -06:00
Samuel Holland
a5bed60ca2 power: pmic: axp: Probe the drivevbus regulator from the DT
Now that some regulator driver exists for this PMIC, add support for
probing regulator drivers from the device tree subnodes.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:02 -06:00
Samuel Holland
97652c0932 power: regulator: Add a driver for the AXP PMIC drivevbus
The first AXP regulator converted to use the regulator uclass is the
drivevbus switch, since it is used by the USB PHY driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:02 -06:00
Samuel Holland
9c5daebdc7 gpio: axp/sunxi: Remove virtual VBUS detection GPIO
Now that this functionality is modeled using the device tree and
regulator uclass, the named GPIO is not referenced anywhere. Remove it.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:01 -06:00
Samuel Holland
bb993c3257 sunxi: Switch to PMIC USB power supply VBUS detection
Update boards to use the USB power supply driver, as referenced in the
device tree, instead of a virtual GPIO. This removes the need for some
DM-incompatible special cases in the GPIO driver.

The following six boards used AXP0-VBUS-DETECT in their config, but are
missing the "usb0_vbus_power-supply" property in their device tree:
 - Ainol_AW1_defconfig / sun7i-a20-ainol-aw1
 - Cubieboard4_defconfig / sun9i-a80-cubieboard4
 - Merrii_A80_Optimus_defconfig / sun9i-a80-optimus
 - Nintendo_NES_Classic_Edition_defconfig /
   sun8i-r16-nintendo-nes-classic-edition
 - Yones_Toptech_BD1078_defconfig / sun7i-a20-yones-toptech-bd1078
 - Yones_Toptech_BS1078_V2_defconfig /
   sun6i-a31s-yones-toptech-bs1078-v2

None of those six boards have the MUSB controller (USB OTG) enabled in
their device trees, so this change should not break anything for them.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:01 -06:00
Samuel Holland
fa41709646 power: regulator: Add a driver for the AXP USB power supply
This driver reports the presence/absence of voltage on the PMIC's USB
VBUS pin. This information is used by the USB PHY driver. The
corresponding Linux driver uses the power supply class, which does not
exist in U-Boot. UCLASS_REGULATOR seems to be the closest match.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:01 -06:00
Samuel Holland
ef62a50abe ARM: dts: sun6i: mixtile-loftq: Add USB1 VBUS regulator
This board is configured with CONFIG_USB1_VBUS_PIN="PH24", but no
regulator exists in its device tree. Add the regulator, so USB will
continue to work when the PHY driver switches to using the regulator
uclass instead of a GPIO.

Update the device tree here because it does not exist in Linux.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:15:01 -06:00
Samuel Holland
fbb3a6f47a sunxi: Remove non-DM I2C clock/pin setup from U-Boot
This is now handled automatically by the clock and pinctrl drivers.

SPL still calls this function because it needes the non-DM code.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:38 -06:00
Samuel Holland
b897efc201 sunxi: Remove options and setup code for I2C2-I2C4
These options are not currently enabled anywhere. Any new users should
use DM clocks and pinctrl.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:38 -06:00
Samuel Holland
f9f55a01d5 pinctrl: sunxi: Add I2C pinmuxes
Where multiple options were available, the one matching board.c and the
device trees was chosen.

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:38 -06:00
Samuel Holland
0ade741191 net: sun8i_emac: Remove non-DM pin setup
This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:38 -06:00
Samuel Holland
7aa24d0cd8 pinctrl: sunxi: Add sun8i EMAC pinmuxes
Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:38 -06:00
Samuel Holland
42033f97eb sunxi: Remove non-DM GMAC pin setup
This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:38 -06:00
Samuel Holland
d604e28adb pinctrl: sunxi: Add sunxi GMAC pinmuxes
Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:38 -06:00
Samuel Holland
7ed332180c net: sunxi_emac: Remove non-DM pin setup
This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:38 -06:00
Samuel Holland
cd33d18885 pinctrl: sunxi: Add sun4i EMAC pinmuxes
Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:38 -06:00
Samuel Holland
b1c0372900 sunxi: Skip non-DM UART pin setup when PINCTRL=y
When a pinctrl driver is available, it will take care of setting up
these pins. However, for now this code is still needed in SPL.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:37 -06:00
Samuel Holland
a2f9c64459 pinctrl: sunxi: Add UART pinmuxes
This includes UART0 and R_UART (s_uart) on all supported platforms, plus
the additional UART configurations from arch/arm/mach-sunxi/board.c.

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:37 -06:00
Samuel Holland
683fd4c806 sunxi: pinctrl: Implement pin configuration
The sunxi pinctrl hardware has bias and drive control. Add driver
support for configuring those options.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:37 -06:00
Samuel Holland
94ad76fe13 sunxi: pinctrl: Implement get_pin_muxing function
The pinmux command uses this function to display pinmux status.

Since the driver cannot map pin numbers to a list of supported
functions, only functions which are common across all pins can be
reported by name.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:37 -06:00
Samuel Holland
420f73b291 sunxi: pinctrl: Implement pin muxing functions
Implement the operations to get pin and function names, and to set the
mux for a pin. The pin count and pin names are calculated as if each
bank has the maximum number of pins. Function names are simply the index
into a list of { function name, mux value } pairs.

We assume all pins associated with a function use the same mux value for
that function. This is generally true within a group of pins on a single
port, but generally false when some peripheral can be muxed to multiple
ports. For example, A64 UART3 uses mux 3 on port D, and mux 2 on port H.
But all of the port D pins use the same mux value, and so do all of the
port H pins. This applies even when the pins for some function are not
contiguous, and when the lower-numbered mux values are unused. A good
example of both of these cases is SPI0 on most SoCs.

This strategy saves a lot of space (which is especially important for
SPL), but where the mux value for a certain function differs across
ports, it forces us to choose a single port for that function at build
time. Since almost all boards use the default (i.e. reference design)
pin muxes[1], this is unlikely to be a problem.

[1]: See commit dda9fa734f81 ("sunxi: Simplify MMC pinmux selection")

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:37 -06:00
Samuel Holland
4c7c1547ee sunxi: pinctrl: Create the driver skeleton
Create a do-nothing driver for each sunxi pin controller variant.

Since only one driver can automatically bind to a DT node, since the
GPIO driver already requires a manual binding process, and since the
pinctrl driver needs access to some of the same information, refactor
the GPIO driver to be bound by the pinctrl driver. This commit should
cause no functional change.

Series-changes: 2
 - Merge all SoC drivers into one file and one U_BOOT_DRIVER.
 - Add a consumer for the APB bus clock

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:37 -06:00
Samuel Holland
5ff2f6809f ARM: dts: sun50i: H6: Sync from Linux v5.15
Copy the devicetree source for the H6 SoC and all existing boards
verbatim from the Linux v5.15 tag.

This update should not impact any existing U-Boot functionality.

Series-to: sunxi
Cover-letter:
sunxi: Devicetree sync from Linux v5.15
This series brings all of our devicetrees up to date with the latest
stable Linux version.

<< something about ABI compat >>

Here is the list of new files which were not added by this sync:
 - sun4i-a10-topwise-a721.dts
 - sun50i-a100-allwinner-perf1.dts
 - sun50i-a100.dtsi
 - sun50i-h6-pine-h64-model-b.dts
 - sun5i-a13-licheepi-one.dts
 - sun5i-a13-pocketbook-touch-lux-3.dts
 - sun5i-gr8-evb.dts
 - sun7i-a20-linutronix-testbox-v2.dts
 - sun7i-a20-olinuxino-lime-emmc.dts
 - sun8i-a23-ippo-q8h-v1.2.dts
 - sun8i-a23-ippo-q8h-v5.dts
 - sun8i-a33-et-q8-v1.6.dts
 - sun8i-a33-ippo-q8h-v1.2.dts
 - sun8i-h3-nanopi-r1.dts
 - sun8i-r16-nintendo-nes-classic.dts
 - sun8i-r16-nintendo-super-nes-classic.dts
 - sun8i-r40-feta40i.dtsi
 - sun8i-r40-oka40i-c.dts
 - sun8i-s3-elimo-impetus.dtsi
 - sun8i-s3-elimo-initium.dts
 - sun8i-t3-cqa3t-bv3.dts
 - sun8i-v3-sl631-imx179.dts
 - sun8i-v3-sl631.dtsi
END

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:34 -06:00
Samuel Holland
0290c2a12e ARM: dts: sun50i: H5: Sync from Linux v5.15
Copy the devicetree source for the H5 SoC and all existing boards
from the Linux v5.15 tag, with minor changes to account for the
different directory layout for 64-bit SoCs.

While there were some recent changes to the shared H3/H5 devicetree,
the only H5-specific change is fixing the EMAC phy-mode in one board.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:34 -06:00
Samuel Holland
ebd3b2ffbe ARM: dts: sun50i: A64: Sync from Linux v5.15
Copy the devicetree source for the A64 SoC and all existing boards
verbatim from the Linux v5.15 tag.

As with the other SoCs, updates of note are EMAC phy-mode changes to set
RGMII delays.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:34 -06:00
Samuel Holland
0f356d7a6c ARM: dts: sun8i: R40: Sync from Linux v5.15
Copy the devicetree for the R40 SoC verbatim from the Linux v5.15 tag.

None of the existing boards had any devicetree updates.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:33 -06:00
Samuel Holland
4bbe0b11e8 ARM: dts: sun8i: V3/V3s/S3: Sync from Linux v5.15
Copy the devicetree source for the V3(s)/S3 SoCs and all existing boards
verbatim from the Linux v5.15 tag.

This update should not impact any existing U-Boot functionality.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:33 -06:00
Samuel Holland
37d049d3a9 ARM: dts: sun8i: H2+/H3: Sync from Linux v5.15
Copy the devicetree source for the H2+/H3 SoCs and all existing boards
verbatim from the Linux v5.15 tag.

As with the other SoCs, updates of note are EMAC phy-mode changes to set
RGMII delays.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:33 -06:00
Samuel Holland
5b1d29fa41 ARM: dts: sun8i: A83T: Sync from Linux v5.15
Copy the devicetree source for the A83T SoC and all existing boards
verbatim from the Linux v5.15 tag.

As with the other SoCs, updates of note are EMAC phy-mode changes to set
RGMII delays, and adding detection GPIO properties in the USB PHY nodes.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:33 -06:00
Samuel Holland
2e6864cd1d ARM: dts: sun9i: Sync from Linux v5.15
Copy the devicetree source for the A80 SoC and all existing boards
verbatim from the Linux v5.15 tag.

This update should not impact any existing U-Boot functionality.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:33 -06:00
Samuel Holland
d80f61c45e ARM: dts: sunxi: A13/A31/A23/A33: Sync from Linux v5.15
Copy the devicetree source for the A10s/A13/GR8, A31(s), and A23/A33/R16
SoCs and all existing boards verbatim from the Linux v5.15 tag.

These SoCs are combined into one commit due to some interdependencies:
 - The unit addresses were removed from bitbanged I2C buses, which
   drives a Kconfig default change. This affects sun5i-a13-utoo-p66.dts
   and sun6i-a31-colombus.dts.
 - The pinctrl nodes were renamed, including some used by the shared
   sunxi-reference-design-tablet.dtsi.

This commit renames the file sun8i-r16-nintendo-nes-classic-edition.dts
to sun8i-r16-nintendo-nes-classic.dts to match the Linux tree.

As with the other SoCs, updates of note are EMAC phy-mode changes to set
RGMII delays, conversion of GPIO pull-up from pinconf to GPIO flags, and
renaming the detection GPIO properties in the USB PHY nodes.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:33 -06:00
Samuel Holland
1e258e7679 ARM: dts: sun7i: Sync from Linux v5.15
Copy the devicetree source for the A20 SoC and all existing boards
verbatim from the Linux v5.15 tag.

An important change here is to the GMAC phy-mode property on several
boards; this needs to be set correctly once the rtl8211e driver starts
configuring the PHY RGMII delays from the devicetree.

This update also includes changes to the USB PHY detection GPIO
properties which are needed to convert that driver to use the DM GPIO
framework.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:33 -06:00
Samuel Holland
19946a3395 ARM: dts: sun4i: Sync from Linux v5.15
Copy the devicetree source for the A10 SoC and all existing boards
verbatim from the Linux v5.15 tag.

While this update should not impact any existing U-Boot functionality,
the changes to the USB PHY detection GPIO properties are needed to
convert that driver to use the DM GPIO framework.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:32 -06:00
Samuel Holland
c750419fd9 [DO NOT MERGE] sunxi: psci: Delegate PSCI to SCPI
This adds a new PSCI implementation which communicates with SCP firmware
running on the AR100 using the SCPI protocol. This allows it to support
the full set of PSCI v1.1 features, including CPU idle states, system
suspend, and multiple reset methods.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:25 -06:00
Samuel Holland
fef78fd619 [DO NOT MERGE] sunxi: Enable remoteproc on some H3 boards
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:25 -06:00
Samuel Holland
60f8dfbcf8 arm: psci: Add definitions for PSCI v1.1
Add the new option, function IDs, and prototypes for PSCI v1.1
implementations. In the process, fix some issues with the existing
definitions:
 - Fix the incorrectly-named ARM_PSCI_0_2_FN64_SYSTEM_RESET2.
 - Replace the deprecated "affinity_level" naming with "power_level".

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:25 -06:00
Samuel Holland
cae683dc77 sunxi: Enable support for SCP firmware on H3
Now that issues with the BROM have been sorted out, we can implement
PSCI system suspend on H3 by delegating to SCP firmware. Let's start by
including the firmware in the FIT image and starting the coprocessor if
valid firmware is loaded.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:25 -06:00
Samuel Holland
c46665fb62 arm: dts: sunxi: h3: Add nodes for AR100 remoteproc
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:25 -06:00
Samuel Holland
9ecfeb198c remoteproc: Add a driver for the Allwinner AR100
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:25 -06:00
Samuel Holland
01cabeb719 sunxi: psci: Add support for H3 CPU 0 hotplug
Due to a bug in the H3 SoC, where the CPU 0 hotplug flag cannot be
written, resuming CPU 0 requires using the "Super Standby" code path in
the BROM instead of the hotplug path. This path requires jumping to an
eGON image in SRAM.

Add support to the build system to generate this eGON image and include
it in the FIT, and add code to direct the BROM to its location in SRAM.

Since the Super Standby code path in the BROM initializes the CPU and
AHB1 clocks to 24 MHz, those registers need to be restored after control
passes back to U-Boot. Furthermore, because the BROM lowers the AHB1
clock divider to /1 before switching to the lower-frequency parent,
PLL_PERIPH0 must be bypassed to prevent AHB1 from temporarily running at
600 MHz. Otherwise, this locks up the SoC.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:25 -06:00
Samuel Holland
15aacda320 sunxi: psci: Avoid hanging when CPU 0 is hot-unplugged
Do not try to send an SGI from CPU 0 to itself. Since FIQs are masked
when entering monitor mode, this will hang. Plus, CPU 0 cannot fully
power itself off anyway. Instead, have it turn FIQs back on and continue
servicing SGIs from other cores.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:24 -06:00
Samuel Holland
28afd11d5c sunxi: binman: Enable SPL FIT loading for 32-bit SoCs
Now that Crust (SCP firmware) has support for H3, we need a FIT image to
load it. H3 also needs to load a SoC-specific eGon blob to support CPU 0
hotplug. Let's first enable FIT support before adding extra firmware.

Update the binman description to work on either 32-bit or 64-bit SoCs:
 - Make BL31 optional, since it is not used on 32-bit SoCs (though BL32
   may be used in the future).
 - Explicitly set the minimum offset of the FIT to 32 KiB, since SPL on
   some boards is still only 24 KiB large even with FIT support enabled.
   CONFIG_SPL_PAD_TO cannot be used because it is not defined for H616.

FIT unlocks more features (signatures, multiple DTBs, etc.), so enable
it by default. A10 (sun4i) only has 24 KiB of SRAM A1, so it needs
SPL_FIT_IMAGE_TINY. For simplicity, enable that option everywhere.

Cover-letter:
sunxi: SPL FIT support for 32-bit sunxi SoCs
This series makes the necessary changes so 32-bit sunxi SoCs can load
additional device trees or firmware from SPL along with U-Boot proper.

There was no existing binman entry property that put the FIT at the
right offset. The minimum offset is 32k, but this matches neither the
SPL size (which is no more than 24k on some SoCs) nor the FIT alignment
(which is 512 bytes in practice due to SPL size constraints). So instead
of adding a new property, I fixed what is arguably a bug in the offset
property -- though this strategy will not work if someone is
intentionally creating overlapping entries.
END
Series-to: sunxi
Series-to: sjg
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:14 -06:00
Samuel Holland
ce68ad0514 binman: Prevent entries in a section from overlapping
Currently, if the "offset" property is given for an entry, the section's
running offset is completely ignored. This causes entries to overlap if
the provided offset is less than the size of the entries earlier in the
section. Avoid the overlap by only using the provided offset when it is
greater than the running offset.

The motivation for this change is the rule used by SPL to find U-Boot on
sunxi boards: U-Boot starts 32 KiB after the start of SPL, unless SPL is
larger than 32 KiB, in which case U-Boot immediately follows SPL.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:14:13 -06:00
Samuel Holland
5d29074f50 Kconfig: Remove an impossible condition
ARCH_SUNXI selects BINMAN, so the condition "!BINMAN && ARCH_SUNXI"
is impossible to satisfy.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:13:55 -06:00
Samuel Holland
d2538b7f23 sunxi: DT: H6: Add USB3 to Pine H64 DTS
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:13:49 -06:00
Samuel Holland
eab8f6715e sunxi: DT: H6: Add device tree for Pine H64 Model B
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:13:49 -06:00
Samuel Holland
3550c1a290 tools: mkimage: Add Allwinner TOC0 support
Most Allwinner sunxi SoCs have separate boot ROMs in non-secure and
secure mode. The "non-secure" or "normal" boot ROM (NBROM) uses the
existing sunxi_egon image type. The secure boot ROM (SBROM) uses a
completely different image type, known as TOC0.

A TOC0 image is composed of a header and two or more items. One item
is the firmware binary. The others form a chain linking the firmware
signature to the root-of-trust public key (ROTPK), which has its hash
burned in the SoC's eFuses. Signatures are made using RSA-2048 + SHA256.

The pseudo-ASN.1 structure is manually assembled; this is done to work
around bugs/quirks in the boot ROM, which vary between SoCs. This TOC0
implementation has been verified to work with the A50, A64, H5, H6,
and H616 SBROMs, and it may work with other SoCs.

Series-changes: 2
 - Moved certificate and key item structures out of sunxi_image.h
 - Renamed "main" and "item" variables for clarity
 - Improved error messages, and added a hint about key generation
 - Added a comment explaining the purpose of the various key files
 - Mentioned testing this code on A50 in the commit message

Series-changes: 3
 - Removed TOOLS_LIBCRYPTO selection for sunxi, since most boards
   do not need it
 - Added __packed to all new "ABI" structs
 - Added entry to MAINTAINERS for sunxi tools

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:13:26 -06:00
Icenowy Zheng
56cc33063b sunxi: specify architecture when generating SPL boot image
As mkimage -T sunxi_egon now gains support for -A parameter, specify the
architecture when generating SPL boot image for sunxi.

Series-to: sunxi
Series-cc: Icenowy Zheng <icenowy@aosc.io>
Series-version: 3
Cover-letter:
mkimage: sunxi_egon: add riscv support
This patchset updates mkimage -T sunxi_egon to be able to generate
an eGON.BT0 image for Allwinner RISC-V SoCs (e.g. D1).

In addition, to keep the compatibility, it will still consider the
architecture to be ARM when no architecture is specified.

This v3 is a minor update to Icenowy's patch series, which I have
also tested. Since the TOC0 patch series touches the same lines in
Makefile.spl, it depends on this series.
END
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:11:53 -06:00
Icenowy Zheng
250bcf30b4 mkimage: sunxi_egon: add support for riscv
There's now a sun20i family in sunxi, which uses RISC-V CPU.

Add support for making eGON.BT0 image for RISC-V.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:11:53 -06:00
Icenowy Zheng
c2d1b7e945 mkimage: sunxi_egon: refactor for multi-architecture support
Refactor some functions in mkimage sunxi_egon type, in order to prepare
for adding support for more CPU architectures (e.g. RISC-V). In
addition, compatibility for operation w/o specified architecture is
kept, in this case the architecture is assumed as ARM.

Series-changes: 3
- Factor out an egon_get_arch() function as suggested by Andre

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:11:52 -06:00
Icenowy Zheng
26f21f8bd0 mkimage: add a flag to describe whether -A is specified
The sunxi_egon type used to take no -A argument (because we assume sunxi
targets are all ARM). However, as Allwinner D1 appears as the first
RISC-V sunxi target, we need to support -A; in addition, as external
projects rely on U-Boot mkimage to generate sunxi eGON.BT0 header, we
need to keep compatibility with command line without -A.

As the default value of arch in mkimage is not proper (IH_ARCH_PPC
instead of IH_ARCH_INVALID), to keep more compatibility, add an Aflag
field to image parameters to describe whether an architecture is
explicitly specified.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-02-26 21:11:52 -06:00
366 changed files with 9855 additions and 3792 deletions

View File

@ -12,6 +12,8 @@ source "scripts/Kconfig.include"
# Allow defaults in arch-specific code to override any given here
source "arch/Kconfig"
source "board/sunxi/Kconfig"
menu "General setup"
config BROKEN
@ -235,7 +237,7 @@ config SYS_MALLOC_F_LEN
default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \
ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \
ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \
ARCH_LS1046A || ARCH_QEMU || ARCH_SUNXI || ARCH_OWL)
ARCH_LS1046A || ARCH_QEMU || ARCH_SUNXI || ARCH_OWL || TARGET_SUNXI)
default 0x400
help
Before relocation, memory is very limited on many platforms. Still,
@ -367,7 +369,7 @@ config BUILD_TARGET
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
RISCV || ARCH_ZYNQMP)
default "u-boot.kwb" if ARCH_KIRKWOOD
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "u-boot-with-spl.imx" if ARCH_MX6 && SPL

View File

@ -516,7 +516,9 @@ F: arch/arm/mach-sunxi/
F: board/sunxi/
F: drivers/clk/sunxi/
F: drivers/phy/allwinner/
F: drivers/pinctrl/sunxi/
F: drivers/video/sunxi/
F: tools/sunxi*
ARM TEGRA
M: Tom Warren <twarren@nvidia.com>

View File

@ -991,6 +991,23 @@ endif
endif
endif
ifeq ($(CONFIG_MACH_SUN8I_H3)$(CONFIG_ARMV7_PSCI),yy)
INPUTS-$(CONFIG_ARMV7_PSCI) += u-boot-resume.img
MKIMAGEFLAGS_u-boot-resume.img := -B 0x400 -T sunxi_egon
u-boot-resume.img: u-boot-resume.bin
$(call if_changed,mkimage)
OBJCOPYFLAGS_u-boot-resume.bin := -O binary
u-boot-resume.bin: u-boot-resume.o
$(call if_changed,objcopy)
u-boot-resume.S: u-boot
@sed -En 's/(0x[[:xdigit:]]+) +psci_cpu_entry/ldr pc, =\1/p' $<.map > $@
endif
INPUTS-$(CONFIG_X86) += u-boot-x86-start16.bin u-boot-x86-reset16.bin \
$(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
$(if $(CONFIG_TPL_X86_16BIT_INIT),tpl/u-boot-tpl.bin)

View File

@ -1070,6 +1070,7 @@ config ARCH_SUNXI
select OF_BOARD_SETUP
select OF_CONTROL
select OF_SEPARATE
select PINCTRL
select SPECIFY_CONSOLE_INDEX
select SPL_SEPARATE_BSS if SPL
select SPL_STACK_R if SPL
@ -1096,13 +1097,17 @@ config ARCH_SUNXI
imply SPL_GPIO
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_LOAD_FIT
imply SPL_MMC if MMC
imply SPL_POWER
imply SPL_SERIAL
imply SYSRESET
imply SYSRESET_WATCHDOG
imply SYSRESET_WATCHDOG_AUTO
imply USB_EHCI_GENERIC
imply USB_ETHER if USB_MUSB_GADGET
imply USB_GADGET
imply USB_OHCI_GENERIC
imply WDT
config ARCH_U8500

View File

@ -44,11 +44,14 @@ config ARMV7_PSCI
choice
prompt "Supported PSCI version"
depends on ARMV7_PSCI
default ARMV7_PSCI_0_1 if ARCH_SUNXI
default ARMV7_PSCI_1_1 if ARCH_SUNXI
default ARMV7_PSCI_1_0
help
Select the supported PSCI version.
config ARMV7_PSCI_1_1
bool "PSCI V1.1"
config ARMV7_PSCI_1_0
bool "PSCI V1.0"

View File

@ -13,7 +13,7 @@ obj-$(CONFIG_MACH_SUN6I) += sram.o
obj-$(CONFIG_MACH_SUN8I) += sram.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMV7_PSCI) += psci.o
obj-$(CONFIG_ARMV7_PSCI) += psci-scpi.o
endif
ifdef CONFIG_SPL_BUILD

View File

@ -0,0 +1,451 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
* Copyright (C) 2018-2021 Samuel Holland <samuel@sholland.org>
*/
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/cpucfg.h>
#include <asm/armv7.h>
#include <asm/gic.h>
#include <asm/io.h>
#include <asm/psci.h>
#include <asm/secure.h>
#include <asm/system.h>
#define GICD_BASE (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
#define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
#define HW_ON 0
#define HW_OFF 1
#define HW_STANDBY 2
#define MPIDR_AFFLVL0(mpidr) (mpidr & 0xf)
#define MPIDR_AFFLVL1(mpidr) (mpidr >> 8 & 0xf)
#define SCPI_SHMEM_BASE 0x0004be00
#define SCPI_SHMEM ((struct scpi_shmem *)SCPI_SHMEM_BASE)
#define SCPI_RX_CHANNEL 1
#define SCPI_TX_CHANNEL 0
#define SCPI_VIRTUAL_CHANNEL BIT(0)
#define SCPI_MESSAGE_SIZE 0x100
#define SCPI_PAYLOAD_SIZE (SCPI_MESSAGE_SIZE - sizeof(struct scpi_header))
#define SUNXI_MSGBOX_BASE 0x01c17000
#define REMOTE_IRQ_STAT_REG (SUNXI_MSGBOX_BASE + 0x0050)
#define LOCAL_IRQ_STAT_REG (SUNXI_MSGBOX_BASE + 0x0070)
#define MSG_STAT_REG(n) (SUNXI_MSGBOX_BASE + 0x0140 + 0x4 * (n))
#define MSG_DATA_REG(n) (SUNXI_MSGBOX_BASE + 0x0180 + 0x4 * (n))
#define RX_IRQ(n) BIT(0 + 2 * (n))
#define TX_IRQ(n) BIT(1 + 2 * (n))
enum {
CORE_POWER_LEVEL = 0,
CLUSTER_POWER_LEVEL = 1,
CSS_POWER_LEVEL = 2,
};
enum {
SCPI_CMD_SCP_READY = 0x01,
SCPI_CMD_SET_CSS_POWER_STATE = 0x03,
SCPI_CMD_GET_CSS_POWER_STATE = 0x04,
SCPI_CMD_SET_SYS_POWER_STATE = 0x05,
};
enum {
SCPI_E_OK = 0,
SCPI_E_PARAM = 1,
SCPI_E_ALIGN = 2,
SCPI_E_SIZE = 3,
SCPI_E_HANDLER = 4,
SCPI_E_ACCESS = 5,
SCPI_E_RANGE = 6,
SCPI_E_TIMEOUT = 7,
SCPI_E_NOMEM = 8,
SCPI_E_PWRSTATE = 9,
SCPI_E_SUPPORT = 10,
SCPI_E_DEVICE = 11,
SCPI_E_BUSY = 12,
SCPI_E_OS = 13,
SCPI_E_DATA = 14,
SCPI_E_STATE = 15,
};
enum {
SCPI_POWER_ON = 0x00,
SCPI_POWER_RETENTION = 0x01,
SCPI_POWER_OFF = 0x03,
};
enum {
SCPI_SYSTEM_SHUTDOWN = 0x00,
SCPI_SYSTEM_REBOOT = 0x01,
SCPI_SYSTEM_RESET = 0x02,
};
struct scpi_header {
u8 command;
u8 sender;
u16 size;
u32 status;
};
struct scpi_message {
struct scpi_header header;
u8 payload[SCPI_PAYLOAD_SIZE];
};
struct scpi_shmem {
struct scpi_message rx;
struct scpi_message tx;
};
static bool __secure_data gic_dist_init;
static u32 __secure_data lock;
static inline u32 __secure read_mpidr(void)
{
u32 val;
asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
return val;
}
static void __secure scpi_begin_command(void)
{
u32 mpidr = read_mpidr();
do {
while (readl(&lock));
writel(mpidr, &lock);
dsb();
} while (readl(&lock) != mpidr);
while (readl(REMOTE_IRQ_STAT_REG) & RX_IRQ(SCPI_TX_CHANNEL));
}
static void __secure scpi_send_command(void)
{
writel(SCPI_VIRTUAL_CHANNEL, MSG_DATA_REG(SCPI_TX_CHANNEL));
}
static void __secure scpi_wait_response(void)
{
while (!readl(MSG_STAT_REG(SCPI_RX_CHANNEL)));
}
static void __secure scpi_end_command(void)
{
while (readl(MSG_STAT_REG(SCPI_RX_CHANNEL)))
readl(MSG_DATA_REG(SCPI_RX_CHANNEL));
writel(RX_IRQ(SCPI_RX_CHANNEL), LOCAL_IRQ_STAT_REG);
writel(0, &lock);
}
static void __secure scpi_set_css_power_state(u32 target_cpu, u32 core_state,
u32 cluster_state, u32 css_state)
{
struct scpi_shmem *shmem = SCPI_SHMEM;
scpi_begin_command();
shmem->tx.header.command = SCPI_CMD_SET_CSS_POWER_STATE;
shmem->tx.header.size = 4;
shmem->tx.payload[0] = target_cpu >> 4 | target_cpu;
shmem->tx.payload[1] = cluster_state << 4 | core_state;
shmem->tx.payload[2] = css_state;
shmem->tx.payload[3] = 0;
scpi_send_command();
scpi_end_command();
}
static s32 __secure scpi_get_css_power_state(u32 target_cpu, u8 *core_states,
u8 *cluster_state)
{
struct scpi_shmem *shmem = SCPI_SHMEM;
u32 cluster = MPIDR_AFFLVL1(target_cpu);
u32 offset;
s32 ret;
scpi_begin_command();
shmem->tx.header.command = SCPI_CMD_GET_CSS_POWER_STATE;
shmem->tx.header.size = 0;
scpi_send_command();
scpi_wait_response();
for (offset = 0; offset < shmem->rx.header.size; offset += 2) {
if ((shmem->rx.payload[offset] & 0xf) == cluster) {
*cluster_state = shmem->rx.payload[offset+0] >> 4;
*core_states = shmem->rx.payload[offset+1];
break;
}
}
ret = shmem->rx.header.status;
scpi_end_command();
return ret;
}
static s32 __secure scpi_set_sys_power_state(u32 sys_state)
{
struct scpi_shmem *shmem = SCPI_SHMEM;
s32 ret;
scpi_begin_command();
shmem->tx.header.command = SCPI_CMD_SET_SYS_POWER_STATE;
shmem->tx.header.size = 1;
shmem->tx.payload[0] = sys_state;
scpi_send_command();
scpi_wait_response();
ret = shmem->rx.header.status;
scpi_end_command();
return ret;
}
void psci_enable_smp(void);
static s32 __secure psci_suspend_common(u32 pc, u32 context_id, u32 core_state,
u32 cluster_state, u32 css_state)
{
u32 target_cpu = read_mpidr();
if (core_state == SCPI_POWER_OFF)
psci_save(MPIDR_AFFLVL0(target_cpu), pc, context_id);
if (css_state == SCPI_POWER_OFF)
gic_dist_init = true;
scpi_set_css_power_state(target_cpu, core_state,
cluster_state, css_state);
psci_cpu_off_common();
wfi();
psci_enable_smp();
return ARM_PSCI_RET_SUCCESS;
}
u32 __secure psci_version(void)
{
return ARM_PSCI_VER_1_1;
}
s32 __secure psci_cpu_suspend(u32 __always_unused function_id,
u32 power_state, u32 pc, u32 context_id)
{
return psci_suspend_common(pc, context_id,
power_state >> 0 & 0xf,
power_state >> 4 & 0xf,
power_state >> 8 & 0xf);
}
s32 __secure psci_cpu_off(void)
{
u32 pc = 0, context_id = 0;
return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
SCPI_POWER_OFF, SCPI_POWER_ON);
}
s32 __secure psci_cpu_on(u32 __always_unused function_id,
u32 target_cpu, u32 pc, u32 context_id)
{
psci_save(MPIDR_AFFLVL0(target_cpu), pc, context_id);
scpi_set_css_power_state(target_cpu, SCPI_POWER_ON,
SCPI_POWER_ON, SCPI_POWER_ON);
return ARM_PSCI_RET_SUCCESS;
}
s32 __secure psci_affinity_info(u32 function_id,
u32 target_cpu, u32 power_level)
{
if (power_level != CORE_POWER_LEVEL)
return ARM_PSCI_RET_INVAL;
/* This happens to have the same HW_ON/HW_OFF encoding. */
return psci_node_hw_state(function_id, target_cpu, power_level);
}
void __secure psci_system_off(void)
{
scpi_set_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
/* Wait to be turned off. */
for (;;) wfi();
}
void __secure psci_system_reset(void)
{
scpi_set_sys_power_state(SCPI_SYSTEM_REBOOT);
/* Wait to be turned off. */
for (;;) wfi();
}
s32 __secure psci_features(u32 __always_unused function_id,
u32 psci_fid)
{
switch (psci_fid) {
case ARM_PSCI_0_2_FN_PSCI_VERSION:
case ARM_PSCI_0_2_FN_CPU_SUSPEND:
case ARM_PSCI_0_2_FN_CPU_OFF:
case ARM_PSCI_0_2_FN_CPU_ON:
case ARM_PSCI_0_2_FN_AFFINITY_INFO:
case ARM_PSCI_0_2_FN_SYSTEM_OFF:
case ARM_PSCI_0_2_FN_SYSTEM_RESET:
case ARM_PSCI_1_0_FN_PSCI_FEATURES:
case ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND:
case ARM_PSCI_1_0_FN_NODE_HW_STATE:
case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND:
case ARM_PSCI_1_1_FN_SYSTEM_RESET2:
return ARM_PSCI_RET_SUCCESS;
default:
return ARM_PSCI_RET_NI;
}
}
s32 __secure psci_cpu_default_suspend(u32 __always_unused function_id,
u32 pc, u32 context_id)
{
return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
SCPI_POWER_OFF, SCPI_POWER_RETENTION);
}
s32 __secure psci_node_hw_state(u32 __always_unused function_id,
u32 target_cpu, u32 power_level)
{
u32 core = MPIDR_AFFLVL0(target_cpu);
u8 core_states, cluster_state;
if (power_level >= CSS_POWER_LEVEL)
return HW_ON;
if (scpi_get_css_power_state(target_cpu, &core_states, &cluster_state))
return ARM_PSCI_RET_NI;
if (power_level == CLUSTER_POWER_LEVEL) {
if (cluster_state == SCPI_POWER_ON)
return HW_ON;
if (cluster_state < SCPI_POWER_OFF)
return HW_STANDBY;
return HW_OFF;
}
return (core_states & BIT(core)) ? HW_ON : HW_OFF;
}
s32 __secure psci_system_suspend(u32 __always_unused function_id,
u32 pc, u32 context_id)
{
return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
SCPI_POWER_OFF, SCPI_POWER_OFF);
}
s32 __secure psci_system_reset2(u32 __always_unused function_id,
u32 reset_type, u32 cookie)
{
s32 ret;
if (reset_type)
return ARM_PSCI_RET_INVAL;
ret = scpi_set_sys_power_state(SCPI_SYSTEM_RESET);
if (ret)
return ARM_PSCI_RET_INVAL;
/* Wait to be turned off. */
for (;;) wfi();
}
/*
* R40 is different from other single cluster SoCs. The secondary core
* entry address register is in the SRAM controller address range.
*/
#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
#ifdef CONFIG_MACH_SUN8I_R40
/* secondary core entry address is programmed differently on R40 */
static void __secure sunxi_set_entry_address(void *entry)
{
writel((u32)entry,
SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
}
#else
static void __secure sunxi_set_entry_address(void *entry)
{
struct sunxi_cpucfg_reg *cpucfg =
(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
writel((u32)entry, &cpucfg->priv0);
if (IS_ENABLED(CONFIG_MACH_SUN8I_H3)) {
/* Redirect CPU 0 to the secure monitor via the resume shim. */
writel(0x16aaefe8, &cpucfg->super_standy_flag);
writel(0xaa16efe8, &cpucfg->super_standy_flag);
writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
}
}
#endif
void __secure psci_arch_init(void)
{
static bool __secure_data one_time_init = true;
if (one_time_init) {
/* Set secondary core power-on PC. */
sunxi_set_entry_address(psci_cpu_entry);
/* Wait for the SCP firmware to boot. */
scpi_begin_command();
scpi_wait_response();
scpi_end_command();
one_time_init = false;
}
/*
* Copied from arch/arm/cpu/armv7/virt-v7.c
* See also gic_resume() in arch/arm/mach-imx/mx7/psci-mx7.c
*/
if (gic_dist_init) {
u32 i, itlinesnr;
/* enable the GIC distributor */
writel(readl(GICD_BASE + GICD_CTLR) | 0x03, GICD_BASE + GICD_CTLR);
/* TYPER[4:0] contains an encoded number of available interrupts */
itlinesnr = readl(GICD_BASE + GICD_TYPER) & 0x1f;
/* set all bits in the GIC group registers to one to allow access
* from non-secure state. The first 32 interrupts are private per
* CPU and will be set later when enabling the GIC for each core
*/
for (i = 1; i <= itlinesnr; i++)
writel((unsigned)-1, GICD_BASE + GICD_IGROUPRn + 4 * i);
gic_dist_init = false;
}
/* Be cool with non-secure. */
writel(0xff, GICC_BASE + GICC_PMR);
}

View File

@ -10,6 +10,7 @@
#include <common.h>
#include <asm/cache.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/cpucfg.h>
#include <asm/arch/prcm.h>
@ -38,6 +39,15 @@
#define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4)
#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
static inline u32 __secure cp15_read_mpidr(void)
{
u32 val;
asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
return val;
}
static void __secure cp15_write_cntp_tval(u32 tval)
{
asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
@ -132,6 +142,13 @@ static void __secure sunxi_set_entry_address(void *entry)
(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
writel((u32)entry, &cpucfg->priv0);
if (IS_ENABLED(CONFIG_MACH_SUN8I_H3)) {
/* Redirect CPU 0 to the secure monitor via the resume shim. */
writel(0x16aaefe8, &cpucfg->super_standy_flag);
writel(0xaa16efe8, &cpucfg->super_standy_flag);
writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
}
}
#endif
@ -246,9 +263,12 @@ out:
int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
u32 context_id)
{
struct sunxi_ccm_reg *ccu = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_cpucfg_reg *cpucfg =
(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
u32 cpu = (mpidr & 0x3);
u32 cpu_clk;
u32 bus_clk;
/* store target PC and context id */
psci_save(cpu, pc, context_id);
@ -265,12 +285,32 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
/* Lock CPU (Disable external debug access) */
clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
/* Save registers that will be clobbered by the BROM. */
cpu_clk = readl(&ccu->cpu_axi_cfg);
bus_clk = readl(&ccu->ahb1_apb1_div);
/* Bypass PLL_PERIPH0 so AHB1 frequency does not spike. */
setbits_le32(&ccu->pll6_cfg, BIT(25));
}
/* Power up target CPU */
sunxi_cpu_set_power(cpu, true);
/* De-assert reset on target CPU */
writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
/* Spin until the BROM has clobbered the clock registers. */
while (readl(&ccu->ahb1_apb1_div) != 0x00001100);
/* Restore the registers and turn off PLL_PERIPH0 bypass. */
writel(cpu_clk, &ccu->cpu_axi_cfg);
writel(bus_clk, &ccu->ahb1_apb1_div);
clrbits_le32(&ccu->pll6_cfg, BIT(25));
}
/* Unlock CPU (Disable external debug access) */
setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
@ -281,9 +321,14 @@ s32 __secure psci_cpu_off(void)
{
psci_cpu_off_common();
/* Ask CPU0 via SGI15 to pull the rug... */
writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
dsb();
if (cp15_read_mpidr() & 3) {
/* Ask CPU0 via SGI15 to pull the rug... */
writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
dsb();
} else {
/* Unmask FIQs to service SGI15. */
asm volatile ("cpsie f");
}
/* Wait to be turned off */
while (1)

View File

@ -103,7 +103,7 @@ void __noreturn psci_system_reset2(u32 reset_level, u32 cookie)
{
struct pt_regs regs;
regs.regs[0] = ARM_PSCI_0_2_FN64_SYSTEM_RESET2;
regs.regs[0] = ARM_PSCI_1_1_FN64_SYSTEM_RESET2;
regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level;
regs.regs[2] = cookie;
if (use_smc_for_psci)

View File

@ -610,7 +610,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-nintendo-nes-classic-edition.dtb \
sun8i-r16-nintendo-nes-classic.dtb \
sun8i-r16-parrot.dtb
dtb-$(CONFIG_MACH_SUN8I_A83T) += \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
@ -668,6 +668,7 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-orangepi-lite2.dtb \
sun50i-h6-orangepi-one-plus.dtb \
sun50i-h6-pine-h64.dtb \
sun50i-h6-pine-h64-model-b.dtb \
sun50i-h6-tanix-tx6.dtb
dtb-$(CONFIG_MACH_SUN50I_H616) += \
sun50i-h616-orangepi-zero2.dtb

View File

@ -57,11 +57,22 @@
status = "disabled";
};
axp_adc: adc {
compatible = "x-powers,axp221-adc";
#io-channel-cells = <1>;
};
battery_power_supply: battery-power-supply {
compatible = "x-powers,axp221-battery-power-supply";
status = "disabled";
};
axp_gpio: gpio {
compatible = "x-powers,axp221-gpio";
gpio-controller;
#gpio-cells = <2>;
};
regulators {
/* Default work frequency for buck regulators */
x-powers,dcdc-freq = <3000>;

View File

@ -50,4 +50,11 @@
compatible = "x-powers,axp809";
interrupt-controller;
#interrupt-cells = <1>;
axp_gpio: gpio {
compatible = "x-powers,axp809-gpio",
"x-powers,axp221-gpio";
gpio-controller;
#gpio-cells = <2>;
};
};

View File

@ -48,6 +48,11 @@
interrupt-controller;
#interrupt-cells = <1>;
ac_power_supply: ac-power-supply {
compatible = "x-powers,axp813-ac-power-supply";
status = "disabled";
};
axp_adc: adc {
compatible = "x-powers,axp813-adc";
#io-channel-cells = <1>;
@ -166,4 +171,8 @@
status = "disabled";
};
};
usb_power_supply: usb-power-supply {
compatible = "x-powers,axp813-usb-power-supply";
};
};

View File

@ -60,15 +60,26 @@
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
red {
led-0 {
label = "a1000:red:usr";
gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>;
};
blue {
led-1 {
label = "a1000:blue:pwr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
default-state = "on";
@ -125,7 +136,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};
@ -133,6 +144,20 @@
status = "okay";
};
&de {
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&i2c0 {
status = "okay";

View File

@ -68,7 +68,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};

View File

@ -131,20 +131,6 @@
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
usb0_vbus_detect_pin: usb0-vbus-detect-pin {
pins = "PH5";
function = "gpio_in";
bias-pull-down;
};
};
&reg_usb0_vbus {
status = "okay";
};
@ -165,10 +151,8 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
status = "okay";

View File

@ -75,12 +75,12 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_cubieboard>;
blue {
led-0 {
label = "cubieboard:blue:usr";
gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* LED1 */
};
green {
led-1 {
label = "cubieboard:green:usr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */
linux,default-trigger = "heartbeat";
@ -114,7 +114,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};
@ -184,12 +184,6 @@
function = "gpio_out";
drive-strength = <20>;
};
usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
};
&reg_ahci_5v {
@ -254,9 +248,7 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb1_vbus-supply = <&reg_usb1_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
status = "okay";

View File

@ -62,6 +62,7 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
power-supply = <&reg_vcc3v3>;
};
chosen {
@ -158,20 +159,6 @@
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
usb0_vbus_detect_pin: usb0-vbus-detect-pin {
pins = "PH5";
function = "gpio_in";
bias-pull-down;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
@ -223,10 +210,8 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
status = "okay";

View File

@ -80,7 +80,7 @@
};
&emac {
phy = <&phy0>;
phy-handle = <&phy0>;
status = "okay";
};

View File

@ -86,20 +86,6 @@
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
usb0_vbus_detect_pin: usb0-vbus-detect-pin {
pins = "PH5";
function = "gpio_in";
bias-pull-down;
};
};
&reg_usb0_vbus {
status = "okay";
};
@ -121,10 +107,8 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
status = "okay";

View File

@ -62,6 +62,7 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
power-supply = <&reg_vcc3v3>;
};
chosen {
@ -164,20 +165,6 @@
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
usb0_vbus_detect_pin: usb0-vbus-detect-pin {
pins = "PH5";
function = "gpio_in";
bias-pull-down;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
@ -233,10 +220,8 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;

View File

@ -1,7 +1,7 @@
/*
* Copyright 2014 Open Source Support GmbH
*
* David Lanzendörfer <david.lanzendoerfer@o2s.ch>
* David Lanzendörfer <david.lanzendoerfer@o2s.ch>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -150,20 +150,6 @@
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
usb0_vbus_detect_pin: usb0-vbus-detect-pin {
pins = "PH5";
function = "gpio_in";
bias-pull-down;
};
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
@ -209,10 +195,8 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
status = "okay";

View File

@ -61,10 +61,6 @@
gpio-keys {
compatible = "gpio-keys-polled";
pinctrl-names = "default";
pinctrl-0 = <&key_pins_inet9f>;
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <20>;
left-joystick-left {
@ -72,7 +68,7 @@
linux,code = <ABS_X>;
linux,input-type = <EV_ABS>;
linux,input-value = <0xffffffff>; /* -1 */
gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */
gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */
};
left-joystick-right {
@ -80,7 +76,7 @@
linux,code = <ABS_X>;
linux,input-type = <EV_ABS>;
linux,input-value = <1>;
gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */
gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */
};
left-joystick-up {
@ -88,7 +84,7 @@
linux,code = <ABS_Y>;
linux,input-type = <EV_ABS>;
linux,input-value = <0xffffffff>; /* -1 */
gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */
};
left-joystick-down {
@ -96,7 +92,7 @@
linux,code = <ABS_Y>;
linux,input-type = <EV_ABS>;
linux,input-value = <1>;
gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */
};
right-joystick-left {
@ -104,7 +100,7 @@
linux,code = <ABS_Z>;
linux,input-type = <EV_ABS>;
linux,input-value = <0xffffffff>; /* -1 */
gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */
gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */
};
right-joystick-right {
@ -112,7 +108,7 @@
linux,code = <ABS_Z>;
linux,input-type = <EV_ABS>;
linux,input-value = <1>;
gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */
gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */
};
right-joystick-up {
@ -120,7 +116,7 @@
linux,code = <ABS_RZ>;
linux,input-type = <EV_ABS>;
linux,input-value = <0xffffffff>; /* -1 */
gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */
gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */
};
right-joystick-down {
@ -128,7 +124,7 @@
linux,code = <ABS_RZ>;
linux,input-type = <EV_ABS>;
linux,input-value = <1>;
gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */
};
dpad-left {
@ -136,7 +132,7 @@
linux,code = <ABS_HAT0X>;
linux,input-type = <EV_ABS>;
linux,input-value = <0xffffffff>; /* -1 */
gpios = <&pio 7 23 GPIO_ACTIVE_LOW>; /* PH23 */
gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */
};
dpad-right {
@ -144,7 +140,7 @@
linux,code = <ABS_HAT0X>;
linux,input-type = <EV_ABS>;
linux,input-value = <1>;
gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */
gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */
};
dpad-up {
@ -152,7 +148,7 @@
linux,code = <ABS_HAT0Y>;
linux,input-type = <EV_ABS>;
linux,input-value = <0xffffffff>; /* -1 */
gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */
gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */
};
dpad-down {
@ -160,55 +156,55 @@
linux,code = <ABS_HAT0Y>;
linux,input-type = <EV_ABS>;
linux,input-value = <1>;
gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */
};
x {
label = "Button X";
linux,code = <BTN_X>;
gpios = <&pio 0 16 GPIO_ACTIVE_LOW>; /* PA16 */
gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */
};
y {
label = "Button Y";
linux,code = <BTN_Y>;
gpios = <&pio 0 14 GPIO_ACTIVE_LOW>; /* PA14 */
gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */
};
a {
label = "Button A";
linux,code = <BTN_A>;
gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */
};
b {
label = "Button B";
linux,code = <BTN_B>;
gpios = <&pio 0 15 GPIO_ACTIVE_LOW>; /* PA15 */
gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */
};
select {
label = "Select Button";
linux,code = <BTN_SELECT>;
gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */
gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */
};
start {
label = "Start Button";
linux,code = <BTN_START>;
gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */
gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */
};
top-left {
label = "Top Left Button";
linux,code = <BTN_TL>;
gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */
};
top-right {
label = "Top Right Button";
linux,code = <BTN_TR>;
gpios = <&pio 0 13 GPIO_ACTIVE_LOW>; /* PA13 */
gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */
};
};
};
@ -308,30 +304,6 @@
status = "okay";
};
&pio {
key_pins_inet9f: key-pins {
pins = "PA0", "PA1", "PA3", "PA4",
"PA5", "PA6", "PA8", "PA9",
"PA11", "PA12", "PA13",
"PA14", "PA15", "PA16", "PA17",
"PH22", "PH23", "PH24", "PH25", "PH26";
function = "gpio_in";
bias-pull-up;
};
usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
usb0_vbus_detect_pin: usb0-vbus-detect-pin {
pins = "PH5";
function = "gpio_in";
bias-pull-down;
};
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
@ -377,10 +349,8 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
status = "okay";

View File

@ -58,7 +58,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};

View File

@ -63,7 +63,7 @@
leds {
compatible = "gpio-leds";
green {
led {
label = "q5:green:usr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */
};
@ -94,7 +94,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};

View File

@ -62,22 +62,22 @@
leds {
compatible = "gpio-leds";
red1 {
led-0 {
label = "marsboard:red1:usr";
gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>;
};
red2 {
led-1 {
label = "marsboard:red2:usr";
gpios = <&pio 1 6 GPIO_ACTIVE_HIGH>;
};
red3 {
led-2 {
label = "marsboard:red3:usr";
gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>;
};
red4 {
led-3 {
label = "marsboard:red4:usr";
gpios = <&pio 1 8 GPIO_ACTIVE_HIGH>;
};
@ -105,7 +105,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};
@ -148,14 +148,6 @@
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
};
&reg_usb1_vbus {
status = "okay";
};
@ -183,9 +175,7 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb1_vbus-supply = <&reg_usb1_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
status = "okay";

View File

@ -74,7 +74,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_olinuxinolime>;
green {
led {
label = "a10-olinuxino-lime:green:usr";
gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
@ -112,7 +112,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};
@ -186,18 +186,6 @@
function = "gpio_out";
drive-strength = <20>;
};
usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
usb0_vbus_detect_pin: usb0-vbus-detect-pin {
pins = "PH5";
function = "gpio_in";
bias-pull-down;
};
};
&reg_ahci_5v {
@ -229,10 +217,8 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH5 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;

View File

@ -63,12 +63,12 @@
leds {
compatible = "gpio-leds";
tx {
led-0 {
label = "pcduino:green:tx";
gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
};
rx {
led-1 {
label = "pcduino:green:rx";
gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
};
@ -76,8 +76,6 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
back {
label = "Key Back";
@ -112,7 +110,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};
@ -156,14 +154,6 @@
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
};
#include "axp209.dtsi"
&reg_dcdc2 {
@ -203,9 +193,7 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb1_vbus-supply = <&reg_vcc5v0>; /* USB1 VBUS is always on */
usb2_vbus-supply = <&reg_vcc5v0>; /* USB2 VBUS is always on */
status = "okay";

View File

@ -62,6 +62,7 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
power-supply = <&reg_vcc3v3>;
};
chosen {
@ -146,20 +147,6 @@
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
usb0_vbus_detect_pin: usb0-vbus-detect-pin {
pins = "PH5";
function = "gpio_in";
bias-pull-down;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
@ -211,10 +198,8 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";

View File

@ -143,7 +143,7 @@
trips {
cpu_alert0: cpu-alert0 {
/* milliCelsius */
temperature = <850000>;
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
@ -184,14 +184,34 @@
status = "disabled";
};
pmu {
compatible = "arm,cortex-a8-pmu";
interrupts = <3>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
default-pool {
compatible = "shared-dma-pool";
size = <0x6000000>;
alloc-ranges = <0x40000000 0x10000000>;
reusable;
linux,cma-default;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram-controller@1c00000 {
compatible = "allwinner,sun4i-a10-sram-controller";
system-control@1c00000 {
compatible = "allwinner,sun4i-a10-system-control";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
@ -224,6 +244,19 @@
status = "disabled";
};
};
sram_c: sram@1d00000 {
compatible = "mmio-sram";
reg = <0x01d00000 0xd0000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x01d00000 0xd0000>;
ve_sram: sram-section@0 {
compatible = "allwinner,sun4i-a10-sram-c1";
reg = <0x000000 0x80000>;
};
};
};
dma: dma-controller@1c02000 {
@ -234,7 +267,7 @@
#dma-cells = <2>;
};
nfc: nand@1c03000 {
nfc: nand-controller@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <37>;
@ -309,6 +342,7 @@
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon0-pixel-clock";
#clock-cells = <0>;
dmas = <&dma SUN4I_DMA_DEDICATED 14>;
ports {
@ -358,6 +392,7 @@
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon1-pixel-clock";
#clock-cells = <0>;
dmas = <&dma SUN4I_DMA_DEDICATED 15>;
ports {
@ -394,6 +429,17 @@
};
};
video-codec@1c0e000 {
compatible = "allwinner,sun4i-a10-video-engine";
reg = <0x01c0e000 0x1000>;
clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
<&ccu CLK_DRAM_VE>;
clock-names = "ahb", "mod", "ram";
resets = <&ccu RST_VE>;
interrupts = <53>;
allwinner,sram = <&ve_sram 1>;
};
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c0f000 0x1000>;
@ -450,13 +496,14 @@
phy-names = "usb";
extcon = <&usbphy 0>;
allwinner,sram = <&otg_sram 1>;
dr_mode = "otg";
status = "disabled";
};
usbphy: phy@1c13400 {
#phy-cells = <1>;
compatible = "allwinner,sun4i-a10-usb-phy";
reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
reg-names = "phy_ctrl", "pmu1", "pmu2";
clocks = <&ccu CLK_USB_PHY>;
clock-names = "usb_phy";
@ -530,8 +577,6 @@
};
hdmi_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
@ -579,6 +624,16 @@
status = "disabled";
};
csi1: csi@1c1d000 {
compatible = "allwinner,sun4i-a10-csi1";
reg = <0x01c1d000 0x1000>;
interrupts = <43>;
clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
clock-names = "bus", "ram";
resets = <&ccu RST_CSI1>;
status = "disabled";
};
spi3: spi@1c1f000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c1f000 0x1000>;
@ -625,6 +680,31 @@
function = "can";
};
/omit-if-no-ref/
csi1_8bits_pg_pins: csi1-8bits-pg-pins {
pins = "PG0", "PG2", "PG3", "PG4", "PG5",
"PG6", "PG7", "PG8", "PG9", "PG10",
"PG11";
function = "csi1";
};
/omit-if-no-ref/
csi1_24bits_ph_pins: csi1-24bits-ph-pins {
pins = "PH0", "PH1", "PH2", "PH3", "PH4",
"PH5", "PH6", "PH7", "PH8", "PH9",
"PH10", "PH11", "PH12", "PH13", "PH14",
"PH15", "PH16", "PH17", "PH18", "PH19",
"PH20", "PH21", "PH22", "PH23", "PH24",
"PH25", "PH26", "PH27";
function = "csi1";
};
/omit-if-no-ref/
csi1_clk_pg_pin: csi1-clk-pg-pin {
pins = "PG1";
function = "csi1";
};
emac_pins: emac0-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
@ -762,13 +842,20 @@
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
interrupts = <22>;
interrupts = <22>,
<23>,
<24>,
<25>,
<67>,
<68>;
clocks = <&osc24M>;
};
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
interrupts = <24>;
clocks = <&osc24M>;
};
rtc: rtc@1c20d00 {
@ -1001,6 +1088,27 @@
status = "disabled";
};
mali: gpu@1c40000 {
compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
reg = <0x01c40000 0x10000>;
interrupts = <69>,
<70>,
<71>,
<72>,
<73>;
interrupt-names = "gp",
"gpmmu",
"pp0",
"ppmmu0",
"pmu";
clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
clock-names = "bus", "core";
resets = <&ccu RST_GPU>;
assigned-clocks = <&ccu CLK_GPU>;
assigned-clock-rates = <384000000>;
};
fe0: display-frontend@1e00000 {
compatible = "allwinner,sun4i-a10-display-frontend";
reg = <0x01e00000 0x20000>;

View File

@ -173,7 +173,7 @@
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
};
};

View File

@ -191,7 +191,7 @@
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
};
};

View File

@ -152,7 +152,7 @@
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
};
};

View File

@ -185,7 +185,7 @@
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
};
};

View File

@ -192,7 +192,7 @@
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
};
};

View File

@ -139,7 +139,7 @@
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
};
};

View File

@ -245,7 +245,7 @@
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
};
};

View File

@ -25,6 +25,11 @@
/* Backlight configuration differs per PinePhone revision. */
};
bt_sco_codec: bt-sco-codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
};
chosen {
stdout-path = "serial0:115200n8";
};
@ -91,6 +96,8 @@
};
&codec {
pinctrl-names = "default";
pinctrl-0 = <&aif3_pins>;
status = "okay";
};
@ -296,7 +303,7 @@
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
};
};
@ -426,6 +433,7 @@
&sound {
status = "okay";
simple-audio-card,name = "PinePhone";
simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
simple-audio-card,widgets = "Microphone", "Headset Microphone",
"Microphone", "Internal Microphone",
@ -447,6 +455,23 @@
"MIC1", "Internal Microphone",
"Headset Microphone", "HBIAS",
"MIC2", "Headset Microphone";
simple-audio-card,dai-link@2 {
format = "dsp_a";
frame-master = <&link2_codec>;
bitclock-master = <&link2_codec>;
bitclock-inversion;
link2_cpu: cpu {
sound-dai = <&bt_sco_codec 0>;
};
link2_codec: codec {
sound-dai = <&codec 2>;
dai-tdm-slot-num = <1>;
dai-tdm-slot-width = <32>;
};
};
};
&uart0 {

View File

@ -266,7 +266,7 @@
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
x-powers,drive-vbus-en;
};
};

View File

@ -79,7 +79,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii-id";
phy-mode = "rgmii-txid";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <&reg_dc1sw>;
status = "okay";

View File

@ -45,7 +45,7 @@
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
};
};

View File

@ -205,7 +205,7 @@
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};

View File

@ -131,12 +131,10 @@
};
sound: sound {
#address-cells = <1>;
#size-cells = <0>;
compatible = "simple-audio-card";
simple-audio-card,name = "sun50i-a64-audio";
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&cpudai>;
simple-audio-card,bitclock-master = <&cpudai>;
simple-audio-card,mclk-fs = <128>;
simple-audio-card,aux-devs = <&codec_analog>;
simple-audio-card,routing =
"Left DAC", "DACL",
@ -145,12 +143,19 @@
"ADCR", "Right ADC";
status = "disabled";
cpudai: simple-audio-card,cpu {
sound-dai = <&dai>;
};
simple-audio-card,dai-link@0 {
format = "i2s";
frame-master = <&link0_cpu>;
bitclock-master = <&link0_cpu>;
mclk-fs = <128>;
link_codec: simple-audio-card,codec {
sound-dai = <&codec>;
link0_cpu: cpu {
sound-dai = <&dai>;
};
link0_codec: codec {
sound-dai = <&codec 0>;
};
};
};
@ -648,6 +653,7 @@
pio: pinctrl@1c20800 {
compatible = "allwinner,sun50i-a64-pinctrl";
reg = <0x01c20800 0x400>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
@ -658,6 +664,18 @@
interrupt-controller;
#interrupt-cells = <3>;
/omit-if-no-ref/
aif2_pins: aif2-pins {
pins = "PB4", "PB5", "PB6", "PB7";
function = "aif2";
};
/omit-if-no-ref/
aif3_pins: aif3-pins {
pins = "PG10", "PG11", "PG12", "PG13";
function = "aif3";
};
csi_pins: csi-pins {
pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
"PE7", "PE8", "PE9", "PE10", "PE11";
@ -798,6 +816,23 @@
};
};
timer@1c20c00 {
compatible = "allwinner,sun50i-a64-timer",
"allwinner,sun8i-a23-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
wdt0: watchdog@1c20ca0 {
compatible = "allwinner,sun50i-a64-wdt",
"allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
spdif: spdif@1c21000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-a64-spdif",
@ -818,6 +853,7 @@
compatible = "allwinner,sun50i-a64-lradc",
"allwinner,sun8i-a83t-r-lradc";
reg = <0x01c21800 0x400>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -878,7 +914,7 @@
};
codec: codec@1c22e00 {
#sound-dai-cells = <0>;
#sound-dai-cells = <1>;
compatible = "allwinner,sun50i-a64-codec",
"allwinner,sun8i-a33-codec";
reg = <0x01c22e00 0x600>;
@ -1208,6 +1244,7 @@
compatible = "allwinner,sun50i-a64-rtc",
"allwinner,sun8i-h3-rtc";
reg = <0x01f00000 0x400>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clock-output-names = "osc32k", "osc32k-out", "iosc";
@ -1219,7 +1256,7 @@
compatible = "allwinner,sun50i-a64-r-intc",
"allwinner,sun6i-a31-r-intc";
interrupt-controller;
#interrupt-cells = <2>;
#interrupt-cells = <3>;
reg = <0x01f00c00 0x400>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
@ -1279,6 +1316,7 @@
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun50i-a64-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
@ -1321,13 +1359,5 @@
#address-cells = <1>;
#size-cells = <0>;
};
wdt0: watchdog@1c20ca0 {
compatible = "allwinner,sun50i-a64-wdt",
"allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
};
};

View File

@ -75,7 +75,7 @@
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
status = "okay";
};

View File

@ -150,14 +150,30 @@
vcc-pg-supply = <&reg_aldo1>;
};
&r_i2c {
&r_ir {
linux,rc-map-name = "rc-beelink-gs1";
status = "okay";
};
&r_pio {
/*
* FIXME: We can't add that supply for now since it would
* create a circular dependency between pinctrl, the regulator
* and the RSB Bus.
*
* vcc-pl-supply = <&reg_aldo1>;
*/
vcc-pm-supply = <&reg_aldo1>;
};
&r_rsb {
status = "okay";
axp805: pmic@36 {
axp805: pmic@745 {
compatible = "x-powers,axp805", "x-powers,axp806";
reg = <0x36>;
reg = <0x745>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
x-powers,self-working-mode;
@ -273,22 +289,6 @@
};
};
&r_ir {
linux,rc-map-name = "rc-beelink-gs1";
status = "okay";
};
&r_pio {
/*
* PL0 and PL1 are used for PMIC I2C
* don't enable the pl-supply else
* it will fail at boot
*
* vcc-pl-supply = <&reg_aldo1>;
*/
vcc-pm-supply = <&reg_aldo1>;
};
&spdif {
status = "okay";
};

View File

@ -175,14 +175,18 @@
vcc-pg-supply = <&reg_vcc_wifi_io>;
};
&r_i2c {
&r_ir {
status = "okay";
};
&r_rsb {
status = "okay";
axp805: pmic@36 {
axp805: pmic@745 {
compatible = "x-powers,axp805", "x-powers,axp806";
reg = <0x36>;
reg = <0x745>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
x-powers,self-working-mode;
@ -291,10 +295,6 @@
};
};
&r_ir {
status = "okay";
};
&rtc {
clocks = <&ext_osc32k>;
};

View File

@ -112,14 +112,22 @@
vcc-pg-supply = <&reg_aldo1>;
};
&r_i2c {
&r_ir {
status = "okay";
};
&r_pio {
vcc-pm-supply = <&reg_bldo3>;
};
&r_rsb {
status = "okay";
axp805: pmic@36 {
axp805: pmic@745 {
compatible = "x-powers,axp805", "x-powers,axp806";
reg = <0x36>;
reg = <0x745>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
x-powers,self-working-mode;
@ -232,14 +240,6 @@
};
};
&r_ir {
status = "okay";
};
&r_pio {
vcc-pm-supply = <&reg_bldo3>;
};
&rtc {
clocks = <&ext_osc32k>;
};

View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (C) 2019 Corentin LABBE <clabbe@baylibre.com>
*/
#include "sun50i-h6-pine-h64.dts"
/ {
model = "Pine H64 model B";
compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6";
/delete-node/ reg_gmac_3v3;
};
&hdmi_connector {
/delete-property/ ddc-en-gpios;
};
&emac {
phy-supply = <&reg_aldo2>;
};

View File

@ -89,6 +89,10 @@
status = "okay";
};
&dwc3 {
status = "okay";
};
&ehci0 {
status = "okay";
};
@ -168,7 +172,7 @@
compatible = "x-powers,axp805", "x-powers,axp806";
reg = <0x36>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
x-powers,self-working-mode;
@ -281,7 +285,7 @@
compatible = "nxp,pcf8563";
reg = <0x51>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <0>;
};
};
@ -332,3 +336,7 @@
usb3_vbus-supply = <&reg_usb_vbus>;
status = "okay";
};
&usb3phy {
status = "okay";
};

View File

@ -32,14 +32,21 @@
};
};
reg_vcc3v3: vcc3v3 {
reg_vcc1v8: regulator-vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vcc3v3: regulator-vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_vdd_cpu_gpu: vdd-cpu-gpu {
reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu {
compatible = "regulator-fixed";
regulator-name = "vdd-cpu-gpu";
regulator-min-microvolt = <1135000>;
@ -91,6 +98,16 @@
status = "okay";
};
&mmc2 {
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc1v8>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
mmc-hs200-1_8v;
status = "okay";
};
&ohci0 {
status = "okay";
};
@ -99,6 +116,12 @@
status = "okay";
};
&pio {
vcc-pc-supply = <&reg_vcc1v8>;
vcc-pd-supply = <&reg_vcc3v3>;
vcc-pg-supply = <&reg_vcc1v8>;
};
&r_ir {
linux,rc-map-name = "rc-tanix-tx5max";
status = "okay";

View File

@ -271,6 +271,15 @@
};
};
timer@3009000 {
compatible = "allwinner,sun50i-h6-timer",
"allwinner,sun8i-a23-timer";
reg = <0x03009000 0xa0>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
watchdog: watchdog@30090a0 {
compatible = "allwinner,sun50i-h6-wdt",
"allwinner,sun6i-a31-wdt";
@ -294,6 +303,7 @@
pio: pinctrl@300b000 {
compatible = "allwinner,sun50i-h6-pinctrl";
reg = <0x0300b000 0x400>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
@ -902,6 +912,7 @@
rtc: rtc@7000000 {
compatible = "allwinner,sun50i-h6-rtc";
reg = <0x07000000 0x400>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clock-output-names = "osc32k", "osc32k-out", "iosc";
@ -927,10 +938,9 @@
};
r_intc: interrupt-controller@7021000 {
compatible = "allwinner,sun50i-h6-r-intc",
"allwinner,sun6i-a31-r-intc";
compatible = "allwinner,sun50i-h6-r-intc";
interrupt-controller;
#interrupt-cells = <2>;
#interrupt-cells = <3>;
reg = <0x07021000 0x400>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
};
@ -938,6 +948,7 @@
r_pio: pinctrl@7022000 {
compatible = "allwinner,sun50i-h6-r-pinctrl";
reg = <0x07022000 0x400>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;

View File

@ -62,7 +62,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_t003>;
red {
led {
label = "t003-tv-dongle:red:usr";
gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
default-state = "on";
@ -75,8 +75,6 @@
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp152: pmic@30 {
@ -89,8 +87,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t003>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
@ -106,13 +102,7 @@
};
&pio {
mmc0_cd_pin_t003: mmc0_cd_pin@0 {
pins = "PG1";
function = "gpio_in";
bias-pull-up;
};
led_pins_t003: led_pins@0 {
led_pins_t003: led-pin {
pins = "PB2";
function = "gpio_out";
drive-strength = <20>;
@ -131,7 +121,7 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

View File

@ -62,7 +62,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_t004>;
red {
led {
label = "t004-tv-dongle:red:usr";
gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
default-state = "on";
@ -71,8 +71,6 @@
reg_vmmc1: vmmc1 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_vcc_en_pin_t004>;
regulator-name = "vmmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -86,8 +84,6 @@
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp152: pmic@30 {
@ -100,8 +96,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
@ -109,8 +103,6 @@
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vmmc1>;
bus-width = <4>;
non-removable;
@ -127,24 +119,7 @@
};
&pio {
usb0_id_detect_pin: usb0_id_detect_pin@0 {
pins = "PG12";
function = "gpio_in";
bias-pull-up;
};
mmc0_cd_pin_t004: mmc0_cd_pin@0 {
pins = "PG1";
function = "gpio_in";
bias-pull-up;
};
mmc1_vcc_en_pin_t004: mmc1_vcc_en_pin@0 {
pins = "PB18";
function = "gpio_out";
};
led_pins_t004: led_pins@0 {
led_pins_t004: led-pin {
pins = "PB2";
function = "gpio_out";
drive-strength = <20>;
@ -158,7 +133,7 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
@ -168,9 +143,7 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

View File

@ -59,10 +59,8 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_mk802>;
red {
led {
label = "mk802:red:usr";
gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
};
@ -74,8 +72,6 @@
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp152: pmic@30 {
@ -88,8 +84,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mk802>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
@ -97,8 +91,6 @@
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
non-removable;
@ -113,33 +105,14 @@
status = "okay";
};
&pio {
led_pins_mk802: led_pins@0 {
pins = "PB2";
function = "gpio_out";
};
mmc0_cd_pin_mk802: mmc0_cd_pin@0 {
pins = "PG1";
function = "gpio_in";
bias-pull-up;
};
usb1_vbus_pin_mk802: usb1_vbus_pin@0 {
pins = "PB10";
function = "gpio_out";
};
};
&reg_usb1_vbus {
pinctrl-0 = <&usb1_vbus_pin_mk802>;
gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

View File

@ -79,7 +79,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_olinuxino>;
green {
led {
label = "a10s-olinuxino-micro:green:usr";
gpios = <&pio 4 3 GPIO_ACTIVE_HIGH>;
default-state = "on";
@ -97,8 +97,8 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_pins_b>;
phy = <&phy1>;
pinctrl-0 = <&emac_pa_pins>;
phy-handle = <&phy1>;
status = "okay";
};
@ -117,8 +117,6 @@
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp152: pmic@30 {
@ -130,11 +128,9 @@
#include "axp152.dtsi"
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
at24@50 {
eeprom@50 {
compatible = "atmel,24c16";
pagesize = <16>;
reg = <0x50>;
@ -143,8 +139,6 @@
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
@ -152,35 +146,35 @@
vref-supply = <&reg_vcc3v0>;
status = "okay";
button@191 {
button-191 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <191274>;
};
button@392 {
button-392 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <392644>;
};
button@601 {
button-601 {
label = "Menu";
linux,code = <KEY_MENU>;
channel = <0>;
voltage = <601151>;
};
button@795 {
button-795 {
label = "Enter";
linux,code = <KEY_ENTER>;
channel = <0>;
voltage = <795090>;
};
button@987 {
button-987 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;
@ -197,8 +191,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
@ -206,8 +198,6 @@
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */
@ -223,34 +213,11 @@
};
&pio {
mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 {
pins = "PG1";
function = "gpio_in";
bias-pull-up;
};
mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 {
pins = "PG13";
function = "gpio_in";
bias-pull-up;
};
led_pins_olinuxino: led_pins@0 {
led_pins_olinuxino: led-pin {
pins = "PE3";
function = "gpio_out";
drive-strength = <20>;
};
usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 {
pins = "PB10";
function = "gpio_out";
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
pins = "PG12";
function = "gpio_in";
bias-pull-up;
};
};
&reg_usb0_vbus {
@ -259,15 +226,14 @@
};
&reg_usb1_vbus {
pinctrl-0 = <&usb1_vbus_pin_olinuxino_m>;
gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_b>,
<&spi2_cs0_pins_b>;
pinctrl-0 = <&spi2_pb_pins>,
<&spi2_cs0_pb_pin>;
status = "okay";
};
@ -277,19 +243,19 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins_b>;
pinctrl-0 = <&uart2_pc_pins>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_a>;
pinctrl-0 = <&uart3_pg_pins>;
status = "okay";
};
@ -299,9 +265,7 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";

View File

@ -63,7 +63,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_r7>;
green {
led {
label = "r7-tv-dongle:green:usr";
gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
@ -76,8 +76,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
@ -85,8 +83,6 @@
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
non-removable;
@ -98,33 +94,21 @@
};
&pio {
mmc0_cd_pin_r7: mmc0_cd_pin@0 {
pins = "PG1";
function = "gpio_in";
bias-pull-up;
};
led_pins_r7: led_pins@0 {
led_pins_r7: led-pin {
pins = "PB2";
function = "gpio_out";
drive-strength = <20>;
};
usb1_vbus_pin_r7: usb1_vbus_pin@0 {
pins = "PG13";
function = "gpio_out";
};
};
&reg_usb1_vbus {
pinctrl-0 = <&usb1_vbus_pin_r7>;
gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

View File

@ -61,10 +61,8 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_wobo_i5>;
blue {
led {
label = "a10s-wobo-i5:blue:usr";
gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
@ -73,8 +71,6 @@
reg_emac_3v3: emac-3v3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&emac_power_pin_wobo>;
regulator-name = "emac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -94,8 +90,8 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_pins_a>;
phy = <&phy1>;
pinctrl-0 = <&emac_pd_pins>;
phy-handle = <&phy1>;
status = "okay";
};
@ -104,8 +100,6 @@
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
@ -126,8 +120,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_wobo_i5>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */
@ -142,24 +134,6 @@
status = "okay";
};
&pio {
led_pins_wobo_i5: led_pins@0 {
pins = "PB2";
function = "gpio_out";
};
mmc0_cd_pin_wobo_i5: mmc0_cd_pin@0 {
pins = "PB3";
function = "gpio_in";
bias-pull-up;
};
emac_power_pin_wobo: emac_power_pin@0 {
pins = "PA02";
function = "gpio_out";
};
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
@ -206,7 +180,7 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

View File

@ -42,15 +42,11 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "skeleton.dtsi"
#include "sun5i.dtsi"
#include <dt-bindings/dma/sun4i-a10.h>
/ {
interrupt-parent = <&intc>;
aliases {
ethernet0 = &emac;
};
@ -60,7 +56,7 @@
#size-cells = <1>;
ranges;
framebuffer@2 {
framebuffer-lcd0-hdmi {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
@ -76,7 +72,7 @@
allwinner,pipelines = <&fe0>;
};
soc@1c00000 {
soc {
hdmi: hdmi@1c16000 {
compatible = "allwinner,sun5i-a10s-hdmi";
reg = <0x01c16000 0x1000>;
@ -104,8 +100,6 @@
};
hdmi_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
@ -125,20 +119,25 @@
compatible = "allwinner,sun5i-a10s-ccu";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
};
&pio {
compatible = "allwinner,sun5i-a10s-pinctrl";
uart0_pins_a: uart0@0 {
uart0_pb_pins: uart0-pb-pins {
pins = "PB19", "PB20";
function = "uart0";
};
uart2_pins_b: uart2@1 {
uart2_pc_pins: uart2-pc-pins {
pins = "PC18", "PC19";
function = "uart2";
};
emac_pins_b: emac0@1 {
emac_pa_pins: emac-pa-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
"PA7", "PA8", "PA9", "PA10",
@ -147,27 +146,24 @@
function = "emac";
};
mmc1_pins_a: mmc1@0 {
mmc1_pins: mmc1-pins {
pins = "PG3", "PG4", "PG5",
"PG6", "PG7", "PG8";
function = "mmc1";
drive-strength = <30>;
};
spi2_pins_b: spi2@1 {
spi2_pb_pins: spi2-pb-pins {
pins = "PB12", "PB13", "PB14";
function = "spi2";
};
spi2_cs0_pins_b: spi2_cs0@1 {
spi2_cs0_pb_pin: spi2-cs0-pb-pin {
pins = "PB11";
function = "spi2";
};
};
&sram_a {
};
&tcon0_out {
tcon0_out_hdmi: endpoint@2 {
reg = <2>;

View File

@ -26,3 +26,7 @@
pinctrl-0 = <&uart1_pins_b>;
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
};

View File

@ -61,6 +61,7 @@
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
power-supply = <&reg_vcc3v3>;
/* TODO: backlight uses axp gpio1 as enable pin */
};
@ -78,8 +79,6 @@
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
@ -91,8 +90,6 @@
#include "axp209.dtsi"
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
pcf8563: rtc@51 {
@ -105,14 +102,14 @@
vref-supply = <&reg_ldo2>;
status = "okay";
button@200 {
button-200 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <200000>;
};
button@400 {
button-400 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
@ -121,8 +118,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
@ -133,29 +128,9 @@
status = "okay";
};
&pio {
mmc0_cd_pin_d709: mmc0_cd_pin@0 {
pins = "PG0";
function = "gpio_in";
bias-pull-up;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
pins = "PG1";
function = "gpio_in";
bias-pull-down;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
pins = "PG2";
function = "gpio_in";
bias-pull-up;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pins>;
pinctrl-0 = <&pwm0_pin>;
status = "okay";
};
@ -197,7 +172,7 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>;
pinctrl-0 = <&uart1_pg_pins>;
status = "okay";
};
@ -207,10 +182,8 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_ldo3>;
status = "okay";

View File

@ -69,8 +69,6 @@
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
@ -80,8 +78,6 @@
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
pcf8563: rtc@51 {
@ -91,8 +87,6 @@
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
@ -100,14 +94,14 @@
vref-supply = <&reg_ldo2>;
status = "okay";
button@200 {
button-200 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <200000>;
};
button@400 {
button-400 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
@ -116,8 +110,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
@ -132,25 +124,6 @@
status = "okay";
};
&pio {
mmc0_cd_pin_h702: mmc0_cd_pin@0 {
pins = "PG0";
function = "gpio_in";
bias-pull-up;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
pins = "PG2";
function = "gpio_in";
bias-pull-up;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
pins = "PG1";
function = "gpio_in";
};
};
#include "axp209.dtsi"
&reg_dcdc2 {
@ -191,7 +164,7 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>;
pinctrl-0 = <&uart1_pg_pins>;
status = "okay";
};
@ -201,9 +174,7 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_ldo3>;

View File

@ -64,7 +64,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_olinuxinom>;
power {
led {
label = "a13-olinuxino-micro:green:power";
gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>;
default-state = "on";
@ -77,26 +77,18 @@
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
@ -112,56 +104,26 @@
};
&pio {
mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 {
pins = "PG0";
function = "gpio_in";
bias-pull-up;
};
led_pins_olinuxinom: led_pins@0 {
led_pins_olinuxinom: led-pin {
pins = "PG9";
function = "gpio_out";
drive-strength = <20>;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
pins = "PG2";
function = "gpio_in";
bias-pull-up;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
pins = "PG1";
function = "gpio_in";
bias-pull-down;
};
usb0_vbus_pin_olinuxinom: usb0_vbus_pin@0 {
pins = "PG12";
function = "gpio_out";
};
usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 {
pins = "PG11";
function = "gpio_out";
};
};
&reg_usb0_vbus {
pinctrl-0 = <&usb0_vbus_pin_olinuxinom>;
gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&reg_usb1_vbus {
pinctrl-0 = <&usb1_vbus_pin_olinuxinom>;
gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>;
pinctrl-0 = <&uart1_pg_pins>;
status = "okay";
};
@ -171,10 +133,8 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";

View File

@ -66,7 +66,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_olinuxino>;
power {
led {
gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
@ -74,8 +74,6 @@
bridge {
compatible = "dumb-vga-dac";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
@ -123,8 +121,6 @@
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
@ -138,14 +134,10 @@
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
@ -153,35 +145,35 @@
vref-supply = <&reg_vcc3v0>;
status = "okay";
button@191 {
button-191 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <191274>;
};
button@392 {
button-392 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <392644>;
};
button@601 {
button-601 {
label = "Menu";
linux,code = <KEY_MENU>;
channel = <0>;
voltage = <601151>;
};
button@795 {
button-795 {
label = "Enter";
linux,code = <KEY_ENTER>;
channel = <0>;
voltage = <795090>;
};
button@987 {
button-987 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;
@ -190,8 +182,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
@ -207,34 +197,11 @@
};
&pio {
mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
pins = "PG0";
function = "gpio_in";
bias-pull-up;
};
led_pins_olinuxino: led_pins@0 {
led_pins_olinuxino: led-pin {
pins = "PG9";
function = "gpio_out";
drive-strength = <20>;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
pins = "PG2";
function = "gpio_in";
bias-pull-up;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
pins = "PG1";
function = "gpio_in";
bias-pull-down;
};
usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 {
pins = "PG11";
function = "gpio_out";
};
};
&reg_usb0_vbus {
@ -243,7 +210,6 @@
};
&reg_usb1_vbus {
pinctrl-0 = <&usb1_vbus_pin_olinuxino>;
gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
status = "okay";
};
@ -263,7 +229,7 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>;
pinctrl-0 = <&uart1_pg_pins>;
status = "okay";
};
@ -273,10 +239,8 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";

View File

@ -49,19 +49,13 @@
compatible = "allwinner,q8-a13", "allwinner,sun5i-a13";
panel: panel {
compatible = "urt,umsh-8596md-t", "simple-panel";
#address-cells = <1>;
#size-cells = <0>;
compatible = "bananapi,s070wv20-ct16";
power-supply = <&reg_vcc3v3>;
enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */
backlight = <&backlight>;
port@0 {
reg = <0>;
/* TODO: lcd panel uses axp gpio0 as enable pin */
backlight = <&backlight>;
#address-cells = <1>;
#size-cells = <0>;
panel_input: endpoint@0 {
reg = <0>;
port {
panel_input: endpoint {
remote-endpoint = <&tcon0_out_lcd>;
};
};

View File

@ -58,13 +58,11 @@
/delete-property/stdout-path;
};
i2c_lcd: i2c@0 {
i2c_lcd: i2c {
/* The lcd panel i2c interface is hooked up via gpios */
compatible = "i2c-gpio";
pinctrl-names = "default";
pinctrl-0 = <&i2c_lcd_pins>;
gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>, /* PG12, sda */
<&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10, scl */
sda-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */
scl-gpios = <&pio 6 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG10 */
i2c-gpio,delay-us = <5>;
};
};
@ -79,13 +77,9 @@
allwinner,pa-gpios = <&pio 6 3 GPIO_ACTIVE_HIGH>; /* PG3 */
};
&codec_pa_pin {
pins = "PG3";
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_a>;
pinctrl-0 = <&mmc2_8bit_pins>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <8>;
non-removable;
@ -98,14 +92,6 @@
};
};
&pio {
i2c_lcd_pins: i2c_lcd_pin@0 {
pins = "PG10", "PG12";
function = "gpio_out";
bias-pull-up;
};
};
&reg_usb0_vbus {
gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
};
@ -128,7 +114,3 @@
/* The P66 uses the uart pins as gpios */
status = "disabled";
};
&usb0_vbus_pin_a {
pins = "PB4";
};

View File

@ -42,17 +42,13 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "skeleton.dtsi"
#include "sun5i.dtsi"
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
thermal-zones {
cpu_thermal {
cpu-thermal {
/* milliseconds */
polling-delay-passive = <250>;
polling-delay = <1000>;
@ -88,7 +84,7 @@
allwinner,pipelines = <&fe0>;
};
soc@1c00000 {
soc {
pwm: pwm@1c20e00 {
compatible = "allwinner,sun5i-a13-pwm";
reg = <0x01c20e00 0xc>;

View File

@ -79,8 +79,6 @@
mmc0_pwrseq: mmc0_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wifi_reg_on_pin_chip_pro>;
reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */
};
};
@ -94,8 +92,6 @@
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
@ -114,20 +110,16 @@
#include "axp209.dtsi"
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "disabled";
};
&i2s0 {
pinctrl-names = "default";
pinctrl-0 = <&i2s0_mclk_pins_a>, <&i2s0_data_pins_a>;
pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>;
status = "disabled";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&mmc0_pwrseq>;
bus-width = <4>;
@ -137,12 +129,10 @@
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
status = "okay";
nand@0 {
#address-cells = <2>;
#size-cells = <2>;
reg = <0>;
allwinner,rb = <0>;
nand-ecc-mode = "hw";
@ -157,21 +147,9 @@
status = "okay";
};
&pio {
usb0_id_pin_chip_pro: usb0-id-pin@0 {
pins = "PG2";
function = "gpio_in";
};
wifi_reg_on_pin_chip_pro: wifi-reg-on-pin@0 {
pins = "PB10";
function = "gpio_out";
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
pinctrl-0 = <&pwm0_pin>, <&pwm1_pins>;
status = "disabled";
};
@ -220,19 +198,19 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>;
pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins_a>, <&uart2_cts_rts_pins_a>;
pinctrl-0 = <&uart2_pd_pins>, <&uart2_cts_rts_pd_pins>;
status = "disabled";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_a>, <&uart3_cts_rts_pins_a>;
pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>;
status = "okay";
};
@ -253,9 +231,7 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_pin_chip_pro>;
usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb1_vbus-supply = <&reg_vcc5v0>;
status = "okay";

View File

@ -54,7 +54,7 @@
allwinner,pipelines = <&fe0>;
};
soc@1c00000 {
soc {
pwm: pwm@1c20e00 {
compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>;
@ -98,28 +98,28 @@
&pio {
compatible = "nextthing,gr8-pinctrl";
i2s0_data_pins_a: i2s0-data@0 {
i2s0_data_pins: i2s0-data-pins {
pins = "PB6", "PB7", "PB8", "PB9";
function = "i2s0";
};
i2s0_mclk_pins_a: i2s0-mclk@0 {
i2s0_mclk_pin: i2s0-mclk-pin {
pins = "PB5";
function = "i2s0";
};
pwm1_pins: pwm1 {
pwm1_pins: pwm1-pin {
pins = "PG13";
function = "pwm1";
};
spdif_tx_pins_a: spdif@0 {
spdif_tx_pin: spdif-tx-pin {
pins = "PB10";
function = "spdif";
bias-pull-up;
};
uart1_cts_rts_pins_a: uart1-cts-rts@0 {
uart1_cts_rts_pins: uart1-cts-rts-pins {
pins = "PG5", "PG6";
function = "uart1";
};

View File

@ -79,16 +79,12 @@
mmc0_pwrseq: mmc0_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&chip_wifi_reg_on_pin>;
reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */
};
onewire {
compatible = "w1-gpio";
gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
pinctrl-names = "default";
pinctrl-0 = <&chip_w1_pin>;
gpios = <&pio 3 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD2 */
};
};
@ -109,8 +105,6 @@
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
@ -137,14 +131,10 @@
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "disabled";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
xio: gpio@38 {
@ -161,13 +151,11 @@
};
};
&mmc0_pins_a {
&mmc0_pins {
bias-pull-up;
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&mmc0_pwrseq>;
bus-width = <4>;
@ -183,29 +171,6 @@
status = "okay";
};
&pio {
chip_vbus_pin: chip_vbus_pin@0 {
pins = "PB10";
function = "gpio_out";
};
chip_wifi_reg_on_pin: chip_wifi_reg_on_pin@0 {
pins = "PC19";
function = "gpio_out";
};
chip_id_det_pin: chip_id_det_pin@0 {
pins = "PG2";
function = "gpio_in";
};
chip_w1_pin: chip_w1_pin@0 {
pins = "PD2";
function = "gpio_in";
bias-pull-up;
};
};
&reg_dcdc2 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
@ -260,7 +225,6 @@
};
&reg_usb0_vbus {
pinctrl-0 = <&chip_vbus_pin>;
vin-supply = <&reg_vcc5v0>;
gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
status = "okay";
@ -268,7 +232,7 @@
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>;
pinctrl-0 = <&spi2_pe_pins>;
status = "disabled";
};
@ -282,14 +246,14 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>;
pinctrl-0 = <&uart1_pg_pins>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_a>,
<&uart3_cts_rts_pins_a>;
pinctrl-0 = <&uart3_pg_pins>,
<&uart3_cts_rts_pg_pins>;
status = "okay";
};
@ -303,11 +267,9 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&chip_id_det_pin>;
status = "okay";
usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_vcc5v0>;

View File

@ -54,7 +54,8 @@
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
/* TODO: backlight uses axp gpio1 as enable pin */
enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; /* AXP GPIO1 */
power-supply = <&reg_vcc3v0>;
};
chosen {
@ -63,8 +64,6 @@
};
&codec {
pinctrl-names = "default";
pinctrl-0 = <&codec_pa_pin>;
allwinner,pa-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */
status = "okay";
};
@ -92,11 +91,10 @@
*/
clock-frequency = <400000>;
touchscreen: touchscreen {
touchscreen: touchscreen@40 {
reg = <0x40>;
interrupt-parent = <&pio>;
interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */
pinctrl-names = "default";
pinctrl-0 = <&ts_power_pin>;
power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
/* Tablet dts must provide reg and compatible */
status = "disabled";
@ -124,7 +122,7 @@
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;
cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
@ -135,43 +133,6 @@
status = "okay";
};
&pio {
codec_pa_pin: codec_pa_pin@0 {
pins = "PG10";
function = "gpio_out";
};
mmc0_cd_pin: mmc0_cd_pin@0 {
pins = "PG0";
function = "gpio_in";
bias-pull-up;
};
ts_power_pin: ts_power_pin {
pins = "PB3";
function = "gpio_out";
drive-strength = <10>;
bias-disable;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
pins = "PG1";
function = "gpio_in";
bias-pull-down;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
pins = "PG2";
function = "gpio_in";
bias-pull-up;
};
usb0_vbus_pin_a: usb0_vbus_pin@0 {
pins = "PG12";
function = "gpio_out";
};
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
@ -210,7 +171,7 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>;
pinctrl-0 = <&uart1_pg_pins>;
status = "okay";
};
@ -224,10 +185,8 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_ldo3>;

View File

@ -42,14 +42,14 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/sun5i-ccu.h>
#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/reset/sun5i-ccu.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
@ -68,7 +68,7 @@
#size-cells = <1>;
ranges;
framebuffer@0 {
framebuffer-lcd0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
@ -77,7 +77,7 @@
status = "disabled";
};
framebuffer@1 {
framebuffer-lcd0-tve0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
@ -93,14 +93,14 @@
#size-cells = <1>;
ranges;
osc24M: clk@1c20050 {
osc24M: clk-24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
osc32k: clk@0 {
osc32k: clk-32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
@ -108,14 +108,30 @@
};
};
soc@1c00000 {
compatible = "simple-bus";
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram-controller@1c00000 {
compatible = "allwinner,sun4i-a10-sram-controller";
/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
default-pool {
compatible = "shared-dma-pool";
size = <0x6000000>;
alloc-ranges = <0x40000000 0x10000000>;
reusable;
linux,cma-default;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
dma-ranges;
ranges;
system-control@1c00000 {
compatible = "allwinner,sun5i-a13-system-control";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
@ -127,12 +143,13 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00000000 0xc000>;
};
emac_sram: sram-section@8000 {
compatible = "allwinner,sun4i-a10-sram-a3-a4";
reg = <0x8000 0x4000>;
status = "disabled";
emac_sram: sram-section@8000 {
compatible = "allwinner,sun5i-a13-sram-a3-a4",
"allwinner,sun4i-a10-sram-a3-a4";
reg = <0x8000 0x4000>;
status = "disabled";
};
};
sram_d: sram@10000 {
@ -143,11 +160,36 @@
ranges = <0 0x00010000 0x1000>;
otg_sram: sram-section@0 {
compatible = "allwinner,sun4i-a10-sram-d";
compatible = "allwinner,sun5i-a13-sram-d",
"allwinner,sun4i-a10-sram-d";
reg = <0x0000 0x1000>;
status = "disabled";
};
};
sram_c: sram@1d00000 {
compatible = "mmio-sram";
reg = <0x01d00000 0xd0000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x01d00000 0xd0000>;
ve_sram: sram-section@0 {
compatible = "allwinner,sun5i-a13-sram-c1",
"allwinner,sun4i-a10-sram-c1";
reg = <0x000000 0x80000>;
};
};
};
mbus: dram-controller@1c01000 {
compatible = "allwinner,sun5i-a13-mbus";
reg = <0x01c01000 0x1000>;
clocks = <&ccu CLK_MBUS>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x00000000 0x40000000 0x20000000>;
#interconnect-cells = <1>;
};
dma: dma-controller@1c02000 {
@ -158,7 +200,7 @@
#dma-cells = <2>;
};
nfc: nand@1c03000 {
nfc: nand-controller@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <37>;
@ -207,11 +249,8 @@
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
tve0_in_tcon0: endpoint@0 {
reg = <0>;
tve0_in_tcon0: endpoint {
remote-endpoint = <&tcon0_out_tve0>;
};
};
@ -238,6 +277,7 @@
compatible = "allwinner,sun5i-a13-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <44>;
dmas = <&dma SUN4I_DMA_DEDICATED 14>;
resets = <&ccu RST_LCD>;
reset-names = "lcd";
clocks = <&ccu CLK_AHB_LCD>,
@ -247,6 +287,7 @@
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon-pixel-clock";
#clock-cells = <0>;
status = "disabled";
ports {
@ -254,12 +295,9 @@
#size-cells = <0>;
tcon0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tcon0_in_be0: endpoint@0 {
reg = <0>;
tcon0_in_be0: endpoint {
remote-endpoint = <&be0_out_tcon0>;
};
};
@ -278,12 +316,25 @@
};
};
video-codec@1c0e000 {
compatible = "allwinner,sun5i-a13-video-engine";
reg = <0x01c0e000 0x1000>;
clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
<&ccu CLK_DRAM_VE>;
clock-names = "ahb", "mod", "ram";
resets = <&ccu RST_VE>;
interrupts = <53>;
allwinner,sram = <&ve_sram 1>;
};
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
clock-names = "ahb", "mmc";
interrupts = <32>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -321,13 +372,14 @@
phy-names = "usb";
extcon = <&usbphy 0>;
allwinner,sram = <&otg_sram 1>;
dr_mode = "otg";
status = "disabled";
};
usbphy: phy@1c13400 {
#phy-cells = <1>;
compatible = "allwinner,sun5i-a13-usb-phy";
reg = <0x01c13400 0x10 0x01c14800 0x4>;
reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
reg-names = "phy_ctrl", "pmu1";
clocks = <&ccu CLK_USB_PHY0>;
clock-names = "usb_phy";
@ -404,7 +456,7 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
emac_pins_a: emac0@0 {
emac_pd_pins: emac-pd-pins {
pins = "PD6", "PD7", "PD10",
"PD11", "PD12", "PD13", "PD14",
"PD15", "PD18", "PD19", "PD20",
@ -413,27 +465,27 @@
function = "emac";
};
i2c0_pins_a: i2c0@0 {
i2c0_pins: i2c0-pins {
pins = "PB0", "PB1";
function = "i2c0";
};
i2c1_pins_a: i2c1@0 {
i2c1_pins: i2c1-pins {
pins = "PB15", "PB16";
function = "i2c1";
};
i2c2_pins_a: i2c2@0 {
i2c2_pins: i2c2-pins {
pins = "PB17", "PB18";
function = "i2c2";
};
ir0_rx_pins_a: ir0@0 {
ir0_rx_pin: ir0-rx-pin {
pins = "PB4";
function = "ir0";
};
lcd_rgb565_pins: lcd_rgb565@0 {
lcd_rgb565_pins: lcd-rgb565-pins {
pins = "PD3", "PD4", "PD5", "PD6", "PD7",
"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
"PD19", "PD20", "PD21", "PD22", "PD23",
@ -441,7 +493,7 @@
function = "lcd0";
};
lcd_rgb666_pins: lcd_rgb666@0 {
lcd_rgb666_pins: lcd-rgb666-pins {
pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
@ -449,7 +501,7 @@
function = "lcd0";
};
mmc0_pins_a: mmc0@0 {
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
function = "mmc0";
@ -457,7 +509,15 @@
bias-pull-up;
};
mmc2_pins_a: mmc2@0 {
mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11";
function = "mmc2";
drive-strength = <30>;
bias-pull-up;
};
mmc2_8bit_pins: mmc2-8bit-pins {
pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12", "PC13",
"PC14", "PC15";
@ -466,15 +526,7 @@
bias-pull-up;
};
mmc2_4bit_pins_a: mmc2-4bit@0 {
pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11";
function = "mmc2";
drive-strength = <30>;
bias-pull-up;
};
nand_pins_a: nand-base0@0 {
nand_pins: nand-pins {
pins = "PC0", "PC1", "PC2",
"PC5", "PC8", "PC9", "PC10",
"PC11", "PC12", "PC13", "PC14",
@ -482,72 +534,79 @@
function = "nand0";
};
nand_cs0_pins_a: nand-cs@0 {
nand_cs0_pin: nand-cs0-pin {
pins = "PC4";
function = "nand0";
};
nand_rb0_pins_a: nand-rb@0 {
nand_rb0_pin: nand-rb0-pin {
pins = "PC6";
function = "nand0";
};
spi2_pins_a: spi2@0 {
pwm0_pin: pwm0-pin {
pins = "PB2";
function = "pwm";
};
spi2_pe_pins: spi2-pe-pins {
pins = "PE1", "PE2", "PE3";
function = "spi2";
};
spi2_cs0_pins_a: spi2-cs0@0 {
spi2_cs0_pe_pin: spi2-cs0-pe-pin {
pins = "PE0";
function = "spi2";
};
uart1_pins_a: uart1@0 {
uart1_pe_pins: uart1-pe-pins {
pins = "PE10", "PE11";
function = "uart1";
};
uart1_pins_b: uart1@1 {
uart1_pg_pins: uart1-pg-pins {
pins = "PG3", "PG4";
function = "uart1";
};
uart2_pins_a: uart2@0 {
uart2_pd_pins: uart2-pd-pins {
pins = "PD2", "PD3";
function = "uart2";
};
uart2_cts_rts_pins_a: uart2-cts-rts@0 {
uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins {
pins = "PD4", "PD5";
function = "uart2";
};
uart3_pins_a: uart3@0 {
uart3_pg_pins: uart3-pg-pins {
pins = "PG9", "PG10";
function = "uart3";
};
uart3_cts_rts_pins_a: uart3-cts-rts@0 {
uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
pins = "PG11", "PG12";
function = "uart3";
};
pwm0_pins: pwm0 {
pins = "PB2";
function = "pwm";
};
};
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
interrupts = <22>;
interrupts = <22>,
<23>,
<24>,
<25>,
<67>,
<68>;
clocks = <&ccu CLK_HOSC>;
};
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
interrupts = <24>;
clocks = <&osc24M>;
};
ir0: ir@1c21800 {
@ -636,6 +695,8 @@
reg = <0x01c2ac00 0x400>;
interrupts = <7>;
clocks = <&ccu CLK_APB1_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -646,6 +707,8 @@
reg = <0x01c2b000 0x400>;
interrupts = <8>;
clocks = <&ccu CLK_APB1_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -656,11 +719,25 @@
reg = <0x01c2b400 0x400>;
interrupts = <9>;
clocks = <&ccu CLK_APB1_I2C2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mali: gpu@1c40000 {
compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
reg = <0x01c40000 0x10000>;
interrupts = <69>, <70>, <71>, <72>, <73>;
interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pmu";
clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
clock-names = "bus", "core";
resets = <&ccu RST_GPU>;
assigned-clocks = <&ccu CLK_GPU>;
assigned-clock-rates = <320000000>;
};
timer@1c60000 {
compatible = "allwinner,sun5i-a13-hstimer";
reg = <0x01c60000 0x1000>;
@ -677,6 +754,8 @@
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_DE_FE>;
interconnects = <&mbus 19>;
interconnect-names = "dma-mem";
status = "disabled";
ports {
@ -684,12 +763,9 @@
#size-cells = <0>;
fe0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
fe0_out_be0: endpoint@0 {
reg = <0>;
fe0_out_be0: endpoint {
remote-endpoint = <&be0_in_fe0>;
};
};
@ -705,33 +781,26 @@
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_DE_BE>;
interconnects = <&mbus 18>;
interconnect-names = "dma-mem";
status = "disabled";
assigned-clocks = <&ccu CLK_DE_BE>;
assigned-clock-rates = <300000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
be0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
be0_in_fe0: endpoint@0 {
reg = <0>;
be0_in_fe0: endpoint {
remote-endpoint = <&fe0_out_be0>;
};
};
be0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
be0_out_tcon0: endpoint@0 {
reg = <0>;
be0_out_tcon0: endpoint {
remote-endpoint = <&tcon0_in_be0>;
};
};

View File

@ -65,22 +65,14 @@
status = "okay";
};
&pio {
usb1_vbus_pin_a: usb1_vbus_pin@0 {
pins = "PH27";
function = "gpio_out";
};
};
&reg_usb1_vbus {
pinctrl-0 = <&usb1_vbus_pin_a>;
gpio = <&pio 7 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

View File

@ -60,13 +60,11 @@
stdout-path = "serial0:115200n8";
};
i2c_lcd: i2c@0 {
i2c_lcd: i2c {
/* The lcd panel i2c interface is hooked up via gpios */
compatible = "i2c-gpio";
pinctrl-names = "default";
pinctrl-0 = <&i2c_lcd_pins>;
gpios = <&pio 0 23 GPIO_ACTIVE_HIGH>, /* PA23, sda */
<&pio 0 24 GPIO_ACTIVE_HIGH>; /* PA24, scl */
sda-gpios = <&pio 0 23 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA23 */
scl-gpios = <&pio 0 24 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA24 */
i2c-gpio,delay-us = <5>;
};
};
@ -77,31 +75,21 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins_rgmii_a>;
phy = <&phy1>;
pinctrl-0 = <&gmac_rgmii_pins>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "fail";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
mma8452: mma8452@1d {
@ -112,48 +100,27 @@
};
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>;
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;
cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
&mmc0_pins_a {
bias-pull-up;
};
&pio {
mmc0_cd_pin_colombus: mmc0_cd_pin@0 {
pins = "PA8";
function = "gpio_in";
bias-pull-up;
};
usb2_vbus_pin_colombus: usb2_vbus_pin@0 {
pins = "PH24";
function = "gpio_out";
};
i2c_lcd_pins: i2c_lcd_pin@0 {
pins = "PA23", "PA24";
function = "gpio_out";
bias-pull-up;
};
};
&reg_usb2_vbus {
pinctrl-names = "default";
pinctrl-0 = <&usb2_vbus_pin_colombus>;
gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

View File

@ -86,31 +86,23 @@
vga-dac {
compatible = "dumb-vga-dac";
vdd-supply = <&reg_vga_3v3>;
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
vga_dac_in: endpoint@0 {
reg = <0>;
vga_dac_in: endpoint {
remote-endpoint = <&tcon0_out_vga>;
};
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vga_dac_out: endpoint@0 {
reg = <0>;
vga_dac_out: endpoint {
remote-endpoint = <&vga_con_in>;
};
};
@ -160,17 +152,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_hummingbird>;
phy = <&phy1>;
phy-mode = "rgmii";
snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
pinctrl-0 = <&gmac_rgmii_pins>;
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -184,21 +169,15 @@
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
/* pull-ups and devices require AXP221 DLDO3 */
status = "failed";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
pcf8563: rtc@51 {
@ -209,27 +188,27 @@
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
pinctrl-0 = <&s_ir_rx_pin>;
status = "okay";
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
&mmc0_pins_a {
/* external pull-ups missing for some pins */
bias-pull-up;
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>, <&wifi_reset_pin_hummingbird>;
vmmc-supply = <&reg_aldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
@ -241,32 +220,14 @@
status = "okay";
};
&pio {
gmac_phy_reset_pin_hummingbird: gmac_phy_reset_pin@0 {
pins = "PA21";
function = "gpio_out";
};
mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 {
pins = "PA8";
function = "gpio_in";
bias-pull-up;
};
wifi_reset_pin_hummingbird: wifi_reset_pin@0 {
pins = "PG10";
function = "gpio_out";
};
};
&p2wi {
status = "okay";
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
x-powers,drive-vbus-en;
};
};
@ -354,7 +315,7 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
@ -368,8 +329,8 @@
};
&usbphy {
usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
usb0_vbus_det-gpio = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */
usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
usb0_vbus_det-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <&reg_drivevbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;

View File

@ -71,10 +71,8 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_i7>;
blue {
led {
label = "i7:blue:usr";
gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>;
};
@ -118,14 +116,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins_mii_a>;
phy = <&phy1>;
pinctrl-0 = <&gmac_mii_pins>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -140,48 +134,31 @@
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
pinctrl-0 = <&s_ir_rx_pin>;
status = "okay";
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_i7>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
status = "okay";
};
&pio {
led_pins_i7: led_pins@0 {
pins = "PH13";
function = "gpio_out";
};
mmc0_cd_pin_i7: mmc0_cd_pin@0 {
pins = "PH22";
function = "gpio_in";
bias-pull-up;
};
usb1_vbus_pin_i7: usb1_vbus_pin@0 {
pins = "PC27";
function = "gpio_out";
};
};
&reg_usb1_vbus {
pinctrl-names = "default";
pinctrl-0 = <&usb1_vbus_pin_i7>;
gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&spdif_pins_a>;
spdif-out = "okay";
pinctrl-0 = <&spdif_tx_pin>;
status = "okay";
};
@ -191,7 +168,7 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

View File

@ -60,10 +60,8 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_m9>;
blue {
led {
label = "m9:blue:pwr";
gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>;
default-state = "on";
@ -85,26 +83,26 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins_mii_a>;
phy = <&phy1>;
pinctrl-0 = <&gmac_mii_pins>;
phy-handle = <&phy1>;
phy-mode = "mii";
phy-supply = <&reg_dldo1>;
status = "okay";
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&s_ir_rx_pin>;
status = "okay";
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
@ -117,31 +115,13 @@
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
};
};
#include "axp22x.dtsi"
&pio {
led_pins_m9: led_pins@0 {
pins = "PH13";
function = "gpio_out";
};
mmc0_cd_pin_m9: mmc0_cd_pin@0 {
pins = "PH22";
function = "gpio_in";
bias-pull-up;
};
usb1_vbus_pin_m9: usb1_vbus_pin@0 {
pins = "PC27";
function = "gpio_out";
};
};
&reg_aldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -215,15 +195,13 @@
};
&reg_usb1_vbus {
pinctrl-names = "default";
pinctrl-0 = <&usb1_vbus_pin_m9>;
gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

View File

@ -60,10 +60,8 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_m9>;
blue {
led {
label = "a1000g:blue:pwr";
gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>;
default-state = "on";
@ -85,26 +83,26 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins_mii_a>;
phy = <&phy1>;
pinctrl-0 = <&gmac_mii_pins>;
phy-handle = <&phy1>;
phy-mode = "mii";
phy-supply = <&reg_dldo1>;
status = "okay";
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&s_ir_rx_pin>;
status = "okay";
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
@ -117,31 +115,13 @@
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
};
};
#include "axp22x.dtsi"
&pio {
led_pins_m9: led_pins@0 {
pins = "PH13";
function = "gpio_out";
};
mmc0_cd_pin_m9: mmc0_cd_pin@0 {
pins = "PH22";
function = "gpio_in";
bias-pull-up;
};
usb1_vbus_pin_m9: usb1_vbus_pin@0 {
pins = "PC27";
function = "gpio_out";
};
};
&reg_aldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -215,15 +195,13 @@
};
&reg_usb1_vbus {
pinctrl-names = "default";
pinctrl-0 = <&usb1_vbus_pin_m9>;
gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

View File

@ -6,6 +6,9 @@
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "sun6i-a31.dtsi"
/ {
@ -19,6 +22,15 @@
chosen {
stdout-path = "serial0:115200n8";
};
reg_usb1_vbus: usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
};
};
&ehci0 {
@ -54,3 +66,8 @@
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

View File

@ -42,8 +42,6 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
@ -52,6 +50,8 @@
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &gmac;
@ -62,7 +62,7 @@
#size-cells = <1>;
ranges;
simplefb_hdmi: framebuffer@0 {
simplefb_hdmi: framebuffer-lcd0-hdmi {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
@ -73,7 +73,7 @@
status = "disabled";
};
simplefb_lcd: framebuffer@1 {
simplefb_lcd: framebuffer-lcd0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
@ -115,27 +115,57 @@
#cooling-cells = <2>;
};
cpu@1 {
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
/* kHz uV */
1008000 1200000
864000 1200000
720000 1100000
480000 1000000
>;
#cooling-cells = <2>;
};
cpu@2 {
cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
/* kHz uV */
1008000 1200000
864000 1200000
720000 1100000
480000 1000000
>;
#cooling-cells = <2>;
};
cpu@3 {
cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
/* kHz uV */
1008000 1200000
864000 1200000
720000 1100000
480000 1000000
>;
#cooling-cells = <2>;
};
};
thermal-zones {
cpu_thermal {
cpu-thermal {
/* milliseconds */
polling-delay-passive = <250>;
polling-delay = <1000>;
@ -144,7 +174,10 @@
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
@ -166,12 +199,8 @@
};
};
memory {
reg = <0x40000000 0x80000000>;
};
pmu {
compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
@ -183,17 +212,20 @@
#size-cells = <1>;
ranges;
osc24M: osc24M {
osc24M: clk-24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-accuracy = <50000>;
clock-output-names = "osc24M";
};
osc32k: clk@0 {
osc32k: clk-32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
clock-accuracy = <50000>;
clock-output-names = "ext_osc32k";
};
/*
@ -205,14 +237,14 @@
* The actual TX clock rate is not controlled by the
* gmac_tx clock.
*/
mii_phy_tx_clk: clk@1 {
mii_phy_tx_clk: clk-mii-phy-tx {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "mii_phy_tx";
};
gmac_int_tx_clk: clk@2 {
gmac_int_tx_clk: clk-gmac-int-tx {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
@ -234,7 +266,7 @@
status = "disabled";
};
soc@1c00000 {
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -253,15 +285,21 @@
compatible = "allwinner,sun6i-a31-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ccu RST_AHB1_LCD0>;
reset-names = "lcd";
dmas = <&dma 11>;
resets = <&ccu RST_AHB1_LCD0>,
<&ccu RST_AHB1_LVDS>;
reset-names = "lcd",
"lvds";
clocks = <&ccu CLK_AHB1_LCD0>,
<&ccu CLK_LCD0_CH0>,
<&ccu CLK_LCD0_CH1>;
<&ccu CLK_LCD0_CH1>,
<&ccu 15>;
clock-names = "ahb",
"tcon-ch0",
"tcon-ch1";
"tcon-ch1",
"lvds-alt";
clock-output-names = "tcon0-pixel-clock";
#clock-cells = <0>;
ports {
#address-cells = <1>;
@ -301,15 +339,20 @@
compatible = "allwinner,sun6i-a31-tcon";
reg = <0x01c0d000 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ccu RST_AHB1_LCD1>;
reset-names = "lcd";
dmas = <&dma 12>;
resets = <&ccu RST_AHB1_LCD1>,
<&ccu RST_AHB1_LVDS>;
reset-names = "lcd", "lvds";
clocks = <&ccu CLK_AHB1_LCD1>,
<&ccu CLK_LCD1_CH0>,
<&ccu CLK_LCD1_CH1>;
<&ccu CLK_LCD1_CH1>,
<&ccu 15>;
clock-names = "ahb",
"tcon-ch0",
"tcon-ch1";
"tcon-ch1",
"lvds-alt";
clock-output-names = "tcon1-pixel-clock";
#clock-cells = <0>;
ports {
#address-cells = <1>;
@ -359,6 +402,8 @@
resets = <&ccu RST_AHB1_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -378,6 +423,8 @@
resets = <&ccu RST_AHB1_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -431,7 +478,6 @@
<&ccu CLK_PLL_VIDEO1_2X>;
clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
resets = <&ccu RST_AHB1_HDMI>;
reset-names = "ahb";
dma-names = "ddc-tx", "ddc-rx", "audio-tx";
dmas = <&dma 13>, <&dma 13>, <&dma 14>;
status = "disabled";
@ -457,8 +503,6 @@
};
hdmi_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
@ -474,6 +518,7 @@
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
dr_mode = "otg";
status = "disabled";
};
@ -557,7 +602,7 @@
ccu: clock@1c20000 {
compatible = "allwinner,sun6i-a31-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
clocks = <&osc24M>, <&rtc 0>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -566,18 +611,19 @@
pio: pinctrl@1c20800 {
compatible = "allwinner,sun6i-a31-pinctrl";
reg = <0x01c20800 0x400>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
gmac_pins_gmii_a: gmac_gmii@0 {
gmac_gmii_pins: gmac-gmii-pins {
pins = "PA0", "PA1", "PA2", "PA3",
"PA4", "PA5", "PA6", "PA7",
"PA8", "PA9", "PA10", "PA11",
@ -593,7 +639,7 @@
drive-strength = <30>;
};
gmac_pins_mii_a: gmac_mii@0 {
gmac_mii_pins: gmac-mii-pins {
pins = "PA0", "PA1", "PA2", "PA3",
"PA8", "PA9", "PA11",
"PA12", "PA13", "PA14", "PA19",
@ -602,7 +648,7 @@
function = "gmac";
};
gmac_pins_rgmii_a: gmac_rgmii@0 {
gmac_rgmii_pins: gmac-rgmii-pins {
pins = "PA0", "PA1", "PA2", "PA3",
"PA9", "PA10", "PA11",
"PA12", "PA13", "PA14", "PA19",
@ -615,22 +661,22 @@
drive-strength = <40>;
};
i2c0_pins_a: i2c0@0 {
i2c0_pins: i2c0-pins {
pins = "PH14", "PH15";
function = "i2c0";
};
i2c1_pins_a: i2c1@0 {
i2c1_pins: i2c1-pins {
pins = "PH16", "PH17";
function = "i2c1";
};
i2c2_pins_a: i2c2@0 {
i2c2_pins: i2c2-pins {
pins = "PH18", "PH19";
function = "i2c2";
};
lcd0_rgb888_pins: lcd0_rgb888 {
lcd0_rgb888_pins: lcd0-rgb888-pins {
pins = "PD0", "PD1", "PD2", "PD3",
"PD4", "PD5", "PD6", "PD7",
"PD8", "PD9", "PD10", "PD11",
@ -641,7 +687,7 @@
function = "lcd0";
};
mmc0_pins_a: mmc0@0 {
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
function = "mmc0";
@ -649,7 +695,7 @@
bias-pull-up;
};
mmc1_pins_a: mmc1@0 {
mmc1_pins: mmc1-pins {
pins = "PG0", "PG1", "PG2", "PG3",
"PG4", "PG5";
function = "mmc1";
@ -657,7 +703,7 @@
bias-pull-up;
};
mmc2_pins_a: mmc2@0 {
mmc2_4bit_pins: mmc2-4bit-pins {
pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11";
function = "mmc2";
@ -665,7 +711,7 @@
bias-pull-up;
};
mmc2_8bit_emmc_pins: mmc2@1 {
mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12",
"PC13", "PC14", "PC15",
@ -675,7 +721,7 @@
bias-pull-up;
};
mmc3_8bit_emmc_pins: mmc3@1 {
mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins {
pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12",
"PC13", "PC14", "PC15",
@ -685,12 +731,12 @@
bias-pull-up;
};
spdif_pins_a: spdif@0 {
spdif_tx_pin: spdif-tx-pin {
pins = "PH28";
function = "spdif";
};
uart0_pins_a: uart0@0 {
uart0_ph_pins: uart0-ph-pins {
pins = "PH20", "PH21";
function = "uart0";
};
@ -703,13 +749,16 @@
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
wdt1: watchdog@1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
spdif: spdif@1c21000 {
@ -754,6 +803,7 @@
lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -849,6 +899,8 @@
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB2_I2C0>;
resets = <&ccu RST_APB2_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -860,6 +912,8 @@
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB2_I2C1>;
resets = <&ccu RST_APB2_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -871,6 +925,8 @@
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB2_I2C2>;
resets = <&ccu RST_APB2_I2C2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -900,8 +956,12 @@
snps,fixed-burst;
snps,force_sf_dma_mode;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
crypto: crypto-engine@1c15000 {
@ -950,6 +1010,8 @@
dma-names = "rx", "tx";
resets = <&ccu RST_AHB1_SPI0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@1c69000 {
@ -962,6 +1024,8 @@
dma-names = "rx", "tx";
resets = <&ccu RST_AHB1_SPI1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi2: spi@1c6a000 {
@ -974,6 +1038,8 @@
dma-names = "rx", "tx";
resets = <&ccu RST_AHB1_SPI2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi3: spi@1c6b000 {
@ -986,10 +1052,12 @@
dma-names = "rx", "tx";
resets = <&ccu RST_AHB1_SPI3>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
gic: interrupt-controller@1c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x2000>,
<0x01c84000 0x2000>,
@ -1073,9 +1141,6 @@
"ram";
resets = <&ccu RST_AHB1_BE1>;
assigned-clocks = <&ccu CLK_BE1>;
assigned-clock-rates = <300000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -1119,9 +1184,6 @@
"ram";
resets = <&ccu RST_AHB1_DRC1>;
assigned-clocks = <&ccu CLK_IEP_DRC1>;
assigned-clock-rates = <300000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -1165,9 +1227,6 @@
"ram";
resets = <&ccu RST_AHB1_BE0>;
assigned-clocks = <&ccu CLK_BE0>;
assigned-clock-rates = <300000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -1189,12 +1248,9 @@
};
be0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
be0_out_drc0: endpoint@0 {
reg = <0>;
be0_out_drc0: endpoint {
remote-endpoint = <&drc0_in_be0>;
};
};
@ -1211,20 +1267,14 @@
"ram";
resets = <&ccu RST_AHB1_DRC0>;
assigned-clocks = <&ccu CLK_IEP_DRC0>;
assigned-clock-rates = <300000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
drc0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
drc0_in_be0: endpoint@0 {
reg = <0>;
drc0_in_be0: endpoint {
remote-endpoint = <&be0_out_drc0>;
};
};
@ -1248,16 +1298,20 @@
};
rtc: rtc@1f00000 {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc32k>;
clock-output-names = "osc32k";
};
nmi_intc: interrupt-controller@1f00c00 {
r_intc: interrupt-controller@1f00c00 {
compatible = "allwinner,sun6i-a31-r-intc";
interrupt-controller;
#interrupt-cells = <2>;
#interrupt-cells = <3>;
reg = <0x01f00c00 0x400>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
@ -1269,7 +1323,7 @@
ar100: ar100_clk {
compatible = "allwinner,sun6i-a31-ar100-clk";
#clock-cells = <0>;
clocks = <&osc32k>, <&osc24M>,
clocks = <&rtc 0>, <&osc24M>,
<&ccu CLK_PLL_PERIPH>,
<&ccu CLK_PLL_PERIPH>;
clock-output-names = "ar100";
@ -1304,7 +1358,7 @@
ir_clk: ir_clk {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
clocks = <&osc32k>, <&osc24M>;
clocks = <&rtc 0>, <&osc24M>;
clock-output-names = "ir";
};
@ -1320,7 +1374,7 @@
};
ir: ir@1f02000 {
compatible = "allwinner,sun5i-a13-ir";
compatible = "allwinner,sun6i-a31-ir";
clocks = <&apb0_gates 1>, <&ir_clk>;
clock-names = "apb", "ir";
resets = <&apb0_rst 1>;
@ -1332,23 +1386,23 @@
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun6i-a31-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
clock-names = "apb", "hosc", "losc";
resets = <&apb0_rst 0>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#size-cells = <0>;
#gpio-cells = <3>;
ir_pins_a: ir@0 {
s_ir_rx_pin: s-ir-rx-pin {
pins = "PL4";
function = "s_ir";
};
p2wi_pins: p2wi {
s_p2wi_pins: s-p2wi-pins {
pins = "PL0", "PL1";
function = "s_p2wi";
};
@ -1362,7 +1416,7 @@
clock-frequency = <100000>;
resets = <&apb0_rst 3>;
pinctrl-names = "default";
pinctrl-0 = <&p2wi_pins>;
pinctrl-0 = <&s_p2wi_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;

View File

@ -53,7 +53,7 @@
vref-supply = <&reg_aldo3>;
status = "okay";
button@1000 {
button-1000 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;

View File

@ -66,28 +66,31 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins_mii_a>;
phy = <&phy1>;
pinctrl-0 = <&gmac_mii_pins>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
pinctrl-0 = <&s_ir_rx_pin>;
status = "okay";
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ohci1 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

View File

@ -54,8 +54,6 @@
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
ft5406ee8: touchscreen@38 {
@ -73,21 +71,21 @@
vref-supply = <&reg_aldo3>;
status = "okay";
button@200 {
button-200 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <200000>;
};
button@900 {
button-900 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <900000>;
};
button@1200 {
button-1200 {
label = "Back";
linux,code = <KEY_BACK>;
channel = <0>;

View File

@ -90,19 +90,13 @@
&i2c0 {
/* pull-ups and device VDDIO use AXP221 DLDO3 */
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "failed";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
ctp@5d {
pinctrl-names = "default";
pinctrl-0 = <&gt911_int_primo81>;
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&pio>;
@ -112,8 +106,6 @@
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
accelerometer@1c {
@ -123,7 +115,6 @@
reg = <0x1c>;
interrupt-parent = <&pio>;
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; /* PA9 */
#io-channel-cells = <1>;
};
};
@ -131,14 +122,14 @@
vref-supply = <&reg_aldo3>;
status = "okay";
button@158 {
button-158 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <158730>;
};
button@349 {
button-349 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
@ -147,8 +138,6 @@
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_primo81>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
@ -156,22 +145,11 @@
};
&pio {
gt911_int_primo81: gt911_int_pin@0 {
pins = "PA3";
function = "gpio_in";
};
mma8452_int_primo81: mma8452_int_pin@0 {
mma8452_int_primo81: mma8452-int-pin {
pins = "PA9";
function = "gpio_in";
bias-pull-up;
};
mmc0_cd_pin_primo81: mmc0_cd_pin@0 {
pins = "PA8";
function = "gpio_in";
bias-pull-up;
};
};
&p2wi {
@ -180,8 +158,8 @@
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
x-powers,drive-vbus-en;
};
};
@ -281,7 +259,7 @@
};
&usbphy {
usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <&reg_drivevbus>;
usb1_vbus-supply = <&reg_dldo1>;

View File

@ -78,8 +78,8 @@
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
};
};
@ -135,7 +135,7 @@
/* UART0 pads available on core board */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

View File

@ -66,8 +66,6 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pin_sina31s>;
status {
label = "sina31s:status:usr";
@ -116,15 +114,11 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins_mii_a>;
phy = <&phy1>;
pinctrl-0 = <&gmac_mii_pins>;
phy-handle = <&phy1>;
phy-mode = "mii";
phy-supply = <&reg_dldo1>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -139,7 +133,7 @@
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
pinctrl-0 = <&s_ir_rx_pin>;
status = "okay";
};
@ -147,14 +141,14 @@
vref-supply = <&reg_aldo3>;
status = "okay";
button@158 {
button-158 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <158730>;
};
button@349 {
button-349 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
@ -162,9 +156,13 @@
};
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina31s>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
@ -175,19 +173,6 @@
status = "okay";
};
&pio {
led_pin_sina31s: led_pin@0 {
pins = "PH13";
function = "gpio_out";
};
mmc0_cd_pin_sina31s: mmc0_cd_pin@0 {
pins = "PA4";
function = "gpio_in";
bias-pull-up;
};
};
&reg_dldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -196,7 +181,7 @@
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&spdif_pins_a>;
pinctrl-0 = <&spdif_tx_pin>;
status = "okay";
};

View File

@ -58,20 +58,18 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_bpi_m2>;
blue {
led-0 {
label = "bpi-m2:blue:usr";
gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
};
green {
led-1 {
label = "bpi-m2:green:usr";
gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */
};
red {
led-2 {
label = "bpi-m2:red:usr";
gpios = <&pio 6 5 GPIO_ACTIVE_HIGH>; /* PG5 */
};
@ -79,8 +77,6 @@
mmc2_pwrseq: mmc2_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pwrseq_pin_bpi_m2>;
reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 WIFI_EN */
};
};
@ -95,42 +91,38 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_bpi_m2>;
phy = <&phy1>;
pinctrl-0 = <&gmac_rgmii_pins>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_dldo1>;
snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
pinctrl-0 = <&s_ir_rx_pin>;
status = "okay";
};
&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>; /* PA21 */
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m2>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
status = "okay";
};
&mmc0_pins_a {
bias-pull-up;
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_a>;
pinctrl-0 = <&mmc2_4bit_pins>;
vmmc-supply = <&reg_aldo1>;
mmc-pwrseq = <&mmc2_pwrseq>;
bus-width = <4>;
@ -146,10 +138,6 @@
};
};
&mmc2_pins_a {
bias-pull-up;
};
&ohci0 {
status = "okay";
};
@ -160,38 +148,13 @@
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
eldoin-supply = <&reg_dcdc1>;
x-powers,drive-vbus-en;
};
};
&pio {
gmac_phy_reset_pin_bpi_m2: gmac_phy_reset_pin@0 {
pins = "PA21";
function = "gpio_out";
};
led_pins_bpi_m2: led_pins@0 {
pins = "PG5", "PG10", "PG11";
function = "gpio_out";
};
mmc0_cd_pin_bpi_m2: mmc0_cd_pin@0 {
pins = "PA4";
function = "gpio_in";
bias-pull-up;
};
};
&r_pio {
mmc2_pwrseq_pin_bpi_m2: mmc2_pwrseq_pin@0 {
pins = "PL8";
function = "gpio_out";
};
};
#include "axp22x.dtsi"
&reg_aldo1 {
@ -291,10 +254,81 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
&usbphy {
status = "okay";
};
&pio {
gpio-line-names =
/* PA */
"ETXD0", "ETXD1", "ETXD2", "ETXD3", "SDC0-DET", "", "",
"", "ETXCLK", "ETXEN", "EGTXCLK", "ERXD0", "ERXD1",
"ERXD2", "ERXD3", "", "", "", "", "ERXDV", "ERXCK",
"ETXERR", "ERXERR", "ECOL", "ECRS", "ECLKIN", "EMDC",
"EMDIO", "", "", "", "",
/* PB */
"CN7-P29", "CN7-P31", "CN7-P33", "CN7-P35", "CN7-P37",
"CN7-P28", "CN7-P27", "CN7-P32", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "", "", "", "", "",
"", "", "", "",
/* PC */
"", "", "", "", "", "", "WL-SDIO-CMD", "WL-SDIO-CLK",
"WL-SDIO-D0", "WL-SDIO-D2", "WL-SDIO-D2", "WL-SDIO-D3",
"", "", "", "", "", "", "", "", "", "", "", "", "", "",
"", "USB-DRV", "", "", "", "",
/* PD */
"CN9-P09", "CN9-P11", "CN9-P13", "CN9-P15", "CN9-P17",
"CN9-P19", "CN9-P21", "CN9-P23", "CN9-P25", "CN9-P27",
"CN9-P29", "CN9-P31", "CN9-P33", "CN9-P35", "CN9-P37",
"CN9-P39", "CN9-P40", "CN9-P38", "CN9-P36", "CN9-P34",
"CN9-P32", "CN9-P30", "CN9-P28", "CN9-P26", "CN9-P22",
"CN9-P14", "CN9-P18", "CN9-P16", "", "", "", "",
/* PE */
"CN6-P20", "CN6-P24", "CN6-P30", "CN6-P28", "CN7-P08",
"CN7-P10", "CN7-P36", "CN7-P38", "CN6-P17", "CN6-P19",
"CN6-P21", "CN6-P23", "CN6-P25", "CN6-P27", "CN6-P29",
"CN6-P31", "", "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "",
/* PF */
"SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
"SDC0-D2", "", "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "", "", "", "", "",
"",
/* PG */
"CN9-P06", "CN9-P08", "CN9-P20", "CN9-P12", "CN9-P07",
"LED-PWR", "CN7-P13", "CN7-P11", "CN7-P22", "CN7-P15",
"LED-G", "LED-B", "CN7-P26", "CN7-P24", "CN7-P23",
"CN7-P19", "CN7-P21", "HCEC", "CN6-P22", "", "", "", "",
"", "", "", "", "", "", "", "", "",
/* PH */
"", "", "", "", "", "", "", "", "", "CN7-P07",
"CN7-P12", "CN7-P16", "CN7-P18", "CN9-P10", "CN6-P16",
"CN6-P14", "CN9-P04", "CN9-P02", "CN7-P05", "CN7-P03",
"CN8-P03", "CN8-P02", "", "", "CN6-P34", "CN6-P32",
"CN6-P26", "CN6-P18", "", "", "", "";
};
&r_pio {
gpio-line-names =
/* PL */
"PMU-SCK", "PMU-SDA", "VBAT-EN", "", "IR-RX",
"WL-WAKE-HOST", "BT-WAKE_HOST", "BT-ENABLE",
"WL-PMU-EN", "", "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "", "", "",
/* PM */
"CN6-P12", "CN6-P35", "CN7-P40", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "";
};

View File

@ -62,14 +62,10 @@
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
@ -89,35 +85,21 @@
status = "okay";
};
&pio {
mmc0_cd_pin_bs1078v2: mmc0_cd_pin@0 {
pins = "PA8";
function = "gpio_in";
bias-pull-up;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bs1078v2>;
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;
cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
&mmc0_pins_a {
bias-pull-up;
};
&p2wi {
status = "okay";
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
};
};
@ -189,11 +171,12 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
usb1_vbus-supply = <&reg_dldo1>;
usb2_vbus-supply = <&reg_dc1sw>;
status = "okay";

View File

@ -66,35 +66,21 @@
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>;
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
&pio {
mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 {
pins = "PA8";
function = "gpio_in";
bias-pull-up;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
pins = "PA15";
function = "gpio_in";
bias-pull-up;
};
};
&p2wi {
status = "okay";
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
drivevbus-supply = <&reg_vcc5v0>;
x-powers,drive-vbus-en;
};
@ -179,9 +165,7 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
usb0_id_det-gpios = <&pio 0 15 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA15 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <&reg_drivevbus>;
usb1_vbus-supply = <&reg_dldo1>;

View File

@ -74,12 +74,12 @@
leds {
compatible = "gpio-leds";
green {
led-0 {
label = "bananapi-m1-plus:green:usr";
gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
};
pwr {
led-1 {
label = "bananapi-m1-plus:pwr:usr";
gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>;
default-state = "on";
@ -129,14 +129,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
phy-supply = <&reg_gmac_3v3>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -171,6 +167,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

View File

@ -77,7 +77,7 @@
leds {
compatible = "gpio-leds";
green {
led {
label = "bananapi:green:usr";
gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
};
@ -131,14 +131,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
phy-supply = <&reg_gmac_3v3>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -171,6 +167,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
@ -246,12 +248,6 @@
"SPI-MISO", "SPI-CE1", "",
"IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "",
"", "", "", "", "", "", "", "";
usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
};
#include "axp209.dtsi"
@ -329,9 +325,7 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;

View File

@ -63,12 +63,12 @@
leds {
compatible = "gpio-leds";
blue {
led-0 {
label = "bananapro:blue:usr";
gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>;
};
green {
led-1 {
label = "bananapro:green:usr";
gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
};
@ -109,14 +109,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
phy-supply = <&reg_gmac_3v3>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
@ -143,6 +139,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

View File

@ -75,12 +75,12 @@
leds {
compatible = "gpio-leds";
blue {
led-0 {
label = "cubieboard2:blue:usr";
gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
};
green {
led-1 {
label = "cubieboard2:green:usr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
};
@ -115,13 +115,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -161,6 +157,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ohci0 {
status = "okay";
};
@ -173,14 +175,6 @@
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
};
&reg_ahci_5v {
status = "okay";
};
@ -236,9 +230,7 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb1_vbus-supply = <&reg_usb1_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
status = "okay";

View File

@ -75,22 +75,22 @@
leds {
compatible = "gpio-leds";
blue {
led-0 {
label = "cubietruck:blue:usr";
gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
};
orange {
led-1 {
label = "cubietruck:orange:usr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
};
white {
led-2 {
label = "cubietruck:white:usr";
gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>;
};
green {
led-3 {
label = "cubietruck:green:usr";
gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>;
};
@ -150,13 +150,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -194,6 +190,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

View File

@ -100,19 +100,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_gmac_vdd>;
/* phy reset config */
snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
snps,reset-active-low;
/* wait 1s after reset, otherwise fail to read phy id */
snps,reset-delays-us = <0 10000 1000000>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
@ -146,6 +137,16 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
reset-assert-us = <10000>;
/* wait 1s after reset, otherwise fail to read phy id */
reset-deassert-us = <1000000>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;

View File

@ -62,12 +62,12 @@
leds {
compatible = "gpio-leds";
red {
led-0 {
label = "i12_tvbox:red:usr";
gpios = <&pio 7 9 GPIO_ACTIVE_LOW>;
};
blue {
led-1 {
label = "i12_tvbox:blue:usr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
};
@ -115,14 +115,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
phy-supply = <&reg_gmac_3v3>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
@ -145,6 +141,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

View File

@ -49,7 +49,8 @@
/ {
model = "ICnova-A20 SWAC";
compatible = "swac,icnova-a20-swac", "incircuit,icnova-a20", "allwinner,sun7i-a20";
compatible = "incircuit,icnova-a20-swac", "incircuit,icnova-a20",
"allwinner,sun7i-a20";
aliases {
serial0 = &uart0;
@ -75,13 +76,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
@ -98,6 +95,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

View File

@ -53,13 +53,13 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_itead_core>;
green {
led-0 {
label = "itead_core:green:usr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
blue {
led-1 {
label = "itead_core:blue:usr";
gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
default-state = "on";
@ -97,10 +97,12 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};

View File

@ -75,7 +75,7 @@
leds {
compatible = "gpio-leds";
green {
led {
label = "lamobo_r1:green:usr";
gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
};
@ -123,8 +123,6 @@
phy-mode = "rgmii";
phy-supply = <&reg_gmac_3v3>;
status = "okay";
/delete-property/#address-cells;
/delete-property/#size-cells;
fixed-link {
speed = <1000>;
@ -229,14 +227,6 @@
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0-id-detect-pin {
pins = "PH4";
function = "gpio_in";
bias-pull-up;
};
};
#include "axp209.dtsi"
&ac_power_supply {
@ -322,9 +312,7 @@
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <&reg_usb0_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;

View File

@ -64,7 +64,7 @@
leds {
compatible = "gpio-leds";
blue {
led {
label = "m3:blue:usr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
};
@ -82,13 +82,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&i2c0 {
@ -111,6 +107,12 @@
status = "okay";
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

View File

@ -75,7 +75,7 @@
leds {
compatible = "gpio-leds";
green {
led {
label = "a20-olimex-som-evb:green:usr";
gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
@ -111,13 +111,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&hdmi {
@ -202,6 +198,12 @@
};
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;

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