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1098 Commits

Author SHA1 Message Date
Samuel Holland
1d993ea68a bl808: Add support for running on M0 and D0 concurrently
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-15 02:46:48 -06:00
Samuel Holland
913809fcc2 bl808: Switch all SRAM to AHB access
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-15 02:46:48 -06:00
Samuel Holland
e4c49b31c7 bl808: Add Ox64 board UART init
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-15 02:46:48 -06:00
Samuel Holland
e093e519f3 riscv: Add BL808 board
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-15 02:46:48 -06:00
Samuel Holland
8bbd8aee0c sysreset: Add BL808 sysreset driver
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-15 02:46:48 -06:00
Samuel Holland
8d1d10918e serial: Add Bouffalo Lab UART serial driver
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-15 02:46:48 -06:00
Samuel Holland
02e7f4f7c1 reset: Add Bouffalo Lab reset driver
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-15 02:46:47 -06:00
Samuel Holland
2baf4bda80 remoteproc: Add BL808 remoteproc driver
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-15 02:46:47 -06:00
Samuel Holland
11b8cb31af remoteproc: Clean up some junk
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-15 01:06:00 -06:00
Samuel Holland
d8b23c96a5 ram: Add BL808 PSRAM driver
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-15 01:06:00 -06:00
Samuel Holland
ffad907cd2 pinctrl: Add Bouffalo Lab pinctrl driver
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-15 01:06:00 -06:00
Samuel Holland
84aea25b76 phy: Add BL808 USB PHY driver
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-15 01:06:00 -06:00
Samuel Holland
c7e587c0e8 mmc: Add Bouffalo Lab SDHCI driver
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-15 01:06:00 -06:00
Samuel Holland
45131b584d clk: bl808: Implement clk dump
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-15 01:06:00 -06:00
Samuel Holland
58c8158e9c clk: Add BL808 clock driver
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-14 11:46:01 -06:00
Samuel Holland
d15344788f clk: Add .get_parent operation
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-14 11:46:01 -06:00
Samuel Holland
6858b7fffb clk: Fix logic in clk_get_parent_rate()
clk_get_rate() can return an error value; recompute the rate if the
cached value is an error value.

There is no need to check the parent clock's ops. clk_get_rate() does
that already.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-14 11:46:01 -06:00
Samuel Holland
52e6bd7cb4 clk: Fix error handling in clk_get_parent()
Do not return both NULL and error pointers. The function is only
documented as returning error pointers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-14 11:46:01 -06:00
Samuel Holland
7eff706d90 clk: Fix error handling in clk_get_rate()
log_ret() cannot work with unsigned values.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-14 11:46:01 -06:00
Samuel Holland
a859c666c7 dm: core: Use full SPL printf() format when enabled
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-14 11:46:01 -06:00
Samuel Holland
30355416b3 riscv: Add BL808 register definitions
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-14 11:46:01 -06:00
Samuel Holland
425696477f riscv: Support !SPL_HAS_BSS_LINKER_SECTION
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-14 11:46:01 -06:00
Samuel Holland
9e684d63c4 riscv: Support CONFIG_REMAKE_ELF
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-14 11:46:01 -06:00
Samuel Holland
0100e7da39 riscv: Use RAM driver if SPL is not enabled
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-14 11:46:01 -06:00
Samuel Holland
7b83a3f8f5 riscv: Probe CPUs in dm_scan_other()
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-14 11:46:01 -06:00
Samuel Holland
38acf8ad62 cpu: Probe CPU devices before relocation
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-14 11:46:01 -06:00
Samuel Holland
1c3cefcfa8 cpu: Move parent plat to uclass plat
Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-01-14 11:46:00 -06:00
Tom Rini
fe4c21de4f Add driver to manage onboard hub supplies
Add calibration support for stm32-adc
 Linux kernel v6.1 DT synchronization for stm32mp151.dtsi
 stm32mp157a-dk1-scmi-u-boot.dtsi update
 Add support of OP-TEE and STM32MP13x in bsec driver
 ECDSA various fixes for stm32mp
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Merge tag 'u-boot-stm32-20230113' of https://source.denx.de/u-boot/custodians/u-boot-stm

Add driver to manage onboard hub supplies
Add calibration support for stm32-adc
Linux kernel v6.1 DT synchronization for stm32mp151.dtsi
stm32mp157a-dk1-scmi-u-boot.dtsi update
Add support of OP-TEE and STM32MP13x in bsec driver
ECDSA various fixes for stm32mp
2023-01-13 09:56:19 -05:00
Tom Rini
b3f6e0ff1f Pull request for efi-2023-04-rc1
Documentation:
 
 * build infodocs target on Gitlab CI, Azure
 
 UEFI:
 
 * fix function descriptions
 * add .rela sections to .text on arm64
 * use EFI_EXIT in efi_riscv_get_boot_hartid
 * improve specification conformance of set_keyboard_layout()
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Merge tag 'efi-2023-04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2023-04-rc1

Documentation:

* build infodocs target on Gitlab CI, Azure

UEFI:

* fix function descriptions
* add .rela sections to .text on arm64
* use EFI_EXIT in efi_riscv_get_boot_hartid
* improve specification conformance of set_keyboard_layout()
2023-01-13 08:37:32 -05:00
Marek Vasut
0e86f813f4 ARM: stm32: Make ECDSA authentication available to U-Boot
With U-Boot having access to ROM API call table, it is possible to use
the ROM API call it authenticate e.g. signed kernel fitImages using the
BootROM ECDSA support. Make this available by pulling the ECDSA BootROM
call support from SPL-only guard.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-13 13:46:57 +01:00
Marek Vasut
6eea541514 ARM: stm32: Pass ROM API table pointer to U-Boot proper
The ROM API table pointer is no longer accessible from U-Boot, fix
this by passing the ROM API pointer through. This makes it possible
for U-Boot to call ROM API functions to authenticate payload like
signed fitImages.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-13 13:46:57 +01:00
Marek Vasut
dbeaca79b7 ARM: stm32: Factor out save_boot_params
The STM32MP15xx platform currently comes with two incompatible
implementations of save_boot_params() weak function override.
Factor the save_boot_params() implementation into common cpu.c
code and provide accessors to read out both ROM API table address
and DT address from any place in the code instead.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-13 13:46:57 +01:00
Marek Vasut
bbafbc044d ARM: stm32: Fix ECDSA authentication with Dcache enabled
In case Dcache is enabled while the ECDSA authentication function is
called via BootROM ROM API, the MMU tables are set up and the BootROM
region is not marked as executable, so an attempt to run code from it
results in a hang. Mark the BootROM region as executable as suggested
by Patrick to prevent the hang.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-13 13:46:57 +01:00
Heinrich Schuchardt
8e4ec3e947 efi_loader: provide agent_handle to efi_disk_add_dev()
In efi_disk_add_dev() we have to open protocols with BY_DRIVER and
BY_CHILD_CONTROLLER. Provide the handle of the EFI block driver. The actual
usage of the value will follow in a later patch.

Change function descriptions to Sphinx style.

Remove a TODO: tag.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-13 09:09:07 +01:00
Vincent Stehlé
4d4ec25810 efi_selftest: add hii set keyboard layout test case
Add a test for the case when the HII database protocol
set_keyboard_layout() function is called with a NULL key_guid argument.

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-01-13 09:09:07 +01:00
Vincent Stehlé
65b91a346e efi_loader: refine set_keyboard_layout() status
As per the EFI specification, the HII database protocol function
set_keyboard_layout() must return EFI_INVALID_PARAMETER when it is called
with a NULL key_guid argument. Modify the function accordingly to improve
conformance.

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-01-13 09:09:07 +01:00
Heinrich Schuchardt
851456693a efi_loader: use EFI_EXIT in efi_riscv_get_boot_hartid
After calling EFI_ENTRY we have to call EFI_EXIT before returning.

Add a missing EFI_EXIT().

Fixes: 1ccf87165e38 ("efi_loader: Enable RISCV_EFI_BOOT_PROTOCOL support")
Reported-by: Dave Jones <dave.jones@canonical.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2023-01-13 09:09:07 +01:00
Heinrich Schuchardt
7e808fcc97 efi_loader: add .rela sections to .text on arm64
_relocate() needs the information in .rela* for self relocation
of the EFI binary.

Fixes: d7ddeb66a6ce ("efi_loader: fix building aarch64 EFI binaries")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-13 09:09:07 +01:00
Heinrich Schuchardt
0763c02eee efi_loader: fix description of memory functions
* Add missing function descriptions
* Adjust to Sphinx style

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-01-13 09:09:07 +01:00
Heinrich Schuchardt
e9cc7029e8 doc: build infodocs target on Gitlab CI, Azure
Add infodocs target to CI testing.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-01-13 09:09:07 +01:00
Heinrich Schuchardt
6c39d0ef1e doc: fix description of u16_strcasecmp()
Remove non-existent parameter 'n' from function description.

Fixes: 7a9b366cd9b7 ("lib: add function u16_strcasecmp()")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-13 09:09:07 +01:00
Tom Rini
87c9e117bf Merge branch '2023-01-12-further-assorted-general-updates'
- Bring in a number of assorted updates, some of which have been waiting
  around for a bit.  Make silent console really be silent, get rid of
  gpio_hog_probe_all, add RNG for imx6, make net/fm use fs_loader, get
  rid of a bad __weak usage and set distro_bootpart_uuid in another case.
2023-01-12 17:05:41 -05:00
Marek Vasut
48b3ecbedf gpio: Get rid of gpio_hog_probe_all()
The gpio_hog_probe_all() functionality can be perfectly well replaced by
DM_FLAG_PROBE_AFTER_BIND DM flag, which would trigger .probe() callback
of each GPIO hog driver instance after .bind() and thus configure the
hogged GPIO accordingly.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2023-01-12 14:06:16 -05:00
Quentin Schulz
942918f2ac dm: fix probing of all devices that have u-boot, dm-pre-reloc in SPL/TPL
Currently, dm_probe_devices checks that the flags of the device contains
DM_FLAG_PRE_RELOC. However DM_FLAG_PRE_RELOC is a driver - and not a
device - flag. This means that the check in pre_reloc_only mode would
always fail.

Instead, what was aimed to be checked is that either the driver of the
device has the flag set, or that the device has the u-boot,dm-pre-reloc
Device Tree property set.

So let's fix the check to allow u-boot,dm-pre-reloc devices to be
probed.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2023-01-12 14:06:16 -05:00
Marek Vasut
d0ba0ca45a distro_bootcmd: Set distro_bootpart_uuid for block devices
The assignment of block device nodes in Linux is not deterministic by
default, i.e. a newly added eMMC controller or other block device can
change the assignment of /dev/mmcblkN (or other block device node like
e.g. /dev/sdXy) and prevent the system from picking the correct block
device for root filesystem in case the root filesystem is specified on
kernel command line using 'root=/dev/mmcblkNpM' (or 'root=/dev/sdXy'
etc.).

One way out is to derive PARTUUID in U-Boot, which is unique identifier
of a partition, and pass that as root=PARTUUID=<partuuid> to Linux via
kernel command line. Linux would then find the partition using PARTUUID,
no matter on which block device the partition resides and which node was
assigned to that block device.

Derive the PARTUUID before scanning for extlinux presence and assign it
into distro_bootpart_uuid environment variable, which can then be used
in extlinux.conf kernel command line specifier.

Note that it is not possible to do this in scan_dev_for_extlinux script
because this script is called from scan_dev_for_boot script, which is
called for both block devices as well as UBI volumes, and we can not
derive PARTUUID for UBI volumes.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-12 14:06:16 -05:00
Harald Seiler
ea3d28ec31 Revert "time: add weak annotation to timer_read_counter declaration"
This reverts commit 65ba7add0d609bbd035b8d42fafdaf428ac24751.

A weak extern is a nasty sight to behold: If the symbol is never
defined, on ARM, the linker will replace the function call with a NOP.
This behavior isn't well documented but there are at least some hints
to it [1].

When timer_read_counter() is not defined, this obviously does the wrong
thing here and it does so silently.  The consequence is that a board
without timer_read_counter() will sleep for random amounts and generally
have erratic get_ticks() values.

Drop the __weak annotation of the extern so a linker error is raised
when timer_read_counter() is not defined.  This is okay, the original
reason for the reverted change - breaking the sandbox build - no longer
applies.

Final sidenote:  This was the only weak extern in the entire tree at
this time as far as I can tell.  I guess we should avoid introduction of
them again as they are obviously a very big footgun.

[1]: https://stackoverflow.com/questions/31203402/gcc-behavior-for-unresolved-weak-functions

Fixes: 65ba7add0d60 ("time: add weak annotation to timer_read_counter declaration")
Reported-by: Serge Bazanski <q3k@q3k.org>
Signed-off-by: Harald Seiler <hws@denx.de>
2023-01-12 14:06:16 -05:00
Sean Anderson
f4426fd68d net: fm: Support loading firmware from a filesystem
This adds a new method to load Fman firmware from a filesystem. This
allows users to use regular files instead of hard-coded offsets for the
firmware.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-01-12 14:06:16 -05:00
Sean Anderson
e4f0cc5ddf net: fm: Add firmware name parameter
In order to read the firmware from the filesystem, we need a file name.
Read the firmware name from the device tree, using the firmware-name
property. This property is commonly used in Linux to determine the
correct name to use (and can be seen in several device trees in U-Boot).

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-01-12 14:06:16 -05:00
Sean Anderson
0998a20cfc misc: fs_loader: Add function to get the chosen loader
The fs_loader device is used to pull in settings via the chosen node.
However, there was no library function for this, so arria10 was doing it
explicitly. This function subsumes that, and uses ofnode_get_chosen_node
instead of navigating the device tree directly. Because fs_loader pulls
its config from the environment by default, it's fine to create a device
with nothing backing it at all. Doing this allows enabling
CONFIG_FS_LOADER without needing to modify the device tree.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-01-12 14:06:15 -05:00
Kshitiz Varshney
7fb4aa14d4 Added configs required for dcp_rng driver
This commit adds configs required for using dcp_rng driver in imx6ull
defconfig files.

Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2023-01-12 11:25:46 -05:00
Kshitiz Varshney
81ceb1695a Added dcp_rng driver initialization code
This commit initializes dcp_rng device driver inside
arch_misc_init() function.

Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2023-01-12 11:25:46 -05:00
Kshitiz Varshney
0d795c356a Uboot RNG Driver using Data Co-processor
This commit introduces Random number generator to uboot. It uses DCP
driver for number generation.
RNG driver can be invoked by using below command on uboot prompt:-
           rng <number of bytes>

Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-12 11:25:46 -05:00
Nikita Shubin
cf7aa03543 common: spl: ram: fix return code
Instead of always retuning success, return actual result of
load_simple_fit_image or spl_parse_image_header, otherwise we
might end up jumping on uninitialized spl_image->entry_point.

Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-01-12 11:25:46 -05:00
chenzhipeng
c40e021b83 cmd: spi: Judge the number of added parameters
When only sspi is entered, help information can be printed.

Signed-off-by: chenzhipeng <chenzhipeng@eswincomputing.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-12 11:25:17 -05:00
Harald Seiler
33965c7e18 console: Add option to keep it silent until env is loaded
Add a config-option which forces the console to stay silent until the
proper environment is loaded from flash.

This is important when the default environment does not silence the
console but no output must be printed when 'silent' is set in the flash
environment.

After the environment from flash is loaded, the console will be
silenced/unsilenced depending on it.  If PRE_CONSOLE_BUFFER is also
used, the buffer will now be flushed if the console should not be
silenced.

Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-12 11:25:17 -05:00
Patrick Delaunay
d3a87e32dd configs: stm32mp13: Activate command stm32key
Activate the command stm32key with CONFIG_CMD_STM32KEY.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:37:13 +01:00
Patrick Delaunay
4b002d9628 board: st: Add support of STM32MP13x boards in stm32board cmd
Add board identifiers for STMicroelectronics STM32MP13x boards:
- DISCO board: MB1635

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:37:13 +01:00
Patrick Delaunay
7de0d10ca7 configs: stm32mp13: Activate CONFIG_CMD_FUSE
Activate the command fuse to access on STM32MP13x OTP with
the BSEC driver.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:37:13 +01:00
Patrick Delaunay
a33885ff49 stm32mp: Add support of STM32MP13x in bsec driver
Add support for "st,stm32mp13-bsec" for STM32MP13x in the
bsec driver based on OP-TEE pseudo TA STM32MP BSEC.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:37:13 +01:00
Patrick Delaunay
33a909a42a stm32mp: Add OP-TEE support in bsec driver
When OP-TEE is used, the SMC for BSEC management are not available and
the STM32MP BSEC pseudo TA must be used (it is mandatory for STM32MP13
and it is a new feature for STM32MP15x).

The BSEC driver try to open a session to this PTA BSEC at probe
and use it for OTP read or write access to fuse or to shadow.

This patch also adapts the commands stm32key and stboard to handle
the BSEC_LOCK_PERM lock value instead of 1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:37:13 +01:00
Patrick Delaunay
27bad4e7fc stm32mp: cosmetic: Update of bsec driver
Remove unnecessary return in stm32mp_bsec_write_lock and replace tab
by space for plat_auto opts.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:37:13 +01:00
Patrick Delaunay
6e391c7d5f ARM: dts: stm32: Add timer interrupts on stm32mp15
The timer units in the stm32mp15x CPUs have interrupts, depending on the
timer flavour either one "global" or four dedicated ones. Add the irqs
to the timer units on stm32mp15x.

Sync the DT Files with linux kernel v6.1 and with commit a9b70102253ce
("ARM: dts: stm32: Add timer interrupts on stm32mp15")

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:30:52 +01:00
Patrick Delaunay
126aa470d6 ARM: dts: stm32mp15: fix typo in stm32mp15xx-dkx.dtsi
Remove unnecessary space in device tree stm32mp15xx-dkx.dtsi.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:30:52 +01:00
Patrick Delaunay
d1d56638c4 ARM: dts: stm32mp15: remove clksrc include in SCMI dtsi file
The include file stm32mp1-clksrc.h is not necessary for the SCMI STM32MP15
dtsi files as the clock tree is not defined in the U-Boot SCMI device tree;
these SCMI device tree only support TFABOOT with stm32mp15_defconfig,
SPL with the basic boot defconfig is not supported.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:30:52 +01:00
Olivier Moysan
17bae7766c adc: stm32mp15: add calibration support
Add support of offset and linear calibration for STM32MP15.
The calibration is performed once at probe. The ADC is set in power on
state for calibration. It remains in this state after calibration,
to give to the kernel the opportunity to retrieve calibration data,
directly from the ADC.

Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:25:51 +01:00
Fabrice Gasnier
214d6e7e68 ARM: dts: stm32: add support for USB2514B onboard hub on stm32mp157c-ev1
Add support for USB2514B onboard hub on stm32mp157c EV1 board. The HUB
is supplied by a 3v3 PMIC regulator.

[backport from linux ad9591b01d24]
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-01-12 16:19:53 +01:00
Fabrice Gasnier
5f74d97c45 configs: stm32: enable USB onboard HUB driver
Activate the USB onboard HUB driver, that is used to enable the HUB supply
on STM32MP15 EVAL, DK1 and DK2 boards.
This avoids marking the 3v3 corresponding regulator as always-on.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-01-12 16:19:53 +01:00
Fabrice Gasnier
ba1fa2abde usb: onboard-hub: add driver to manage onboard hub supplies
The main issue the driver addresses is that a USB hub needs to be
powered before it can be discovered. This is often solved by using
"regulator-always-on".

This driver is inspired by the Linux v6.1 driver. It only enables (or
disables) the hub vdd (3v3) supply, so it can be enumerated.
Scanning of the device tree is done in a similar manner to the sandbox,
by the usb-uclass. DT part looks like:

&usbh_ehci {
	...
	#address-cells = <1>;
	#size-cells = <0>;
	hub@1 {
		compatible = "usb424,2514";
		reg = <1>;
		vdd-supply = <&v3v3>;
	};
};

When the bus gets probed, the driver is automatically probed/removed from
the bus tree, as an example on stm32:
STM32MP> usb start
starting USB...
STM32MP> dm tree
 Class     Index  Probed  Driver                Name
-----------------------------------------------------------
 usb           0  [ + ]   ehci_generic          |   |-- usb@5800d000
 usb_hub       0  [ + ]   usb_onboard_hub       |   |   `-- hub@1
 usb_hub       1  [ + ]   usb_hub               |   |       `-- usb_hub

STM32MP> usb tree
USB device tree:
  1  Hub (480 Mb/s, 0mA)
  |  u-boot EHCI Host Controller
  |
  +-2  Hub (480 Mb/s, 2mA)

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-01-12 16:19:53 +01:00
Tom Rini
f58885d002 Merge branch '2023-01-11-assorted-general-updates'
- Assorted Kconfig cleanups, code clean ups, env+ubi updates, correct
  return value propagation out of environment scripts, and update CI to
  latest "jammy" tag.
2023-01-12 10:15:24 -05:00
Fabrice Gasnier
79da4074dd ARM: dts: stm32: update vbus-supply of usbphyc_port0 on stm32mp157c-ev1
phy-stm32-usbphyc bindings uses a connector node with vbus-supply
property.

[backport from linux 43e55d778a6b]
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-12 16:08:43 +01:00
Tom Rini
85fd48984e CI/Docker: Update to jammy-20221130 tag
Update to the latest "jammy" tag. This requires us to list libc6-i386 as
a required package to install (for nokia_rx51 tests) that was previously
implicit.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-11 15:02:24 -05:00
Ville Skyttä
fe482b886d Use grep -E or plain grep instead of egrep
`egrep` has been deprecated in GNU grep since 2007,
and since 3.8 it emits obsolescence warnings:
https://git.savannah.gnu.org/cgit/grep.git/commit/?id=a9515624709865d480e3142fd959bccd1c9372d1
Acked-by: Dhruva Gole <d-gole@ti.com>
2023-01-11 15:02:24 -05:00
Heinrich Schuchardt
89d47b33b5 Kconfig: move NXP specific stuff into a sub-menu
Having NXP specific items in the main menu is confusing. Especially
the comment line

   *** Other functionality shared between NXP SoCs ***

is simply misleading.

Move all NXP stuff into a separate sub-menu.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-11 15:02:24 -05:00
Heinrich Schuchardt
c394e8d0ee Kconfig: clean up skipping low-level initialization
Put all entries for skipping low-level initialization into a sub-menu.
Use different titles for main U-Boot, SPL, TPL.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-01-11 15:02:24 -05:00
Heinrich Schuchardt
5f7a507eb3 Dockerfile: add package texinfo
In preparation of adding the infodocs target to our CI install the
prerequisite texinfo software package.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-11 15:02:24 -05:00
Qu Wenruo
11d5670125 fs/btrfs: handle data extents, which crosss stripe boundaries, correctly
[BUG]
Since btrfs supports single device RAID0 at mkfs time after btrfs-progs
v5.14, if we create a single device raid0 btrfs, and created a file
crossing stripe boundary:

  # mkfs.btrfs -m dup -d raid0 test.img
  # mount test.img mnt
  # xfs_io -f -c "pwrite 0 128K" mnt/file
  # umount mnt

Since btrfs is using 64K as stripe length, above 128K data write is
definitely going to cross at least one stripe boundary.

Then u-boot would fail to read above 128K file:

 => host bind 0 /home/adam/test.img
 => ls host 0
 <   >     131072  Fri Dec 30 00:18:25 2022  file
 => load host 0 0 file
 BTRFS: An error occurred while reading file file
 Failed to load 'file'

[CAUSE]
Unlike tree blocks read, data extent reads doesn't consider cases in which
one data extent can cross stripe boundary.

In read_data_extent(), we just call btrfs_map_block() once and read the
first mapped range.

And if the first mapped range is smaller than the desired range, it
would return error.

But since even single device btrfs can utilize RAID0 profiles, the first
mapped range can only be at most 64K for RAID0 profiles, and cause false
error.

[FIX]
Just like read_whole_eb(), we should call btrfs_map_block() in a loop
until we read all data.

Since we're here, also add extra error messages for the following cases:

- btrfs_map_block() failure
  We already have the error message for it.

- Missing device
  This should not happen, as we only support single device for now.

- __btrfs_devread() failure

With this bug fixed, btrfs driver of u-boot can properly read the above
128K file, and have the correct content:

 => host bind 0 /home/adam/test.img
 => ls host 0
 <   >     131072  Fri Dec 30 00:18:25 2022  file
 => load host 0 0 file
 131072 bytes read in 0 ms
 => md5sum 0 0x20000
 md5 for 00000000 ... 0001ffff ==> d48858312a922db7eb86377f638dbc9f
 ^^^ Above md5sum also matches.

Reported-by: Sam Winchenbach <swichenbach@tethers.com>
Signed-off-by: Qu Wenruo <wqu@suse.com>
2023-01-11 15:02:24 -05:00
Pali Rohár
3133651aa4 ata: Fix dependency for CONFIG_SATA_SIL
sata_sil.c is PCI driver and without CONFIG_PCI is building of U-Boot failing:

      LD      u-boot
    ld.bfd: drivers/ata/sata_sil.o: in function `sil_exec_cmd':
    drivers/ata/sata_sil.c:148: undefined reference to `dm_pci_phys_to_bus'
    ld.bfd: drivers/ata/sata_sil.o: in function `sil_pci_probe':
    drivers/ata/sata_sil.c:687: undefined reference to `dm_pci_get_bdf'
    ld.bfd: drivers/ata/sata_sil.c:691: undefined reference to `dm_pci_read_config16'
    ld.bfd: drivers/ata/sata_sil.c:701: undefined reference to `dm_pci_map_bar'
    ld.bfd: drivers/ata/sata_sil.c:704: undefined reference to `dm_pci_map_bar'
    ld.bfd: drivers/ata/sata_sil.c:713: undefined reference to `dm_pci_write_config16'
    ld.bfd: drivers/ata/sata_sil.c:717: undefined reference to `dm_pci_read_config16'
    ld.bfd: drivers/ata/sata_sil.o: in function `sil_cmd_identify_device':
    drivers/ata/sata_sil.c:256: undefined reference to `dm_pci_phys_to_bus'
    ld.bfd: drivers/ata/sata_sil.o: in function `sil_sata_rw_cmd':
    drivers/ata/sata_sil.c:330: undefined reference to `dm_pci_phys_to_bus'
    ld.bfd: drivers/ata/sata_sil.o: in function `sil_sata_rw_cmd_ext':
    drivers/ata/sata_sil.c:377: undefined reference to `dm_pci_phys_to_bus'
    make: *** [Makefile:1778: u-boot] Error 1

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-01-11 15:02:24 -05:00
Brandon Maier
bde4c49c17 test: compression: use ut_assert for errors
Use the ut_assert macros for more useful error messages.

Signed-off-by: Brandon Maier <brandon.maier@collins.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-11 15:02:24 -05:00
Brandon Maier
43b059884a test: compression: check with trailing garbage in input
The Linux kernel appends 4 bytes to the end of compressed kernel Images
containing the uncompressed image size. They are used to make
self-decompressing Images easier. However for archs that don't support
self-decompression, like ARM64, U-Boot must be able to decompress the
image with the garbage data.

The existing decompressors already support this. This unit test was
added while working on zstd support as upstream zstd will error if there
is garbage data in the input buffer, and special care was needed to
support this.

Signed-off-by: Brandon Maier <brandon.maier@collins.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-11 15:02:24 -05:00
David Oberhollenzer
bf48dde80a fs/squashfs: Only use export table if available
For a squashfs filesystem, the fragment table is followed by
the following tables: NFS export table, ID table, xattr table.

The export and xattr tables are both completely optional, but
the ID table is mandatory. The Linux implementation refuses to
mount the image if the ID table is missing. Tables that are no
present have their location in the super block set
to 0xFFFFFFFFFFFFFFFF.

The u-boot implementation previously assumed that it can always
rely on the export table location as an upper bound for the fragment
table, trying (and failing) to read past filesystem bounds if it
is not present.

This patch changes the driver to use the ID table instead and only
use the export table location if it lies between the two.

Signed-off-by: David Oberhollenzer <goliath@infraroot.at>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2023-01-11 15:02:24 -05:00
Marek Vasut
f08dcd9fd0 test: cmd: exit: Add unit test for exit and partly run commands
Add a test which validates that exit from environment script works as
expected, including return value propagation and clipping to positive
integers.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-11 15:02:24 -05:00
Marek Vasut
721307eba0 cmd: exit: Fix return value propagation out of environment scripts
Make sure the 'exit' command as well as 'exit $val' command exits
from environment scripts immediately and propagates return value
out of those scripts fully. That means the following behavior is
expected:

"
=> setenv foo 'echo bar ; exit 1' ; run foo ; echo $?
bar
1
=> setenv foo 'echo bar ; exit 0' ; run foo ; echo $?
bar
0
=> setenv foo 'echo bar ; exit -2' ; run foo ; echo $?
bar
0
"

As well as the followin behavior:

"
=> setenv foo 'echo bar ; exit 3 ; echo fail'; run foo; echo $?
bar
3
=> setenv foo 'echo bar ; exit 1 ; echo fail'; run foo; echo $?
bar
1
=> setenv foo 'echo bar ; exit 0 ; echo fail'; run foo; echo $?
bar
0
=> setenv foo 'echo bar ; exit -1 ; echo fail'; run foo; echo $?
bar
0
=> setenv foo 'echo bar ; exit -2 ; echo fail'; run foo; echo $?
bar
0
=> setenv foo 'echo bar ; exit ; echo fail'; run foo; echo $?
bar
0
"

Fixes: 8c4e3b79bd0 ("cmd: exit: Fix return value")
Reviewed-by: Hector Palacios <hector.palacios@digi.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-11 15:02:24 -05:00
Sean Anderson
f3d914cfdd fastboot: Add OEM run command
This adds the UUU UCmd functionality as an OEM command. While the
fastboot tool allows sending arbitrary commands as long as they are
prefixed with "oem". This allows running generic U-Boot commands over
fastboot without UUU, which is especially useful when not using USB.
This is really the route we should have gone in the first place when
adding these commands.

While we're here, clean up the UUU Kconfig a bit.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-01-11 15:02:24 -05:00
Patrick Delaunay
d037990046 fastboot: remove #ifdef CONFIG when it is possible
Much of the fastboot code predates the introduction of Kconfig and
has quite a few #ifdefs in it which is unnecessary now that we can use
IS_ENABLED() et al.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # on vim3l
2023-01-11 15:02:24 -05:00
Patrick Delaunay
59dacc3190 optee: bind the TA drivers on OP-TEE node
In U-Boot driver model the devices can be referenced by
phandle in the U-Boot configuration nodes.

Without a valid node provided during the bind, the driver
associated to OP-TEE TA can't be referenced.

For example to force the sequence number with alias
(.flags = DM_UC_FLAG_SEQ_ALIAS)

 	aliases {
		rng0 = &optee;
 	};

or other configuration:

board-sysinfo {
   compatible = "vendor,sysinfo-board";
   ramdom = <&optee>;
}

With this patch all drivers bound from OP-TEE service
discovery are now associated are associated to OP-TEE
node, allowing to identify by phandle the driver
provided by the TA for one UCLASS without modifying
device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-11 15:02:24 -05:00
Patrick Delaunay
1c44d10879 env: add failing trace in env_erase
Add trace in env save to indicate any errors to end user and avoid
silent output when the command 'env erase' is not executed as it is
done in env_save with commit 8968288cb477 ("env: add failing trace in
env_save")

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-01-11 15:02:24 -05:00
Patrick Delaunay
91fc785834 env: ubi: add support of command env erase
Add support of opts erase for ubi env backend, this opts is used by
command 'env erase'.

This command only zero-fill the env UBI volume CONFIG_ENV_UBI_VOLUME
and CONFIG_ENV_UBI_VOLUME_REDUND, so the saved environment becomes
invalid.

This patch introduces a local define ENV_UBI_VOLUME_REDUND
only to avoid #if in the code, as CONFIG_ENV_UBI_VOLUME_REDUND
is only defined when CONFIG_SYS_REDUNDAND_ENVIRONMENT is defined.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-01-11 15:02:24 -05:00
Max Krummenacher
e64289e1ec test: env: add test for u-boot-initial-env creation
Checks that `make u-boot-initial-env` creates the text file
u-boot-initial-env and checks that it at least contains
`board=<something>`.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-11 15:02:23 -05:00
Shenlin Liang
5b333b9324 cmd: change the return value when argc error
When the number of parameters is wrong, the return value should be processed in
the same way as other cmds, return CMD_RET_USAGE so that it can print the information.

Signed-off-by: Shenlin Liang <liangshenlin@eswincomputing.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-11 11:54:50 -05:00
Patrick Delaunay
6762c8dd89 cmd: mtdparts: add SYS_MTDPARTS_RUNTIME dependency on CONFIG_MTDIDS/MTDPARTS_DEFAULT
The two configuration CONFIG_MTDIDS_DEFAULT and CONFIG_MTDPARTS_DEFAULT
are not needed with mtd configuration CONFIG_SYS_MTDPARTS_RUNTIME which
allows the MTDIDS and MTDPARTS to be configured at runtime.

This patch has no defconfig impacts because CONFIG_SYS_MTDPARTS_RUNTIME
is only used by two platforms (stm32mp and igep00x0) which don't define
CONFIG_MTDIDS_DEFAULT or CONFIG_MTDPARTS_DEFAULT.

This patch solves an UBI environment load issue for NAND boot for
stm32mp15 platform. In mtd_uboot.c, when GD_FLG_ENV_READY is not set,
env_get_f() return a EMPTY string, define in default_environment[]
because CONFIG_MTDIDS_DEFAULT="" and CONFIG_MTDPARTS_DEFAULT="",
but a NULL pointer is expected to allow call of board_mtdparts_default.
Without mtdparts, the env partition [CONFIG_ENV_UBI_PART="UBI"] is not
found in env/ubi.c [CONFIG_ENV_IS_IN_UBI].

It is not a problem when env becomes ready, as these empty variables are
removed form U-Boot environment in env_import() / himport_r().

Fixes: a331017c237c ("Complete migration of MTDPARTS_DEFAULT / MTDIDS_DEFAULT, include in environment")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-11 11:54:50 -05:00
Haijun Qin
dd02c66790 lib: rsa: cosmetic: fix building warning
add initialization of variable 'node',this can aviod the building
warning:

    'node' may be used uninitialized [-Wmaybe-uninitialized]

Signed-off-by: Haijun Qin <qinhaijun@eswincomputing.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-11 11:54:50 -05:00
Sean Anderson
46b2e5e92c reboot-mode: Add NVMEM reboot mode
This adds an NVMEM reboot mode driver, similar to Linux's
implementation. This allows using the same device tree binding for Linux
and U-Boot in most cases.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-11 11:54:50 -05:00
Sean Anderson
546795b579 rtc: abx8xx: Add support for reading RAM
This adds support for reading the battery-backed memory present on these
RTCs. This modifies the read/write methods to access the RAM instead of
raw register offsets. No one was using these in-tree, so we should be
fine changing them.

We use the "standard" address space window to access the RAM. The
extension RAM address register has some reserved bits, but we write the
whole thing for simplicity (as these bits default to 0).

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2023-01-11 11:54:50 -05:00
Shenlin Liang
c9c42ad21f common:autoboot:modify function parameters
the blob parameter of the function process_fdt_options has not been
invoked in the function body and should be changed to void type

Signed-off-by: Shenlin Liang <liangshenlin@eswincomputing.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-11 11:54:49 -05:00
Tom Rini
ee4f86cc04 Merge branch '2023-01-10-platform-updates'
- Platform updates for TI, nuvoton pinctrl, starqltechn/sdm845 fixes,
  and assorted platform CONFIG_BUILD_TARGET corrections
2023-01-10 21:13:57 -05:00
Andrew Davis
367c9e0614 ARM: omap3: evm: Name this directory omap3evm
Before this was named just evm, which doesn't match the naming
of the other TI board file directory and makes it look like a
common directory for evms. Name this omap3evm.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Derald Woods <woods.technical@gmail.com>
2023-01-10 15:39:08 -05:00
Pali Rohár
f7f14cf027 powerpc/mpc85xx: Unset CONFIG_SPL_TARGET="u-boot-with-spl.bin"
CONFIG_SPL_TARGET should specify additional SPL make target. But
u-boot-with-spl.bin is final U-Boot binary, not SPL binary in some custom
format. Moreover u-boot-with-spl.bin is already set in CONFIG_BUILD_TARGET,
so make will build it by default.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-01-10 15:39:07 -05:00
Pali Rohár
e0025d9957 powerpc/mpc85xx: Set default CONFIG_BUILD_TARGET
Final U-Boot binary for mpc85xx boards which use SPL and are not PBL-based
based is u-boot-with-spl.bin. PBL is not used only on boards with e500v1
and e500v2 cores. Apparently CONFIG_E500 is set not only for e500 cores,
but also for all other mpc85xx cores e500mc, e5500 and e5600. So do not use
CONFIG_E500 and instead filter new cores with PBL based bootrom.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-01-10 15:39:07 -05:00
Pali Rohár
f0b1a1e13e arm: mvebu: Fix default CONFIG_BUILD_TARGET
u-boot-with-spl.kwb is built only for SPL enabled 32-bit armada boards.
u-boot.kwb is built for 32-bit armada and kirkwood boards but only for
non-SPL targets.

So replace CONFIG_ARCH_MVEBU by CONFIG_ARMADA_32BIT (it implies
CONFIG_ARCH_MVEBU) for u-boot-with-spl.kwb.

And add additional CONFIG_ARMADA_32BIT && !CONFIG_SPL for u-boot.kwb.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-01-10 15:39:07 -05:00
Dzmitry Sankouski
971ccee2fb SoC: sdm845: find and save KASLR to env variables
KASLR address is needed to boot fully functional Android.
KASLR is set by primary bootloader, and since u-boot is used
as a secondary bootloader(replacing kernel) on sdm845 platform,
KASLR may be found by comparing memory chunks at relocaddr over
supposed KASLR range.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-01-10 15:39:07 -05:00
Dzmitry Sankouski
40c69cc922 board: starqltechn: enable serial console
It was temporary disabled due to problem with boot.
Issue was fixed in
commit f5ed6c9ccf3e ("uart: sdm845: Fix debug UART pinmux")

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
2023-01-10 15:39:07 -05:00
Bryan Brattlof
221ae89bc8 configs: am62a: use kernel fitImage when using secure bootflow
In order to maintain the chain of trust, each stage of the boot process
will first authenticate each binary it loads before continuing. To
extend this to the kernal and its dtbs we can package the kernal and
its dtbs into another fitImage for Uboot to authenticate and extend the
chain of trust all the way to the kernel.

When 'boot_fit' is set, indicating we're using the secure bootflow, look
for and authenticate the kernel's fitImage.

Signed-off-by: Judith Mendez <jm@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-01-10 15:39:07 -05:00
Bryan Brattlof
e625bfe5ad configs: am62a: convert bootcmd to distro_bootcmd
We're currently using CONFIG_BOOTCOMMAND to run custom boot scripts to
jump into linux. While this works, let's begin the transition to more
distribution friendly jumps to linux by enabling distro_bootcmd.

Convert the custom bootcmd to a distro_bootcmd

Signed-off-by: Judith Mendez <jm@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-01-10 15:39:07 -05:00
Bryan Brattlof
b672e85810 arm: mach-k3: copy bootindex to OCRAM for main domain SPL
Texas Instruments has begun enabling security settings on the SoCs it
produces to instruct ROM and TIFS to begin protecting the Security
Management Subsystem (SMS) from other binaries we load into the chip by
default.

One way ROM and TIFS do this is by enabling firewalls to protect the
OCSRAM and HSM RAM regions they're using during bootup.

The HSM RAM the wakeup SPL is in is firewalled by TIFS to protect
itself from the main domain applications. This means the 'bootindex'
value in HSM RAM, left by ROM to indicate if we're using the primary
or secondary boot-method, must be moved to OCSRAM (that TIFS has open
for us) before we make the jump to the main domain so the main domain's
bootloaders can keep access to this information.

Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-01-10 15:39:07 -05:00
Bryan Brattlof
940b7128c9 configs: am62a: move stack and heap to HSM RAM
Texas Instruments has begun enabling security setting on the SoCs they
produce to instruct ROM and TIFS to begin protecting the Security
Management Subsystem (SMS) from other binaries we load into the chip by
default.

One way ROM does this is by enabling firewalls to protect the OCSRAM
region it's using during bootup. Only after TIFS has started (and had
time to disable the OCSRAM firewall region) will we have write access to
the region.

This means we will need to move the stack & heap from OCSRAM to HSM RAM
and reduce the size of BSS and the SPL to allow it to fit properly.

Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-01-10 15:39:07 -05:00
Bryan Brattlof
d12561211d configs: restrict am62ax wakup SPL size
In its current form, the am62a's wakeup SPL is fairly small, however
this will not remain as more boot modes are eventually added. To protect
us from overflowing our ~256k of HSM SRAM, add limits and check during
the wakeup SPL build.

Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-01-10 15:39:07 -05:00
Martyn Welch
83f5195e32 configs: Enable distroboot on am625
TI boards use a custom (though faily common to TI boards) mechanism for
booting Linux. We would like to use the "distroboot" approach.

Enable distroboot as a further option to use for booting on am625 should
the existing options fail.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2023-01-10 15:39:07 -05:00
Martyn Welch
7c34b71a42 arm64:mach-k3 am625_init: Correct boot mode detection
The boot mode detection assumes that BOOT_DEVICE_MMC2 should always
result in MMCSD_MODE_FS, but MMCSD_MODE_RAW is also a valid option for
this port.

The current logic also avoids looking at the bootmode pin strapping,
which should be the primary means of determining whether a device is
being booted in MMCSD_MODE_EMMCBOOT mode.

Switch around the logic to check the boot mode to determine whether the
eMMC boot mode is expected or MMC/SD boot mode. From there we can look
at the boot mode config if in MMC/SD boot mode to determine whether to
attempt RAW or FS based booting.

This change allows U-Boot to also be successfully booted from RAW
offsets in addition to from a filesystem.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2023-01-10 15:39:06 -05:00
Sjoerd Simons
92a15f69d5 configs: am62x_evm_a53: Enable ethernet
Enable ethernet support for u-boot on am62x evm

Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
2023-01-10 15:39:06 -05:00
Sjoerd Simons
39248d3260 arm: dts: k3-am625-sk: Enable first ethernet port
The K3 am625 sk EVM has two ethernet ports; Enable the first one for
usage in u-boot.

Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
2023-01-10 15:39:06 -05:00
Sjoerd Simons
21d39eb5a5 configs: am62x_evm_*: Run savedefconfig
Clean configuration for am62x_evm using savedefconfig

Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
Tested-by: Dhruva Gole <d-gole@ti.com>
2023-01-10 15:39:06 -05:00
Sjoerd Simons
a8ddc37ec3 configs: am62x_evm_*: Correct SPI configuration option
In f422c4bec the configuration option to support s28hs512t SPI flashes
was changed from CONFIG_SPI_FLASH_S28HS512T to CONFIG_SPI_FLASH_S28HX_T
to support the wider family. Follow this change in the AM62x EVM
configurations.

Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2023-01-10 15:39:06 -05:00
Jim Liu
7ee1c4d1d1 pinctrl: nuvoton: add NPCM7xx/NPCM8xx reset type detect
add reset type detect and persist setting.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-01-10 15:39:06 -05:00
Tom Rini
92bdaecf39 Merge branch '2023-01-10-env-mmc-improvements-and-corrections'
To quote the author:

Update in U-Boot env mmc backend with several cosmetic changes or
corrections and 2 new features:

1/ CONFIG_ENV_MMC_USE_DT = no more use CONFIG_ENV_OFFSET
   in the mmc ENV backend when this config is activated.

   Requested by the STM32MP STMicroelectronics boards which activate
   several ENV_IS_IN_XXX; the value of CONFIG_ENV_OFFSET is invalid for
   SD-Card / eMMC boot; this offset should only used in SPIFlash backend
   (sf.c) for SPI-NOR boot.

   If this offset is used on mmc backend, when partition name in GPT is
   not aligned with  U-Boot DT: "u-boot,mmc-env-partition", the behavior
   is difficult to debug: a partition is corrupted on 'env save' command.

2/ selects the GPT env partition by the "u-boot-env" type GUID introduced
   by the commit c0364ce1c695 ("doc/README.gpt: define partition
   type GUID for U-Boot environment")

   This feature can also avoid issue when 'u-boot-env' partition name
   change in GPT partitioning but not in the U-Boot DT with
   "u-boot,mmc-env-partition"
2023-01-10 14:49:32 -05:00
Patrick Delaunay
6a90e92564 env: mmc: cosmetic: remove unused macro STR(X)
Remove the unused macro STR(X) since the commit 2b2f727500dc ("env: mmc:
allow support of mmc_get_env_dev with OF_CONTROL")

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-10 12:37:09 -05:00
Patrick Delaunay
52e9aa3cd2 env: mmc: add debug message when mmc-env-partition is not found
Add a debug message to indicate a potential issue when
"u-boot,mmc-env-partition" is present in config node of device tree
but this partition name is not found in the mmc device.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-10 12:37:09 -05:00
Patrick Delaunay
80105d8fd5 env: mmc: select GPT env partition by type guid
Since commit c0364ce1c695 ("doc/README.gpt: define partition type GUID for
U-Boot environment"), a specific type GUID can be used to indicate
the U-Boot environment partition on the device with GPT partition table.

This patch uses this type GUID to found the env partition as fallback
when the partition name property "u-boot,mmc-env-partition" is not present
in config node or if the indicated partition name is not found.

The mmc_offset_try_partition() function is reused, it selects the first
partition with the correct type GUID when the parameter 'str' is NULL.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-10 12:37:09 -05:00
Patrick Delaunay
0902bcdbb3 configs: stm32mp: activate CONFIG_ENV_MMC_USE_DT
Activate by default CONFIG_ENV_MMC_USE_DT as "u-boot,mmc-env-partition"
should be always use in STMicroelectronics boards device tree to locate
the environment for mmc backend. The 2 defines:
  CONFIG_ENV_OFFSET=0x280000
  CONFIG_ENV_OFFSET_REDUND=0x2C0000
are only valid for spi-nor and not for SD-Card or eMMC.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-10 12:37:09 -05:00
Patrick Delaunay
d2103e20a9 env: mmc: add CONFIG_ENV_MMC_USE_DT
Add a new config CONFIG_ENV_MMC_USE_DT to force configuration of the
U-Boot environment offset with device tree config node.

This patch avoids issues when several CONFIG_ENV_IS_IN_XXX are activated,
the defconfig file uses the same value for CONFIG_ENV_OFFSET or
CONFIG_ENV_OFFSET_REDUND for the several ENV backends (SPI_FLASH, EEPROM
NAND, SATA, MMC).

After this patch a bad offset value is not possible when the selected
partition in device tree is not found.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-10 12:37:09 -05:00
Patrick Delaunay
8566050e24 env: mcc: fix compilation error with ENV_IS_EMBEDDED
When ENV_IS_EMBEDDED is enabled, ret is not defined but is used as a
return value in env_mmc_load().
This patch correct this issue and simplify the existing code, test only
one time #if defined(ENV_IS_EMBEDDED) and not in the function.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-10 12:37:09 -05:00
Patrick Delaunay
46c9016b7f env: mcc: Drop unnecessary #ifdefs
This file has a lot of conditional code and much of it is unnecessary.
Clean this up to reduce the number of build combinations.

This patch replaces the test on CONFIG_ENV_OFFSET_REDUND for the
more coherent CONFIG_SYS_REDUNDAND_ENVIRONMENT.

This patch also corrects a compilation issue in init_mmc_for_env()
when CONFIG_SYS_MMC_ENV_PART is not activated, env_mmc_orig_hwpart is
not defined.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-10 12:37:09 -05:00
Patrick Delaunay
f7e07a7ef4 env: mmc: introduced ENV_MMC_OFFSET
Introduce ENV_MMC_OFFSET defines.
It is a preliminary step to the next patches to simplify the code.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-01-10 12:37:09 -05:00
Tom Rini
7b84c973b9 ns16650: Correct CONFIG_SYS_NS16550_MEM32 platforms
There are currently no platform that are both CONFIG_SYS_NS16550_MEM32
and not (per how the logic was prior to being broken in 0478dac62a9a
("kbuild: Remove uncmd_spl logic")) enabled in CONFIG_DM_SERIAL. We drop
this line out now so that platforms which do use
CONFIG_SYS_NS16550_MEM32 and depending on stage may or may not have
DM_SERIAL set.

Fixes: 0478dac62a9a ("kbuild: Remove uncmd_spl logic")
Reported-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> #on Ringneck PX30, Puma RK3399
2023-01-09 11:30:49 -05:00
Tom Rini
cebdfc22da Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-09 11:30:08 -05:00
Tom Rini
62e2ad1cea Prepare v2023.01
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-09 11:07:33 -05:00
Jagan Teki
31500e7bcf board: rockchip: Fix binman_init failure on EVB-RK3568
For some newer SoCs like RK3568, the Rockchip has not released
any DDR drivers yet so idbloader needs to create manually using
DDR binaries offered by rkbin. This indeed no requirement to
enable TPL in the U-Boot source code.

If we mark TPL disabled and mark BINMAN enabled by default then
there would be an issue of binman_init failure during board
relocation. This is true as binman failed to find the top-level
node like u-boot-tpl here.

Here is the boot issue observed in Radxa-CM3 RK3566 board,

 U-Boot 2023.01-rc4-00057-gac2505d463-dirty (Jan 04 2023 - 23:44:18 +0530)

 Model: Radxa Compute Module 3(CM3) IO Board
 DRAM:  2 GiB
 binman_init failed:-2
 initcall sequence 000000007ffd2008 failed at call 0000000000a18cac (err=-2)
 ### ERROR ### Please RESET the board ###

This might be fixed via binman node in rockchip-u-boot.dtsi however
disable BINMAN_FDT for evb-rk3568 defconfig for now as we are at the
end of the release cycle.

Fixes: 05713d570762 ("rockchip: generate u-boot-rockchip.bin with binman
for ARM64 boards")
Cc: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-09 08:29:15 -05:00
Tom Rini
fe33066d24 Pull request for u-boot-nand-20230108
- rawnand: omap_gpmc: driver model support
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Merge tag 'u-boot-nand-20230108' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next

Pull request for u-boot-nand-20230108

- rawnand: omap_gpmc: driver model support
2023-01-08 13:12:42 -05:00
Marek Vasut
53e5b584e6 distro_bootcmd: Fix copy-paste error
The "SCRIPT FAILED" string is copied from scan_dev_for_scripts script,
update it so it prints "EXTLINUX FAILED" instead in scan_dev_for_extlinux
script.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-08 08:45:17 -05:00
Roger Quadros
7363cf0581 mtd: rawnand: omap_elm: u-boot driver model support
Support u-boot driver model. We still retain
support legacy way of doing things if ELM_BASE
is defined in <asm/arch/hardware.h>

We could completely get rid of that if all
platforms defining ELM_BASE get rid of that definition
and enable CONFIG_SYS_NAND_SELF_INIT and are verified
to work.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Link: https://lore.kernel.org/all/20221220102203.52398-9-rogerq@kernel.org
Link: https://lore.kernel.org/all/CABGWkvrvKiVA_yaDnHJcHEKwc+pEuLdz=i6HQEY0oJQvohCUsw@mail.gmail.com
2023-01-08 10:38:50 +01:00
Roger Quadros
8993d5f2ac dt-bindings: mtd: Add ti, elm DT binding documentation
Adds DT binding documentation for the TI Error Location Module.
This is picked up from the Linux Kernel.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221220102203.52398-8-rogerq@kernel.org
2023-01-08 10:38:50 +01:00
Roger Quadros
c2147bc7ec mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC
The symbol is required for NAND support in SPL when using
OMAP_GPMC driver.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221220102203.52398-7-rogerq@kernel.org
2023-01-08 10:38:50 +01:00
Roger Quadros
b747090705 mtd: rawnand: omap_gpmc: Add SPL NAND support
Enables SPL NAND support for ARCH_K3 by enabling
SPL_NAND_INIT and SPL_SYS_NAND_SELF_INIT.

Legacy OMAP2plus platforms still rely on SPL_NAND_AM33XX_BCH
instead.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221220102203.52398-6-rogerq@kernel.org
2023-01-08 10:38:50 +01:00
Roger Quadros
ff0d078942 mtd: rawnand: omap_gpmc: support u-boot driver model
Adds driver model support.

We need to be able to self initialize the NAND controller/chip
at probe and so enable CONFIG_SYS_NAND_SELF_INIT.

Doing so requires nand_register() API which is provided by nand.c
and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT.
But nand.c also provides nand_init() so we need to get rid of nand_init()
in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221220102203.52398-5-rogerq@kernel.org
2023-01-08 10:38:50 +01:00
Roger Quadros
dbb8711530 dt-bindings: mtd: Add ti, gpmc-nand DT binding documentation
Add DT binding documentation for the TI GPMC NAND controller.
This is picked up from the Linux Kernel.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221220102203.52398-4-rogerq@kernel.org
2023-01-08 10:38:50 +01:00
Roger Quadros
fa87360b3a mtd: rawnand: nand_base: Allow base driver to be used in SPL without nand_bbt
nand_bbt.c is not being built with the nand_base driver during SPL
build. This results in build failures if we try to access any nand_bbt
related functions.

Don't use any nand_bbt functions for SPL build.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221220102203.52398-3-rogerq@kernel.org
2023-01-08 10:38:30 +01:00
Roger Quadros
04fcd25873 mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction
The BCH detection hardware can generate ECC bytes for multiple
sectors in one go. Use that feature.

correct() only corrects one sector at a time so we need to call it
repeatedly for each sector.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221220102203.52398-2-rogerq@kernel.org
2023-01-08 10:33:20 +01:00
Tom Rini
051f409d25 pylibfdt: Allow version normalization to fail
In some cases, we might not have the sic portion of setuputils
available. Make our import and use of this be done in try/except blocks
as this is done to suppress a run-time warning that is otherwise
non-fatal.

Reported-by: Pali Rohár <pali@kernel.org>
Fixes: 141659187667 ("pylibfdt: Fix disable version normalization")
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-01-07 18:02:26 -05:00
Pali Rohár
d1f4b090dd common/memsize.c: Check for overflow in get_effective_memsize() only for mpc85xx
This reverts commit 777aaaa706bc ("common/memsize.c: Fix
get_effective_memsize() to check for overflow") for non-mpc85xx platforms.

The changes to this generic function, which is intended to help with
32bit platforms with large amounts of memory has unintended side effects
(which in turn lead to boot failures) on other platforms which were
previously functional.

For now do overflow check only for powerpc mpc85xx platform. It is needed
to prevent crashing of P1/P2 boards with 4GB DDR module in 32-bit mode.

Fixes: 777aaaa706bc ("common/memsize.c: Fix get_effective_memsize() to check for overflow")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-01-07 18:01:53 -05:00
Tom Rini
be914b00df Pull request efi-2023-01-rc5-4
UEFI:
 
 * correct the vexpress loaddr which collides with memory used by EFI
 * consider the EFI memory map for LMB memory reservation
 * avoid RWX section warnings for .data section of *_efi.so files
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Merge tag 'efi-2023-01-rc5-4' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request efi-2023-01-rc5-4

UEFI:

* correct the vexpress loaddr which collides with memory used by EFI
* consider the EFI memory map for LMB memory reservation
* avoid RWX section warnings for .data section of *_efi.so files
2023-01-07 12:32:42 -05:00
Heinrich Schuchardt
4bba71ff83 efi_loader: make .data section of *_efi.so files RW
When building with binutils 2.39 warnings

    *_efi.so has a LOAD segment with RWX permissions

occur.

Use SHF_WRITE | SHF_ALLOC as section flags for the .data section.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-01-06 22:27:30 +01:00
Heinrich Schuchardt
06d514d77c lmb: consider EFI memory map
Add reservations for all EFI memory areas that are not
EFI_CONVENTIONAL_MEMORY.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-06 22:27:30 +01:00
Heinrich Schuchardt
eff4440195 efi_loader: carve out efi_get_memory_map_alloc()
Carve out code from efidebug command used to read the memory map.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-06 22:27:30 +01:00
Heinrich Schuchardt
f4af97cdb4 vexpress: adjust loadaddr
On the vexpress_ca9x4 $loadaddr points to a memory area used by the EFI
sub-system. Use the same value as $kernel_addr_r which is safe.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-06 22:27:30 +01:00
Tom Rini
b82f12b642 First set of u-boot-at91 features for the 2023.04 cycle
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Merge tag 'u-boot-at91-2023.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next

First set of u-boot-at91 features for the 2023.04 cycle:

This feature set includes the new DM-based NAND flash driver (old non-DM
driver is still kept for backwards compatibility), and the move to DM
NAND flash driver for sam9x60ek board. Feature set also includes
devicetree alignment for sama7g5 with Linux, devicetree alignment on USB
with Linux for all boards (sama5, sam9x60), chip id for sama7g5, minor
configs and tweaks.
2023-01-06 11:53:26 -05:00
Tom Rini
9ddcdcc03c - stm32mp: Fix board_get_usable_ram_top(): workaround to avoid issue after the
commit 777aaaa706b ("common/memsize.c: Fix get_effective_memsize() to check
   for overflow") because the effective DDR effective size is reduce by 4KiB
   and sometime the board hang on boot
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Merge tag 'u-boot-stm32-20230106' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- stm32mp: Fix board_get_usable_ram_top(): workaround to avoid issue after the
  commit 777aaaa706b ("common/memsize.c: Fix get_effective_memsize() to check
  for overflow") because the effective DDR effective size is reduce by 4KiB
  and sometime the board hang on boot
2023-01-06 08:16:15 -05:00
Tom Rini
bd7fbd58b7 Merge branch '2023-01-06-further-regression-fixes'
- Bring in a number of important regression fixes for among others,
  uniphier, PXE booting, socrates, imx7d-pico, rockchip video and
  rzg2_beacon as well as making the python version warning fix more
  portable.
2023-01-06 08:14:28 -05:00
Adam Ford
5404dfcc4d arm: rmobile: rzg2_beacon: Enable alternative Ethernet PHY
Due to the part shortage, the AR8031 PHY was replaced with a
Micrel KSZ9131. Enabling both config options keeps backward
compatibility with either platform, and both appear to be
auto-detected.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2023-01-06 08:14:19 -05:00
Adam Ford
edd9c891d2 arm: dts: rz-g2-beacon-u-boot: Fix QSPI Regression
The QSPI is accessed via the RPC-IF, but the compatible flags
previously used a different name.  This compatibel name was changed
which broke the ability to access the QSPI.  Fix this by removing
the custom naming reference.

Fixes: 68083b897b57 ("renesas: Fix RPC-IF compatible values")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2023-01-06 08:14:19 -05:00
Philippe Schenker
1416591876 pylibfdt: Fix disable version normalization
On Arch Linux based systems python setuptools does not contain
"setuptools.extern" hence it is failing with the following
error-message:
"
ModuleNotFoundError: No module named 'setuptools.extern'
"

According to a eschwartz `setuptools.extern` is not a public API and
shall not be assumed to be present in the setuptools package. He
mentions that the setuptools project anyway wants to drop this. [1]

Use the correct solution introduced by python setuptools developers to
disable normalization. [2]

[1] https://bbs.archlinux.org/viewtopic.php?id=259608
[2] https://github.com/pypa/setuptools/pull/2026
Fixes: 440098c42e73 ("pylibfdt: Fix version normalization warning")
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-06 08:14:19 -05:00
Marek Vasut
519e6641db cmd: pxe_utils: Limit fdtcontroladdr usage to non-fitImage
Commit d5ba6188dfb ("cmd: pxe_utils: Check fdtcontroladdr in label_boot")
forces '$fdtcontroladdr' DT address as a third parameter of bootm command
even if the PXE transfer pulls in a fitImage which contains configuration
node with its own DT that is preferrable to be passed to Linux. Limit the
$fdtcontroladdr fallback utilization to non-fitImages, since it is highly
likely a fitImage would come with its own DT, while single-file images do
need a separate DT.

Fixes: d5ba6188dfb ("cmd: pxe_utils: Check fdtcontroladdr in label_boot")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Tested-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Peter Hoyes <peter.hoyes@arm.com>
Tested-by: Peter Hoyes <peter.hoyes@arm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-06 08:14:19 -05:00
Marek Vasut
bee3551e00 Revert "Revert "cmd: pxe_utils: Check fdtcontroladdr in label_boot""
This reverts commit ed6251187afabf811a5fd49a44ebd61c53c7b378.

Superseded by "cmd: pxe_utils: Limit fdtcontroladdr usage to non-fitImage"
which is less heavy-handed approach and retains part of the original
behavior for non-fitImage.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-06 08:14:19 -05:00
Jagan Teki
ab644db9ba rockchip: Fix the broken Video out for rk3288 boards
Video out on RK3288 boards has been broken since from few
releases due to the adding of reset support on vop but
missed enabling DM_RESET on associated boards.

This patch fixes those RK3288 boards.

Cc: Simon Glass <sjg@chromium.org>
Cc: Lin Huang <hl@rock-chips.com>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
Fixes: <9749d2ea29e1> ("rockchip: video: vop: Add reset support")
Reported-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-06 08:14:19 -05:00
Dai Okamura
4671435c54 i2c: uniphier-f: correct error recovery
The uniphier i2c block can recognize some handshake errors.
But driver handles all error detections as no error if no timeout.
So this makes unrecoverable state.

This replaces the return values with the right ones to tell the i2c
framework the errors:
- EDEADLK for arbitration lost error
- ENODATA for no answer error

Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-01-06 08:14:19 -05:00
Fabio Estevam
f8548ce0e0 imx7d-pico: Fix the name of the u-boot.dtsi file
Since commit 2f96d4dd95f8 ("imx7s/d: synchronise device trees with linux")
the imx7d-pico board no longer boots.

The reason is that prior to the above commit there was an explicit
inclusion of arch/arm/dts/imx7d-pico-u-boot.dtsi inside imx7d-pico.dtsi.

After the syncing with the Linux upstream dtsi, this u-boot.dtsi inclusion
is gone and the board fails to boot.

U-Boot uses the imx7d-pico-pi.dtb file, so rename the u-boot.dtsi to
imx7d-pico-pi-u-boot.dtsi which gets included automatically by U-Boot
standard make logic and makes the board boot again.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-01-06 08:14:19 -05:00
Pali Rohár
1b697407ae powerpc/mpc85xx: socrates: Re-enable building u-boot-socrates.bin
U-Boot build system builds final U-Boot binary for socrates board in custom
file u-boot-socrates.bin (instead of standard u-boot.bin). Output target
file u-boot-socrates.bin is generated by binman as defined in board binman
config file arch/powerpc/dts/socrates-u-boot.dtsi.

But binman was disabled in commit 5af42eafd7e1 ("Makefile: Reduce usage of
custom mpc85xx u-boot.bin target") for all mpc85xx boards which do not use
standard powerpc binman config file arch/powerpc/dts/u-boot.dtsi and boards
which do not require binman at all.

The only such mpc85xx board is socrates. So since that commit, U-Boot does
not final binary for socrates board anymore.

Fix this issue by re-enabling binman for socrates board. And build process
starts again producing u-boot-socrates.bin binary.

Note that build process for this socrates board always produce u-boot.bin
binary which is broken and not usable for socrates board. Long term
solution should be to disable building broken binary u-boot.bin and then
renaming u-boot-socrates.bin to u-boot.bin, or switching to use common
powerpc binman config file arch/powerpc/dts/socrates-u-boot.dtsi (if it is
possible).

Fixes: 5af42eafd7e1 ("Makefile: Reduce usage of custom mpc85xx u-boot.bin target")
Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Heiko Schocher <hs@denx.de>
2023-01-06 08:14:19 -05:00
Marek Vasut
a2e0b041d6 arm: stm32mp: Fix board_get_usable_ram_top() again
Do not access gd->ram_size and assume this is actual valid RAM size. Since commit
777aaaa706b ("common/memsize.c: Fix get_effective_memsize() to check for overflow")
the RAM size may be less than gd->ram_size , call get_effective_memsize() to get
the limited value instead.

The aforementioned commit makes STM32MP15xx boards with 1 GiB of DRAM
at 0xc0000000 hang on boot, which is a grave defect.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-01-06 11:02:17 +01:00
Tom Rini
b63905cfc6 patman enhancements and fixes
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Merge tag 'dm-next-5jan23' of https://source.denx.de/u-boot/custodians/u-boot-dm into next

patman enhancements and fixes
2023-01-05 22:54:26 -05:00
Maxim Cournoyer
8c042fb7f9 patman: add '--get-maintainer-script' argument
This makes it possible to configure a project to use some other
location or script than the default scripts/get_maintainer.pl one used
in the U-Boot and Linux projects. It can be configured via a .patman
configuration file and accepts arguments, as documented.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
8f8d3f72f2 patman: additionally honor a local .patman config file
This enables versioning a project specific patman configuration file.
It also makes it possible to declare the project name, which is not a
useful thing to do in $HOME/.patman.  A new test is added, along
updated documentation.

Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
db16edd8ce patman: fail early in Setup when provided config file does not exist
Rationale: if the user explicitly provide this argument, they probably
intend for it to be used.

Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
2c58a5e275 patman: set the default config_fname argument value to None
This better matches Python conventions, allowing to easily test
whether the optional argument is provided.

Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
57e3b03fe1 patman: import gitutil module where it is needed
Instead of propagating it from the module entry point (main script).

Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
8b73f9bf9e patman: replace deprecated SafeConfigParser with ConfigParser
The SafeConfigParser class has been renamed in Python 3.2 to
ConfigParser, and the old alias has been deprecated since.

Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
872f3a4ce2 patman: fix pep8 warnings in settings module
Remove extraneous imports, variables and comply to PEP 8 maximum line
width, among other PEP 8 changes suggested by Pyflake.

Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
3052930714 patman: document default 'send' command
Document that this command is the default and what it's intended for.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
f393f59e5d patman: document how to run test suite via pytest
Pytest offers useful features such as selecting tests by means of a
regular expression, or running the pdb debugger upon encountering a
test failure.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
52c1c333ea patman: hide the 'test' command unless test data is available
Some tests would fail when the test data is not available, so it
doesn't make much sense to expose the action when patman is running
outside of the u-boot git checkout.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
a3997a0a00 patman: add pytest configuration file
With this change, a user can run the patman test suite using Pytest
the same as when using 'patman test':

    $ cd tools/patman && pytest
    [...]
    44 passed, 8 warnings in 8.87s

    $ ./patman test
    Ran 44 tests in 8.460s

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
579916beb1 patman: rename main script to __main__.py
This allows running the package as a Python module, like e.g.:

    $ python -m patman

It also prevents Pytest from attempting to parse main.py, which
would cause errors.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
Fix up main.py in __init__.py:
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
648d8186dd patman: invoke the checkpatch.pl script with '--u-boot' and '--strict'
This resolves 10 out of 11 test failures seen when running './patman
test' from the 'tools/patman' subdirectory. This was caused by the
.checkpatch.conf configuration file at the root of the project not
being picked up. Make the test suite of patman independent from it by
always invoking the checkpatch.pl script with the minimally required
arguments for the test suite to pass.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
1c77598402 patman: locate test data files via __file__ and pathlib
Previously it would rely on the executing script location, which could
break for example when running the tests via 'pytest'.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
f9e20e3bff patman: cosmetic: Fix PEP 8 warnings for the gitutil module.
This patch fixes all the PEP 8 warnings reported by Pyflake for the
gitutil module.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
a5197fc9c3 patman: locate README.rst via importlib
Rationale: this is more robust than assumptions about the file
hierarchy layout of the installation of patman, for example on non
file-hierarchy standard (FHS) systems such as Guix System or Nix OS.

Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-05 19:21:57 -07:00
Maxim Cournoyer
425bbed247 patman: fix installation of README.rst data file
This fixes a regression introduced in commit 74df491051d6 ("buildman:
Convert documentation to rST").

Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-05 19:21:56 -07:00
Maxim Cournoyer
291ab6c74c patman: remove extraneous imports
* tools/patman/main.py: Remove extraneous imports and fix indentation.

Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-05 19:21:56 -07:00
Yuepeng Xing
7943ae241c test:dm:fix typo
Fix typos in the 'test/dm' directory.

Signed-off-by: Yuepeng Xing <xingyuepeng@eswincomputing.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-05 19:21:56 -07:00
Sean Anderson
e0ddd895f6 patman: Switch to setuptools
distutils is about to meet its demise [1]. Switch to setuptools.

[1] https://peps.python.org/pep-0632/

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-05 19:21:56 -07:00
Sergiu Moga
61040097a9 reset: at91: Add reset driver for basic assert/deassert operations
Add support for at91 reset controller's basic assert/deassert
operations. Since this driver conflicts with the
SYSRESET driver because they both bind to the same RSTC node,
implement a custom bind hook that would manually bind the
sysreset driver, if enabled, to the same RSTC DT node.
Furthermore, delete the no longer needed compatibles from the
SYSRESET driver and rename it to make sure than any possible
conflicts are avoided.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Tested-by: Mihai Sain <mihai.sain@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-01-05 10:06:35 +02:00
Cristian Birsan
11c037ab92 ARM: at91: add sama7 SFR definitions
Special Function Registers(SFR) definitions for SAMA7 product family.

Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:06:09 +02:00
Sergiu Moga
e4ad98d67b ARM: dts: sama5d27_wlsom1_ek: Add pinctrl nodes for USB DT nodes
Add the pinctrl nodes required by the USB related DT nodes.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
20bc95f8c8 ARM: dts: sama5d2_icp: Add pinctrl nodes for USB related DT nodes
Add the pinctrl subnodes required by the USB related DT nodes.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
3cd06bfa96 ARM: dts: sama7g5ek: Add pinctrl, gpio and phy properties for USB
Add the required pinctrl, gpio and phy properties required by the
USB DT nodes of the sama7g5ek boards. Since these have not yet been
defined in upstream Linux, place them in the U-Boot specific DT file.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
851960e591 ARM: dts: sama7g5: Add USB and UTMI DT nodes
Define the USB and UTMI DT nodes for the sama7g5 SoC's. Since these have
not yet been defined in upstream Linux, place them in the U-Boot specific
DT file.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-01-05 10:04:57 +02:00
Sergiu Moga
ee25ed5899 dt-bindings: clk: at91: Define additional UTMI related clocks
Add definitions for an additional main UTMI clock as well as its
respective subclocks.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
7b88887ba7 dt-bindings: reset: add sama7g5 definitions
Upstream linux commit 5994f58977e0.

Add reset bindings for SAMA7G5. At the moment only USB PHYs are
included.

The three reset USB phy's have their ID's mapped from 4 to 6. There are
no USB phy's with ID's numbered from 0 to 3.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
205ecbdccd ARM: dts: sam9x60ek: Add pinctrl and gpio properties for USB
Add the required pinctrl and gpio properties required by the USB DT
nodes of the sam9x60ek boards.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
445ff8bb5a ARM: dts: sam9x60_curiosity: Add pinctrl and gpio properties for USB
Add the required pinctrl and gpio properties needed by the USB DT nodes
of the sam9x60_curiosity boards.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
2023-01-05 10:04:57 +02:00
Sergiu Moga
3631be3ed6 ARM: dts: sam9x60: Add OHCI and EHCI DT nodes
Add the OHCI and EHCI DT nodes for the sam9x60 SoC's.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2023-01-05 10:04:57 +02:00
Tom Rini
8d6cbf5e6b Pull request for efi-2023-01-rc5-3
Documentation:
 
 * Describe building documentation
 
 UEFI:
 
 * Add .data section to aarch64 EFI binaries and correct section flags
 * Correct sorting of capsules when updating
 * Populate console handles in system table
 
 Other:
 
 * Fix description of eth_env_[gs]et_enetaddr() return value
 * Avoid endless loop in sound play command
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Merge tag 'efi-2023-01-rc5-3' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2023-01-rc5-3

Documentation:

* Describe building documentation

UEFI:

* Add .data section to aarch64 EFI binaries and correct section flags
* Correct sorting of capsules when updating
* Populate console handles in system table

Other:

* Fix description of eth_env_[gs]et_enetaddr() return value
* Avoid endless loop in sound play command
2023-01-04 08:50:24 -05:00
Heinrich Schuchardt
60bba6e205 efi_loader: populate console handles in system table
The fields ConsoleInHandle, ConsoleOutHandle, ConsoleErrHandle must point
to the handles with the respective console protocols. Failure to do so
leads to an error in the EFI Shell:

    No SimpleTextInputEx was found. CTRL-based features are not usable.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-01-04 13:17:42 +01:00
Heinrich Schuchardt
93cdb95238 efi_loader: adjust sorting of capsules
Up to now we only compared the first letter of the capsule name to sort
them alphabetically. Properly sort by the Unicode alphabet.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-04 13:17:42 +01:00
Heinrich Schuchardt
07355760b1 test: unit test for u16_strcasecmp()
Provide a unit test for u16_strcasecmp().

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-04 13:17:42 +01:00
Heinrich Schuchardt
7a9b366cd9 lib: add function u16_strcasecmp()
Provide a function for comparing UTF-16 strings in a case insensitive
manner.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-04 13:17:42 +01:00
Heinrich Schuchardt
d7ddeb66a6 efi_loader: fix building aarch64 EFI binaries
While our EFI binaries execute without problems on EDK II they crash on
a Lenovo X13s. Let our binaries look more like what EDK II produces:

* move all writable data to a .data section
* align sections to 4 KiB boundaries (matching EFI page size)
* remove IMAGE_SCN_LNK_NRELOC_OVFL from .reloc section flags

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-01-04 13:17:42 +01:00
Heinrich Schuchardt
673a92c5d2 efi_loader: defines for PE-COFF section flags
Provide constants for the section flags used by binaries.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-01-04 13:17:42 +01:00
Marek Vasut
fbc595b412 doc: Fix eth_env_[gs]et_enetaddr() return value
Per env/common.c, eth_env_get_enetaddr() returns the same return
values as is_valid_ethaddr(), i.e. true if valid, false otherwise.
Per env/common.c, eth_env_set_enetaddr() may return -EEXIST is the
ethaddr is already set. Fix both.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-04 13:17:42 +01:00
Heinrich Schuchardt
566b7b2f51 doc: building documentation
Provide a man-page describing how to build the U-Boot documentation.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-01-04 13:17:42 +01:00
Heinrich Schuchardt
532952f63c cmd: avoid endless loop in sound play command
A parameter starting with a hyphen leads to an endless loop in the sound
play command.

Leave it to dectoul() to handle the hyphen. It will return 0 for a negative
number.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-04 13:17:42 +01:00
Mihai Sain
8a2f52f44a configs: sam9x60: add mmc config for sdmmc1
Add new config for storing environment from SDMMC1.

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2023-01-04 09:28:04 +02:00
Mihai Sain
77aa6456bf board: at91: sam9x60: set blue led on at boot time
Set blue led on at boot time in order to highlight that u-boot is loaded.
This is done for all sam9x60 based boards which contain an RGB led.

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2023-01-04 09:28:04 +02:00
Mihai Sain
ee43b1e744 ARM: dts: at91: sam9x60: add sdhci1 node and pinctrl
Add node for sdhci1 controller and its pinctrl.

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2023-01-03 10:58:15 +02:00
Tom Rini
a95410696d Merge branch '2023-01-02-platform-updates' into next
- Synquacer updates / fixes, PowerPC keymile platform dts fix, assorted
  TI platform updates, ht1380 RTC driver, serial driver cleanups,
  pg_wcom defconfig updates, s5p4418 DM_SERIAL (and legacy code removal).
2023-01-02 18:07:41 -05:00
Stefan Bosch
28663622cf arm: s5p4418: dm_serial: remove old code / add DEBUG_UART
Remove init of UART-clock and UART-reset in arch_cpu_init(). Add DEBUG_UART
to s5p4418_nanopi2_defconfig.

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2023-01-02 16:06:08 -05:00
Stefan Bosch
5745de2c9d arm: s5p4418: dm_serial: switch to DM_SERIAL
Switch the S5P4418-SOC and therefore the s5p4418_nanopi2 board to
DM_SERIAL.

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2023-01-02 16:06:08 -05:00
Stefan Bosch
c8ba27f760 arm: s5p4418: dm_serial: add uarts to dts
Add S5P4418 UARTs and appropriate pinctrl to dts. Add UART to
s5p4418-nanopi2.dts.

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2023-01-02 16:06:08 -05:00
Stefan Bosch
5ec6cbcc7f arm: s5p4418: dm_serial: add driver source code
Add dm_serial driver source code for S5P4418 SOC. Extend the "arm,pl011"
driver by init of UART-clock and UART-reset.

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2023-01-02 16:06:08 -05:00
Holger Brunck
bfd4e660de board/pg_wcom: rework defconfig
Switch off SCSI related config options to get rid of the board
removal warning. We don't use this interface. Also disable UBIFS
to decrease the image size, as this is also not used.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2023-01-02 16:06:08 -05:00
Neha Malcom Francis
9f393a2d7a board: ti: common: board_detect: Fix EEPROM read quirk for 2-byte
EEPROM detection logic in ti_i2c_eeprom_get() involves figuring out
whether addressing is 1-byte or 2-byte. There are currently different
behaviours seen across boards as documented in commit bf6376642fe8
("board: ti: common: board_detect: Fix EEPROM read quirk"). Adding to
the list, we see that there are 2-byte EEPROMs that read properly
with 1-byte addressing with no offset.

For ti_i2c_eeprom_am6_get where eeprom parse operation is dynamic, the
earlier commit d2ab2a2bafd5 ("board: ti: common: board_detect: Fix
EEPROM read quirk for AM6 style data") tried to resolve this by running
ti_i2c_eeprom_get() twice. However this commit along with its former
commit fails on J7 platforms where EEPROM successfully return back the
header on 1-byte addressing and continues to do so until an offset is
introduced. So the second read incorrectly determines the EEPROM as
1-byte addressing.

A more generic solution is introduced here to solve
this issue: 1-byte read without offset and 1-byte read with offset. If
both passes, it follows 1-byte addressing else we proceed with 2-byte
addressing check.

Tested on J721E, J7200, DRA7xx, AM64x

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Fixes: d2ab2a2bafd5 (board: ti: common: board_detect: Fix EEPROM read quirk for AM6 style data)
Fixes: bf6376642fe8 (board: ti: common: board_detect: Fix EEPROM read quirk)
Tested-By: Matwey V. Kornilov <matwey.kornilov@gmail.com>
2023-01-02 16:06:07 -05:00
Lokanathan, Raaj
357c352cdc Add CONFIG_SYS_NAND_SELF_INIT to Kconfig for NAND DENALI driver
Add the CONFIG_SYS_NAND_SELF_INIT to the Kconfig to follow the changes from
mainline.

Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
2023-01-02 16:01:40 -05:00
Pali Rohár
1138bbe05e serial: Use -EAGAIN in getc and putc
U-Boot serial code already handles -EAGAIN value from getc and putc
callbacks. So change drivers code to return -EAGAIN when HW is busy instead
of doing its own busy loop and waiting until HW is ready.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-01-02 16:01:40 -05:00
Pali Rohár
59440d83d3 serial: Do not write additional \r before \n for dm_serial drivers
serial-uclass.c code already puts \r before \n for all dm_serial drivers.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-02 16:01:40 -05:00
Sergei Antonov
fcb624be47 rtc: add ht1380 driver
Support Holtek HT1380/HT1381 Serial Timekeeper Chip. It provides seconds
, minutes, hours, day of the week, date, month and year information.

Datasheet:
https://www.holtek.com.tw/documents/10179/11842/ht1380_1v130.pdf

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-02 16:01:40 -05:00
Dai Okamura
872413bb0a arm: uniphier: use DM_TIMER of arm a9 global timer
All uniphier v7 SoCs have cortex-a9 and use cortex-a9 global timer
in a simple implementation. Now DM_TIMER of it is available
on 35751c7f3f ("timer: sti: convert sti-timer to arm a9 global timer"),
so let's switch to it.

The old driver reads the lower 32bits of counter field
and sets the prescaler as 50 with PERIPHCLK(=50MHz),
so the global timer works as a 32-bit 1MHz timer.

The DM_TIMER uses the whole 64bits with no prescaler,
so the global timer works as a 64-bit PERIPHCLK timer.

CONFIG_SYS_HZ_CLOCK is set as the default PERIPHCLK frequency,
if there is no 'clocks' property in devicetree.

Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
2023-01-02 16:01:39 -05:00
Dai Okamura
ef75d482aa pinctrl: uniphier: add ethernet TX pin data for PXs3
PXs3 Ref boards need to change the strength of ethernet ports
for stability, like LD20's one.

This adds the table data and fixes the boot issue on PXs3 Ref board.

Fixes: 0852033309 ("ARM: uniphier: sync with Linux 5.8-rc4")
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
2023-01-02 14:10:23 -05:00
Dai Okamura
1e91a0ea32 pinctrl: uniphier: add check if pins are valid
The pinctrl datas of uniphier SoCs are the minimal subsets of kernel's one,
and some tables has no data to save the footprint size.
If the board dts tries to match a pin name on no pins defined SoC,
the footprint magic code causes "Synchronous Abort".

This checks if the 'pins' data is valid,
and if empty, avoids the abort with the warning as follows:

  WARNING at drivers/pinctrl/uniphier/pinctrl-uniphier-core.c:36/uniphier_pinctrl_get_pins_count()!
  pinctrl_select_state_full: pinctrl_config_one: err=-38

Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
2023-01-02 14:10:23 -05:00
Rob Herring
bd8851c5b4 dts: synquacer: Drop unused and undocumented GPIO 'base' property
The 'base' GPIO controller property is unused in u-boot and Linux. It is
also not documented in the binding. So drop it.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2023-01-02 14:10:23 -05:00
Rob Herring
36ee37632c dts: synquacer: Drop unused and undocumented SPI properties
'active_clk_edges' and 'chipselect_num' SPI controller properties are
unused in u-boot and Linux. They are also not documented in the binding.
So drop them.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2023-01-02 14:10:23 -05:00
Pali Rohár
499fe577c8 powerpc: dts: keymile: Deduplicate binman code
kmcent2-u-boot.dtsi file contains copy of powerpc u-boot.dtsi binman file.
So remove code duplication and replace it by including u-boot.dtsi file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-01-02 14:06:31 -05:00
Rob Herring
00723684e4 dts: synquacer: Fix idle-states 'entry-method' value
The correct value for 'entry-method' in the idle-states binding is 'psci',
not 'arm,psci'. It hasn't mattered because it isn't used by the OS.

Signed-off-by: Rob Herring <robh@kernel.org>
2023-01-02 14:05:44 -05:00
Rob Herring
563f238b67 dts: synquacer: Fix "arm, armv7-timer-mem" node address sizes
The "arm,armv7-timer-mem" schema defines the address sizes for child
nodes to be 32-bit as there's no need for 64-bit offsets and sizes of
the child 'frame' nodes.

Signed-off-by: Rob Herring <robh@kernel.org>
2023-01-02 14:05:44 -05:00
Rob Herring
cc891c41f2 dts: synquacer: Use generic node names
DT node names should follow generic names defined in the DT spec. These
are also now checked by dtschema tools.

Signed-off-by: Rob Herring <robh@kernel.org>
2023-01-02 14:05:44 -05:00
Rob Herring
6136c85ed0 dts: synquacer: Drop CPU 'arm,armv8' compatibles
'arm,armv8' compatible is for software models only. so drop it from cpu
nodes.

Signed-off-by: Rob Herring <robh@kernel.org>
2023-01-02 14:05:43 -05:00
Christian Gmeiner
e93efaf9cc arm: dts: ti: k3-am64-mcu: Add pinctrl
Add the definition of the pinctrl for the MCU domain.

Same as kernel commit 500e6dfbb465531150ac6e2ff0856dd357ddc8a4

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2023-01-02 14:05:43 -05:00
Tom Rini
582e3c9fb2 Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- orion-timer: Fix problem with early static variable (Stefan)
2023-01-02 09:36:13 -05:00
Stefan Roese
5387b093cb timer: orion-timer: Fix problem with early static variable
We've noticed that at least one Kirkwood board (Pogo v4) has problems
with the new orion DM timer implementation. Debugging revealed that this
issue is related with the static variable "early_init_done" which does
not work correctly before relocation in all cases.

This patch removes this static variable and replaces it's functionality
via a function that detects if the timer is already initialized.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pali Rohár <pali@kernel.org>
Cc: Michael Walle <michael@walle.cc>
Cc: Tony Dinh <mibodhi@gmail.com>
Tested-by: Tony Dinh <mibodhi@gmail.com>
2023-01-02 09:14:16 +01:00
Tom Rini
3aa14d7618 Merge branch '2022-12-31-cmd-source-support-specifying-config-name' into next
To quote the author:
This series adds support for using configs with the source command.

And to paraphrase the rest, see the patch commit messages for more
details.
2022-12-31 16:30:31 -05:00
Sean Anderson
bcc85b96b5 cmd: source: Support specifying config name
As discussed previously [1,2], the source command is not safe to use with
verified boot unless there is a key with required = "images" (which has its
own problems). This is because if such a key is absent, signatures are
verified but not required. It is assumed that configuration nodes will
provide the signature. Because the source command does not use
configurations to determine the image to source, effectively no
verification takes place.

To address this, allow specifying configuration nodes. We use the same
syntax as the bootm command (helpfully provided for us by fit_parse_conf).
By default, we first try the default config and then the default image. To
force using a config, # must be present in the command (e.g. `source
$loadaddr#my-conf`). For convenience, the config may be omitted, just like
the address may be (e.g. `source \#`). This also works for images
(`source :` behaves exactly like `source` currently does).

[1] https://lore.kernel.org/u-boot/7d711133-d513-5bcb-52f2-a9dbaa9eeded@prevas.dk/
[2] https://lore.kernel.org/u-boot/042dcb34-f85f-351e-1b0e-513f89005fdd@gmail.com/

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-31 13:35:19 -05:00
Sean Anderson
c4f5738e69 cmd: source: Clean up a few lines
This simplifies a few lines and corrects an error message.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-31 13:35:19 -05:00
Sean Anderson
30fb045f2d treewide: Use NULL for script image name
Two callers of image_source_script specify an image name. However, both
use the deprecated @ syntax, indicating that they have not been updated
in a while. If CONFIG_FIT_SIGNATURE is enabled, we will reject such
names outright. Back in commit 152576a598c ("stm32mp: stm32prog: handle
U-Boot script in flashlayout alternate"), we even renamed one of the
nodes. Instead of hard-coding a script image name, just use the default
image.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-12-31 13:35:19 -05:00
Sean Anderson
895999261c test: Add test for source command
This adds a basic test for FIT image handling by the source command.
It's a python test becase we need to run mkimage.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-31 13:35:19 -05:00
Sean Anderson
b5fd7b4a31 image: Add fallback for fit_config_verify
Add a fallback for this function so it can be used without regard to
whether FIT_SIGNATURE is enabled or not.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-31 13:35:19 -05:00
Tom Rini
3089d12a02 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-29 13:44:21 -05:00
Tom Rini
d36bc89be2 Pull request for efi-2023-01-rc5-2
Documentation:
 
 * Reorganize existing TI docs and add K3 generation page
 * Add texinfodocs and infodocs targets
 * Update qemu-ppce500 documentation
 * Use "changesets" not "csets" in statistics pages
 
 UEFI
 
 * Fix merging of preseeded non-volatile variables
 * Fix a return value in the  EFI_HII_DATABASE_PROTOCOL
 * Set UEFI specification version to 2.10
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Merge tag 'efi-2023-01-rc5-2' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2023-01-rc5-2

Documentation:

* Reorganize existing TI docs and add K3 generation page
* Add texinfodocs and infodocs targets
* Update qemu-ppce500 documentation
* Use "changesets" not "csets" in statistics pages

UEFI

* Fix merging of preseeded non-volatile variables
* Fix a return value in the  EFI_HII_DATABASE_PROTOCOL
* Set UEFI specification version to 2.10
2022-12-29 13:32:50 -05:00
Tom Rini
6f975524cb Merge branch '2022-12-29-assorted-further-fixes'
- Rework Azure CI jobs for Rockchip, minor fixes for wget and correct
  runtime problems on a number of PowerPC platforms.
2022-12-29 13:31:40 -05:00
Tom Rini
88c2e9157c PowerPC: Update dependencies on *SYS_MPC85XX_NO_RESETVEC
In 96699f097a02 ("powerpc: mpc85xx: Use binman to embed dtb inside
U-Boot") we introduce CONFIG_MPC85XX_HAVE_RESET_VECTOR and do so via
Kconfig. However, much later in de47ff536363 ("Convert
CONFIG_SYS_MPC85XX_NO_RESETVEC to Kconfig") I converted the symbol that
is the inverse of this to Kconfig. This should have included a
dependency on the first symbol as they are logically opposite.

The dependency being missing lead to some platforms being broken at
runtime due to discarding the require reset vector.

Fixes: de47ff536363 ("Convert CONFIG_SYS_MPC85XX_NO_RESETVEC to Kconfig")
Reported-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Pali Rohár <pali@kernel.org>
2022-12-29 13:31:30 -05:00
Tom Rini
9348d93b0d Merge branch '2022-12-29-assorted-further-fixes'
- Rework Azure CI jobs for Rockchip, minor fixes for wget and correct a
  one of the runtime problems on a number of PowerPC platforms.
2022-12-29 09:51:00 -05:00
Tom Rini
ec9efcf62a PowerPC: Rework PBL location choice
When converting CONFIG_SDCARD and CONFIG_SPIFLASH to Kconfig, one set of
uses wasn't converted correctly. Allow for the case where platforms
don't rely on "PBL" to boot but instead use other mechanisms. See the
link below for more details.

Link: https://lore.kernel.org/all/20220802091338.f4g45ldhc7qbg6hm@pali/
Fixes: d433c74eecdc ("Convert CONFIG_SDCARD et al to Kconfig")
Tested-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-29 09:50:53 -05:00
Michael Walle
20422d6930 cmd: net: wget: fix Kconfig dependency
The wget command uses TCP, but fails to select PROT_TCP in Kconfig.
Instead it selects the non-existing symbol TCP. Fix the typo.

Signed-off-by: Michael Walle <michael@walle.cc>
2022-12-29 09:50:53 -05:00
Michael Walle
fe1489bc6d net: wget: fix implicit declaration
The compiler complains about the missing declaration of print_size():
net/wget.c:415:3: warning: implicit declaration of function ‘print_size’ [-Wimplicit-function-declaration]

Fix it.

Signed-off-by: Michael Walle <michael@walle.cc>
2022-12-29 09:50:53 -05:00
Tom Rini
478ed23e11 CI: Rework rockchip jobs in Azure
The rockchip job is getting close to the hard time limit in Azure for
the free tier. Split this in to 32bit and 64bit board jobs.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-29 09:50:53 -05:00
Heinrich Schuchardt
f557cf08b9 efi_loader: use u16_strlen() in efi_var_mem_ins()
Don't duplicate library functionality.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-29 12:52:39 +01:00
Ilias Apalodimas
77bb14758d efi_loader: avoid adding variables twice
When the efi subsystem starts we restore variables that are both in a
file or stored into the .efi_runtime section of U-Boot.  However once
a variable gets created or changed the preseeded entries will end up in
the file.  As a consequence on the next boot we will end up adding
identical variable entries twice.

Fix this by checking if the to be inserted variable already exists.
Also swap the restoration order and start with the file instead of the
builtin variables,  so a user can replace the preseeded ones if needed.

Tested-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-29 10:51:50 +01:00
Heinrich Schuchardt
fcf583b4a7 efi_loader: typo non-volatile in efi_var_restore
It is volatile variables that we do not allow to be restored from file.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-29 10:51:50 +01:00
Heinrich Schuchardt
eff6b7157c efi_loader: set UEFI specification version to 2.10
Claim to implement UEFI 2.10 setting EFI_SPECIFICATION_VERSION accordingly.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-29 10:51:50 +01:00
Heinrich Schuchardt
3ec07c99d8 efi_loader: set IMAGE_FILE_LARGE_ADDRESS_AWARE
For the 64bit EFI binaries that we create set the
IMAGE_FILE_LARGE_ADDRESS_AWARE characteristic in the PE-COFF header
to indicate that they can handle addresses above 2 GiB.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-29 10:51:50 +01:00
Vincent Stehlé
c33d389c7a efi_loader: fix get_package_list_handle() status
When the HII protocol function get_package_list_handle() is called with an
invalid package list handle, it returns EFI_NOT_FOUND but this is not in
its list of possible status codes as per the EFI specification.
Return EFI_INVALID_PARAMETER instead to fix conformance.

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-29 10:51:50 +01:00
Heinrich Schuchardt
159dbe1fb1 doc: improve wget man-page
* correct formatting of synopsis
* improve description of TCP SACK configuration

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-29 10:51:50 +01:00
Tom Rini
f16086e3e2 doc: Use "changesets" not "csets" in statistics pages
To make things more human readable, say "changesets from" rather than
"csets from" in all our historical pages here. Moving forward this has
been changed in our gitdm with b034e399e31a ("gitdm: fix typo csets").

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-29 10:51:50 +01:00
Maxim Cournoyer
7fa4c27a2e doc: add texinfodocs and infodocs targets
Sphinx supports generating Texinfo sources and Info documentation,
which can be navigated easily and is convenient to search (via the
indexed nodes or anchors, for example).  This is basically the same as
1f050e904dd6f2955eecbd22031d912ccb2e7683, which was recently applied
to the Linux kernel.

Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-29 10:51:50 +01:00
Pali Rohár
a17be96b62 doc: board: qemu-ppce500: Update supported and unsupported
qemu can emulate also e500v1 core but cannot emulate CPUs from Freescale
PowerPC QorIQ T and P series.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-29 10:51:50 +01:00
Bryan Brattlof
16a30b3474 doc: ti: add the K3 generation page
Texas Instrument's entire K3 generation of SoCs use much of the same
frameworks and boot flow, especially at the uboot level. Though there
are small differences introduced as each new K3 based SoC is developed
and as the K3 generation matures that will also need to be documented.

Rather than copying the same documentation, with the small differences
applicable to that specific SoC to a new page, introduce a new K3
page that can describe the general boot flow and design decisions for
the entire K3 generation of chips, leaving the specifics for that
particular SoC to a unique sub-page below this one.

Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-29 10:51:50 +01:00
Bryan Brattlof
0820e117c3 doc: ti: reorganize existing ti docs
Texas Instruments produces quite a lot of SoCs based upon a common
architecture 'generation'. (eg: OMAP, K3) TI's existing documentation
layout makes noticing this generation jump rather difficult.

To make navigation easier, split the existing documentation into
individual SoC families so we may begin grouping them according to their
generational (eg: OMAP, K3) families.

Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-29 10:51:50 +01:00
Tom Rini
adcee0791f Merge https://source.denx.de/u-boot/custodians/u-boot-pmic
- power: regulator: Add support for NPCM8xx
2022-12-26 21:00:20 -05:00
Jim Liu
dbedf4a56b power: regulator: Add support for NPCM8xx
Add support for setting nuvoton BMC NPCM845 voltage supply.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-12-26 15:44:00 +09:00
Tom Rini
3e4cbe184a Merge branch '2022-12-23-complete-phase1-CONFIG-migration' into next
- Bring in the final series to complete the main portion of migrating
  CONFIG symbols to either Kconfig or CFG namespace (or removing /
  renaming entirely). With this, we have stricter CI tests as well now.
2022-12-23 22:19:39 -05:00
Tom Rini
90c7888c9d common/spl/spl_ram: Remove unused default
We ask for CONFIG_SPL_LOAD_FIT_ADDRESS in Kconfig, so we cannot define
it in C as a fall-back. However, this option previously was buried under
"if ... endif" Kconfig logic. Rework a number of config options to now
have more robust dependency lines so that we can ask this address when
needed. With that done, we can remove the fallback in spl_ram.c.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 13:01:13 -05:00
Tom Rini
648d675a2f cf_spi.c: Rename CONFIG_SPI_IDLE_VAL to SPI_IDLE_VAL
This value is never changed by boards, so just rename it to
SPI_IDLE_VAL to fit with the rest of the code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 13:01:13 -05:00
Tom Rini
50e88c0fea pci-rcar-gen3: Rename CONFIG_SEND_ENABLE
We rename the symbol CONFIG_SEND_ENABLE to just SEND_ENABLE, and remove
the second whitespace following the define.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 13:01:13 -05:00
Tom Rini
1e01950333 post: Move CONFIG_SYS_POST to CFG_SYS_POST
Migrate the rest of the CONFIG_SYS_POST macros over to CFG_SYS_POST
namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 13:01:13 -05:00
Tom Rini
9ef3ba85bf kbuild: Remove checking for adhoc CONFIG symbols
At this point all listed adhoc CONFIG symbols have been migrated to
Kconfig or removed from the tree or renamed to CFG (or similar). We also
now have CI tests that will error on any new introductions, and
checkpatch.pl also looks. We can now remove these hooks and related
scripts.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 13:01:13 -05:00
Tom Rini
bb9b9c1e20 CI: Replace unmigrated symbol test with non-Kconfig introduction test
Now that all symbols have been migrated to Kconfig, or are part of the
CFG namespace we do not need a complex check for unmigrated CONFIG
symbols. Any instance of #define (or #undef) or a CONFIG value is wrong,
so cause CI to fail.

This test is not as strict as possible yet as we have more symbols that
were not previously caught to deal with.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 13:01:12 -05:00
Tom Rini
2a06da08e7 checkpatch.pl: Update CONFIG logic in U-Boot section
Now that all CONFIG symbols are in Kconfig, checkpatch.pl should check
for and error on any case of define/undef CONFIG_*.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
0478dac62a kbuild: Remove uncmd_spl logic
At this point in the conversion there should be no need to have logic to
disable some symbol during the SPL build as all symbols should have an
SPL counterpart.

The main real changes done here are that we now must make proper use of
CONFIG_IS_ENABLED(DM_SERIAL) rather than many of the odd tricks we
developed prior to CONFIG_IS_ENABLED() being available.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
e95bcfb56c bcmcygnus: Convert CONFIG_IPROC to Kconfig
Select this symbol as needed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
f5dd0c5e19 configs: Remove unused or redundant CONFIG symbols
A number of CONFIG symbols have crept in that are never referenced in
code, so drop them here. Further, we have two symbols being enabled
in headers while already enabled correctly in Kconfig, so these lines
can also be removed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
e1d6c16d80 librem5: Rename CONFIG_POWER_BD71837 symbols
Rename the CONFIG_POWER_BD71837_I2C_* symbols to not have the CONFIG
prefix and be local to the file they are used in.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
92a5c89998 global: Migrate CONFIG_X86_REFCODE_RUN_ADDR to CFG
Perform a simple rename of CONFIG_X86_REFCODE_RUN_ADDR to CFG_X86_REFCODE_RUN_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
d4143373f1 global: Migrate CONFIG_X86_REFCODE_ADDR to CFG
Perform a simple rename of CONFIG_X86_REFCODE_ADDR to CFG_X86_REFCODE_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
fa2fd534b5 global: Migrate CONFIG_X86_MRC_ADDR to CFG
Perform a simple rename of CONFIG_X86_MRC_ADDR to CFG_X86_MRC_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:13 -05:00
Tom Rini
bb34410509 global: Migrate CONFIG_WATCHDOG_PRESC et al to CFG
Perform simple renames of:
   CONFIG_WATCHDOG_PRESC to CFG_WATCHDOG_PRESC
   CONFIG_WATCHDOG_RC to CFG_WATCHDOG_RC

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
438654c87c global: Migrate CONFIG_VSC7385_IMAGE et al to CFG
Perform simple renames of:
   CONFIG_VSC7385_IMAGE to CFG_VSC7385_IMAGE
   CONFIG_VSC7385_IMAGE_SIZE to CFG_VSC7385_IMAGE_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
1d0eaf2f32 global: Migrate CONFIG_USB_ISP1301_I2C_ADDR to CFG
Perform a simple rename of CONFIG_USB_ISP1301_I2C_ADDR to CFG_USB_ISP1301_I2C_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
61693acbce global: Migrate CONFIG_USART_ID to CFG
Perform a simple rename of CONFIG_USART_ID to CFG_USART_ID

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
805482d187 global: Migrate CONFIG_USART_BASE to CFG
Perform a simple rename of CONFIG_USART_BASE to CFG_USART_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
e7cebff656 global: Migrate CONFIG_TSEC_TBICR_SETTINGS to CFG
Perform a simple rename of CONFIG_TSEC_TBICR_SETTINGS to CFG_TSEC_TBICR_SETTINGS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
39d4e7b0b0 global: Migrate CONFIG_TESTPIN_REG to CFG
Perform a simple rename of CONFIG_TESTPIN_REG to CFG_TESTPIN_REG

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
77cfb3d345 global: Migrate CONFIG_TESTPIN_MASK to CFG
Perform a simple rename of CONFIG_TESTPIN_MASK to CFG_TESTPIN_MASK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
e660e972c4 global: Migrate CONFIG_TEGRA_BOARD_STRING to CFG
Perform a simple rename of CONFIG_TEGRA_BOARD_STRING to CFG_TEGRA_BOARD_STRING

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
d8964b3e1d global: Migrate CONFIG_SYS_I2C_DIRECT_BUS to CFG
Perform a simple rename of CONFIG_SYS_I2C_DIRECT_BUS to CFG_SYS_I2C_DIRECT_BUS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
e02e5e5188 global: Migrate CONFIG_STD_DEVICES_SETTINGS to CFG
Perform a simple rename of CONFIG_STD_DEVICES_SETTINGS to CFG_STD_DEVICES_SETTINGS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
6786ce1ce1 global: Migrate CONFIG_STACKBASE to CFG
Perform a simple rename of CONFIG_STACKBASE to CFG_STACKBASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
3e204427c8 global: Migrate CONFIG_SMP_PEN_ADDR to CFG
Perform a simple rename of CONFIG_SMP_PEN_ADDR to CFG_SMP_PEN_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
59f3a09a6c global: Migrate CONFIG_SLIC to CFG
Perform a simple rename of CONFIG_SLIC to CFG_SLIC

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
97148cb614 global: Migrate CONFIG_SH_ETHER_USE_PORT to CFG
Perform a simple rename of CONFIG_SH_ETHER_USE_PORT to CFG_SH_ETHER_USE_PORT

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
85b5511708 global: Migrate CONFIG_SH_ETHER_PHY_MODE to CFG
Perform a simple rename of CONFIG_SH_ETHER_PHY_MODE to CFG_SH_ETHER_PHY_MODE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
7c480bab14 global: Migrate CONFIG_SH_ETHER_PHY_ADDR to CFG
Perform a simple rename of CONFIG_SH_ETHER_PHY_ADDR to CFG_SH_ETHER_PHY_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
ff53ecc387 global: Migrate CONFIG_SH_ETHER_CACHE_WRITEBACK to CFG
Perform a simple rename of CONFIG_SH_ETHER_CACHE_WRITEBACK to CFG_SH_ETHER_CACHE_WRITEBACK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
c253cea724 global: Migrate CONFIG_SH_ETHER_CACHE_INVALIDATE to CFG
Perform a simple rename of CONFIG_SH_ETHER_CACHE_INVALIDATE to CFG_SH_ETHER_CACHE_INVALIDATE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
24513c3ac8 global: Migrate CONFIG_SH_ETHER_ALIGNE_SIZE to CFG
Perform a simple rename of CONFIG_SH_ETHER_ALIGNE_SIZE to CFG_SH_ETHER_ALIGNE_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
ddc4187033 global: Migrate CONFIG_SET_DFU_ALT_BUF_LEN to CFG
Perform a simple rename of CONFIG_SET_DFU_ALT_BUF_LEN to CFG_SET_DFU_ALT_BUF_LEN

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
3cdd6302a5 global: Migrate CONFIG_SC_TIMER_CLK to CFG
Perform a simple rename of CONFIG_SC_TIMER_CLK to CFG_SC_TIMER_CLK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:12 -05:00
Tom Rini
77d0870c29 global: Migrate CONFIG_SCSI_DEV_LIST to CFG
Perform a simple rename of CONFIG_SCSI_DEV_LIST to CFG_SCSI_DEV_LIST

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:11 -05:00
Tom Rini
dbfaeecf59 global: Migrate CONFIG_SCIF_A to CFG
Perform a simple rename of CONFIG_SCIF_A to CFG_SCIF_A

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:11 -05:00
Tom Rini
9dbe356ef4 global: Migrate CONFIG_SAR_REG to CFG
Perform a simple rename of CONFIG_SAR_REG to CFG_SAR_REG

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:11 -05:00
Tom Rini
f9932d38a3 global: Migrate CONFIG_SAR2_REG to CFG
Perform a simple rename of CONFIG_SAR2_REG to CFG_SAR2_REG

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:11 -05:00
Tom Rini
3db78c830f global: Migrate CONFIG_RESET_VECTOR_ADDRESS to CFG
Perform a simple rename of CONFIG_RESET_VECTOR_ADDRESS to CFG_RESET_VECTOR_ADDRESS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:11 -05:00
Tom Rini
d4c8dd1e6f global: Migrate CONFIG_RAMDISK_ADDR to CFG
Perform a simple rename of CONFIG_RAMDISK_ADDR to CFG_RAMDISK_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:11 -05:00
Tom Rini
62350c72d4 global: Migrate CONFIG_QBMAN_CLK_DIV to CFG
Perform a simple rename of CONFIG_QBMAN_CLK_DIV to CFG_QBMAN_CLK_DIV

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:11 -05:00
Tom Rini
7c5c137c41 global: Migrate CONFIG_PRAM to CFG
Perform a simple rename of CONFIG_PRAM to CFG_PRAM

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:15:11 -05:00
Tom Rini
193b3fe175 global: Migrate CONFIG_POWER_PFUZE3000_I2C_ADDR to CFG
Perform a simple rename of CONFIG_POWER_PFUZE3000_I2C_ADDR to CFG_POWER_PFUZE3000_I2C_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:52 -05:00
Tom Rini
aa3efb6c64 global: Migrate CONFIG_POWER_PFUZE100_I2C_ADDR to CFG
Perform a simple rename of CONFIG_POWER_PFUZE100_I2C_ADDR to CFG_POWER_PFUZE100_I2C_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:52 -05:00
Tom Rini
6d38c69e83 global: Migrate CONFIG_POWER_LTC3676_I2C_ADDR to CFG
Perform a simple rename of CONFIG_POWER_LTC3676_I2C_ADDR to CFG_POWER_LTC3676_I2C_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:52 -05:00
Tom Rini
2adbb29747 global: Migrate CONFIG_POSTBOOTMENU to CFG
Perform a simple rename of CONFIG_POSTBOOTMENU to CFG_POSTBOOTMENU

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:52 -05:00
Tom Rini
b33953b796 global: Migrate CONFIG_PME_PLAT_CLK_DIV to CFG
Perform a simple rename of CONFIG_PME_PLAT_CLK_DIV to CFG_PME_PLAT_CLK_DIV

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
b861574bd9 global: Migrate CONFIG_PL01x_PORTS to CFG
Perform a simple rename of CONFIG_PL01x_PORTS to CFG_PL01x_PORTS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
f410d0ac8a global: Migrate CONFIG_PL011_CLOCK to CFG
Perform a simple rename of CONFIG_PL011_CLOCK to CFG_PL011_CLOCK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
830fd095a3 global: Migrate CONFIG_PHY_IRAM_BASE to CFG
Perform a simple rename of CONFIG_PHY_IRAM_BASE to CFG_PHY_IRAM_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
52d596eabb global: Migrate CONFIG_PHY_ID to CFG
Perform a simple rename of CONFIG_PHY_ID to CFG_PHY_ID

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
e9212bffe3 global: Migrate CONFIG_PHY_ET1011C_TX_CLK_FIX to CFG
Perform a simple rename of CONFIG_PHY_ET1011C_TX_CLK_FIX to CFG_PHY_ET1011C_TX_CLK_FIX

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
52139620be global: Migrate CONFIG_PCIE_IMX_POWER_GPIO to CFG
Perform a simple rename of CONFIG_PCIE_IMX_POWER_GPIO to CFG_PCIE_IMX_POWER_GPIO

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
7906f91789 global: Migrate CONFIG_PCIE_IMX_PERST_GPIO to CFG
Perform a simple rename of CONFIG_PCIE_IMX_PERST_GPIO to CFG_PCIE_IMX_PERST_GPIO

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
a2c164cbb4 global: Migrate CONFIG_OTHBOOTARGS to CFG
Perform a simple rename of CONFIG_OTHBOOTARGS to CFG_OTHBOOTARGS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
1c3ba55798 global: Migrate CONFIG_ODROID_REV_AIN to CFG
Perform a simple rename of CONFIG_ODROID_REV_AIN to CFG_ODROID_REV_AIN

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
dd11fdc31f global: Migrate CONFIG_MXC_USB_FLAGS et al to CFG
Perform simple renames of:
   CONFIG_MXC_USB_FLAGS to CFG_MXC_USB_FLAGS
   CONFIG_MXC_USB_PORT to CFG_MXC_USB_PORT
   CONFIG_MXC_USB_PORTSC to CFG_MXC_USB_PORTSC

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
4db386655a global: Migrate CONFIG_MXC_UART_BASE to CFG
Perform a simple rename of CONFIG_MXC_UART_BASE to CFG_MXC_UART_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
d1c723895b global: Migrate CONFIG_MXC_NAND_REGS_BASE to CFG
Perform a simple rename of CONFIG_MXC_NAND_REGS_BASE to CFG_MXC_NAND_REGS_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
55eef1d629 global: Migrate CONFIG_MXC_NAND_IP_REGS_BASE to CFG
Perform a simple rename of CONFIG_MXC_NAND_IP_REGS_BASE to CFG_MXC_NAND_IP_REGS_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
8f52920a4a global: Migrate CONFIG_MFG_ENV_SETTINGS to CFG
Perform a simple rename of CONFIG_MFG_ENV_SETTINGS to CFG_MFG_ENV_SETTINGS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
8a897c4f97 global: Migrate CONFIG_MAX_RAM_BANK_SIZE to CFG
Perform a simple rename of CONFIG_MAX_RAM_BANK_SIZE to CFG_MAX_RAM_BANK_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
1d457dbb91 global: Migrate CONFIG_MAX_MEM_MAPPED to CFG
Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
dd5b58c491 global: Migrate CONFIG_MALLOC_F_ADDR to CFG
Perform a simple rename of CONFIG_MALLOC_F_ADDR to CFG_MALLOC_F_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
bd79d3d616 global: Migrate CONFIG_LPC32XX_NAND_SLC_WWIDTH to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_WWIDTH to CFG_LPC32XX_NAND_SLC_WWIDTH

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
308ed80839 global: Migrate CONFIG_LPC32XX_NAND_SLC_WSETUP to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_WSETUP to CFG_LPC32XX_NAND_SLC_WSETUP

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
b0c548273e global: Migrate CONFIG_LPC32XX_NAND_SLC_WHOLD to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_WHOLD to CFG_LPC32XX_NAND_SLC_WHOLD

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
fa32dc7d15 global: Migrate CONFIG_LPC32XX_NAND_SLC_WDR_CLKS to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_WDR_CLKS to CFG_LPC32XX_NAND_SLC_WDR_CLKS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:51 -05:00
Tom Rini
fa0e72a34e global: Migrate CONFIG_LPC32XX_NAND_SLC_RWIDTH to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_RWIDTH to CFG_LPC32XX_NAND_SLC_RWIDTH

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
416ef8c7c6 global: Migrate CONFIG_LPC32XX_NAND_SLC_RSETUP to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_RSETUP to CFG_LPC32XX_NAND_SLC_RSETUP

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
bba52ab080 global: Migrate CONFIG_LPC32XX_NAND_SLC_RHOLD to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_RHOLD to CFG_LPC32XX_NAND_SLC_RHOLD

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
c102eb5ca7 global: Migrate CONFIG_LPC32XX_NAND_SLC_RDR_CLKS to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_RDR_CLKS to CFG_LPC32XX_NAND_SLC_RDR_CLKS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
39fa17718f global: Migrate CONFIG_LPC32XX_NAND_MLC_WR_LOW to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_WR_LOW to CFG_LPC32XX_NAND_MLC_WR_LOW

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
196690dfda global: Migrate CONFIG_LPC32XX_NAND_MLC_WR_HIGH to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_WR_HIGH to CFG_LPC32XX_NAND_MLC_WR_HIGH

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
259ec2ce11 global: Migrate CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY to CFG_LPC32XX_NAND_MLC_TCEA_DELAY

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
3c35c036ad global: Migrate CONFIG_LPC32XX_NAND_MLC_RD_LOW to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_RD_LOW to CFG_LPC32XX_NAND_MLC_RD_LOW

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
ab8c6e370c global: Migrate CONFIG_LPC32XX_NAND_MLC_RD_HIGH to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_RD_HIGH to CFG_LPC32XX_NAND_MLC_RD_HIGH

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
ea93286e5f global: Migrate CONFIG_LPC32XX_NAND_MLC_NAND_TA to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_NAND_TA to CFG_LPC32XX_NAND_MLC_NAND_TA

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
dff9de5c2c global: Migrate CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY to CFG
Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY to CFG_LPC32XX_NAND_MLC_BUSY_DELAY

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
8000ac874c global: Migrate CONFIG_LOWPOWER_FLAG to CFG
Perform a simple rename of CONFIG_LOWPOWER_FLAG to CFG_LOWPOWER_FLAG

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
77db07ce1c global: Migrate CONFIG_LOWPOWER_ADDR to CFG
Perform a simple rename of CONFIG_LOWPOWER_ADDR to CFG_LOWPOWER_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
1cd60b3cc0 global: Migrate CONFIG_LEGACY_BOOTCMD_ENV to CFG
Perform a simple rename of CONFIG_LEGACY_BOOTCMD_ENV to CFG_LEGACY_BOOTCMD_ENV

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
e9f508cf01 global: Migrate CONFIG_KSNET_SERDES_SGMII_BASE to CFG
Perform a simple rename of CONFIG_KSNET_SERDES_SGMII_BASE to CFG_KSNET_SERDES_SGMII_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
81d239aede global: Migrate CONFIG_KSNET_SERDES_SGMII2_BASE to CFG
Perform a simple rename of CONFIG_KSNET_SERDES_SGMII2_BASE to CFG_KSNET_SERDES_SGMII2_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
d036606142 global: Migrate CONFIG_KSNET_SERDES_LANES_PER_SGMII to CFG
Perform a simple rename of CONFIG_KSNET_SERDES_LANES_PER_SGMII to CFG_KSNET_SERDES_LANES_PER_SGMII

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
d4e4bc898b global: Migrate CONFIG_KSNET_NETCP_BASE to CFG
Perform a simple rename of CONFIG_KSNET_NETCP_BASE to CFG_KSNET_NETCP_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
f060d1885c global: Migrate CONFIG_KSNET_MAC_ID_BASE to CFG
Perform a simple rename of CONFIG_KSNET_MAC_ID_BASE to CFG_KSNET_MAC_ID_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:50 -05:00
Tom Rini
21bd204239 global: Migrate CONFIG_KSNET_CPSW_NUM_PORTS to CFG
Perform a simple rename of CONFIG_KSNET_CPSW_NUM_PORTS to CFG_KSNET_CPSW_NUM_PORTS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:14:49 -05:00
Tom Rini
7201b76978 global: Migrate CONFIG_IRAM_TOP to CFG
Perform a simple rename of CONFIG_IRAM_TOP to CFG_IRAM_TOP

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:10:40 -05:00
Tom Rini
7b5f75cffa global: Migrate CONFIG_IRAM_BASE to CFG
Perform a simple rename of CONFIG_IRAM_BASE to CFG_IRAM_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:10:40 -05:00
Tom Rini
e6014294dd global: Migrate CONFIG_IMX6_PWM_PER_CLK to CFG
Perform a simple rename of CONFIG_IMX6_PWM_PER_CLK to CFG_IMX6_PWM_PER_CLK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:10:40 -05:00
Tom Rini
cdbf8459d0 global: Migrate CONFIG_ICS307_REFCLK_HZ to CFG
Perform a simple rename of CONFIG_ICS307_REFCLK_HZ to CFG_ICS307_REFCLK_HZ

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:10:40 -05:00
Tom Rini
35661f86eb global: Migrate CONFIG_I2C_MVTWSI_BASE1 to CFG
Perform a simple rename of CONFIG_I2C_MVTWSI_BASE1 to CFG_I2C_MVTWSI_BASE1

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:10:40 -05:00
Tom Rini
45ede979e8 global: Migrate CONFIG_I2C_MVTWSI_BASE0 to CFG
Perform a simple rename of CONFIG_I2C_MVTWSI_BASE0 to CFG_I2C_MVTWSI_BASE0

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:10:40 -05:00
Tom Rini
e06b9b8d75 global: Migrate CONFIG_I2C_MULTI_BUS to CFG
Perform a simple rename of CONFIG_I2C_MULTI_BUS to CFG_I2C_MULTI_BUS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:10:40 -05:00
Tom Rini
d2cd9f4121 global: Migrate CONFIG_FTRTC010_PCLK to CFG
Perform a simple rename of CONFIG_FTRTC010_PCLK to CFG_FTRTC010_PCLK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:43 -05:00
Tom Rini
bf09562222 global: Migrate CONFIG_FTRTC010_EXTCLK to CFG
Perform a simple rename of CONFIG_FTRTC010_EXTCLK to CFG_FTRTC010_EXTCLK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:43 -05:00
Tom Rini
315390e467 global: Migrate CONFIG_FSL_SERDES2 to CFG
Perform a simple rename of CONFIG_FSL_SERDES2 to CFG_FSL_SERDES2

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:43 -05:00
Tom Rini
da49557003 global: Migrate CONFIG_FSL_SERDES1 to CFG
Perform a simple rename of CONFIG_FSL_SERDES1 to CFG_FSL_SERDES1

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:43 -05:00
Tom Rini
193d7ab1e3 global: Migrate CONFIG_FSL_PMIC_MODE to CFG
Perform a simple rename of CONFIG_FSL_PMIC_MODE to CFG_FSL_PMIC_MODE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:43 -05:00
Tom Rini
f200d710d8 global: Migrate CONFIG_FSL_PMIC_CS to CFG
Perform a simple rename of CONFIG_FSL_PMIC_CS to CFG_FSL_PMIC_CS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:43 -05:00
Tom Rini
3a8be4da79 global: Migrate CONFIG_FSL_PMIC_CLK to CFG
Perform a simple rename of CONFIG_FSL_PMIC_CLK to CFG_FSL_PMIC_CLK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:43 -05:00
Tom Rini
eaaca4245e global: Migrate CONFIG_FSL_PMIC_BUS to CFG
Perform a simple rename of CONFIG_FSL_PMIC_BUS to CFG_FSL_PMIC_BUS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:43 -05:00
Tom Rini
e3e4efc04f global: Migrate CONFIG_FSL_PMIC_BITLEN to CFG
Perform a simple rename of CONFIG_FSL_PMIC_BITLEN to CFG_FSL_PMIC_BITLEN

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:43 -05:00
Tom Rini
72fc264504 global: Migrate CONFIG_FPGA_DELAY to CFG
Perform a simple rename of CONFIG_FPGA_DELAY to CFG_FPGA_DELAY

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:42 -05:00
Tom Rini
452e33efa8 global: Migrate CONFIG_FM_PLAT_CLK_DIV to CFG
Perform a simple rename of CONFIG_FM_PLAT_CLK_DIV to CFG_FM_PLAT_CLK_DIV

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:42 -05:00
Tom Rini
c20d7cc95c global: Migrate CONFIG_FLASH_OR_PRELIM to CFG
Perform a simple rename of CONFIG_FLASH_OR_PRELIM to CFG_FLASH_OR_PRELIM

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:42 -05:00
Tom Rini
8938f59d54 global: Migrate CONFIG_FLASH_BR_PRELIM to CFG
Perform a simple rename of CONFIG_FLASH_BR_PRELIM to CFG_FLASH_BR_PRELIM

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:42 -05:00
Tom Rini
fa760c3240 global: Migrate CONFIG_FEC_MXC_PHYADDR to CFG
Perform a simple rename of CONFIG_FEC_MXC_PHYADDR to CFG_FEC_MXC_PHYADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:42 -05:00
Tom Rini
4daffb58e6 global: Migrate CONFIG_FEC_ENET_DEV to CFG
Perform a simple rename of CONFIG_FEC_ENET_DEV to CFG_FEC_ENET_DEV

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:42 -05:00
Tom Rini
2aac334a9b global: Migrate CONFIG_FB_ADDR to CFG
Perform a simple rename of CONFIG_FB_ADDR to CFG_FB_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:42 -05:00
Tom Rini
0613c36a7a global: Migrate CONFIG_EXTRA_ENV_SETTINGS to CFG
Perform a simple rename of CONFIG_EXTRA_ENV_SETTINGS to CFG_EXTRA_ENV_SETTINGS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:09:42 -05:00
Tom Rini
fb55ac2cfe global: Migrate CONFIG_ETHBASE to CFG
Perform a simple rename of CONFIG_ETHBASE to CFG_ETHBASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:08:35 -05:00
Tom Rini
b9abcb8c9f global: Migrate CONFIG_ET1100_BASE to CFG
Perform a simple rename of CONFIG_ET1100_BASE to CFG_ET1100_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:08:35 -05:00
Tom Rini
ef2e1745da global: Migrate CONFIG_ENV_TOTAL_SIZE to CFG
Perform a simple rename of CONFIG_ENV_TOTAL_SIZE to CFG_ENV_TOTAL_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:08:35 -05:00
Tom Rini
3673a47b55 global: Migrate CONFIG_ENV_SROM_BANK to CFG
Perform a simple rename of CONFIG_ENV_SROM_BANK to CFG_ENV_SROM_BANK

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:04 -05:00
Tom Rini
d6ae6c7076 global: Migrate CONFIG_ENV_SETTINGS_V2 to CFG
Perform a simple rename of CONFIG_ENV_SETTINGS_V2 to CFG_ENV_SETTINGS_V2

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
10bb746127 global: Migrate CONFIG_ENV_SETTINGS_V1 to CFG
Perform a simple rename of CONFIG_ENV_SETTINGS_V1 to CFG_ENV_SETTINGS_V1

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
4a609781d5 global: Migrate CONFIG_ENV_SETTINGS_NAND_V2 to CFG
Perform a simple rename of CONFIG_ENV_SETTINGS_NAND_V2 to CFG_ENV_SETTINGS_NAND_V2

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
fe5a5393bd global: Migrate CONFIG_ENV_SETTINGS_NAND_V1 to CFG
Perform a simple rename of CONFIG_ENV_SETTINGS_NAND_V1 to CFG_ENV_SETTINGS_NAND_V1

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
7c5b8c7c64 global: Migrate CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS to CFG
Perform a simple rename of CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS to CFG_ENV_SETTINGS_BUTTONS_AND_LEDS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
acf29d8ccb global: Migrate CONFIG_ENV_FLAGS_LIST_STATIC to CFG
Perform a simple rename of CONFIG_ENV_FLAGS_LIST_STATIC to CFG_ENV_FLAGS_LIST_STATIC

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
42119de8b5 global: Migrate CONFIG_DW_WDT_CLOCK_KHZ to CFG
Perform a simple rename of CONFIG_DW_WDT_CLOCK_KHZ to CFG_DW_WDT_CLOCK_KHZ

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
b8089c6d68 global: Migrate CONFIG_DFU_ALT et al to CFG
Perform simple renames of:
   CONFIG_DFU_ALT to CFG_DFU_ALT
   CONFIG_DFU_ALT_BOOT_EMMC to CFG_DFU_ALT_BOOT_EMMC
   CONFIG_DFU_ALT_BOOT_SD to CFG_DFU_ALT_BOOT_SD
   CONFIG_DFU_ALT_SYSTEM to CFG_DFU_ALT_SYSTEM
   CONFIG_DFU_ENV_SETTINGS to CFG_DFU_ENV_SETTINGS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
207972acfc global: Migrate CONFIG_BOARDDIR to CFG
Perform a simple rename of CONFIG_BOARDDIR to CFG_BOARDDIR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
04501ecca2 global: Migrate CONFIG_ARM_GIC_BASE_ADDRESS to CFG
Perform a simple rename of CONFIG_ARM_GIC_BASE_ADDRESS to CFG_ARM_GIC_BASE_ADDRESS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
137de2cf0d rsa-verify: Rework host check for CONFIG_RSA_VERIFY_WITH_PKEY
While we do not want to use CONFIG_RSA_VERIFY_WITH_PKEY on the host, we
cannot undef the symbol in this manner. As this ends up being a test
within another function we can use !tools_build() as a test here.

Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-23 10:07:03 -05:00
Tom Rini
218ce3695b global: Remove undef CONFIG_... for unused values
We have a number of places that undef CONFIG_... while we never
reference CONFIG_... in the first place. Remove these lines.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
d5c4b8b063 log: Remove some places where we redefine LOGLEVEL
We cannot redefine a CONFIG value per file in this manner.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
dc2c451a94 valgrind: Rework test for unsupported platforms
Change things so that on an unsupported platform we will #error rather
than undef the feature.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
991bc16951 atmel_nand: Remove undef during SPL_BUILD
We cannot disable features in SPL in this manner, remove the undef here.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
2c065aeeee mtd: ubi: Finish moving configuration to Kconfig
We have some unused and undefined symbols to remove references to, so do
that. Move the final things that we do set (or need to keep unset) to
Kconfig instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
f00f676af6 Convert CONFIG_SYS_FPGA_CHECK_BUSY to Kconfig
This converts the following to Kconfig:
    CONFIG_SYS_FPGA_CHECK_BUSY

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
7ee2f977b7 Convert CONFIG_NEVER_ASSERT_ODT_TO_CPU to Kconfig
This converts the following to Kconfig:
    CONFIG_NEVER_ASSERT_ODT_TO_CPU

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23 10:07:03 -05:00
Tom Rini
957848882c rk32xx: Use standard TPL linker script
As of 2f41ade79e59 ("linker: Modify linker scripts to be more generic")
we can use the same linker script for SPL and TPL and not have to make
use of #undef tricks. Remove these last remnants.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-23 10:07:03 -05:00
Tom Rini
b9d1f88b3a exynos: Rework legacy PWM usage
The way that the timer support is currently done for exynos/nexell
platforms relies on the legacy PWM infrastructure, and that needs to be
updated. However, we really cannot safely undef CONFIG_DM_PWM to build
the timer.c file without warnings. For now, rename the relevant legacy
functions to be prefixed with s5p_ and add prototypes to the arch pwm.h
files.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Stefan Bosch <stefan_b@posteo.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-23 10:07:03 -05:00
Tom Rini
e1befc8512 OP-TEE autodiscovery
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 iQIzBAABCgAdFiEEgWII69YpahbL5iK5gS8AYozs+qIFAmOlZoUACgkQgS8AYozs
 +qIqDA//QLRmx5+Rq8+MkXar6Xpt6nP877+onIxJLeZ4RaNY1I9EIv2hjHcR5NpB
 Wj4K4wP7EQobHTfMDD2owEJ5jOPjmMgYrd8j+7g8q+G7160JTYV6FDxYa3V6b55/
 qifW8T6eTyeaNwKEZyLb7+aNHJ/ULx51RQ8AlTM+ttv2iiYeB7+DegqdF3Df6hjT
 8uFHOPX0+ln+8UUKHCm0NKxUsply4qGlJiuK99Pq1xnGTxyZ1G1+qqXvuFazGOZm
 wHm1Ha08hep6Ye2azjBof8FdA7cjM//7SSUgOctEf1agloxblmt26XfDsxn0U3Oa
 5AbGLrPnL5KJjv/ij5TeaAGdOYPhsgsKJj3vwbbdoARLOb3x91rt7e/ZtThrKcF5
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Merge tag 'tpm-23122022' of https://source.denx.de/u-boot/custodians/u-boot-tpm

OP-TEE autodiscovery
2022-12-23 07:46:41 -05:00
Tom Rini
24a0a00f07 Merge branch '2022-12-22-assorted-important-fixes'
- Split up the aarch64 Azure CI job more, to avoid time limits, nuvoton
  network fix, SPL_OPTEE_IMAGE dependency fix, some fixes to the IPv6
  code, PowerPC build flag fixes, silence pylibfdt version warning.
2022-12-23 07:44:30 -05:00
Etienne Carriere
fe8a4ed011 tee: optee: discover services dependent on tee-supplicant
Makes OP-TEE to enumerate also services depending on tee-supplicant
support in U-Boot. This change allows OP-TEE services like fTPM TA
to be discovered and get a TPM device registered in U-Boot.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-23 10:26:15 +02:00
Etienne Carriere
476a3d58df tee: optee: don't fail probe because of optee-rng
Fixes optee-rng driver bind sequence in optee driver to print a warning
message but not report an error status when a optee-rng service driver
fails to be bound as the optee driver itself is still fully functional.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-23 10:26:11 +02:00
Marek Vasut
440098c42e pylibfdt: Fix version normalization warning
Fix the following version normalization warning:
"
/usr/lib/python3/dist-packages/setuptools/dist.py:530: UserWarning: Normalizing '2023.01' to '2023.1'
"

Using suggestion from Richard Jones:
https://github.com/pypa/setuptools/issues/308#issuecomment-405817468

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-22 15:39:13 -05:00
Jim Liu
dd5f07eb6b net: nuvoton: fix build broken for use phy_get_interface_by_name
The original patch is use phy_get_interface_by_name to set interface.
The new patch is use dev_read_phy_mode to replace it.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-12-22 15:39:13 -05:00
Pali Rohár
1db706edcd powerpc/mpc85xx: Disable AltiVec and VSX instructions
All vector instructions on powerpc mpc85xx must not be used because U-Boot
does not enable them. Usage cause random crashes. SPE vector instructions
are already disabled by compiler flags, so disable also AltiVec and VSX
vector instructions.

Linux kernel disables AltiVec and VSX instructions too.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-12-22 15:39:13 -05:00
Pali Rohár
138b6061a1 powerpc/mpc85xx: Improve disabling of SPE instructions
Specifying -mspe=no also disables usage of SPE instructions. It is
documented in "[PATCH,rs6000] make -mno-spe work as expected" email:
http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html

So replace -mspe=yes by -mspe=no, so make it clear that u-boot has to be
compiled without SPE instructions.

Linux kernel contains following Makefile code to achieve it:

    # No SPE instruction when building kernel
    # (We use all available options to help semi-broken compilers)
    KBUILD_CFLAGS += $(call cc-option,-mno-spe)
    KBUILD_CFLAGS += $(call cc-option,-mspe=no)

Do same for U-Boot.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-12-22 15:39:13 -05:00
Pali Rohár
c0d0569cf6 powerpc/mpc85xx: Pass correct cpu compiler flags
When gcc's default cpu (selected by --with-cpu= during gcc's configure
phase) does not match target U-Boot board cpu then U-Boot binary does not
have to be compiled correctly. Lot of distributions sets gcc's default cpu
to generic powerpc variant which works fine.

U-Boot already pass -Wa,-me500 flag to gcc which instructs GNU AS to accept
e500 specific instructions when processing assembler source files (.S).

This affects also assembly files generated by gcc from C source files. And
because gcc for generic powerpc cpu puts '.machine ppc' at the beginning of
the generated assembly file, it basically overwrites -me500 flag by which
was GNU AS invoked (from U-boot build system).

It started to be an issue since binutils 2.38 which does not keep enabled
extra functional units selected by previous cpu. Hence issuing directive
'.machine ppc' (generated by gcc for generic powerpc) after '.machine e500'
(specifying at command line) disables usage of e500 specific instructions.

And compiling arch/powerpc/cpu/mpc85xx/tlb.c code throws following
assembler errors:

    {standard input}: Assembler messages:
    {standard input}:127: Error: unrecognized opcode: `tlbre'
    {standard input}:418: Error: unrecognized opcode: `tlbre'
    {standard input}:821: Error: unrecognized opcode: `msync'
    {standard input}:821: Error: unrecognized opcode: `tlbwe'
    {standard input}:884: Error: unrecognized opcode: `tlbsx'

This issue was already hit by Debian people and is reported in bug tracker:
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1003490

Calling gcc with -mcpu=8540 flag fixes this issue because -mcpu=8540 tells
gcc to compile code for e500 core/cpu (overwriting gcc's default cpu) and
does not put '.machine ppc' directive into assembly anymore.

Also if gcc is invoked with -mcpu=8540 then it pass -me500 flag to GNU AS.
So it is unnecessary to manually specify -Wa,-me500 flag because it is
implicitly added.

Fix this issue properly by specifying correct -mcpu compiler flag for all
supported powerpc cores in U-Boot mpc85xx platform, which are: e500v1,
e500v2, e500mc, e5500 and e6500. For specifying e500v1 and e500v2 cores,
gcc has unintuitive -mcpu=8540 and -mcpu=8548 flag names, for other cores
-mcpu matches core name.

The only difference between gcc's -mcpu=8540 and -mcpu=8548 flags is
support for double precision floating point SPE instructions. As U-Boot
does not use floating point, it is fine to use -mcpu=8540 for both e500v1
and e500v2 cores. Moreover gcc 9 completely removed e500 floating point
support, so since gcc 9 -mcpu=8548 is just alias to -mcpu=8540.

Note that U-Boot's CONFIG_E500 option is set also for other cpus, not only
for e500v1 and e500v2. So do not check for CONFIG_E500 and rather set e500
as last fallback value when no other mpc85xx cpu matches.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-12-22 15:39:13 -05:00
Heinrich Schuchardt
56e3b14703 net: don't memcpy to NULL
In ndisc_receive() 7 bytes are copied from a buffer of size 6 to NULL.

net_nd_packet_mac is a pointer. If it is NULL, we should set it to the
address of the buffer with the MAC address.

Addresses-Coverity-ID: 430974 ("Out-of-bounds access")
Fixes: c6610e1d90ea ("net: ipv6: Add Neighbor Discovery Protocol (NDP)")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
2022-12-22 15:39:13 -05:00
Viacheslav Mitrofanov
0d6d5a4aa6 net: ipv6: Add missing break into IPv6 protocol handler
IPv6 protocol handler is not terminated with a break statment.
It can lead to running unexpected code.

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2022-12-22 15:39:13 -05:00
Jagan Teki
f365971229 spl: Kconfig: Fix SPL_OPTEE_IMAGE dependency
fdt_addr will build as part of SPL_LOAD_FIT or SPL_LOAD_FIT_FULL
which is indeed required to build optee image support in SPL.

common/spl/spl.c: In function ‘jump_to_image_optee’:
common/spl/spl.c:220:46: error: ‘struct spl_image_info’ has no member named ‘fdt_addr’
  220 |         spl_optee_entry(NULL, NULL, spl_image->fdt_addr,

Fix the dependency support.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2022-12-22 15:39:13 -05:00
Tom Rini
dcb0cc0169 CI: Reduce aarch64 catchall job matches
The aarch64 catch-all job is getting close to the hard time limit in
Azure for the free tier. Move i.MX9 boards to the i.MX8 job and move
amlogic entirely to its own job. This brings us down from 85 boards to
51 boards and so should be safe for a while.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 15:39:13 -05:00
Tom Rini
52d91e1c20 Merge branch '2022-12-21-CONFIG-migration-work' into next
- Bring in the second to last big batch of CONFIG migrations and
  renames. Of note here we fix a few inconsistencies around the baudrate
  tables on some SoCs and now are consistent in hostname/etc handling in
  the environment.
2022-12-22 10:33:04 -05:00
Tom Rini
8214b772cf T104xRDB: Remove non-TARGET_T1042D4RDB variants
At this point only the TARGET_T1042D4RDB variant of this is supported in
tree, so remove the remaining parts of the other platforms.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:49 -05:00
Tom Rini
46df77669e nxp: Rename CONFIG_U_BOOT_HDR_SIZE to FSL_U_BOOT_HDR_SIZE
This is always defined to 16K, so we move this over to
include/fsl_validate.h to start with. Next, we rename this from CONFIG_
to FSL_. Coalesce the various comments around this definition to be in
fsl_validate.h as well to explain the usage.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:49 -05:00
Tom Rini
0c3a6d443f usb: Remove CONFIG_USBD_HS
This define is not enabled by the only platform which currently enables
the legacy option of CONFIG_USB_DEVICE. We can drop this code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:49 -05:00
Tom Rini
8747decc9b net: vsc9953: Remove this driver
No platforms enable this driver as there's no T1040D4RDB nor T1040RDB
support at this time.  Remove.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:49 -05:00
Tom Rini
4fd9373bbb net: Remove more legacy functions
Remove some of the board and arch specific non-DM_ETH helper code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:49 -05:00
Tom Rini
60910a3f02 Convert CONFIG_THOR_RESET_OFF to Kconfig
This converts the following to Kconfig:
   CONFIG_THOR_RESET_OFF

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
d14f3f2725 Convert CONFIG_TEGRA_ENABLE_UARTA et al to Kconfig
This converts the following to Kconfig:
   CONFIG_TEGRA_ENABLE_UARTA
   CONFIG_TEGRA_ENABLE_UARTB
   CONFIG_TEGRA_ENABLE_UARTC
   CONFIG_TEGRA_ENABLE_UARTD
   CONFIG_TEGRA_SPI
   CONFIG_TEGRA_UARTA_GPU
   CONFIG_TEGRA_UARTA_SDIO1
   CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
   CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
32b7e39db4 Convert CONFIG_STANDALONE_LOAD_ADDR to Kconfig
This converts the following to Kconfig:
   CONFIG_STANDALONE_LOAD_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
c46597155e sandbox: Finish migration to Kconfig
Stop using CONFIG_SANDBOX_ARCH and use CONFIG_SANDBOX instead. For the
SPI related defines, set them directly in Kconfig. This now empties
arch/sandbox/include/asm/config.h.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-22 10:31:48 -05:00
Tom Rini
abbb4043c4 powerpc: Migrate CONFIG_PPC_SPINTABLE_COMPATIBLE to Kconfig
Move this symbol to Kconfig, and preserve the current behavior. The
help text here comes from where the relevant code is implemented and it
is quite likely at this point in time we could either disable this
option or at least make it configurable.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
f55281665a arm: ti814x: Remove remaining support code
When the ti814x_evm config was removed most, but not all, of the
relevant support code was remove.  Get rid of what was missed.

Fixes: 50b532686849 ("ti814x: Remove platform")
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
2b210540b1 Convert CONFIG_PEN_ADDR_BIG_ENDIAN to Kconfig
This converts the following to Kconfig:
   CONFIG_PEN_ADDR_BIG_ENDIAN

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
0a69d6afca Convert CONFIG_OVERWRITE_ETHADDR_ONCE to Kconfig
This converts the following to Kconfig:
   CONFIG_OVERWRITE_ETHADDR_ONCE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
3348c6b6a5 etamin: Rework CONFIG_NAND_CS_INIT
Enable this in the board Kconfig file, but then check for it via
CONFIG_IS_ENABLED so that it will only be true in the non-SPL case, as
is done today.  As part of this we move some defines local to where
they are used as it's board specific.

Cc: Samuel Egli <samuel.egli@siemens.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
71894173bb Convert CONFIG_MXC_NAND_HWECC to Kconfig
This converts the following to Kconfig:
   CONFIG_MXC_NAND_HWECC

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
e52fca2236 Convert CONFIG_MONITOR_IS_IN_RAM to Kconfig
This converts the following to Kconfig:
   CONFIG_MONITOR_IS_IN_RAM

As part of this, reword some of the documentation slightly to reflect
that this is in Kconfig and not a define now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
829e9d2236 ddr: fsl: Remove CONFIG_MEM_INIT_VALUE
The way all of the memory init code here works is that we pass
0xDEADBEEF around for the initial value (as it's a well known 'poison'
value and so easily recognized in debuggers, etc). The only point of
this CONFIG symbol was to pass in a different value for that purpose.
Drop this symbol and cleanup the code slightly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
2cc61a631b malta: Rename CONFIG_MALTA to CONFIG_TARGET_MALTA
Fixup this last remnant of CONFIG_MALTA.

Cc: Paul Burton <paul.burton@mips.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
960379d450 Convert CONFIG_L2_CACHE to Kconfig
This converts the following to Kconfig:
   CONFIG_L2_CACHE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
acdf89ec06 Convert CONFIG_KSNET_NETCP_V1_0 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_KSNET_NETCP_V1_0
   CONFIG_KSNET_NETCP_V1_5

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
308520b8f2 global: Remove unused CONFIG symbols
This removes the following unreferenced CONFIG symbols:
   CONFIG_FDTADDR
   CONFIG_FDTFILE
   CONFIG_FLASH_SECTOR_SIZE
   CONFIG_FSL_CPLD
   CONFIG_HDMI_ENCODER_I2C_ADDR
   CONFIG_I2C_MVTWSI
   CONFIG_I2C_RTC_ADDR
   CONFIG_IRAM_END
   CONFIG_IRAM_SIZE
   CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
   CONFIG_L1_INIT_RAM
   CONFIG_MACB_SEARCH_PHY
   CONFIG_MIU_2BIT_21_7_INTERLEAVED
   CONFIG_MTD_NAND_VERIFY_WRITE
   CONFIG_MVGBE_PORTS
   CONFIG_NETDEV
   CONFIG_NUM_DSP_CPUS
   CONFIG_PHY_BASE_ADR
   CONFIG_PHY_INTERFACE_MODE
   CONFIG_PSRAM_SCFG
   CONFIG_RAMBOOT_SPIFLASH
   CONFIG_RAMBOOT_TEXT_BASE
   CONFIG_RD_LVL
   CONFIG_ROCKCHIP_SDHCI_MAX_FREQ
   CONFIG_SETUP_INITRD_TAG
   CONFIG_SH_QSPI_BASE
   CONFIG_SMDK5420
   CONFIG_SOCRATES
   CONFIG_SPI_ADDR
   CONFIG_SPI_FLASH_QUAD
   CONFIG_SPI_FLASH_SIZE
   CONFIG_SPI_HALF_DUPLEX
   CONFIG_SPI_N25Q256A_RESET
   CONFIG_TEGRA_SLINK_CTRLS
   CONFIG_TPM_TIS_BASE_ADDRESS
   CONFIG_UBOOT_SECTOR_COUNT
   CONFIG_UBOOT_SECTOR_START
   CONFIG_VAR_SIZE_SPL
   CONFIG_VERY_BIG_RAM

And also:
   BL1_SIZE
   PHY_NO
   RESERVE_BLOCK_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
1353b25ec5 i2c: Remove CONFIG_I2C_MULTI_BUS
This functionality is part of the legacy I2C subsystem and is currently
unused anywhere.  Remove the remaining references.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
495fc3e836 env: eeprom: Remove CONFIG_I2C_ENV_EEPROM_BUS support
This functionality is currently unused, and has not been migrated to
using DM_I2C, even. Drop this.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
b5f7d88162 arm: samsung: Rename CONFIG_G_DNL_*_NUM variables
Following how g_dnl_bind_fixup is used on other platforms, rename the
unchanging defines used here to be prefixed with EXYNOS rather than
Samsung, and define them here.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
54f80dd290 Convert CONFIG_HOSTNAME et al to Kconfig
This converts the following to Kconfig:
   CONFIG_GATEWAYIP
   CONFIG_HOSTNAME
   CONFIG_IPADDR
   CONFIG_NETMASK
   CONFIG_ROOTPATH
   CONFIG_SERVERIP
   CONFIG_UBOOTPATH

To do this, we introduce a CONFIG_USE_ form of each of the above and
change include/env_default.h to test for that to be set before setting a
value. Further, we don't want to stringify the IP address related values
as they are now properly strings via Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
3f7a496531 Convert CONFIG_POWER_PCA9450 to Kconfig
This converts the following to Kconfig:
   CONFIG_POWER_PCA9450

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
b95de034c5 meson64: Fix missing CFG_SYS_BAUDRATE_TABLE migration
CONFIG_SYS_BAUDRATE_TABLE has already been migrated to CFG_SYS but this
instance was missed, correct.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
f3b516852e CONFIG_SYS_MPC8xxx_GUTS_ADDR: Migrate to CFG_SYS
Due to whitespace, CONFIG_SYS_MPC8xxx_GUTS_ADDR wasn't migrated to
CFG_SYS previously. Do this now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
ade03b55c4 env: nvram: Drop CONFIG_SYS_NVRAM_ACCESS_ROUTINE
This option is unused anywhere and likely untested for quite a long
while. Drop this support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
5388aa2851 Convert CONFIG_FSL_ESDHC_PIN_MUX to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_ESDHC_PIN_MUX

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
3a581af21a Convert CONFIG_FLASH_SPANSION_S29WS_N et al to Kconfig
This converts the following to Kconfig:

   CONFIG_FLASH_SPANSION_S29WS_N
   CONFIG_FLASH_VERIFY
   CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
   CONFIG_FSL_ISBC_KEY_EXT
   CONFIG_FSL_TRUST_ARCH_v1
   CONFIG_FSL_SDHC_V2_3
   CONFIG_MAX_DSP_CPUS
   CONFIG_MIU_2BIT_INTERLEAVED
   CONFIG_SERIAL_BOOT
   CONFIG_SPI_BOOTING
   CONFIG_X86EMU_RAW_IO

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
98fbad631f Convert CONFIG_FLASH_SHOW_PROGRESS to Kconfig
This converts the following to Kconfig:
   CONFIG_FLASH_SHOW_PROGRESS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00
Tom Rini
21491883d2 fec_mxc: Remove CONFIG_FEC_FIXED_SPEED support
This option is only used on one platform currently. However, with PHYLIB
enabled, which this platform also does, this option is not checked and
the functional use case is handled. Remove this code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:47 -05:00
Tom Rini
9b0240f8c6 Convert CONFIG_DM9000_BYTE_SWAPPED et al to Kconfig
This converts the following to Kconfig:
   CONFIG_DM9000_BYTE_SWAPPED
   CONFIG_DM9000_NO_SROM
   CONFIG_DM9000_USE_16BIT
   CONFIG_DM9000_DEBUG
   CONFIG_MXC_GPT_HCLK
   CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:47 -05:00
Tom Rini
6bd2372094 env: Rework ENV_IS_EMBEDDED and related logic slightly
- Drop CONFIG_BUILD_ENVCRC as this is never set directly but instead
  means ENV_IS_EMBEDDED, so reference that in code and rename the Makefile
  usage to BUILD_ENVCRC.
- Remove extra-$(CONFIG_ENV_IS_EMBEDDED) line as it could never be true,
  and likely why there is an extra- line for CONFIG_ENV_IS_IN_FLASH (the
  only use case today of embedded environments).
- With these slight changes we can then see that using the calculated
  symbol of ENV_IS_EMBEDDED is the right thing to use in any code which
  needs to know this situation and can remove CONFIG_ENV_IS_EMBEDDED
  entirely.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:47 -05:00
Tom Rini
2440b5bb52 Convert CONFIG_HSMMC2_8BIT to Kconfig
This converts the following to Kconfig:
   CONFIG_HSMMC2_8BIT

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:47 -05:00
Tom Rini
5125e136a9 arm: trats2: Set mmcdev directly
Only this platform sets mmcdev via CONFIG_MMC_DEFAULT_DEV so we
hard-code that default directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:47 -05:00
Tom Rini
5732cf24dd x530: Remove unused symbols
The symbols CONFIG_UBI_PART and CONFIG_UBIFS_VOLUME are not referenced
anywhere, drop them.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:47 -05:00
Tom Rini
b41eb5a27e p1_p2_rdb: Remove unused environment sections
The CONFIG_USB_FAT_BOOT, CONFIG_USB_EXT2_BOOT and CONFIG_NORBOOT defines
are not referenced anywhere, so remove them.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:37 -05:00
Tom Rini
4475d017c5 arm: exynos5: Migrate USB_BOOTING to Kconfig
This symbol is enabled for all exynos5 platforms, move to Kconfig and
select it.

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-21 19:04:33 -05:00
Tom Rini
7d212af2b1 usb: Update USB_STORAGE dependencies
As it's no longer possible to have !DM_USB set, we can remove these
dependencies.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-21 19:04:33 -05:00
Tom Rini
14f43797d0 Prepare v2023.01-rc4
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Merge tag 'v2023.01-rc4' into next

Prepare v2023.01-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-21 13:09:01 -05:00
Tom Rini
1154e965d0 Pull request for efi-2023-01-rc5
UEFI:
 
 * Improve parameter checking in efi_get_next_variable_name_mem()
 * Fix a bugs in management of security database via the eficonfig command
 
 Other:
 
 * Allow sound command to play multiple sounds
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Merge tag 'efi-2023-01-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2023-01-rc5

UEFI:

* Improve parameter checking in efi_get_next_variable_name_mem()
* Fix a bugs in management of security database via the eficonfig command

Other:

* Allow sound command to play multiple sounds
2022-12-20 12:50:48 -05:00
Tom Rini
566bc672a7 fTPM privileged login
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Merge tag 'tpm-20122022' of https://source.denx.de/u-boot/custodians/u-boot-tpm

fTPM privileged login
2022-12-20 12:50:24 -05:00
Masahisa Kojima
ad50ca5019 eficonfig: EFI_VARIABLE_APPEND_WRITE is not set for null key
The signed null key with authenticated header is used to clear
the PK, KEK, db and dbx. When CONFIG_EFI_MM_COMM_TEE is enabled
(StMM and OP-TEE based RPMB storage is used as the EFI variable
storage), clearing KEK, db and dbx by enrolling a signed null
key does not work as expected if EFI_VARIABLE_APPEND_WRITE
attritube is set.

This commit checks the selected file is null key, then
EFI_VARIABLE_APPEND_WRITE attibute will not be used for the null key.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-20 16:06:48 +01:00
Heinrich Schuchardt
9ba35e64fa efi_selftest: conformance test for GetNextVariableName
Test that GetNextVariableName() checks the parameters.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-20 16:06:48 +01:00
Heinrich Schuchardt
70a4ac693d efi_loader: fix efi_get_next_variable_name_mem()
The VariableNameSize parameter is in bytes but u16_strnlen() counts u16.

Fix the parameter check for null termination.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-20 16:06:48 +01:00
Masahisa Kojima
645502743a eficonfig: avoid SetVariable between GetNextVariableName calls
The current code calls efi_set_variable_int() to delete the
invalid boot option between calls to efi_get_next_variable_name_int(),
it may produce unpredictable results.

This commit moves removal of the invalid boot option outside
of the efi_get_next_variable_name_int() calls.
EFI_NOT_FOUND returned from efi_get_next_variable_name_int()
indicates we retrieved all EFI variables, it should be treated
as EFI_SUCEESS.

To address the checkpatch warning of too many leading tabs,
combine two if statement into one.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-20 16:06:48 +01:00
Masahisa Kojima
ce3270849b eficonfig: carve out efi_get_next_variable_name_int calls
To retrieve the EFI variable name by efi_get_next_variable_name_int(),
the sequence of alloc -> efi_get_next_variable_name_int ->
realloc -> efi_get_next_variable_name_int is required.
In current code, this sequence repeatedly appears in
the several functions. It should be curved out a common function.

This commit also fixes the missing free() of var_name16
in eficonfig_delete_invalid_boot_option().

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-20 16:06:48 +01:00
Heinrich Schuchardt
f823e32388 test: add unit test for u16_strnlen()
Add the missing unit test. It can be executed with:

    ut unicode u16_strnlen

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-20 16:06:48 +01:00
Heinrich Schuchardt
f9178e19a1 doc: correct heading level in printenv man-page
The 'Configuration' heading should be on level 2, not on level 1.

Fixes: eaa268589e9c ("doc: man-page for the printenv command")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-20 16:06:48 +01:00
Heinrich Schuchardt
ea58b9a404 cmd: allow sound command to play multiple sounds
Currently the sound command accepts only one value each for duration and
frequency. Allowing more duration and frequency arguments enables playing a
tune.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-20 16:06:48 +01:00
Eugen Hristev
8374617637 ARM: dts: at91: sama5d2: fix wrong interrupt-cells property
The PMC node is not an interrupt provider, so it must not have
interrupt-cells.

This fixes the warning (on newer DTC):
arch/arm/dts/sama5d2.dtsi:82.22-602.6: Warning (interrupt_provider): /ahb/apb/pmc@f0014000: '#interrupt-cells' found, but node is not an interrupt provider

Fixes: 2c4b2dd289 ("ARM: at91/dt: Add device tree for SAMA5D2 Xplained")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2022-12-20 11:59:07 +02:00
Mihai Sain
a60c5a986e ARM: mach-at91: add support for sama7g5 chip id and extended id definition
Add SAMA7G5 series chip id definitions to align with linux SoC driver.
Add support for SAMA7G5 System-In-Package (SIP):
SAMA7G54D1G, SAMA7G54D2G, SAMA7G54D4G.

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2022-12-20 11:59:07 +02:00
Eugen Hristev
4df35b38d1 ARM: dts: at91: sama7g5/sama7g5ek: align DT with kernel 6.1
Align the DT with current Linux 6.1 tree, wherever possible.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2022-12-20 11:59:07 +02:00
Eugen Hristev
9859b9a722 sysreset: at91: add compatible with microchip, sama7g5-rstc
As documented in bindings doc in kernel 6.0:
https://elixir.bootlin.com/linux/v6.0/source/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2022-12-20 11:59:07 +02:00
Eugen Hristev
f2d6c888f4 dt-bindings: mfd: add at91-usart.h from Linux
Copy include file dt-bindings/mfd/at91-usart.h from Linux

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2022-12-20 11:59:07 +02:00
Etienne Carriere
33ba80303e tpm2: ftpm: open session with privileged ree login
Opens the fTPM session with TEE_LOGIN_REE_KERNEL as fTPM may restrict
access to that login when Linux based OS is running as applications are
expected to got through the Linux TPMv2 driver.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-20 09:37:36 +02:00
Tom Rini
2243922edc Prepare v2023.01-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-19 08:45:26 -05:00
Tom Rini
daa531cc5c Merge tag 'u-boot-rockchip-20221219' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Only call binman when TPL available;
- rk3128 DTS fix;
- Fix GPT table corruption for rk3399 puma ;
- Fix i2c for rk3399 Pinebookpro;
- Enable UEFI capsule update for RockPi4;
2022-12-19 08:33:24 -05:00
Sughosh Ganu
bdd3a47e02 rockpi4: capsule: Enable UEFI capsule update on RockPi4 boards
Enable the UEFI capsule update functionality on the RockPi4B and
RockPi4C boards. Support is being enabled for updating the idbloader
and u-boot firmware images residing on GPT partitioned uSD card
storage device.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Sughosh Ganu
e86c789ca3 rockpi4: board: Add firmware image information for capsule updates
Add information that will be needed for enabling the UEFI capsule
update feature on the RockPi4 boards. With the feature enabled, it
would be possible to update the idbloader and u-boot.itb images on the
RockPi4B and RockPi4C variants.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Sughosh Ganu
bea9267d7e rockchip: capsule: Add functions for supporting capsule updates
Add functions needed to support the UEFI capsule update feature on
rockchip boards. Currently, the feature is being enabled on the
RockPi4 boards with firmware images residing on GPT partitioned
storage media.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
John Keeping
b5194c2258 phy: rockchip: handle clock without enable function
If a clock doesn't supply the enable hook, clk_enable() will return
-ENOSYS.  In this case the clock is always enabled so there is no error
and the phy initialisation should continue.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Michal Suchanek
216928c772 rockchip: Pinebook Pro: Do not initialize i2c before relocation
The i2c locks up when initialized before relocation, and it stays broken
in Linux as well breaking the ability to boot Linux.

The i2c bus and pmic was not actually used in pre-reloc before
commit ad607512f575 ("power: pmic: rk8xx: Support sysreset shutdown method")

The cause is not known.

This is board-specific, other boards that do not add the option to
include the i2c bus in pre-reloc DT are not affected.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Quentin Schulz
c74f6e748b rockchip: puma: fix GPT table corruption when saving U-Boot environment
The GPT table is taking the first 34 sectors, which amounts to 0x4400
bytes. Saving the environment below this address in storage will corrupt
the GPT table.

While technically the table ends at 0x4400, some tools (e.g. bmaptool)
are rounding everything to the logical block size (0x1000), so it is
safer to make it point to 0x5000 so that the environment could still
persist when flashing a sparse image with bmaptool or similar tools.

Obviously, the default 0x4000 environment size does not work anymore, so
let's set it to 0x3000 so it does fill the gap between the GPT table
(rounded to 0x1000) and the start of the idbloader.img.

Fixes: 56f580d3eb8d ("rockchip: dts: rk3399-puma: put environment (in MMC/SD configurations) before SPL")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
FUKAUMI Naoki
75a364eb05 arm: dts: rockchip: enable ums/rockusb command for ROCK Pi 4
this patch add USB mass storage function and Rockusb function for
Radxa ROCK Pi 4 series.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Manoj Sai
22e443c76d configs:rockchip:roc-rk3399-pc:Enable more configs
This patch enables the following:

1) use preboot configuration to enable usb devices.

2) Enable USB configs so keyboards and other USB devices work,
   update the number of ports of the usb root hub.

   - with this addition the updated USB device Tree:

	1  Hub (12 Mb/s, 0mA)
	U-Boot Root Hub
	1  Hub (12 Mb/s, 0mA)
	|   U-Boot Root Hub
	|
	+-2  Hub (12 Mb/s, 100mA)
	USB 2.0 Hub [MTT]

	1  Hub (5 Gb/s, 0mA)
	U-Boot XHCI Host Controller

3) enable crypto RNG support.

4) Change SPI speed and frequency:
    - increase the maximum SPI slave device speed,
      SPI flash max frequency for the environment from 10Mhz to 30MHz.

    - performance stats for speed update from 10MHz to 30MHz:

    	with 10Mhz speed update:
    	 => sf update 0x300000 0x800000 0x400000
    	    4194304 bytes written, 0 bytes skipped in 36.819s, speed 119837 B/s

        with 30Mhz speed update:
    	 => sf update 0x300000 0x800000 0x400000
    	    4194304 bytes written, 0 bytes skipped in 20.319s, speed 220752 B/s

Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Da Xue <da.xue@libretech.co>
Signed-off-by: dsx724 <da@lessconfused.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Johan Jonker
58eb6675da arm: dts: rockchip: rk3128: fix clocks, compatible and phys
Fix rk3128 clocks, compatible and phys, so that they match the bindings.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
2022-12-19 10:56:12 +08:00
Johan Jonker
565d77b4c0 arm: dts: rockchip: rk3128: fix DT node names
The rk3128 DT node names should be generic.
Rename them to the pattern defined in the DT bindings.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
2022-12-19 10:56:12 +08:00
Johan Jonker
b919d43af5 arm: dts: rockchip: move all rk3128 u-boot specific properties in separate dtsi files
Move all rk3128 u-boot specific properties in separate dtsi files.
Sort emmc node.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Johan Jonker
c643468849 arm: dts: rockchip: rk3128: bulk convert gpios to their constant counterparts
Bulk convert rk3128 DT gpios to their constant counterparts.

sed -i -f script.sed rk3128.dtsi
sed -i -f script.sed rk3128-evb.dts

================================

/rockchip,pins *=/bcheck
b # to end of script
:append-next-line
N
:check
/^[^;]*$/bappend-next-line
s/<RK_GPIO\([0-9]\) /<\1 /g
s/<\([^ ][^ ]*  *\)0 /<\1RK_PA0 /g
s/<\([^ ][^ ]*  *\)1 /<\1RK_PA1 /g
s/<\([^ ][^ ]*  *\)2 /<\1RK_PA2 /g
s/<\([^ ][^ ]*  *\)3 /<\1RK_PA3 /g
s/<\([^ ][^ ]*  *\)4 /<\1RK_PA4 /g
s/<\([^ ][^ ]*  *\)5 /<\1RK_PA5 /g
s/<\([^ ][^ ]*  *\)6 /<\1RK_PA6 /g
s/<\([^ ][^ ]*  *\)7 /<\1RK_PA7 /g
s/<\([^ ][^ ]*  *\)8 /<\1RK_PB0 /g
s/<\([^ ][^ ]*  *\)9 /<\1RK_PB1 /g
s/<\([^ ][^ ]*  *\)10 /<\1RK_PB2 /g
s/<\([^ ][^ ]*  *\)11 /<\1RK_PB3 /g
s/<\([^ ][^ ]*  *\)12 /<\1RK_PB4 /g
s/<\([^ ][^ ]*  *\)13 /<\1RK_PB5 /g
s/<\([^ ][^ ]*  *\)14 /<\1RK_PB6 /g
s/<\([^ ][^ ]*  *\)15 /<\1RK_PB7 /g
s/<\([^ ][^ ]*  *\)16 /<\1RK_PC0 /g
s/<\([^ ][^ ]*  *\)17 /<\1RK_PC1 /g
s/<\([^ ][^ ]*  *\)18 /<\1RK_PC2 /g
s/<\([^ ][^ ]*  *\)19 /<\1RK_PC3 /g
s/<\([^ ][^ ]*  *\)20 /<\1RK_PC4 /g
s/<\([^ ][^ ]*  *\)21 /<\1RK_PC5 /g
s/<\([^ ][^ ]*  *\)22 /<\1RK_PC6 /g
s/<\([^ ][^ ]*  *\)23 /<\1RK_PC7 /g
s/<\([^ ][^ ]*  *\)24 /<\1RK_PD0 /g
s/<\([^ ][^ ]*  *\)25 /<\1RK_PD1 /g
s/<\([^ ][^ ]*  *\)26 /<\1RK_PD2 /g
s/<\([^ ][^ ]*  *\)27 /<\1RK_PD3 /g
s/<\([^ ][^ ]*  *\)28 /<\1RK_PD4 /g
s/<\([^ ][^ ]*  *\)29 /<\1RK_PD5 /g
s/<\([^ ][^ ]*  *\)30 /<\1RK_PD6 /g
s/<\([^ ][^ ]*  *\)31 /<\1RK_PD7 /g
s/<\([^ ][^ ]*  *[^ ][^ ]*  *\)0 /<\1RK_FUNC_GPIO /g
s/<\([^ ][^ ]*  *[^ ][^ ]*  *\)RK_FUNC_\([1-9]\) /<\1\2 /g

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Johan Jonker
4d89330b8a rockchip: rk3128-cru: sync the clock dt-binding header from Linux
In order to update the DT for rk3128
sync the clock dt-binding header.
This is the state as of v6.0 in Linux.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
FUKAUMI Naoki
96d926cac3 rockchip: enable fdt overlays for ROCK Pi 4 series
add CONFIG_OF_LIBFDT_OVERLAY=y to support fdt overlays.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19 10:56:12 +08:00
Kever Yang
f5315dd629 rockchip: Only call binman when TPL available
Rockchip platform use TPL to do the DRAM initialize for all the SoCs,
if TPL is not available, means no available DRAM init program, and the
u-boot-rockchip.bin is not functionable.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I2299f1eddce5aa7d5fb1a3fb4d8aeaa995b397fa
2022-12-19 10:55:58 +08:00
Tom Rini
93685d0dcb Makefile: With BINMAN_ALLOW_MISSING=1 don't error on missing
When the user builds with BINMAN_ALLOW_MISSING=1 they're explicitly
setting the flag to allow for additional binaries to be missing and so
have acknowledged the output might not work. In this case we want to
default to not passing a non-zero exit code.

Cc: Simon Glass <sjg@chromium.org>
Reported-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-18 20:50:40 -05:00
Tom Rini
255cebbfa3 Pull request for efi-2023-01-rc4
Documentation:
 
 * Fix htmldoc build dependency
 
 UEFI:
 
 * Adjust EBBR version for compatibility table
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Merge tag 'efi-2023-01-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2023-01-rc4

Documentation:

* Fix htmldoc build dependency

UEFI:

* Adjust EBBR version for compatibility table
2022-12-18 08:10:09 -05:00
Tom Rini
55e374f508 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
This cleans up each board's defconfig, and fixes the serial console on
some Olimex board. Also we lose another legacy config variable.
The rest are minor cleanups, that actually shouldn't change anything
in the build.

Passed the gitlab CI, plus briefly tested on Pine64-LTS, LicheePi Nano,
and BananaPi M1.
2022-12-18 08:08:55 -05:00
Heinrich Schuchardt
5b5f6e0d61 doc: update Sphinx requirements for certifi
Upgrade to version 2022.12.7.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-17 15:25:52 +00:00
Vincent Stehlé
63db1561f1 efi: adjust ebbr to v2.1 in conformance profile
The EFI Conformance Profile Table entry for EBBR appears in v2.1.0 of the
EBBR specification[1]. Update naming accordingly.

While at it, update the EBBR version referenced in the documentation.

[1]: https://github.com/ARM-software/ebbr/releases/tag/v2.1.0

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-17 13:37:33 +00:00
Maxim Cournoyer
e7d962bc3c doc: fix typos
Fix a few typos spot during a first read of the contribution process.

Signed-off-by: Maxim Cournoyer <maxim.cournoyer@savoirfairelinux.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-17 13:37:33 +00:00
Tom Rini
9bd3d354a1 Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- Adjust CONFIG_TEXT_BASE for BayTrail based platforms
- 2 cosmetic issue fixes
2022-12-15 13:06:00 -05:00
Andre Przywara
64531496f9 sunxi: board: annotate #endif lines
The legacy Allwinner code is cluttered with #ifdef's, some of them even
nested, which makes the code hard to read and error prone.
Eventually we will get rid of most of them, but for now let's at least
annotate the #endif lines with the corresponding symbol the bracket
started with.

Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-12-14 22:31:33 +00:00
Andre Przywara
eeaca6ac27 sunxi: remove bogus mmc_pinmux_setup() prototype
Since all callers of mmc_pinmux_setup() are located after the definition
of that function, there is no need for a forward declaration (anymore?).

Remove the prototype along with its #ifdef guards.

Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-12-14 22:31:25 +00:00
Andre Przywara
ed82586c40 sunxi: remove unused CONFIG_MMC_SUNXI_SLOT
There is a CONFIG_MMC_SUNXI_SLOT definition in our sunxi_common.h config
header, which was used to note the first MMC controller to initialise.
The definition in that header was always set to 0, with no easy way of
overriding this, and certainly none of the existing boards made any use
of that (non-)feature.
Remove that definition and replace it with a constant 0 in the only
user, in board.c. It turns out that this is safe, as this is only used
in the SPL, and the BROM also unconditionally initialises MMC0.
This also removes the last legacy config symbol with SUN*I in it from
the whitelist.

Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-12-14 22:31:06 +00:00
Bin Meng
58e2a35f2e x86: cosmetic: Fix a typo in the reserve_arch() comments
It should be fsp_continue().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-14 12:04:51 +08:00
Bin Meng
e23cae3080 x86: som-db5800-som-6867: Adjust CONFIG_TEXT_BASE
At present U-Boot no longer builds as a complete rom for som-db5800-som-6867.

    BINMAN  .binman_stamp
  Wrote map file './rom.map' to show errors
  binman: Section '/binman/rom': contents size 0x80302c (8400940) exceeds section size 0x800000 (8388608)

Checking rom.map we see 'intel-vga' section is overlapped with
other sections:

  <none>     fff00000  0009f7c8  u-boot-with-ucode-ptr
  <none>     fff90000  00010000  intel-vga
  <none>     fff9f7c8  00001aae  u-boot-dtb-with-ucode

Let's adjust CONFIG_TEXT_BASE to allow more space for U-Boot codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2022-12-14 12:04:51 +08:00
Bin Meng
5d1c8342ae x86: dfi-bt700: Adjust CONFIG_TEXT_BASE
At present U-Boot no longer builds as a complete rom for all the
configs of dfi-bt700.

    BINMAN  .binman_stamp
  Wrote map file './rom.map' to show errors
  binman: Section '/binman/rom': contents size 0x80e836 (8448054) exceeds section size 0x800000 (8388608)

Checking rom.map we see 'intel-vga' section is overlapped with
other sections:

  <none>     fff00000  000aac90  u-boot-with-ucode-ptr
  <none>     fffa0000  00010000  intel-vga
  <none>     fffaac90  00001df0  u-boot-dtb-with-ucode
  <none>     fffaca80  00019800  u-boot-ucode

Let's adjust CONFIG_TEXT_BASE to allow more space for U-Boot codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-12-14 12:04:51 +08:00
Bin Meng
388f93f963 x86: conga-qeval20-qa3-e3845: Adjust CONFIG_TEXT_BASE
At present U-Boot no longer builds as a complete rom for all the
configs of conga-qeval20-qa3-e3845.

    BINMAN  .binman_stamp
  Wrote map file './rom.map' to show errors
  binman: Section '/binman/rom': contents size 0x80b680 (8435328) exceeds section size 0x800000 (8388608)

Checking rom.map we see 'intel-vga' section is overlapped with
other sections:

  <none>     fff00000  000a7cb0  u-boot-with-ucode-ptr
  <none>     fffa0000  00010000  intel-vga
  <none>     fffa7cb0  00001c1a  u-boot-dtb-with-ucode
  <none>     fffa98d0  00019800  u-boot-ucode

Let's adjust CONFIG_TEXT_BASE to allow more space for U-Boot codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2022-12-14 12:04:51 +08:00
Bin Meng
66e2c665f3 x86: minnowmax: Adjust CONFIG_TEXT_BASE
At present U-Boot no longer builds as a complete rom for minnowmax.

    BINMAN  .binman_stamp
  Wrote map file './rom.map' to show errors
  binman: Section '/binman/rom': contents size 0x803146 (8401222) exceeds section size 0x800000 (8388608)

Checking rom.map we see 'fdtmap' section is overlapped with
'intel-vga' section:

  <none>     fffa1390  00019800  u-boot-ucode
  <none>     fffb0000  00010000  intel-vga
  <none>     fffbab90  00000539  fdtmap

Let's adjust CONFIG_TEXT_BASE to allow more space for U-Boot codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-14 12:04:51 +08:00
Bin Meng
f38be30868 x86: bayleybay: Adjust CONFIG_TEXT_BASE
At present U-Boot no longer builds as a complete rom for bayleybay.

    BINMAN  .binman_stamp
  Wrote map file './rom.map' to show errors
  binman: Section '/binman/rom': contents size 0x814706 (8472326) exceeds section size 0x800000 (8388608)

Checking rom.map we see 'fdtmap' section is overlapped with
'intel-vga' and 'intel-fsp' sections:

  <none>     fffa2150  0002a000  u-boot-ucode
  <none>     fffb0000  00010000  intel-vga
  <none>     fffc0000  00038000  intel-fsp
  <none>     fffcc150  00000539  fdtmap

Let's adjust CONFIG_TEXT_BASE to allow more space for U-Boot codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2022-12-14 12:04:51 +08:00
Alistair Delva
767df6a27d x86: Fix i8259 ifdef include guard
When building U-Boot with clang, it notices that the i8259.h include
guard does not work correctly due to a typo. Fix it.

Signed-off-by: Alistair Delva <adelva@google.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-12-14 12:04:51 +08:00
Mark Kettenis
705209a095 sunxi: Fix serial console for A10s-OLinuXino-MICRO
On this board CONFIG_CONS_INDEX needs to be 1 unlike other sun5i
boards.  Since this is the default, remove to bogus setting.

Fixes: 7095f8641863 ("sunxi: Convert CONS_INDEX to Kconfig")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-12-14 01:37:04 +00:00
Samuel Holland
6cad8bea4f pinctrl: sunxi: Add P2WI and RSB pinmuxes
P2WI and RSB are used to communicate with a PMIC. Most SoCs have only
one possible pinmux. F1C100s has two possibilities, with different mux
values, so omit it until some board needs one of them.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-12-13 20:33:37 +00:00
Andre Przywara
b072aefbbe sunxi: define SYS_MONITOR_LEN in Kconfig, not _defconfig
Commit 08574ed339fb ("Convert CONFIG_SYS_MONITOR_LEN to Kconfig") moved
the definition of said config variable from the common sunxi header to
*every board's* defconfig.
This is a platform choice, not board specific, so remove the variable
from there, instead set the one value for all Allwinner boards in
Kconfig.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-12-13 20:33:31 +00:00
Tom Rini
9c955393f7 Merge branch '2022-12-12-build-related-updates' into next
- Updates to the keymile platforms for DM_I2C and text based
  environment migration
- Finish migration of MTDPART/MTDIDS_DEFAULT to defconfig
- Disable warning about RWX segments with gcc-12.2
2022-12-13 11:34:59 -05:00
Tom Rini
ed6251187a Revert "cmd: pxe_utils: Check fdtcontroladdr in label_boot"
With the change here, all extlinux.conf files with only "KERNEL
/fitImage" don't work anymore. One common example of this would be those
files generated by thee Poky/OE WIC bootimg-partition bootloader
partition generator.

This reverts commit d5ba6188dfbf6bb68354bec86e483623f1f6dae2.

Reported-by: Neil Armstrong <neil.armstrong@linaro.org>
Reported-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-13 09:26:25 -05:00
Holger Brunck
aeb13924f4 km/mpc8360: remove unused CONFIG_SYS_PAXE defines
These are unused defines and can be dropped.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2022-12-12 16:51:00 -05:00
Holger Brunck
31464f9455 km/ppc: migrate all mpc83xx to DM_I2C
Enable DM_I2C and I2C mux to get rid of the usage of the legacy
i2c driver.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2022-12-12 16:49:54 -05:00
Holger Brunck
400d1a7c94 board/km: remove obsolete ARCH_KIRKWOOD
We already removed the support for these boards.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2022-12-12 16:49:25 -05:00
Holger Brunck
3bcf9c08a3 board/km/secu: migrate to use environment text files
Instead of having these defines in a header file, move them to
a simple text file.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2022-12-12 16:49:25 -05:00
Holger Brunck
6f7c936fbd board/km/cent2: migrate to environment text file
Use like the other boards a text file for the environment.
As this is the last user of keymile-common.h we can now remove this
file completely.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2022-12-12 16:49:24 -05:00
Holger Brunck
0cc0c098c8 km/powerpc: migrate to env.txt file
Use already present common.env file and add a powerpc specific env
so that we can move all the environment defines to text files.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2022-12-12 16:48:33 -05:00
Holger Brunck
553d7607c6 board/km: move ls102xa boards to environment text files
Create a common.env which we can use later on also for other boards.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2022-12-12 16:47:21 -05:00
Patrick Delaunay
8b83d54f9e configs: remove support of MTDIDS_DEFAULT/MTDPARTS_DEFAULT
Complete the migration of MTDPARTS_DEFAULT / MTDIDS_DEFAULT in Kconfig;
this patch removes the support of MTDIDS_DEFAULT / MTDPARTS_DEFAULT
in the configuration files (include/configs/*.h).

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-12-12 16:46:07 -05:00
Patrick Delaunay
72e79f998e configs: SBx81LIFKW: move MTDPART_DEFAULT in defconfig
Replace MTDPARTS_DEFAULT in the config include file by
CONFIG_MTDPARTS_DEFAULT in defconfig to complete the Kconfig migration.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-12-12 16:46:07 -05:00
Patrick Delaunay
91b9551fb3 configs: SBx81LIFXCAT: move MTDPART_DEFAULT in defconfig
Replace MTDPARTS_DEFAULT in the config include file by
CONFIG_MTDPARTS_DEFAULT in defconfig to complete the Kconfig migration.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-12-12 16:46:07 -05:00
Patrick Delaunay
bde4a407ea configs: x530: move MTDPART/MTDIDS_DEFAULT in defconfig
Replace MTDIDS_DEFAULT and MTDPARTS_DEFAULT in the config include file by
CONFIG_MTDIDS_DEFAULT and CONFIG_MTDPARTS_DEFAULT in defconfig to complete
the Kconfig migration.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-12-12 16:46:07 -05:00
Patrick Delaunay
828d7e6022 configs: am333x_guardian: move MTDIDS_DEFAULT in defconfif
Replace MTDIDS_DEFAULT in config include file by CONFIG_MTDIDS_DEFAULT
in defonfig to complete the Kconfig migration

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-12-12 16:46:07 -05:00
Tom Rini
1e1c51f8ac Makefile: link with --no-warn-rwx-segments
We borrow from the Linux Kernel 0d362be5b142 ("Makefile: link with -z
noexecstack --no-warn-rwx-segments") here to disable the RWX segment
linking warnings. We do not also bring in -z noexecstack as that
requires auditing and using ".note.GNU-stack" on assembly functions
which do need this feature. Further, we now introduce KBUILD_EFILDFLAGS
so that we can also pass --no-warn-rwx-segments when linking EFI
applications, and those do explicitly pass -z execstack.

Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-12 16:46:07 -05:00
Tom Rini
259420703b Merge branch '2022-12-12-assorted-improvements' into next
- A number of PXE / sysboot related improvements
- Nuvoton updates
- Small updates to omap4, ARCH_OMAP2PLUS itself, mediatek
  pcie_designware.
2022-12-12 16:32:37 -05:00
Daniel Golle
178cbadb52 configs: set CONFIG_LMB_MAX_REGIONS=64 for all mt798[16] boards
With recently added wireless offloading features in Linux [1] the
number of reserved memory regions with MediaTek SoCs supporting
offloading wireless-to-Ethernet traffic grew beyond the default (8)
which breaks booting Linux:
ERROR: Failed to allocate 0xa6ac bytes below 0xc0000000.
device tree - allocation error
FDT creation failed!
resetting ...

Raise CONFIG_LMB_MAX_REGIONS to 64 like it is already done for other
SoCs which require a larger number of reserved memory regions, eg.
exynos78x0 based a3y17lte, a5y17lte and a7y17lte or dragonboard845c.

[1]: https://lore.kernel.org/netdev/e3489a697b404bd47447190cd2e5adf090ae61c2.1667687249.git.lorenzo@kernel.org/
     https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=eed4f1ddad8c5ad7596b229caec8bd7b477b81ee

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-12-12 14:03:12 -05:00
Jim Liu
8debdf1417 ARM: dts: npcm7xx: add npcm750 gpio node compatible name
Add npcm750 gpio node compatible name

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-12-12 14:03:12 -05:00
Jim Liu
74bf4899b5 ARM: dts: npcm8xx: add npcm845 function node
1. add usb phy
2. add ehci ohci sdhci
3. add pinctrl node
4. add fiu node

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-12-12 14:03:12 -05:00
Jim Liu
5e6becefb0 ARM: config: enable function for nuvoton npcm845 bmc
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-12-12 14:03:12 -05:00
Andreas Kemnade
3419416a3a omap4: make musb probeable by simple bus
Like other peripherals important for booting,
do not rely on ti-sysc compatibility alone

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
2022-12-12 14:03:12 -05:00
Manuel Traut
739e8361f3 distro/pxeboot: Handle prompt variable
Regarding the documentation found here:
https://github.com/u-boot/u-boot/blob/master/common/menu.c#L347

If both timeout and prompt is set to 0 the default entry shall
be booted immediately. However the current behaviour is that
the prompt is shown (tested with distroboot) until the user
selects an entry (no timeout).

This change implements a behaviour as documented. It was tested
with distroboot.

Signed-off-by: Manuel Traut <manuel.traut@mt.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-12 14:03:12 -05:00
Patrick Delaunay
51c5c28af5 cmd: pxe: use strdup to copy config
Replace malloc and strcpy by strdup in
function parse_label_kernel.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2022-12-12 14:03:12 -05:00
Patrick Delaunay
a5dacef738 cmd: pxe: support INITRD and FDT selection with FIT
Since the commit d5ba6188dfbf ("cmd: pxe_utils: Check fdtcontroladdr
in label_boot") the FDT or the FDTDIR label is required in extlinux.conf
and the fallback done by bootm command when only the device tree present
in this command parameters is no more performed when FIT is used for
kernel.

When the label FDT or FDTDIR are absent or if the device tree file is
absent, the PXE command in U-Boot uses the default U-Boot device tree
selected by fdtcontroladdr = gd->fdt_blob, it is the "Scenario 3".

With this scenario the bootm FIP fallback is no more possible with
the extlinux.conf when only "kernel" label is present and is a FIP:

  kernel <path>#<conf>[#<extra-conf[#...]]

As the U-Boot FDT is always provided in the third bootm argument,
the device tree found in FIP is not used as fallback, it was done
previously in boot_get_fdt().

This patch adds a new field kernel_label to save the full kernel label.
The FDT bootm parameters use the kernel address (to avoid to load a
second time the same FIP) and the config when this full label is reused
for "fdt" or "initrd" label.

This FIP support in extlinux.conf is restored when the "FDT" label
can be found and select the same FIP (identical file and configuration):

  kernel <path>#<conf>[#<extra-conf[#...]]
  fdt <path>#<conf>[#<extra-conf[#...]]

The patch add also this possibility for initrd.

  initrd <path>#<conf>[#<extra-conf[#...]]

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2022-12-12 14:03:12 -05:00
Patrick Delaunay
f723c2778c cmd: pxe: reorder kernel treatment in label_boot
Reorder kernel treatment in label_boot at the beginning of the function.

This patch doesn't change the pxe command behavior, it is only a
preliminary step for next patch, build kernel_addr before parsing
the label initrd and fdt to build the next bootm arguments.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2022-12-12 14:03:12 -05:00
Ben Dooks
4c56d75117 drivers: pci: pcie_dw_common: add upper-limit to iATU
The 4.6 spec added an upper 32bits to the ATU limit, and since this
driver is already assuming the unrolled feature added in the 4.8
specification this really should be set.

This is causing a bug with testing against the QEMU model as it
defaults the viewports to fully open and not setting this causes
the config viewport to become most of memory (obviously stopping
the emulated system working correctly)

Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
2022-12-12 14:03:11 -05:00
Andrew Davis
1eaffe3958 arm: mach-omap2: Move common image process functions out of board files
The functions board_fit_image_post_process() and board_tee_image_process()
are not actually board specific (despite their names). Any board using the
OMAP2 family can use these functions. Move them to boot-common.c.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-12-12 14:03:11 -05:00
Tom Rini
c917865c7f Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: Espressobin: Fix default env variables (Derek)
2022-12-12 09:00:58 -05:00
Tom Rini
b560f2c61f phy: usbphyc: use regulator_set_enable_if_allowed for disabling vbus supply
dm: pmic: ignore disabled node in pmic_bind_children
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Merge tag 'u-boot-stm32-20221212' of https://source.denx.de/u-boot/custodians/u-boot-stm

phy: usbphyc: use regulator_set_enable_if_allowed for disabling vbus supply
dm: pmic: ignore disabled node in pmic_bind_children
2022-12-12 08:59:13 -05:00
Patrick Delaunay
30257f4699 dm: pmic: ignore disabled node in pmic_bind_children
Ignore the disabled children node in pmic_bind_children() so the
disabled regulators in device tree are not registered.

This patch is based on the dm_scan_fdt_node() code - only the
activated nodes are bound -  and it solves possible issue when a
deactivated regulator is bound, error for duplicated regulator name
for example.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-12 11:25:28 +01:00
Patrick Delaunay
91dae6d0a1 phy: usbphyc: use regulator_set_enable_if_allowed for disabling vbus supply
Use regulator_set_enable_if_allowed() api instead of regulator_set_enable()
while disabling vbus supply. This way the driver doesn't see an error
when it disable an always-on regulator for VBUS.

This patch is needed for STM32MP157C-DK2 board when the regulator
v3v3: buck4 used as the phy vbus supply in kernel device tree
is always on with the next hack for low power use-case:

&usbphyc_port0 {
        ...
	/*
	 * Hack to keep hub active until all connected devices are suspended
	 * otherwise the hub will be powered off as soon as the v3v3 is disabled
	 * and it can disturb connected devices.
	 */
	connector {
		compatible = "usb-a-connector";
		vbus-supply = <&v3v3>;
	};
};

Without this patch and the previous update in DT the command
"usb stop" failed and the next command "usb start" cause a crash.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2022-12-12 11:25:19 +01:00
Derek LaHousse
3a68fda33f arm: mvebu: Espressobin: Fix default env variables
Default env variables on Espressobin boards are broken since commit c4df0f6f315c
("arm: mvebu: Espressobin: Set default value for $fdtfile env variable") as well
as the 'env default -a' command.

The algorithm to find free space in the default_environment[] array returns
after the first env variable instead of the correct position of the last
variable, where there is allocated free space.

This causes that U-Boot board_late_init() function to overwrite a portion of the
default environment with $ethXaddr and $fdtfile variables immediately after the
first env variable and so it is overwriting other variables.

This patch also adds an additional null byte to terminate the environment array.

But U-Boot board_late_init() function do not fill this nul byte explicitly. And
because of that, U-Boot is later trying to interpret remaining buffer as a
continuation of variable list. Normally buffer should be empty but due to the
above issue, it contains garbage from remaining env variables.

For example 'env default -a' command results in damaging variable names. It was
observed that scritaddr variable name was changed to criptaddr (without leading
's').

This bug was reported and discussed on the Armbian forum:
https://forum.armbian.com/topic/19564-making-espressobin-v7-work-in-2022/?do=findComment&comment=138136

Fix these issues in two steps:

1) Change code which finds free space for dynamic env variables in
default_environment[] array by jumping to the end of the variable list instead
of jumping after the first defined variable. [By Derek]

2) Add code which appends terminating nul byte as indication of the end of the
env list, after the last nul term env string. [By Pali]

Fixes: c4df0f6f315c ("arm: mvebu: Espressobin: Set default value for $fdtfile env variable")
Signed-off-by: Derek LaHousse <derek@seaofdirac.org>
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2022-12-12 07:36:04 +01:00
Tom Rini
7a7b0856ca Merge tag 'u-boot-nand-20221211' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash
- cmd: nand: Extend nand info to print ecc information
 - rawnand: omap_gpmc: driver model support (the first patches of the series)
 - mtd: nand: make Samsung SLC NAND usable again
 - cmd: mtd: check if a block has to be skipped or erased
 - spl: spl_legacy: fix invalid offset in SPL_COPY_PAYLOAD_ONLY
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Merge tag 'u-boot-nand-20221211' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash

Merge tag 'u-boot-nand-20221211' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash

- cmd: nand: Extend nand info to print ecc information
- rawnand: omap_gpmc: driver model support (the first patches of the series)
- mtd: nand: make Samsung SLC NAND usable again
- cmd: mtd: check if a block has to be skipped or erased
- spl: spl_legacy: fix invalid offset in SPL_COPY_PAYLOAD_ONLY
2022-12-11 09:40:25 -05:00
Dai Okamura
fda2253d12 spl: spl_legacy: fix invalid offset in SPL_COPY_PAYLOAD_ONLY
This fixes the header offset calculation.

This issue was found on uniphier v7 SoCs with SPL.

Fixes: 06377c5a1f ("spl: spl_legacy: Fix NAND boot on OMAP3 BeagleBoard")
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221209114021.3074978-1-okamura.dai@socionext.com
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10 14:35:55 +01:00
Dario Binacchi
17c2ccde22 mtd: nand: mxs_nand_spl: don't read useless pages
The patch prevents pages beyond the last from being unnecessarily read.
This occurs when the last page to be read is not the last page of the
last block. Before this change we would have read all the pages up to
the end of the last block.

Suggested-by: Michael Trimarchi <michael@amarulasolutions.com>
Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221120095705.3019295-1-dario.binacchi@amarulasolutions.com
2022-12-10 14:35:55 +01:00
Dario Binacchi
670789f5ba mtd: nand: drop EXPORT_SYMBOL_GPL for nanddev_erase()
This function is only used within this module, so it is no longer
necessary to use EXPORT_SYMBOL_GPL().

This patch parallels the work done in the following patch:
https://lore.kernel.org/linux-mtd/20221018170205.1733958-1-dario.binacchi@amarulasolutions.com

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221108090719.3631621-1-dario.binacchi@amarulasolutions.com
2022-12-10 14:35:55 +01:00
Dario Binacchi
d09807ad14 cmd: mtd: check if a block has to be skipped or erased
As reported by patch [1], the `mtd erase' command should not erase bad
blocks.
To force bad block erasing you have to use the `mtd erase.dontskipbad'
command.

This patch tries to fix the same issue without modifying code taken
from the linux kernel, in order to make further upgrades easier.

[1] https://lore.kernel.org/all/20221006031501.110290-2-mikhail.kshevetskiy@iopsys.eu/
Suggested-by: Michael Trimarchi <michael@amarulasolutions.com>
Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Co-developed-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Tested-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10 14:35:55 +01:00
Michael Trimarchi
c21b0ca525 mtd: nand: make Samsung SLC NAND usable again
Upstream linux commit 69fc01296c9281

commit a1286a1fc416 ("mtd: nand: Move Samsung specific init/detection
logic in nand_samsung.c") introduced a regression for Samsung SLC NAND
chips. Prior to this commit chip->bits_per_cell was initialized by calling
nand_get_bits_per_cell() before using nand_is_slc().
With the offending commit this call is skipped, leaving
chip->bits_per_cell cleared to zero when the manufacturer specific
'.detect' function calls nand_is_slc() which in turn interprets
bits_per_cell != 1 as indication for an MLC chip.
The effect is that e.g. a K9F1G08U0F NAND chip is falsely detected as
MLC NAND with 4KiB page size rather than SLC with 2KiB page size.

Add a call to nand_get_bits_per_cell() before calling the .detect hook
function in nand_manufacturer_detect(), so that the nand_is_slc()
calls in the manufacturer specific code will return correct results.

Reported-by: Marcin Gołaś <marcingol30@gmail.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221021060536.11747-1-michael@amarulasolutions.com
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10 14:35:55 +01:00
Roger Quadros
ec2c9240d5 mtd: rawnand: omap_gpmc: Reduce .bss usage
Allocate omap_ecclayout on the heap as we have
limited .bss space on AM64 R5 SPL configuration.

Reduces .bss usage by 2984 bytes.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221011115012.6181-9-rogerq@kernel.org
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10 14:35:54 +01:00
Roger Quadros
664d536926 mtd: rawnand: nand_spl_loaders: Fix cast type build warning
Fixes the below build warning on 64-bit platforms.

drivers/mtd/nand/raw/nand_spl_loaders.c:26:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
      dst = (void *)((int)dst - page_offset);

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221011115012.6181-8-rogerq@kernel.org
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10 14:35:54 +01:00
Roger Quadros
cd72a950e0 mtd: rawnand: omap_gpmc: Optimize NAND reads
Rename omap_nand_read() to omap_nand_read_buf() to reflect
actual behaviour.

Use FIFO read address instead of raw read address for reads.

The GPMC automatically converts 32-bit/16-bit reads to NAND
device specific reads (8/16 bit). Use the largest possible
read granularity size for more efficient reads.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221011115012.6181-5-rogerq@kernel.org
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10 11:11:25 +01:00
Roger Quadros
7e4a494c5f mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms
Pointer size cannot be assumed to be 32-bit, so use
use uintptr_t instead of uint32_t.

Fixes the below build warning on 64-bit builds.

drivers/mtd/nand/raw/omap_gpmc.c:439:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
  head = ((uint32_t) buf) % 4;

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221011115012.6181-4-rogerq@kernel.org
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10 11:11:25 +01:00
Roger Quadros
472229fcfc mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms
The GPMC module is present on some K2 and K3 SoCs.
Enable building GPMC NAND driver for K2/K3 platforms.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221011115012.6181-3-rogerq@kernel.org
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10 11:11:25 +01:00
Roger Quadros
c6bafdae50 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h
We want to get rid of <asm/arch/mem.h> so don't
enforce it for new platforms.

This also means GPMC_MAX CS doesn't have to be defined
by platform code.

Define it locally here for now.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221011115012.6181-2-rogerq@kernel.org
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10 11:11:25 +01:00
Michael Trimarchi
308bd74663 cmd: nand: Extend nand info to print ecc information
Extract the information about ecc strength and ecc step size
from mtd controller. This information is usefull to check if
what we think as ecc is what we really configured.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20220922133937.277463-1-michael@amarulasolutions.com
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-12-10 11:11:25 +01:00
Tom Rini
bc71afc3c5 Merge branch '2022-12-09-platform-updates' into next
- Assorted TI platform updates
- Add DM_RTC callback functions, and a related x86 clean-up.
2022-12-09 17:50:51 -05:00
Dhruva Gole
04150400c9 configs: enable OSPI related configs in AM62x
Add am62x_evm_r5_defconfig for OSPI Flash support in R5 SPL
and am62x_evm_a53_defconfig for A53 SPL and U-Boot
support.
These configs enable OSPI Flash boot functionality in the board as well
as the usage of OSPI Flash from U-Boot.

Signed-off-by: Dhruva Gole <d-gole@ti.com>
2022-12-09 14:12:53 -05:00
Dhruva Gole
8994ac365a arm: dts: Add OSPI support for AM62-SK
Add OSPI Support such that this device can boot up using OSPI Flash.
Also can use the flash for other purposes if required from uboot.

Signed-off-by: Dhruva Gole <d-gole@ti.com>
2022-12-09 14:12:53 -05:00
Dhruva Gole
8bd8a5d022 arm: dts: k3-am62x: sync dt with linux kernel
Sync the DT Files with linux kernel (tag v6.0.3)

Signed-off-by: Dhruva Gole <d-gole@ti.com>
2022-12-09 14:12:53 -05:00
Bryan Brattlof
719bd650c3 configs: introduce configs for the am62a
Introduce the minimum configs, only SD-MMC and UART boot related
settings, to serve as a good starting point for the am62a as we add more
functionality.

Signed-off-by: Bryan Brattlof <bb@ti.com>
[trini: Disable CONFIG_NET as it's not used, in both platforms]
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-09 14:12:28 -05:00
Bryan Brattlof
d90c8bc441 board: ti: introduce the basic files needed to support the am62a
Introduce the bare minimum SD and UART support for the am62a sk.

Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-12-09 14:10:28 -05:00
Bryan Brattlof
b6cbcd6155 arm: mach-k3: am62a: introduce auto-generated SoC data
Introduce the auto-generated clock tree and power domain data needed to
attach the am62a into the power-domain and clock frameworks of uboot

Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-12-09 14:10:28 -05:00
Bryan Brattlof
b511b371ad arm: mach-k3: introduce basic files to support the am62a
Introduce the mach-k3 files needed to properly boot TI's am62a SoC
family of devices

Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-12-09 14:10:28 -05:00
Bryan Brattlof
e38025c8b5 soc: ti: k3-socinfo: add am62a SoC entry
Add identification support for TI's am62ax family of SoCs

Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-12-09 14:10:28 -05:00
Bryan Brattlof
f54febe1b1 ram: k3-ddrss: add am62a controller support
TI's am62a family of SoCs uses a new 32bit DDR controller that shares
much of the same functionality with the existing am64 and j721e
controllers.

Select this controller by default when u-boot is build for the am62a

Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-12-09 14:10:28 -05:00
Bryan Brattlof
6bdfa69155 arm: dts: introduce am62a7 u-boot dtbs
Introduce the base dts files needed for u-boot or to augment the
linux dtbs for use in the u-boot-spl and u-boot binaries

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-12-09 14:10:28 -05:00
Bryan Brattlof
253802912a arm: dts: introduce am62a7 dtbs from linux kernel
Introduce the basic am62a7 SoC dtbs from the v6.1-rc3 tag of the linux
kernel along with the new am62a specific pinmux definition that we will
use to generate the dtbs for the u-boot-spl and u-boot binaries

Co-developed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-12-09 14:10:28 -05:00
Bryan Brattlof
ee31be429b ram: k3-ddrss: add auto-generated macros for am62a support
The new 32bit DDR controller for TI's am62a family of SoCs shares much
of the same functionality with the existing 16bit (am64) and 32bit
(j721e) controllers, so this patch reorganizes the existing
auto-generated macros for the 16bit and 32bit controllers to make room
for the macros for the am62a's controller

This patch consists mostly of header/macro renames and additions with a
new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new
macros during compilation.

Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-12-09 14:10:28 -05:00
Sean Anderson
640aecb416 rtc: Add fallbacks for dm functions
This adds fallbacks for the various dm_rtc_* functions. This allows
common code to use these functions without ifdefs.

Fixes: c8ce7ba87d1 ("misc: Add support for nvmem cells")
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-12-09 14:10:28 -05:00
Sean Anderson
0db588caf9 x86: fsp: Only compile fsp_save_s3_stack if (SPL_)DM_RTC is enabled
This function calls rtc_write32, which has a different signature
depending on if (SPL_)DM_RTC is enabled or not. This could result in a
mismatch in SPL if DM_RTC was enabled but SPL_DM_RTC, as the non-DM
declaration would still be used in SPL even though the implementation
would be for non-DM_RTC. We are switching to the correct definitions in
the next commit, so this will become a compilation error. Since
fsp_save_s3_stack is not called from SPL, avoid compiling it if
(SPL_)DM_RTC is disabled.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-12-09 14:10:28 -05:00
Pali Rohár
544071ac4a Nokia RX-51: Use ENTRY/ENDPROC for save_boot_params
ENTRY/ENDPROC macros from linux/linkage.h will make code more readable and
also will properly mark assembly symbol in ELF binary as function symbol.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-12-09 14:10:28 -05:00
Tom Rini
0494ab37c2 Merge branch '2022-12-08-assorted-tooling-and-fs-fixes' into next
- Assorted fixes for squashfs, ext4, a number of host tools (including
  reworking u-boot-initial-env) and then a few unrelated code cleanups /
  fixes.
2022-12-08 15:13:19 -05:00
Tom Rini
8f17040877 - Drop MMCI interrupt-names in STM32H743, STM32MP15 and STM322MP13 DT
DHSOM:
   - Enable assorted ST specific commands
   - Add version variable
   - Add boot counter
 STM32MP13:
   - Add sdmmc cd-gpios for STM32MP135F-DK
   - Add clock & reset support
 STM32 ADC:
   - Split channel init into several routines
   - Add support of generic channels binding
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Merge tag 'u-boot-stm32-20221207' of https://source.denx.de/u-boot/custodians/u-boot-stm

- Drop MMCI interrupt-names in STM32H743, STM32MP15 and STM322MP13 DT

DHSOM:
  - Enable assorted ST specific commands
  - Add version variable
  - Add boot counter
STM32MP13:
  - Add sdmmc cd-gpios for STM32MP135F-DK
  - Add clock & reset support
STM32 ADC:
  - Split channel init into several routines
  - Add support of generic channels binding
2022-12-08 11:25:08 -05:00
Tom Rini
573359d14d Merge https://source.denx.de/u-boot/custodians/u-boot-usb
- DFU and RNDIS fixes
2022-12-08 11:24:50 -05:00
Balamanikandan Gunasundar
c41e05bab0 board: sam9x60ek: remove nand init from board file
Move this out of board file as this is done by the DM based NAND flash
driver. The EBI chip select configuration, iomux and timings are
handled by the driver

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
2022-12-08 18:06:27 +02:00
Balamanikandan Gunasundar
70cbf2f097 ARM: dts: at91: sam9x60ek: Enable NAND support
Enable the EBI and NAND flash controller. Define the pinctrl and
partition table

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
2022-12-08 18:06:27 +02:00
Balamanikandan Gunasundar
2d35bf2420 ARM: dts: at91: sam9x60: Add nodes for EBI and NAND
Add new bindings for EBI and NAND controller

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
2022-12-08 18:06:27 +02:00
Balamanikandan Gunasundar
2cf5d0aa8e configs: at91: sam9x60ek: Enable DM based nand driver
Enable Device model supported NAND driver and remove legacy Atmel NAND
driver.

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
2022-12-08 18:06:27 +02:00
Balamanikandan Gunasundar
2dc1b8fe17 mfd: syscon: atmel-smc: Add new helpers to ease SMC regs manipulation
Add helper functions for atmel Static Memory Controller. The functions
are required to configure SMC. This file is inherited from the work
done by Boris Brezillon for Linux

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
2022-12-08 18:06:27 +02:00
Balamanikandan Gunasundar
68ddf18dc3 memory: atmel-ebi: add Atmel EBI (External Bus Interface) driver
The EBI is used to access peripherals like NAND, SRAM, NOR etc. Add
this driver to probe the nand flash controller. This is a dummy driver
and not yet a complete device driver for EBI.

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
2022-12-08 18:06:27 +02:00
Balamanikandan Gunasundar
de32a2a32a mfd: syscon: Add atmel-matrix registers definition
This file is copied from Linux. AT91 SoCs have a memory range reserved
for internal bus configuration. Expose those registers so that drivers
can make use of the matrix syscon declared in at91 DTs.

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
2022-12-08 18:06:27 +02:00
Balamanikandan Gunasundar
a490e1b7c0 nand: atmel: Add pmecc driver
Add driver for atmel pmecc. This implementation is ported from
Linux. The reference taken is linux-5.4-at91.

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
2022-12-08 18:06:27 +02:00
Balamanikandan Gunasundar
6a8dfd5722 nand: atmel: Add DM based NAND driver
This implementation is ported from the rework done by Boris Brezillon
in Linux. This porting is done based on linux-5.4-at91. The driver is
tested in sam9x60ek, sama5d3_xplained, sam9x75eb and sama7g54-ddr3-eb.

Changes done includes

- Adapt GPIO descriptor apis for U-Boot. Use gpio_request_by_name_nodev,
  dm_gpio_get_value etc.
- Use U_BOOT_DRIVER instead of platform_driver.
- Replace struct platform_device with struct udevice
- Check the status of nfc exec operation by polling the status
  register instead of interrupt based handling
- DMA operations not supported. Remove it
- Adapt DT parsing to U-Boot APIs

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
2022-12-08 18:06:18 +02:00
Pali Rohár
bd0ed9a2d2 ata: ahci-pci: Replace magic constant by macro
Replace 0x1b21 by macro PCI_VENDOR_ID_ASMEDIA with the same value.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-08 10:46:01 -05:00
Kasper Revsbech
aeea67f9a0 fs/squashfs: use lldiv function for math
When compling for x86:
u-boot/fs/squashfs/sqfs.c:90: undefined reference to `__udivmoddi4'

Signed-off-by: Kasper Revsbech <kasper.revsbech.ext@siemensgamesa.com>
Tested-by: Sean Nyekjaer <sean@geanix.com>
2022-12-08 09:29:02 -05:00
Max Krummenacher
486aef08de u-boot-initial-env: rework make target
With LTO enabled the U-Boot initial environment is no longer stored
in an easy accessible section in env/common.o. I.e. the section name
changes from build to build, its content maybe compressed and it is
annotated with additional data.

Drop trying to read the initial env with elf tools from the compiler
specific object file in favour of adding and using a host tool with
the only functionality of printing the initial env to stdout.

See also:
https://lore.kernel.org/all/927b122e-1f62-e790-f5ca-30bae4332c77@foss.st.com/

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-08 09:29:02 -05:00
Patrick Delaunay
55b0affd26 firmware: scmi: use protocol node name to bind the scmi regulator driver
In scmi firmware driver, it is better to bind the scmi protocol driver
"scmi_voltage_domain" with the node name of the protocol 17 and not
the sub-node named "regulator", because is a fixed string which doesn't
provide information and because it is not aligned with the other scmi
protocol nodes.

For example on stm32mp135f-dk board with device tree in stm32mp131.dtsi

scmi: scmi {
	compatible = "linaro,scmi-optee";
	#address-cells = <1>;
	#size-cells = <0>;
	linaro,optee-channel-id = <0>;
	shmem = <&scmi_shm>;
	scmi_clk: protocol@14 {
		reg = <0x14>;
		#clock-cells = <1>;
	};
	scmi_reset: protocol@16 {
		reg = <0x16>;
		#reset-cells = <1>;
	};
	scmi_voltd: protocol@17 {
		reg = <0x17>;
		scmi_regu: regulators {
			#address-cells = <1>;
			#size-cells = <0>;
			scmi_reg11: voltd-reg11 {
				reg = <VOLTD_SCMI_REG11>;
				regulator-name = "reg11";
			};
			scmi_reg18: voltd-reg18 {
				reg = <VOLTD_SCMI_REG18>;
				regulator-name = "reg18";
			};
			scmi_usb33: voltd-usb33 {
				reg = <VOLTD_SCMI_USB33>;
				regulator-name = "usb33";
			};
		};
	};
};

Before the patch:

> dm tree

 scmi_agent    0  [ + ]   scmi-over-optee       |-- scmi
 clk           1  [ + ]   scmi_clk              |   |-- protocol@14
 ...
 reset         1  [   ]   scmi_reset_domain     |   |-- protocol@16
 nop           2  [ + ]   scmi_voltage_domain   |   `-- regulators
 regulator     0  [ + ]   scmi_regulator        |       |-- voltd-reg11
 regulator     1  [ + ]   scmi_regulator        |       |-- voltd-reg18
 regulator     2  [ + ]   scmi_regulator        |       |-- voltd-usb33
 ...

after the patch:

> dm tree

 scmi_agent    0  [ + ]   scmi-over-optee       |-- scmi
 clk           1  [ + ]   scmi_clk              |   |-- protocol@14
 ...
 reset         1  [   ]   scmi_reset_domain     |   |-- protocol@16
 nop           2  [ + ]   scmi_voltage_domain   |   `-- protocol@17
 regulator     0  [ + ]   scmi_regulator        |       |-- voltd-reg11
 regulator     1  [ + ]   scmi_regulator        |       |-- voltd-reg18
 regulator     2  [ + ]   scmi_regulator        |       |-- voltd-usb33
 ...

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-12-08 09:29:02 -05:00
Marc Kleine-Budde
28f924f265 tools: mkimage: add new image type "fdt_legacy"
If the user select the image type "flat_dt" a FIT image will be build.
This breaks the legacy use case of putting a Flat Device Tree into a
legacy u-boot image.

Add a new image type "fdt_legacy" to build a legacy u-boot image
with a "flat_dt" type.

Link: https://lore.kernel.org/all/20221028155205.ojw6tcso2fofgnhm@pengutronix.de
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-12-08 09:29:02 -05:00
Marc Kleine-Budde
72c3f5dbd9 tools: mkimage: don't print error message "Success" in case of failure
In case there's no struct image_type_params::set_header callback, no
"errno" will be set. Don't fail with an error message, followed by
"Success". Remove the printing of the human readable "errno" value.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-08 09:29:02 -05:00
Mikhail Ilin
4b95e8407e tools: fdtgrep: Fix handle leak
The handle "fd" was created in fdtgrep.c:708 by calling the
 "open" function and is lost in fdtgrep.c:716 and fdtgrep.c:723.
 Close file descriptor 'fd' before exiting with an error from function
 utilfdt_read_err_len(const char *filename, char **buffp, off_t *len).

Fixes: 1043d0a0296a ("fdt: Add fdtgrep tool")
Signed-off-by: Mikhail Ilin <ilin.mikhail.ol@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-08 09:29:02 -05:00
Mikhail Ilin
17f8a74876 tools: mkimage: Fix nullptr at strchr()
The copy_datafile(ifd, params.datafile) function has been
 implemented to copy data by reducing the number of lines in the main
 function.

Signed-off-by: Mikhail Ilin <ilin.mikhail.ol@gmail.com>
2022-12-08 09:29:01 -05:00
Mikhail Ilin
04e6332ec0 fs: ext4: Fix free(NULL)
The 'depth_dirname', 'ptr', 'parent_inode' and 'first_inode' pointers
may be null. Thus, it is necessary to check them before using free() to
avoid free(NULL) cases.

Fixes: 934b14f2bb30 ("ext4: free allocations by parse_path()")
Signed-off-by: Mikhail Ilin <ilin.mikhail.ol@gmail.com>
2022-12-08 09:28:31 -05:00
Mikhail Ilin
2d1b2ac13f tool: ifwitool: Fix buffer overflow
An incorrect 1st parameter is passed to the fix_member()
 function. Should use a pointer to the beginning of the parent structure
 (bpdt or subpart_dir, because are boxed), not to their fields. Otherwise,
 this leads to an overrun of the structure boundary, since in the
 fix_member() function, an 'offset' is made, relative to the 1st argument,
 which itself is an 'offset' from the beginning of the structure.

Signed-off-by: Mikhail Ilin <ilin.mikhail.ol@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-08 09:25:44 -05:00
Mikhail Ilin
164232943c tool: ifwitool: The function localtime() can return NULL.
This will cause the local_time pointer is passed as the 4th argument
 to function strftime() to also point to NULL. This result in a
 segmentation fault. Thus, it's necessary to add a check of the local_time
 pointer to NULL.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Signed-off-by: Mikhail Ilin <ilin.mikhail.ol@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-08 09:25:44 -05:00
Jaehoon Chung
c059a22b77 tools: env: fw_env: Fix unused-result warning
Fix unused-result warning about fread.

tools/env/fw_env.c: In function ‘find_nvmem_device’:
tools/env/fw_env.c:1751:3: warning: ignoring return value of ‘fread’, declared with attribute warn_unused_result [-Wunused-result]
 1751 |   fread(buf, sizeof(buf), 1, fp);
      |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-12-08 09:25:44 -05:00
Szymon Heidrich
51a0e215ec usb: gadget: rndis: Prevent InformationBufferOffset manipulation
Prevent access to arbitrary memory locations in gen_ndis_set_resp
via manipulation of buf->InformationBufferOffset. Original
implementation permits manipulation of InformationBufferOffset to
exploit OID_GEN_CURRENT_PACKET_FILTER to set arbitrary memory contents
within a 32byte offset as the devices packet filter. The packet filter
value may be next retrieved using gen_ndis_query_resp so it is possible
to extract specific memory regions two bytes a time.

The rndis_query_response was not modified as neither the buffer offset
nor length passed to gen_ndis_query_resp is used.

Signed-off-by: Szymon Heidrich <szymon.heidrich@gmail.com>
2022-12-08 14:30:39 +01:00
Patrick Delaunay
bcd4110702 dfu: Make DFU virtual backend SPL friendly
Define stub for dfu_*_virt function in SPL, because
CONFIG_SPL_DFU_VIRT is not defined.

This patch avoids compilation issue in dfu_fill_entity() when
CONFIG_SPL_DFU is activated because the dfu_fill_entity_virt()
function is not available.

Fixes: ec44cace4b8d2 ("dfu: add DFU virtual backend")
Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
2022-12-08 14:30:39 +01:00
Hugo SIMELIERE
14dc0ab138 usb: gadget: dfu: Fix check of transfer direction
Commit fbce985e28eaca3af82afecc11961aadaf971a7e to fix CVE-2022-2347
blocks DFU usb requests.
The verification of the transfer direction was done by an equality
but it is a bit mask.

Signed-off-by: Hugo SIMELIERE <hsimeliere.opensource@witekio.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Sultan Qasim Khan <sultan.qasimkhan@nccgroup.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
2022-12-08 14:30:39 +01:00
Tom Rini
9060919822 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- Kautuk's semihosting patch:
  move semihosting library from arm directory to common place and add
  RISC-V support
- Zong's Kconfig patch:
  use "imply" instead of "select" to allow user to decide if
  SPL_SEPARATE_BSS should be selected
2022-12-08 08:28:14 -05:00
Tom Rini
341ba8d94b Second set of u-boot-at91 fixes for the 2023.01 cycle
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Merge tag 'u-boot-at91-fixes-2023.01-b' of https://source.denx.de/u-boot/custodians/u-boot-at91

Second set of u-boot-at91 fixes for the 2023.01 cycle:

This is a single tiny fix that allows the correct name for one pin on
sama7g5 device. People with DT coming from Linux will have build errors
without this if they add NAND device.
2022-12-08 08:27:50 -05:00
Zong Li
57b9900cd5 riscv: use imply instead of select for SPL_SEPARATE_BSS
Use imply instead of select, then it can still be disabled by
board-specific defconfig, or be set to n manually.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
2022-12-08 15:50:22 +08:00
Kautuk Consul
ac14155a2a common/spl/Kconfig: add dependency on SPL_SEMIHOSTING for SPL payload
When we enable CONFIG_SPL and CONFIG_SPL_SEMIHOSTING then the code
in common/spl/spl_semihosting.c tries to use the
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME string which remains undeclared
unless SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS are configured.

Add a dependency of SPL_SEMIHOSTING in the depends for
SPL_FS_LOAD_PAYLOAD_NAME so that the code compiles fine.

Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-12-08 15:16:10 +08:00
Kautuk Consul
ae3527f088 arch/riscv: add semihosting support for RISC-V
We add RISC-V semihosting based serial console for JTAG based early
debugging.

The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-12-08 15:15:58 +08:00
Kautuk Consul
1c03ab9f4b lib: Add common semihosting library
We factor out the arch-independent parts of the ARM semihosting
implementation as a common library so that it can be shared
with RISC-V.

Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-12-08 15:15:22 +08:00
Tom Rini
2b2e9127cc Merge branch '2022-12-07-Kconfig-migrations' into next
- Import another batch of Kconfig migrations and in this case, also
  legacy code removal.
2022-12-07 18:08:01 -05:00
Tom Rini
e524f3a449 net: Remove eth_legacy.c
As there are no more non-DM_ETH cases for networking, remove this legacy
file and update the Makefile to match current usage.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
9e0bcf8043 qe: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
2098a3b8fe usb: gadget: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
b8daa6e9ee usb: eth: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code fro usb_ether itself.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
0a9cbd4f3c usb: eth: smsc95xx: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
82cdcd5792 usb: eth: r8152: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
05d654b564 usb: eth: msc7830: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
d9e81b0dd7 usb: eth: asix88179: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
3aa2003b51 usb: eth: asix: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
8a9e3464e4 net: keystone_net: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
f8dc288c7f net: cpsw: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
8f5c7cc96b net: sunxi_emac: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
61af2af3f7 net: smc911x: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
85fdaea66c net: sh_eth: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
f1ee1e1ef1 net: rtl8169: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
f6fa0715ce net: rtl8139: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
36af92ba85 net: phy: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
32dc677276 net: pcnet: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
fa9ea7607f net: netconsole: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
c7f15a3ee8 net: mvgbe: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
c00e9467bc net: mcfmii: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
047a086fa3 net: macb: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
cde5a844fb net: ldpaa_eth: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
3c7e652bbb net: fsl-mc: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
b669c54bfd net: fec_mxc: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
ecca44805d net: ethoc: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
4fb814f571 net: eepro100: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to
remove the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
53fa409f59 net: e1000: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
9f2d365ed3 net: dm9000x: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:17 -05:00
Tom Rini
acb30ccc7c net: designware: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:16 -05:00
Tom Rini
d55a003904 net: dc2114x: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:16 -05:00
Tom Rini
cc2bf624eb net: fm: Remove non-DM_ETH code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:16 -05:00
Tom Rini
2f420f135f net: tsec: Remove non-DM_ETH support code
As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.  Doing this removes some board support code
which was also unused. Finally, this removes some CONFIG symbols that
otherwise needed to be migrated to Kconfig, but were unused in code now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:16 -05:00
Tom Rini
8457d023b8 global: Remove extraneous DM_ETH imply/select
We only need to enable DM_ETH if we have a networking driver. All
networking drivers depend on DM_ETH being enabled, and their selection
ensures DM_ETH will be enabled.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 16:04:16 -05:00
Tom Rini
f6301702c1 net: Remove extraneous dependencies
With DM_ETH being required now for all drivers, we don't need this
listed on individual drivers as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 12:20:17 -05:00
Tom Rini
8459276445 chromebook_samus_tpl: Disable SPL networking
We don't appear to actually use networking in SPL here, disable it.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-07 12:20:17 -05:00
Tom Rini
da752ac3c4 topic_miami*: Disable networking support more fully
This platform had largely disabled networking support before. More
completely disable it by turning off CONFIG_NET.

Cc: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Mike Looijmans <mike.looijmans@topic.nl>
2022-12-07 12:20:17 -05:00
Tom Rini
3c6ee7bb72 pinecube: Disable networking support more fully
This platform had largely disabled networking support before. More
completely disable it by turning off CONFIG_NET.

Cc: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 12:20:17 -05:00
Tom Rini
66900cb7c4 LicheePi_Zero: Disable networking support more fully
This platform had largely disabled networking support before. More
completely disable it by turning off CONFIG_NET.

Cc: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 12:20:17 -05:00
Tom Rini
ebef190e13 xenguest_arm64: Disable networking support more fully
This platform had largely disabled networking support before. More
completely disable it by turning off CONFIG_NET.

Cc: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Cc: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-07 12:20:17 -05:00
Marek Vasut
f708283ab9 ARM: stm32: Increment WDT by default on DHSOM
Enable watchdog timer on the DHSOM by default, both in U-Boot proper and
in SPL. This can be used in combination with boot counter by either SPL
or U-Boot proper to boot either copy of system software, e.g. in case of
full A/B update strategy.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-12-07 17:09:19 +01:00
Marek Vasut
1ca617f5fd ARM: stm32: Increment boot counter in SPL on DHSOM
Increment the boot counter already in U-Boot SPL instead of incrementing
it only later in U-Boot proper. This can be used by SPL to boot either of
two U-Boot copies and improve redundancy of software on the platform, e.g.
in case of full A/B update strategy.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-12-07 17:09:19 +01:00
Marek Vasut
0eca0b1075 ARM: stm32: Enable assorted ST specific commands on DHSOM
Enable the stm32prog, stm32key, stboard commands on DHSOM.
Those can be used e.g. to implement verified boot.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-12-07 17:09:19 +01:00
Marek Vasut
bf98da5feb ARM: stm32: Add version variable to DHSOM
Enable insertion of version variable into U-Boot environment on DHSOM,
to make it possible to check U-Boot version e.g. in U-Boot scripts.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-12-07 17:07:31 +01:00
Marek Vasut
ac803d9cae ARM: stm32: Add boot counter to DHSOM
Add boot counter to STM32MP15xx DHSOM. This aligns the software with
other upstream DHSOM products which already do enable boot counter.

The boot counter on STM32MP15xx is placed in the TAMP block TAMP_BKPxR
register 19, right past register 17 and 18 used for CM4 resource table
and state by the Linux kernel. The TAMP_BKPxR register block is used
because its contents survives warm reset, but not cold reset.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-12-07 17:06:26 +01:00
Marek Vasut
666b1a712d ARM: dts: stm32: Drop MMCI interrupt-names
The pl18x MMCI driver does not use the interrupt-names property,
the binding document has been updated to recommend this property
be unused, remove it.
Backport of Marek's Linux patch:
https://lore.kernel.org/linux-arm-kernel/20221013221242.218808-3-marex@denx.de/

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-12-07 17:04:08 +01:00
Yann Gautier
3068bb60c6 ARM: dts: stm32: add sdmmc cd-gpios for STM32MP135F-DK
On STM32MP135F-DK, the SD card detect GPIO is GPIOH4.
Backport of the Linux patch:
https://lore.kernel.org/linux-arm-kernel/20220921160334.3227138-1-yann.gautier@foss.st.com/

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-12-07 17:03:35 +01:00
Olivier Moysan
a9aa2aef5f adc: stm32mp15: add support of generic channels binding
Add support of generic IIO channels binding:
./devicetree/bindings/iio/adc/adc.yaml
Keep support of st,adc-channels for backward compatibility.

Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-12-07 17:00:26 +01:00
Olivier Moysan
1727d46bf9 adc: stm32mp15: split channel init into several routines
Split stm32_adc_chan_of_init channel initialization function into
several routines to increase readability and prepare channel
generic binding handling.

Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-12-07 17:00:26 +01:00
Gabriel Fernandez
2c8d548f4e arm: dts: stm32mp13: add support of RCC driver
Adds support of Clock and Reset drivers for STM32MP13 platform.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-12-07 16:49:35 +01:00
Gabriel Fernandez
c8df960c8d clk: stm32mp13: introduce STM32MP13 RCC driver
STM32MP13 RCC driver uses Common Clock Framework and also a
'clk-stm32-core' API. Then STM32MPx RCC driver will contain only data
configuration (gates, mux, dividers and the way to check security)
or some specific clocks.
This API will be used by all new other generations of ST Socs.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-12-07 16:49:35 +01:00
Gabriel Fernandez
01c8b664d2 dt-bindings: stm32mp13: add clock & reset support for STM32MP13
Add support of stm32mp13 DT bindings of clock and reset.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-12-07 16:49:35 +01:00
Tom Rini
b071de9843 Merge branch '2022-12-06-update-to-gcc-12-clang-14' into next
- Bring in changes to default CI to using gcc-12.2 and clang-14 for
  building.
2022-12-06 15:47:59 -05:00
Tom Rini
09ed7e62f3 CI: Update to gcc-12.2
- Update to gcc-12.2, and cherry-pick a fix in grub for risc-v

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-06 15:30:30 -05:00
Tom Rini
6caf6f5c83 pogo_v4: Disable LTO
With gcc-12.2 we now get:
lib/zlib/inflate.c:360: undefined reference to `__gnu_thumb1_case_si'
when building this platform. This seems like some odd problem with LTO
and Thumb, but since the platform continues to link, I assume it's
within size constraints, so lets just disable LTO for now.

Cc: Tony Dinh <mibodhi@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-06 15:30:30 -05:00
Tom Rini
fc2240046c arm: Use the WEAK assembly entry point consistently
It is a bad idea, and more modern toolchains will fail, if you declare
an assembly function to be global and then weak, instead of declaring it
weak to start with. Update assorted assembly files to use the WEAK macro
directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Pali Rohár <pali@kernel.org>
2022-12-06 15:30:30 -05:00
Tom Rini
583f124aac event: Re-add file paths to the tests
Now that we are enforcing dwarf-4 to be used we will have the full file
paths present.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-06 15:30:30 -05:00
Tom Rini
409e4b5478 Makefile: Enforce DWARF4 output
At this point in time, using DWARF-5 format isn't easy to do by default
with all toolchains that we support.  And relying on the implicit
default can lead to mixing 4 and 5 and then the debug info not being
useful to tools.  For now, enforce using DWARF-4 only.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-06 15:30:30 -05:00
Tom Rini
83e37a8345 buildman: Fetch 12.2.0 toolchains by default
Update the toolchain list to be first 12.2.0 and second 11.1.0 and
that's it.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-06 15:30:30 -05:00
Heinrich Schuchardt
f17fe71222 powerpc: fix fdt_fixup_liodn_tbl_fman()
Builiding with GCC 12.2 fails:

    arch/powerpc/cpu/mpc85xx/liodn.c: In function 'fdt_fixup_liodn_tbl_fman':
    arch/powerpc/cpu/mpc85xx/liodn.c:340:35: error: the comparison will
    always evaluate as 'false' for the address of 'compat'
    will never be NULL [-Werror=address]
      340 |                 if (tbl[i].compat == NULL)
          |

Remove the superfluous check.

Fixes: 97a8d010e029 ("net/fman: Support both new and legacy FMan Compatibles")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-06 15:30:30 -05:00
Tom Rini
14f2d087a3 Pull request for sound-2023-01-rc4
* Avoid endless loop and amend unit test
 * Add man-page for the sound command
 * Fix sandbox sound driver
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Merge tag 'sound-2023-01-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for sound-2023-01-rc4

* Avoid endless loop and amend unit test
* Add man-page for the sound command
* Fix sandbox sound driver
2022-12-06 10:07:01 -05:00
Tom Rini
d2ad92927e Merge branch '2022-12-05-Kconfig-migrations-and-renames' into next
- First batch of the patches that end up with
  scripts/config_whitelist.tx being empty. Mostly migrations and a
  little bit of code removal and CFG renaming.
2022-12-05 21:04:24 -05:00
Tom Rini
7102d324f6 m68k: Rename CONFIG_WATCHDOG_TIMEOUT to CONFIG_WATCHDOG_TIMEOUT_MSECS
In practice, it is clear that the usage in m68k of
CONFIG_WATCHDOG_TIMEOUT is setting a value in milliseconds. Rename this
to the existing symbol and move to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 18:16:43 -05:00
Tom Rini
9cebc4ad8e post: Migrate to Kconfig
We move the existing CONFIG_POST_* functionality over to CFG_POST and
then introduce CONFIG_POST to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:11:50 -05:00
Tom Rini
d948c8988c sandbox: Rework how SDL is enabled / disabled
Given that we can use Kconfig logic directly to see if we have a program
available on the host or not, change from passing NO_SDL to instead
controlling CONFIG_SANDBOX_SDL in Kconfig directly. Introduce
CONFIG_HOST_HAS_SDL as the way to test for sdl2-config and default
CONFIG_SANDBOX_SDL on if we have that, or not.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:11:50 -05:00
Tom Rini
17f13e7119 scripts/config_whitelist.txt: Remove more referenced symbols
Perform some deeper investigation on the remaining symbols listed in
this file and remove more.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:11:50 -05:00
Tom Rini
5bacad6462 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:09:46 -05:00
Tom Rini
5afc87eadb net: ftmac100: Remove non-DM_ETH code
At this point all users of this driver enable DM_ETH, so remove the
legacy code paths.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-12-05 16:08:38 -05:00
Tom Rini
be3bea2ba3 Convert CONFIG_VSC7385_ENET et al to Kconfig
This converts the following to Kconfig:
   CONFIG_VSC7385_ENET
   CONFIG_VSC9953

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:08:38 -05:00
Tom Rini
a9c3bce362 Convert CONFIG_USB_GADGET_AT91 to Kconfig
This converts the following to Kconfig:
   CONFIG_USB_GADGET_AT91

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:08:37 -05:00
Tom Rini
08d01cda45 Nokia RX-51: Migrate legacy USB device options to Kconfig
Move a number of legacy USB UDC options to Kconfig, over from the config
header.

Cc: Pali Rohár <pali@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:08:37 -05:00
Tom Rini
b43295a277 Convert CONFIG_TEGRA_CLOCK_SCALING et al to Kconfig
This converts the following to Kconfig:
   CONFIG_TEGRA_CLOCK_SCALING
   CONFIG_TEGRA_LP0
   CONFIG_TEGRA_PMU

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:08:37 -05:00
Tom Rini
fcd7ba655e Convert CONFIG_TPS6586X_POWER et al to Kconfig
This converts the following to Kconfig:
   CONFIG_TPS6586X_POWER
   CONFIG_TWL6030_POWER

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:08:37 -05:00
Tom Rini
8ce59b5932 Convert CONFIG_SPD_EEPROM to Kconfig
This converts the following to Kconfig:
   CONFIG_SPD_EEPROM

Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:08:37 -05:00
Tom Rini
d91365203c Convert CONFIG_SMSC_LPC47M et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SMSC_LPC47M
   CONFIG_SMSC_SIO1007

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:08:37 -05:00
Tom Rini
1c34f7885d Convert CONFIG_SH_GPIO_PFC et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SH_GPIO_PFC
   CONFIG_TMU_TIMER

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:08:37 -05:00
Tom Rini
ea467ea1cd Convert CONFIG_RTC_DS1337 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_RTC_DS1337
   CONFIG_RTC_DS1337_NOOSC
   CONFIG_RTC_DS1338
   CONFIG_RTC_DS1374
   CONFIG_RTC_DS3231
   CONFIG_RTC_MC13XXX
   CONFIG_RTC_MXS
   CONFIG_RTC_PT7C4338

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:08:37 -05:00
Tom Rini
c3187fb144 Convert CONFIG_PCA953X to Kconfig
This converts the following to Kconfig:
   CONFIG_PCA953X

Cc: Uri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:13 -05:00
Tom Rini
9200011e95 Convert CONFIG_NAND_KMETER1 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_NAND_ECC_BCH
   CONFIG_NAND_KIRKWOOD
   CONFIG_NAND_KMETER1

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:13 -05:00
Tom Rini
6c03a65275 Convert CONFIG_MXS_OCOTP to Kconfig
This converts the following to Kconfig:
   CONFIG_MXS_OCOTP

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:13 -05:00
Tom Rini
2568bd6db7 arm: Remove unused mx27 code
We no longer have any i.MX27 platforms, remove the remaining support
code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:13 -05:00
Tom Rini
4982e123b2 arm: samsung: Move CONFIG_MISC_COMMON to Kconfig
This option controls using board/samsung/common/misc.c, so add a Kconfig
file there as well and select it from the boards which use this
functionality.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-12-05 16:07:13 -05:00
Tom Rini
00faea644a arm: ls102xa: Migrate LS102XA_STREAM_ID
This symbol appears to be globally used in the architecture, select it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:13 -05:00
Tom Rini
d5596cbc6e arm: lpc32xx: Remove unused hsuart driver
This driver is not enabled in any config currently, remove it.

Cc: Trevor Woerner <twoerner@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:13 -05:00
Tom Rini
68e54040cc sandbox: Move CONFIG_IO_TRACE to Kconfig
This is only used on sandbox, so select it there.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:07:13 -05:00
Tom Rini
c136a86105 Convert CONFIG_IOMUX_SHARE_CONF_REG et al to Kconfig
This converts the following to Kconfig:
   CONFIG_IOMUX_LPSR
   CONFIG_IOMUX_SHARE_CONF_REG

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:12 -05:00
Tom Rini
d5c77533b4 Convert CONFIG_IODELAY_RECALIBRATION to Kconfig
This converts the following to Kconfig:
   CONFIG_IODELAY_RECALIBRATION

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:12 -05:00
Tom Rini
500dfebf22 mpc8548cds: Migrate CONFIG_INTERRUPTS to Kconfig
Only this platform sets this option, define it in the board Kconfig
file.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:12 -05:00
Tom Rini
0ea156ba00 Convert CONFIG_IMX_VIDEO_SKIP et al to Kconfig
This converts the following to Kconfig:
   CONFIG_IMX_VIDEO_SKIP
   CONFIG_IMX_HDMI

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:12 -05:00
Tom Rini
4eea765740 pwm: imx: Remove unused references to CONFIG_IMX6_PWM_PER_CLK
On platforms that use DM_PWM, we do not need to define this value
anymore, so remove it from config files.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:12 -05:00
Tom Rini
98cb4c6b8e arm920t: Remove unused imx code
This code is currently unused, remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:12 -05:00
Tom Rini
19b4040df0 Convert CONFIG_HWCONFIG to Kconfig
This converts the following to Kconfig:
   CONFIG_HWCONFIG

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:12 -05:00
Tom Rini
d9feb83505 Convert CONFIG_POWER_LTC3676 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_POWER_FSL
   CONFIG_POWER_FSL_MC13892
   CONFIG_POWER_HI6553
   CONFIG_POWER_LTC3676
   CONFIG_POWER_PFUZE100
   CONFIG_POWER_PFUZE3000
   CONFIG_POWER_SPI
   CONFIG_POWER_TPS65090_EC
   CONFIG_POWER_TPS65218
   CONFIG_POWER_TPS65910

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:07:12 -05:00
Tom Rini
022dc9e505 Convert CONFIG_HIKEY_GPIO et al to Kconfig
This converts the following to Kconfig:
   CONFIG_HIKEY_GPIO
   CONFIG_TCA642X

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:06:43 -05:00
Tom Rini
5cafaedeac Convert CONFIG_FSL_SERDES to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_SERDES

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:06:43 -05:00
Tom Rini
d58d0663cb Convert CONFIG_FSL_LBC to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_LBC

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:06:43 -05:00
Tom Rini
060613f119 Convert CONFIG_FSL_IIM to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_IIM

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:06:43 -05:00
Tom Rini
345c09de5e Convert CONFIG_FSL_DEVICE_DISABLE to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_DEVICE_DISABLE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:06:43 -05:00
Tom Rini
2a776c79db Convert CONFIG_FSL_CADMUS to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_CADMUS

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:06:43 -05:00
Tom Rini
518c5dfab0 power: pmic: Guard non-DM_PMIC drivers with a check for POWER_LEGACY
As we have more legacy PMIC drivers to move to Kconfig, guard them all
with POWER_LEGACY or SPL_POWER_LEGACY. Do the same kind of check for
building the drivers too. This also means that we need to resort the
list slightly in the Makefile.

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:43 -05:00
Tom Rini
65cc0e2a65 global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:08 -05:00
Tom Rini
a322afc9f9 global: Move remaining CONFIG_*SRIO_* to CFG_*
The rest of the unmigrated CONFIG symbols in the SRIO namespace do not
easily transition to Kconfig. In many cases they likely should come from
the device tree instead. Move these out of CONFIG namespace and in to
CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:08 -05:00
Tom Rini
97396cc9ce Convert CONFIG_SYS_SRIO et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SRIO1
   CONFIG_SRIO2
   CONFIG_SRIO_PCIE_BOOT_MASTER
   CONFIG_SYS_SRIO

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
3b8dfc42a2 Convert CONFIG_SYS_TIMER_COUNTS_DOWN to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_TIMER_COUNTS_DOWN

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
aa6e94deab global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
aec118ebe6 imx6/imx7: Remove now empty imx6_spl.h and imx7_spl.h
There are now no flags being set in these files, so remove them.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
f16b1a6c00 spl: Migrate SYS_SATA_FAT_BOOT_PARTITION to Kconfig
This moves SYS_SATA_FAT_BOOT_PARTITION to Kconfig and enforces the
current default via Kconfig rather than C code.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
2db82bf2bd Convert CONFIG_SYS_PMAN et al to Kconfig
This converts the following to Kconfig:
   CONFIG_NOBQFMAN
   CONFIG_SYS_DPAA_DCE
   CONFIG_SYS_DPAA_FMAN
   CONFIG_SYS_DPAA_PME
   CONFIG_SYS_DPAA_RMAN
   CONFIG_SYS_PMAN

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
ecc8d425fd global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and
CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many
cases they likely should come from the device tree instead. Move these
out of CONFIG namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
789bb9537a Convert CONFIG_SYS_OMAP_ABE_SYSCK to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_OMAP_ABE_SYSCK

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
3408d96e6c Remove unused symbols
This commit removes the following unused symbols:
   CONFIG_SYS_NVRAM_BASE_ADDR
   CONFIG_SYS_NVRAM_SIZE
   CONFIG_SYS_PAXE_BASE
   CONFIG_SYS_PCCNT
   CONFIG_SYS_PCDAT
   CONFIG_SYS_PCDDR
   CONFIG_SYS_PCI1_ADDR
   CONFIG_SYS_PCI2_ADDR
   CONFIG_SYS_PCI1_IO_BUS
   CONFIG_SYS_PCI1_IO_SIZE
   CONFIG_SYS_PCI1_MEM_BUS
   CONFIG_SYS_PCI1_MEM_SIZE
   CONFIG_SYS_PCIE3_ADDR
   CONFIG_SYS_PCIE4_ADDR
   CONFIG_SYS_PCIE3_IO_PHYS
   CONFIG_SYS_PCIE3_IO_VIRT
   CONFIG_SYS_PCIE4_IO_PHYS
   CONFIG_SYS_PCIE4_IO_VIRT
   CONFIG_SYS_PLL_SETTLING_TIME
   CONFIG_SYS_QMAN_CENA_BASE
   CONFIG_SYS_QMAN_SP_CENA_SIZE
   CONFIG_SYS_RCAR_I2C0_BASE
   CONFIG_SYS_RCAR_I2C1_BASE
   CONFIG_SYS_RCAR_I2C2_BASE
   CONFIG_SYS_RCAR_I2C3_BASE
   CONFIG_SYS_SATA
   CONFIG_SYS_SDRAM_BASE2
   CONFIG_SYS_SGMII_REFCLK_MHZ
   CONFIG_SYS_SGMII_LINERATE_MHZ
   CONFIG_SYS_SGMII_RATESCALE
   CONFIG_SYS_SH_SDHI0_BASE
   CONFIG_SYS_SH_SDHI0_BASE
   CONFIG_SYS_SH_SDHI1_BASE
   CONFIG_SYS_SH_SDHI2_BASE
   CONFIG_SYS_SH_SDHI3_BASE
   CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
   CONFIG_SYS_SPI_U_BOOT_SIZE
   CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
   CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
   CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT
   CONFIG_SYS_VCXK_BASE
   CONFIG_SYS_VCXK_DEFAULT_LINEALIGN
   CONFIG_SYS_VCXK_DOUBLEBUFFERED
   CONFIG_SYS_VCXK_ENABLE_DDR
   CONFIG_SYS_VCXK_ENABLE_PIN
   CONFIG_SYS_VCXK_ENABLE_PORT
   CONFIG_SYS_VCXK_INVERT_DDR
   CONFIG_SYS_VCXK_INVERT_PIN
   CONFIG_SYS_VCXK_INVERT_PORT
   CONFIG_SYS_VCXK_REQUEST_DDR
   CONFIG_SYS_VCXK_REQUEST_PIN
   CONFIG_SYS_VCXK_REQUEST_PORT
   CONFIG_SYS_VSC7385_BR_PRELIM
   CONFIG_SYS_VSC7385_OR_PRELIM

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
a6b537266f rtc: Remove unused drivers
These RTC drivers are currently unused and reference other unused CONFIG
variables, so remove them.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
cdc5ed8f1f global: Move remaining CONFIG_SYS_NUM_* to CFG_SYS_NUM_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
91092132ba global: Move remaining CONFIG_SYS_NS16550_* to CFG_SYS_NS16550_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
9591b63531 Convert CONFIG_SYS_NS16550_MEM32 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_NS16550_MIN_FUNCTIONS
   CONFIG_SYS_NS16550_MEM32
   CONFIG_SYS_NS16550_PORT_MAPPED
   CONFIG_SYS_NS16550_REG_SIZE
   CONFIG_SYS_NS16550_SERIAL

To do this we also introduce CONFIG_SPL_SYS_NS16550_SERIAL so that
platforms can enable the legacy driver here for SPL.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 16:06:07 -05:00
Tom Rini
57c3afbc27 powerpc: Rename CONFIG_NS16550_MIN_FUNCTIONS
This symbol is specific to the PowerPC SPL implementation, so rename
this to reflect that it's in SPL and used / tested there, so that we can
then safely migrate it to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:05:38 -05:00
Tom Rini
0ed384fd2f global: Move remaining CONFIG_SYS_NOR_* to CFG_SYS_NOR_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NOR
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:05:38 -05:00
Tom Rini
4e5909450e global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:05:38 -05:00
Tom Rini
0cd0325964 Convert CONFIG_SYS_NAND_SIZE to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:05:38 -05:00
Tom Rini
a9f03760c1 Convert CONFIG_SYS_NAND_PAGE_2K et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_PAGE_2K
   CONFIG_SYS_NAND_PAGE_4K

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:05:38 -05:00
Tom Rini
1a792803d8 Convert CONFIG_SYS_NAND_NO_SUBPAGE_WRITE to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_NO_SUBPAGE_WRITE

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:05:38 -05:00
Tom Rini
4d3495deb6 Convert CONFIG_SYS_NAND_MAX_OOBFREE et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_MAX_OOBFREE
   CONFIG_SYS_NAND_MAX_ECCPOS

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:05:38 -05:00
Tom Rini
b41641d52e mtd: nand: raw: atmel_nand: Use ATMEL_BASE_ECC directly
This is the only driver, and only one platform makes use of, setting
CONFIG_SYS_NAND_ECC_BASE. Reference ATMEL_BASE_ECC directly in this
case.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:05:38 -05:00
Tom Rini
41fa8f471d Convert CONFIG_SYS_NAND_HW_ECC to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_HW_ECC

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:05:38 -05:00
Tom Rini
60db32502c Convert CONFIG_SYS_NAND_HW_ECC_OOBFIRST to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_HW_ECC_OOBFIRST

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:05:38 -05:00
Tom Rini
50493dd1f9 Remove unused symbols
This commit removes the following unused symbols:
   CONFIG_SYS_NAND_DDR_LAW
   CONFIG_SYS_NAND_ECCSTEPS
   CONFIG_SYS_NAND_ECCTOTAL
   CONFIG_SYS_NAND_ENABLE_PIN_SPL
   CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
   CONFIG_SYS_NAND_U_BOOT_RELOC_SP

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:05:38 -05:00
Tom Rini
715cce65b8 Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_DBW_8
   CONFIG_SYS_NAND_DBW_16

Note that all instances of the code check for CONFIG_SYS_NAND_DBW_16
being defined, and then "else" to CONFIG_SYS_NAND_DBW_8 whereas all of
the configs set CONFIG_SYS_NAND_DBW_8. So we introduce
CONFIG_SYS_NAND_DBW_16 as an option.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:05:38 -05:00
Tom Rini
1c470f32f7 Prepare v2023.01-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05 15:21:53 -05:00
Tom Rini
6616ddb0f0 Merge branch '2022-12-05-add-IPv6-support'
To quote the author:
This patch set adds basic IPv6 support to U-boot.
It is based on Chris's Packham patches
(https://lists.denx.de/pipermail/u-boot/2017-January/279366.html)
Chris's patches were taken as base. There were efforts to launch it on
HiFive SiFive Unmatched board but the board didn't work well. The code was
refactored, fixed some bugs as CRC for little-endian, some parts were implemented in
our own way, something was taken from Linux. Finally we did manual tests and the
board worked well.

Testing was done on HiFive SiFive Unmatched board (RISC-V)
2022-12-05 13:28:22 -05:00
Viacheslav Mitrofanov
a72926257c configs: Add IPV6 config to sandbox_flattree_defconfig
Allow to use IPV6 tests in sandbox

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
2022-12-05 12:47:17 -05:00
Viacheslav Mitrofanov
bbd77c3e8b configs: Add IPV6 config to sandbox64_defconfig
Allow to use IPV6 tests in sandbox

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
2022-12-05 12:47:17 -05:00
Viacheslav Mitrofanov
3688cf5927 configs: Add IPV6 config to sandbox_defconfig
Allow to use IPV6 tests in sandbox

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
2022-12-05 12:47:17 -05:00
Viacheslav Mitrofanov
e4d30fd110 test: dm: eth: Add ip6_make_lladdr test
Add a test that checks generated Link Local Address. Use in sandbox

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:17 -05:00
Viacheslav Mitrofanov
789a2c7d37 test: dm: eth: Add ip6_make_snma test
Add a test that checks generated Solicited Node Multicast Address from our
ipv6 address. Use in sandbox

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:17 -05:00
Viacheslav Mitrofanov
8576dcdf00 test: dm: eth: Add ip6_addr_in_subnet test
Add a test if two address are in the same subnet. Use in sandbox

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:17 -05:00
Viacheslav Mitrofanov
d9f5c41e9a test: dm: eth: Add csum_ipv6_magic test
Test checksum computation. csum_ipv6_magic() uses in upper layer
protocols as TCP/UDP/ICMPv6/etc to calculate payload checksum.

Series-changes: 3
- Fixed style problems

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:17 -05:00
Viacheslav Mitrofanov
184ded4bec test: dm: eth: Add string_to_ip6 test
Add a test to check convertation from char* to struct in6_addr.
Use in sandbox

Series-changes: 3
- Fixed tests to use length param in string_to_ip6()

Series-changes: 5
- Add test under #ifdef

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:17 -05:00
Viacheslav Mitrofanov
eeb0a2c693 net: ping6: Add ping6 command
Implement ping6 command to ping hosts using IPv6. It works the same way as
an ordinary ping command. There is no ICMP request so it is not possible
to ping our host. This patch adds options in Kconfig and Makefile to
build ping6 command.

Series-changes: 3
- Added structures and functions descriptions
- Added to ping6_receive() return value instead of void

Series-changes: 4
- Fixed structures and functions description style

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:16 -05:00
Viacheslav Mitrofanov
7fbf230d79 net: tftp: Add IPv6 support for tftpboot
The command tftpboot uses IPv4 by default. Add the possibility to use IPv6
instead. If an address in the command is an IPv6 address it will use IPv6
to boot or if there is a suffix -ipv6 in the end of the command it also
force using IPv6. All other tftpboot features and parameters are left
the same.

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:16 -05:00
Viacheslav Mitrofanov
ffdbf3bad5 net: ipv6: Incorporate IPv6 support into u-boot net subsystem
Add net_ip6_handler (an IPv6 packet handler) into net_loop. Add
neighbor discovery mechanism into network init process. That is the
main step to run IPv6 in u-boot. Now u-boot is capable to use NDP and
handle IPv6 packets.

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:16 -05:00
Viacheslav Mitrofanov
1feb697830 net: ipv6: Add implementation of main IPv6 functions
Functions that were exposed in "net: ipv6: Add IPv6 basic primitives"
had only empty implementations and were exposed as API for futher
patches. This patch add implementation of these functions. Main
functions are: net_ip6_handler() - IPv6 packet handler for incoming
packets; net_send_udp_packet6() - make up and send an UDP packet;
csum_ipv6_magic() - compute checksum of IPv6 "psuedo-header" per RFC2460
section 8.1; ip6_addr_in_subnet() - check if an address is in our
subnet. Other functions are auxiliary.

Series-changes: 3
- Added comments
- Fixed style problems
- Fixed return codes instead of -1

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:16 -05:00
Viacheslav Mitrofanov
43ab8ecc7d net: ipv6: Add ip6addr, gatewayip6, serverip6 variables callbacks
Implement actions on ip6addr, gatewayip6, serverip6 varaibles.
on_ip6addr - convert IPv6 string addr to struct ip6_addr
on_gatewayip6 - convert IPv6 string addr to struct ip6_addr
on_serverip6 - convert IPv6 string addr to struct ip6_addr

Series-changes: 3
- Removed memory allocation
- Substituted -1 for error code

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:16 -05:00
Viacheslav Mitrofanov
d807199da7 net: ipv6: Enable IPv6 typeconversion specifier
Add the possibility to recognize IPv6 address in print function.
To output IPv6 address use %pI6 specifier.

Series-changes: 3
- Substituted #if (...) for if (...) to get better readability

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:16 -05:00
Viacheslav Mitrofanov
2f7f2f2aa9 net: ipv6: Add string_to_ip6 converter
This functions is used as a converter from IPv6 address string notation
to struct ip6_addr that is used everywhere in IPv6 implementation. For
example it is used to parse and convert IPv6 address from tftpboot
command. Conversion algorithm uses two passes, first to verify syntax and
locate colons and second pass to read the address. In case of valid IPv6
address it returns 0.

Examples of valid strings:
	2001:db8::0:1234:1
	2001:0db8:0000:0000:0000:0000:1234:0001
	::1
	::ffff:192.168.1.1

Examples of invalid strings
	2001:db8::0::0          (:: can only appear once)
	2001:db8:192.168.1.1::1 (v4 part can only appear at the end)
	192.168.1.1             (we don't implicity map v4)

Series-changes: 3
- Added function description
- Added length parameter to string_to_ip6()

Series-changes: 4
- Fixed function description style

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:16 -05:00
Viacheslav Mitrofanov
c6610e1d90 net: ipv6: Add Neighbor Discovery Protocol (NDP)
Implement basic of NDP. It doesn't include such things as Router
Solicitation, Router Advertisement and Redirect. It just has Neighbor
Solicitation and Neighbor Advertisement. Only these two features are used
in u-boot IPv6. Implementation of some NDP functions uses API that was
exposed in "net: ipv6: Add IPv6 basic primitives".

Also this patch inlcudes update in Makefile to build NDP.

Series-changes: 3
- Added structures and functions descriptions
- Fixed style problems

Series-changes: 4
- Fixed structures and functions description style

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:16 -05:00
Viacheslav Mitrofanov
1dfa4ef14d net: ipv6: Add callbacks declarations to get access to IPv6 variables
Set up callbacks for main IPv6 variables ip6add, serverip6, gatewayip6
and set options to them in flag file. These variables are often set up by
users.

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:16 -05:00
Viacheslav Mitrofanov
3cc04a3ab2 net: ipv6: Add IPv6 build options
Add options to Makefile and Kconfig file to build IPv6

Series-changes: 3
- Added help for IPv6 support

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:16 -05:00
Viacheslav Mitrofanov
33b5066a59 net: ipv6: Add IPv6 basic primitives
This patch is a collection of basic primitives that are prerequisite for
further IPv6 implementation.

There are structures definition such as IPv6 header, UDP header
(for TFTP), ICMPv6 header. There are auxiliary defines such as protocol
codes, padding, struct size and etc. Also here are functions prototypes
and its empty implementation that will be used as API for further patches.
Here are variables declaration such as IPv6 address of our host,
gateway, ipv6 server.

Series-changes: 3
- Added functions and structures descriptions
- Removed enums ND_OPT_*. It will be moved into further patches
- Substituted -1 for error codes

Series-changes: 4
- Changed functions and structures description style

Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 12:47:15 -05:00
Heinrich Schuchardt
304bc9f437 sandbox: fix sound driver
In the callback function we have to use memcpy(). Otherwise we add
the new samples on top of what is stored in the stream buffer.

If we don't have enough data, zero out the rest of the stream buffer.

Our sampling frequency is 48000. Let the batch size for the callback
function be 960. If we play a multiple of 20 ms, this will always be
a full batch.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 17:43:23 +01:00
Heinrich Schuchardt
3f01307ced doc: man-page for the sound command
Provide a man-page for the sound command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 17:43:21 +01:00
Heinrich Schuchardt
ff414fcc44 cmd: fix long text for sound command
Make it clear that if only 1 parameter is provided this is the duration.

The ISO symbol for hertz is Hz.

Fixes: c0c88533fffd ("Sound: Add command for audio playback")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 17:43:21 +01:00
Heinrich Schuchardt
968eaaeaa7 test: test sandbox sound driver more rigorously
Consider unexpected values for frequency:

* negative frequency
* zero frequency
* frequency exceeding sampling frequency

As in these cases the sum of the samples is zero also check the count of
the samples.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 17:43:21 +01:00
Heinrich Schuchardt
d0e8777bee sound: avoid endless loop
'sound play 1 100000' results in an endless loop on the sandbox.

If the frequency exceeds half the sampling rate, zero out the output
buffer.

Fixes: 511ed5fdd389 ("SOUND: SAMSUNG: Add I2S driver")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 17:43:21 +01:00
Tom Rini
a50622d78c Xilinx changes for v2023.01-rc3-v2
xilinx:
 - Fix MAC address selection for System Controller from FRU
 - Cleanup Kconfig (ZYNQ_MAC_IN_EEPROM symbol)
 
 versal:
 - Create u-boot.elf for mini spi configurations
 
 versal-net:
 - Enable MT35XU flash
 
 zynq:
 - Add missing timer to DT for mini configurations
 
 zynqmp:
 - Do not include psu_init to U-Boot by default
 - Do not enable IPI by default to mini U-Boot
 - Update Luca's fragment
 - Fix SPL_FS_LOAD_PAYLOAD_NAME usage
 
 spi:
 - gqspi: Fix tapdelay values
 - gqspi: Fix 64bit address support
 - cadence: Remove condition for calling enable linear mode
 - nor-core: Invert logic to reflect sst26 flash unlocked
 
 net:
 - Add PCS/PMA phy support
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Merge tag 'xilinx-for-v2023.01-rc3-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.01-rc3-v2

xilinx:
- Fix MAC address selection for System Controller from FRU
- Cleanup Kconfig (ZYNQ_MAC_IN_EEPROM symbol)

versal:
- Create u-boot.elf for mini spi configurations

versal-net:
- Enable MT35XU flash

zynq:
- Add missing timer to DT for mini configurations

zynqmp:
- Do not include psu_init to U-Boot by default
- Do not enable IPI by default to mini U-Boot
- Update Luca's fragment
- Fix SPL_FS_LOAD_PAYLOAD_NAME usage

spi:
- gqspi: Fix tapdelay values
- gqspi: Fix 64bit address support
- cadence: Remove condition for calling enable linear mode
- nor-core: Invert logic to reflect sst26 flash unlocked

net:
- Add PCS/PMA phy support
2022-12-05 08:33:19 -05:00
Tom Rini
bdaf047f51 Merge tag 'i2cfixes-for-v2023.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c Fixes for v2023.01-rc3

- nuovoton driver:
  rename npcm_i2c -> npcm-i2c from Jim Liu
2022-12-05 08:33:01 -05:00
Algapally Santosh Sagar
7ad3c09e79 mtd: spi-nor-core: Invert logic to reflect sst26 flash unlocked
flash_is_locked is changed to flash_is_unlocked with commit 513c6071ce73
("mtd: spi: Convert is_locked callback to is_unlocked"). sst26_is_locked()
is also changed to sst26_is_unlocked() but the logic remained same.
Invert the logic for the flash lock/unlock to work properly.

Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20221122051833.13306-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05 10:01:45 +01:00
Michal Simek
b40d154ced xilinx: zynqmp: Fix SPL_FS_LOAD_PAYLOAD_NAME usage
SPL_FS_LOAD_PAYLOAD_NAME depends on SPL to be enabled.
If SPL is not enabled code still expects SPL_FS_LOAD_PAYLOAD_NAME to be
present. That's why setup proper dependency in the code.
And by doing so also change the logic around dfu_alt_info string
composition to be simpler.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3989c390a4acae13a1b05c040e14fb3d68bced02.1669986373.git.michal.simek@amd.com
2022-12-05 08:55:55 +01:00
Ashok Reddy Soma
7d13f72d74 arm64: versal-net: Enable defconfig for Micron octal flashes
Micron mt35 series octal flashes are under config option
CONFIG_SPI_FLASH_MT35XU. Enable it in default defconfig for octal
flashes to be detected.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/dfaf73a72c7b408f1b8530f411c405d3dcf9f854.1669717110.git.michal.simek@amd.com
2022-12-05 08:55:55 +01:00
Ashok Reddy Soma
0d1a55fcbc spi: cadence-qspi: Remove condition for calling enable linear mode
cadence_qspi_apb_enable_linear_mode() has a weak function defined, so no
need to gaurd this under if (CONFIG_IS_ENABLED(ARCH_VERSAL)).

In cadence_qspi_apb_write_execute(), enable linear mode is called twice by
mistake, remove extra one.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20221129114134.18909-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05 08:55:55 +01:00
Michal Simek
6a664a7bd4 ARM: zynq: Add missing twd timer for mini configurations
The commit b7e0750d8872 ("zynq: Convert arm twd timer to DM driver")
switched timer to DM but missing to add nodes to all mini configurations.
Based on it missing timer end up in non functional system where any delay
doesn't work.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2020fc7e3d4760e890265485b3c7e18eb1caf8be.1669724598.git.michal.simek@amd.com
2022-12-05 08:55:55 +01:00
Michal Simek
92e6900536 arm64: zynqmp: Do not enable IPI by default
ZynqMP mini configurations are not using IPI driver and enabling this is
adding additional ~1200 Bytes (depends on configuration).
This ends up in situation that there is no enough space in OCM for
relocation that's why disable this driver for all mini configurations.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c71bab3927cb71ae517d9c21f59f3d5cf0caf712.1669734580.git.michal.simek@amd.com
2022-12-05 08:55:55 +01:00
Michal Simek
74673ca705 arm64: zynqmp: Do not include psu_init to U-Boot by default
The commit ed35de617013 ("Convert CONFIG_ZYNQMP_PSU_INIT_ENABLED to
Kconfig") converted CONFIG_ZYNQMP_PSU_INIT_ENABLED symbol and enabled it by
default which is not correct configuration.
Intention of this config was to have it enabled by default for SPL and
provide an option to users to also do low level initialization directly
from U-Boot.
That's why it is necessary to define second symbol with SPL marking in it
and properly use symbols depends on usage in Makefile.
Also disable ZYNQMP_PSU_INIT_ENABLED from boards which enables it by
default. CONFIG_SPL_ZYNQMP_PSU_INIT_ENABLED is enabled by default when SPL
is enabled.

Reported-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d5fcbd66b05bf0d7ef594e66464ee23b48c5e4cc.1669969083.git.michal.simek@amd.com
2022-12-05 08:55:55 +01:00
Luca Ceresoli
9129a6b49a board/xilinx/zynqmp/MAINTAINERS: change e-mail address for Luca Ceresoli
My Bootlin address is the preferred one now.

Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20221203214939.56608-1-luca@lucaceresoli.net
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05 08:55:55 +01:00
Michal Simek
2e3c10eea0 xilinx: Remove unused ZYNQ_MAC_IN_EEPROM/ZYNQ_GEM_I2C_MAC_OFFSET entries
The commit ba74bcf3e07b ("xilinx: common: Remove
zynq_board_read_rom_ethaddr()") removed zynq_board_read_rom_ethaddr()
because xlnx,eeprom link via DT chosen node is no longer used. But forget
to remove Kconfig entries which are used by this code only.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f97451ed33409838efea4071553b6da795cfc578.1669192026.git.michal.simek@amd.com
2022-12-05 08:55:55 +01:00
Michal Simek
f3538a3cbe xilinx: Add option to select SC id instead of DUT id for SC support
Reading MAC address from on board EEPROM requires different type for System
Controller (SC).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/90bb7cc5463568a690b979f18c8d42556986b46d.1669204122.git.michal.simek@amd.com
2022-12-05 08:55:54 +01:00
Venkatesh Yadav Abbarapu
906e20a613 spi: zynqmp_qspi: Add support for 64-bit read/write
When we pass the 64-bit address to read/write, only lower 32-bit
address is getting updated. Program the upper 32-bit address in the
DMA destination memory address MSBs register, which can handle upto
44-bit destination address.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221125104413.26140-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05 08:55:54 +01:00
Venkatesh Yadav Abbarapu
31e66aea37 arm64: versal: Enable REMAKE_ELF for mini_ospi/mini_qspi
Enable the config REMAKE_ELF in xilinx_versal_mini_ospi_defconfig
and xilinx_versal_mini_qspi_defconfig which generates u-boot.elf.
This commit a8c281d4b737("Convert CONFIG_REMAKE_ELF to Kconfig")
misses to enable this config in these defconfigs.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221125084639.23835-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05 08:55:54 +01:00
T Karthik Reddy
a5e770b21c spi: zynqmp_gqspi: Update tapdelay value
The driver was using an incorrect value for GQSPI_LPBK_DLY_ADJ_DLY_1
tapdelay for Versal for frequencies above 100MHz. Change it from 2 to 1
based on the recommended value in IP spec.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20221123090451.11409-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05 08:55:54 +01:00
Lukas Funke
d9efdc7d42 arm64: zynqmp: dynamically mark r5 cores as used
When Linux boot takes over control of the pmu
(by signaling PM_INIT_FINALIZE via ipi), pmu will switch off 'unused'
rpu cores. The Xilinx zynqmp fsbl prevents switching off those cores by
marking rpu cores as 'used' when loading code partitions to those cores.
The current u-boot SPL is missing this behaviour, which results in
halting rpu cores during Linux boot.

This commit mimics the xilinx zynqmp fsbl behavior by marking r5 cores as
used when they are released during boot.

Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com>
Signed-off-by: Lukas Funke <lukas.funke-oss@weidmueller.com>
Link: https://lore.kernel.org/r/20221028121547.26464-2-lukas.funke-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05 08:55:54 +01:00
Andy Chiu
f3558be91e net: xilinx_axi: check PCS/PMA PHY status in setup_phy
Both PCS/PMA PHY and the external PHY need to have a valid link status
in order to have Ethernet traffic. Check and wait this status at
setup_phy() so that we could diagnose if there is a PHY issue.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
Link: https://lore.kernel.org/r/20221101035800.912644-3-andy.chiu@sifive.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05 08:55:54 +01:00
Andy Chiu
e23544cffe net: xilinx_axi: add PCS/PMA PHY
If we bridge an external PHY to Xilinx's PCS/PMA PHY and would like to
get and set the real status of the PHY facing the external world. Then
we should phy_connect() to the external PHY instead of the PCS/PMA one.
Thus, we add a pcs-handle DT entry, which have been merged in Linux, and
leave the configuration of it to the driver itself.

Unlike Linux, where the PCS/PMA PHY is managed by phylink, managing the
PCS/PMA PHY is only internal to the driver in U-Boot. The PCS/PMA PHY
pressents only when the phy-mode is configured as SGMII or 1000Base-X,
so it is always 1 Gbps and full-duplex and we may skip passing link
information out.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
Link: https://lore.kernel.org/r/20221101035800.912644-2-andy.chiu@sifive.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05 08:55:54 +01:00
Jim Liu
d7b8fa1a6c i2c: nuvoton: renamed the NPCM i2c driver
The Makefile name is npcm_i2c but the driver is npcm-i2c.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-12-05 06:00:37 +01:00
Tom Rini
d2c5607edd Pull request for efi-2023-01-rc3
Documentation:
 
 * describe DM firmware needed for j721e_evm
 * describe management of UEFI security data base with eficonfig
 
 UEFI:
 
 * code clean-up for eficonfig command
 * fix handling of DHCP aknowledge
 * correct EFI memory type used for U-Boot code
 * unit test for FatToStr() truncation
 * add an EFI binary to print boot hart ID
 
 Other:
 
 * improve parameter checks in console functions
 * fix variable initialization in blk_get_device_part_str
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Merge tag 'efi-2023-01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2023-01-rc3

Documentation:

* describe DM firmware needed for j721e_evm
* describe management of UEFI security data base with eficonfig

UEFI:

* code clean-up for eficonfig command
* fix handling of DHCP aknowledge
* correct EFI memory type used for U-Boot code
* unit test for FatToStr() truncation
* add an EFI binary to print boot hart ID

Other:

* improve parameter checks in console functions
* fix variable initialization in blk_get_device_part_str
2022-12-04 10:01:48 -05:00
Masahisa Kojima
30124c2bb9 doc: eficonfig: add description for UEFI Secure Boot Configuration
This commits adds the description for the UEFI Secure Boot
Configuration through the eficonfig menu.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>

Redacted the complete document.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-02 19:17:25 +01:00
Masahisa Kojima
140a8959d4 eficonfig: use efi_get_next_variable_name_int()
eficonfig command reads all possible UEFI load options
from 0x0000 to 0xFFFF to construct the menu. This takes too much
time in some environment.
This commit uses efi_get_next_variable_name_int() to read all
existing UEFI load options to significantlly reduce the count of
efi_get_var() call.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
2022-12-02 19:17:25 +01:00
Masahisa Kojima
3ac026ae46 efi_loader: utility function to check the variable name is "Boot####"
Some commands need to enumerate the existing UEFI load
option variable("Boot####"). This commit transfers some code
from cmd/efidebug.c to lib/efi_loder/, then exposes
efi_varname_is_load_option() function to check whether
the UEFI variable name is "Boot####".

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-02 19:17:25 +01:00
Masahisa Kojima
78b1ccc430 eficonfig: use u16_strsize() to get u16 string buffer size
Use u16_strsize() to simplify the u16 string buffer
size calculation.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-02 19:17:25 +01:00
Masahisa Kojima
c67d3c9e23 eficonfig: fix going one directory up issue
The directory name in eficonfig menu entry contains the
'\' separator. strcmp() argument ".." is wrong and one directory
up handling does not work correctly. strcmp() argument must
include '\' separator.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-02 19:17:25 +01:00
Heinrich Schuchardt
7fb73cd999 doc: board: typo GIUD Microchip MPFS Icicle Kit doc
%s/GIUD/GUID/

Fixes: 9e550e18305f ("doc: board: Add Microchip MPFS Icicle Kit doc")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
2022-12-02 19:17:24 +01:00
Heinrich Schuchardt
1a12796292 efi_loader: don't use EFI_LOADER_DATA internally
EFI_LOADER_DATA/CODE is reserved for EFI applications.
Memory allocated by U-Boot for internal usage should be
EFI_BOOT_SERVICES_DATA or _CODE or EFI_RUNTIME_SERVICES_DATA or _CODE.

Reported-by: François-Frédéric Ozog <ff@ozog.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: François-Frédéric Ozog <ff@ozog.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-02 19:17:24 +01:00
Heinrich Schuchardt
1702055eb3 efi_loader: fix handling of DHCP acknowledge
The dhcp command may be executed after the first UEFI command.
We should still update the EFI_PXE_BASE_CODE_PROTOCOL.

Don't leak content of prior acknowledge packages.

Handle failing allocation when calling malloc().

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-12-02 19:17:24 +01:00
Heinrich Schuchardt
f2833d451c efi_selftest: test FatToStr() truncation
Let the FatToStr test check that the FatSize parameter is considered.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-02 19:17:24 +01:00
Heinrich Schuchardt
f2d60f6257 efi_loader: add an EFI binary to print boot hart ID
Provide an EFI binary that prints the boot hart ID as found in the
device-tree as /chosen/boot-hartid property and as provided by the
RISCV_EFI_BOOT_PROTOCOL.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-02 19:17:24 +01:00
Andrew Davis
4bc50978e6 doc: board: j721e_evm: Fix code-block type and indents
* BASH code should be labeled as such.
 * Code blocks should be indented by 4 spaces.

Fix these here.

Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2022-12-02 19:17:24 +01:00
Andrew Davis
2434a01d8a doc: board: j721e_evm: Add DM firmware steps
J721e needs DM firmware when using updated SYSFW. Add steps to fetch,
build, and deploy the same.

Signed-off-by: Andrew Davis <afd@ti.com>
2022-12-02 19:17:24 +01:00
Heinrich Schuchardt
bdb060a3eb net: CONFIG_NET_DEVICES in dhcp_handler()
The symbol CONFIG_NET_DEVICES does not exist.
The correct name is CONFIG_NETDEVICES.

Fixes: 77b5c4a5b1dc ("efi_loader: Let networking support depend on NETDEVICES")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-02 19:17:24 +01:00
Heinrich Schuchardt
be2e42fa95 disk: fix blk_get_device_part_str()
blk_get_device_part_str() should always initialize all info fields
including sys_ind. As a side effect the code is simplified.

Replace '(0 ==' by '(!' to conform with Linux coding style.

Fixes: 4d907025d6a5 ("sandbox: restore ability to access host fs through standard commands")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-12-02 19:17:24 +01:00
Heinrich Schuchardt
27380d885d console: file should always be non-negative
We use the parameter file in console functions to choose from an array
after checking against MAX_FILES but we never check if the value of file
is negative.

Running ./u-boot -T -l and issuing the poweroff command has resulted in
crashes because os_exit() results in std::ostream::flush() calling U-Boot's
fflush with file being a pointer which when converted to int may be
represented by a negative number.

This shows that checking against MAX_FILES is not enough. We have to ensure
that the file argument is always positive.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-02 19:17:24 +01:00
Tom Rini
a32f6341cc Merge branch '2022-12-02-assorted-updates'
- Add Peter Robinson as a co-custodian for Pi, update the maintainer
  record for common/usb_storage.c, re-add bmp_logo to tools-only and fix
  SPI booting on the SanCloud BBE
2022-12-02 10:00:55 -05:00
Paul Barker
c9311b5a90 MAINTAINERS: Adopt SanCloud boards
Signed-off-by: Paul Barker <paul.barker@sancloud.com>
Cc: Marc Murphy <marc.murphy@sancloud.com>
2022-12-02 08:39:00 -05:00
Paul Barker
b9829e9846 am335x-sancloud-bbe: Add -u-boot.dtsi files
The SanCloud BBE requires the same dtb nodes to be present in the SPL as
the AM335x EVM.

The SanCloud BBE Lite also requires the SPI flash node and all
dependencies to be present in the SPL to support SPI boot.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02 08:39:00 -05:00
Paul Barker
8328022d05 am335x-sancloud-bbe-lite: SPI flash is JEDEC compatible
Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02 08:39:00 -05:00
Paul Barker
d883280b91 am335x-evm: Support STMicro/Micron SPI flash
This change enables access to the SPI flash on the SanCloud BBE Lite
board.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02 08:39:00 -05:00
Paul Barker
f3b9abf5ba am335x-evm: Fix spiboot configuration
The advanced address translation provided by CONFIG_SPL_OF_TRANSLATE is
needed to determine the base address of the uart0 peripheral on am335x
platforms when CONFIG_SPL_OF_CONTROL is enabled.

If CONFIG_SPL_OF_CONTROL is enabled in the base (non-spiboot)
am335x_evm_defconfig, then CONFIG_SPL_OF_TRANSLATE will also need to be
enabled there. Unfortunately this cannot be done pre-emptively due to
the kconfig dependencies.

The TI clk-ctrl & TI sysc drivers are also required to bring up the SPI
bus on am335x platforms.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02 08:39:00 -05:00
Paul Barker
78b9afd2c3 am335x-evm: Enable required dtb nodes in SPL
For successful boot when CONFIG_SPL_OF_CONTROL=y, we need to ensure that
the board EEPROM on i2c0, the uart0 serial port and the relevant boot
device (mmc1 or mmc2) can be accessed in the SPL. We also need to
preserve the parent nodes for each required dtb node.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02 08:39:00 -05:00
Paul Barker
07744f2ac0 bus: Optionally include TI sysc driver in SPL/TPL
The TI sysc bus driver is required to allow access to the SPI bus on
am335x platforms. To support SPI boot this driver needs to be enabled in
the SPL/TPL as appropriate.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02 08:39:00 -05:00
Paul Barker
e92f47c06a bus: TI sysc driver requires DM
This driver does not build if CONFIG_DM is disabled as it uses the
function `dev_get_priv`.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02 08:39:00 -05:00
Paul Barker
dec64d55af dm: core: Fix iteration over driver_info records
We should only perform additional iteration steps when needed to
initialize the parent of a device. Other binding errors (such as a
missing driver) should not lead to additional iteration steps.

Unnecessary iteration steps can cause issues when memory is tightly
constrained (such as in the TPL/SPL) since device_bind_by_name()
unconditionally allocates memory for a struct udevice. On the SanCloud
BBE this led to boot failure caused by memory exhaustion in the SPL
when booting from SPI flash.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02 08:39:00 -05:00
Marek Vasut
9f52e765dc MAINTAINERS: Move usb_storage from DFU to USB
The usb_storage.c is the host-side USB mass storage device support,
it is not the DFU/UMS gadget-side implementation. Fix the entry.

Signed-off-by: Marek Vasut <marex@denx.de>
2022-12-02 08:39:00 -05:00
Peter Robinson
1cfba53ca4 config: tools only: add VIDEO to build bmp_logo
Pre 2023.01 the bmp_logo was built as part of the tools-only_defconfig
build, something changed and the VIDEO dep needed to build it
is no longer pulled in so fix that by explicitly defining it.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-02 08:39:00 -05:00
Matthias Brugger
58880b5208 MAINTAINERS: add RaspberryPi co-maintainer
Peter accpeted to step up as a co-maintainer for the RPis.
Reflect that in the corresponding MAINTAINERS files.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
2022-12-02 08:39:00 -05:00
Mihai Sain
94256dc610 ARM: dts: at91: sama7g5: fix signal name of pin PD8
The signal name of pin PD8 with function D is A22_NANDCLE
as it is defined in the datasheet.

Fixes: 558378a4cd ("ARM: mach-at91: add support for new SoC sama7g5")
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2022-12-02 09:48:49 +02:00
Tom Rini
39b81955d3 Merge branch '2022-11-28-networking-updates-and-improvements'
- LiteX Ethernet support, dwc_eth_qos fixes, re-work fixing
  CVE-2022-{30790,30552}, macb race fix, Intel XWAY PHY support
  and add wget command and TCP support.
2022-11-28 13:12:40 -05:00
Tim Harvey
5e6c069b2c phy: add driver for Intel XWAY PHY
Add a driver for the Intel XWAY GbE PHY:
 - configure RGMII using dt phy-mode and standard delay properties
 - use genphy_config

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-11-28 13:06:40 -05:00
Yaron Micher
d1559435d7 net: macb: Fix race caused by flushing unwanted descriptors
The rx descriptor list is in cached memory, and there may be multiple
descriptors per cache-line. After reclaim_rx_buffers marks a descriptor
as unused it does a cache flush, which causes the entire cache-line to
be written to memory, which may override other descriptors in the same
cache-line that the controller may have written to.

The fix skips freeing descriptors that are not the last in a cache-line,
and if the freed descriptor is the last one in a cache-line, it marks
all the descriptors in the cache-line as unused.
This is similarly to what is done in drivers/net/fec_mxc.c

In my case this bug caused tftpboot to fail some times when other
packets are sent to u-boot in addition to the ongoing tftp (e.g. ping).
The driver would stop receiving new packets because it is waiting
on a descriptor that is marked unused, when in reality the descriptor
contains a new unprocessed packet but while freeing the previous buffer
descriptor & flushing the cache, the driver accidentally marked the
descriptor as unused.

Signed-off-by: Yaron Micher <yaronm@hailo.ai>
2022-11-28 13:06:40 -05:00
Ying-Chun Liu (PaulLiu)
d6abc7e2e0 test: cmd: add test for wget command.
Simulate a TCP HTTP server's response for testing wget command.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28 13:06:40 -05:00
Ying-Chun Liu (PaulLiu)
bfce0ca9d4 doc: cmd: wget: add documentation
Add documentation for the wget command.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28 13:06:39 -05:00
Ying-Chun Liu (PaulLiu)
cfbae48219 net: Add wget application
This commit adds a simple wget command that can download files
from http server.

The command syntax is
wget ${loadaddr} <path of the file from server>

Signed-off-by: Duncan Hare <DuncanCHare@yahoo.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28 13:06:39 -05:00
Ying-Chun Liu (PaulLiu)
a3bf193bf4 net: Add TCP protocol
Currently file transfers are done using tftp or NFS both
over udp. This requires a request to be sent from client
(u-boot) to the boot server.

The current standard is TCP with selective acknowledgment.

Signed-off-by: Duncan Hare <DH@Synoia.com>
Signed-off-by: Duncan Hare <DuncanCHare@yahoo.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28 13:06:39 -05:00
Tim Harvey
3cdbbe52f7 drivers: net: aquantia: fix typos
Fix a couple of typos:
- s/Acquantia/Aquantia/
- s/firmare/firmware/

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28 13:06:39 -05:00
Rasmus Villemoes
0686968639 net: deal with fragment-overlapping-two-holes case
With a suitable sequence of malicious packets, it's currently possible
to get a hole descriptor to contain arbitrary attacker-controlled
contents, and then with one more packet to use that as an arbitrary
write vector.

While one could possibly change the algorithm so we instead loop over
all holes, and in each hole puts as much of the current fragment as
belongs there (taking care to carefully update the hole list as
appropriate), it's not worth the complexity: In real, non-malicious
scenarios, one never gets overlapping fragments, and certainly not
fragments that would be supersets of one another.

So instead opt for this simple protection: Simply don't allow the
eventual memcpy() to write beyond the last_byte of the current hole.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-11-28 13:06:39 -05:00
Rasmus Villemoes
087648b5df net: tftp: sanitize tftp block size, especially for TX
U-Boot does not support IP fragmentation on TX (and unless
CONFIG_IP_DEFRAG is set, neither on RX). So the blocks we send must
fit in a single ethernet packet.

Currently, if tftpblocksize is set to something like 5000 and I
tftpput a large enough file, U-Boot crashes because we overflow
net_tx_packet (which only has room for 1500 bytes plus change).

Similarly, if tftpblocksize is set to something larger than what we
can actually receive (e.g. 50000, with NET_MAXDEFRAG being 16384), any
tftp get just hangs because we never receive any packets.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28 13:06:39 -05:00
Rasmus Villemoes
4b8c44e39c net: tftp: use IS_ENABLED(CONFIG_NET_TFTP_VARS) instead of #if
Nothing inside this block depends on NET_TFTP_VARS to be set to parse
correctly. Switch to C if() in preparation for adding code before
this (to avoid a declaration-after-statement warning).

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
[trini: Update to cover CONFIG_TFTP_PORT case as well]
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-11-28 13:06:14 -05:00
Rasmus Villemoes
06653c7010 net: fix ip_len in reassembled IP datagram
For some reason, the ip_len field in a reassembled IP datagram is set
to just the size of the payload, but it should be set to the value it
would have had if the datagram had never been fragmented in the first
place, i.e. size of payload plus size of IP header.

That latter value is currently returned correctly via the "len"
variable. And before entering net_defragment(), len does have the
value ntohs(ip->ip_len), so if we're not dealing with a
fragment (so net_defragment leaves *len alone), that relationship of
course also holds after the net_defragment() call.

The only use I can find of ip->ip_len after the net_defragment call is
the ntohs(ip->udp_len) > ntohs(ip->ip_len) sanity check - none of the
functions that are passed the "ip" pointer themselves inspect ->ip_len
but instead use the passed len.

But that sanity check is a bit odd, since the RHS really should be
"ntohs(ip->ip_len) - 20", i.e. the IP payload size.

Now that we've fixed things so that len == ntohs(ip->ip_len) in all
cases, change that sanity check to use len-20 as the RHS.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-11-28 10:25:18 -05:00
Rasmus Villemoes
1817c3824a net: (actually/better) deal with CVE-2022-{30790,30552}
I hit a strange problem with v2022.10: Sometimes my tftp transfer
would seemingly just hang. It only happened for some files. Moreover,
changing tftpblocksize from 65464 to 65460 or 65000 made it work again
for all the files I tried. So I started suspecting it had something to
do with the file sizes and in particular the way the tftp blocks get
fragmented and reassembled.

v2022.01 showed no problems with any of the files or any value of
tftpblocksize.

Looking at what had changed in net.c or tftp.c since January showed
only one remotely interesting thing, b85d130ea0ca.

So I fired up wireshark on my host to see if somehow one of the
packets would be too small. But no, with both v2022.01 and v2022.10,
the exact same sequence of packets were sent, all but the last of size
1500, and the last being 1280 bytes.

But then it struck me that 1280 is 5*256, so one of the two bytes
on-the-wire is 0 and the other is 5, and when then looking at the code
again the lack of endianness conversion becomes obvious. [ntohs is
both applied to ip->ip_off just above, as well as to ip->ip_len just a
little further down when the "len" is actually computed].

IOWs the current code would falsely reject any packet which happens to
be a multiple of 256 bytes in size, breaking tftp transfers somewhat
randomly, and if it did get one of those "malicious" packets with
ip_len set to, say, 27, it would be seen by this check as being 6912
and hence not rejected.

====

Now, just adding the missing ntohs() would make my initial problem go
away, in that I can now download the file where the last fragment ends
up being 1280 bytes. But there's another bug in the code and/or
analysis: The right-hand side is too strict, in that it is ok for the
last fragment not to have a multiple of 8 bytes as payload - it really
must be ok, because nothing in the IP spec says that IP datagrams must
have a multiple of 8 bytes as payload. And comments in the code also
mention this.

To fix that, replace the comparison with <= IP_HDR_SIZE and add
another check that len is actually a multiple of 8 when the "more
fragments" bit is set - which it necessarily is for the case where
offset8 ends up being 0, since we're only called when

  (ip_off & (IP_OFFS | IP_FLAGS_MFRAG)).

====

So, does this fix CVE-2022-30790 for real? It certainly correctly
rejects the POC code which relies on sending a packet of size 27 with
the MFRAG flag set. Can the attack be carried out with a size 27
packet that doesn't set MFRAG (hence must set a non-zero fragment
offset)? I dunno. If we get a packet without MFRAG, we update
h->last_byte in the hole we've found to be start+len, hence we'd enter
one of

	if ((h >= thisfrag) && (h->last_byte <= start + len)) {

or

	} else if (h->last_byte <= start + len) {

and thus won't reach any of the

		/* overlaps with initial part of the hole: move this hole */
		newh = thisfrag + (len / 8);

		/* fragment sits in the middle: split the hole */
		newh = thisfrag + (len / 8);

IOW these division are now guaranteed to be exact, and thus I think
the scenario in CVE-2022-30790 cannot happen anymore.

====

However, there's a big elephant in the room, which has always been
spelled out in the comments, and which makes me believe that one can
still cause mayhem even with packets whose payloads are all 8-byte
aligned:

    This code doesn't deal with a fragment that overlaps with two
    different holes (thus being a superset of a previously-received
    fragment).

Suppose each character below represents 8 bytes, with D being already
received data, H being a hole descriptor (struct hole), h being
non-populated chunks, and P representing where the payload of a just
received packet should go:

  DDDHhhhhDDDDHhhhDDDD
        PPPPPPPPP

I'm pretty sure in this case we'd end up with h being the first hole,
enter the simple

	} else if (h->last_byte <= start + len) {
		/* overlaps with final part of the hole: shorten this hole */
		h->last_byte = start;

case, and thus in the memcpy happily overwrite the second H with our
chosen payload. This is probably worth fixing...

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-11-28 10:25:18 -05:00
Rasmus Villemoes
ad359d89ec net: compare received length to sizeof(ip_hdr), not sizeof(ip_udp_hdr)
While the code mostly/only handles UDP packets, it's possible for the
last fragment of a fragmented UDP packet to be smaller than 28 bytes;
it can be as small as 21 bytes (an IP header plus one byte of
payload). So until we've performed the defragmentation step and thus
know whether we're now holding a full packet, we should only check for
the existence of the fields in the ip header, i.e. that there are at
least 20 bytes present.

In practice, we always seem to be handed a "len" of minimum 60 from the
device layer, i.e. minimal ethernet frame length minus FCS, so this is
mostly theoretical.

After we've fetched the header's claimed length and used that to
update the len variable, check that the header itself claims to be the
minimal possible length.

This is probably how CVE-2022-30552 should have been dealt with in the
first place, because net_defragment() is not the only place that wants
to know the size of the IP datagram payload: If we receive a
non-fragmented ICMP packet, we pass "len" to receive_icmp() which in
turn may pass it to ping_receive() which does

  compute_ip_checksum(icmph, len - IP_HDR_SIZE)

and due to the signature of compute_ip_checksum(), that would then
lead to accessing ~4G of address space, very likely leading to a
crash.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-11-28 10:25:18 -05:00
Rasmus Villemoes
b0fcc48cb3 net: improve check for no IP options
There's no reason we should accept an IP packet with a malformed IHL
field. So ensure that it is exactly 5, not just <= 5.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28 10:25:18 -05:00
Marek Vasut
e9d3fc7e46 net: dwc_eth_qos: Add support for bulk RX descriptor cleaning
Add new desc_per_cacheline property which lets a platform run RX descriptor
cleanup after every power-of-2 - 1 received packets instead of every packet.
This is useful on platforms where (axi_bus_width EQOS_AXI_WIDTH_n * DMA DSL
inter-descriptor word skip count + DMA descriptor size) is less than cache
line size, which necessitates packing multiple DMA descriptors into single
cache line.

In case of TX descriptors, this is not a problem, since the driver always
does synchronous TX, i.e. the TX descriptor is always written, flushed and
polled for completion in eqos_send().

In case of RX descriptors, it is necessary to update their status in bulk,
i.e. after the entire cache line worth of RX descriptors has been used up
to receive data.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28 10:25:17 -05:00
Marek Vasut
f94d008a9d net: dwc_eth_qos: Split TX and RX DMA rings
Separate TX and RX DMA rings to make their handling slightly clearer.
This is a preparatory patch for bulk RX descriptor flushing.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28 10:25:17 -05:00
Joel Stanley
3167b4d722 liteeth: LiteX Ethernet device
LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic
network device that is commonly used in LiteX designs.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28 10:25:17 -05:00
Tom Rini
597e7b784d Merge https://source.denx.de/u-boot/custodians/u-boot-usb
- DWC3 fixes / improvements
2022-11-28 09:35:02 -05:00
Marek Vasut
db5bace4f6 usb: dwc3: Drop support for "snps, ref-clock-period-ns" DT property
Drop support for quickly deprecated DT property "snps,ref-clock-period-ns"
to prevent its proliferation.

Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2022-11-27 15:34:56 +01:00
Sean Anderson
c55ac51a55 usb: dwc3: Program GFLADJ
GUCTL.REFCLKPER can only account for clock frequencies with integer
periods. To address this, program REFCLK_FLADJ with the relative error
caused by period truncation. The formula given in the register reference
has been rearranged to allow calculation based on rate (instead of
period), and to allow for fixed-point arithmetic.

Additionally, calculate a value for 240MHZDECR. This configures a
simulated 240Mhz clock using a counter with one fractional bit (PLS1).

This register is programmed only for versions >= 2.50a, since this is
the check also used by commit db2be4e9e30c ("usb: dwc3: Add frame length
adjustment quirk").

[ marek: Ported from Linux kernel commit
         596c87856e08d ("usb: dwc3: Program GFLADJ") ]

Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
2022-11-27 15:34:56 +01:00
Sean Anderson
6bae0eb5b8 usb: dwc3: Calculate REFCLKPER based on reference clock
Instead of using a special property to determine the reference clock
period, use the rate of the reference clock. When we have a legacy
snps,ref-clock-period-ns property and no reference clock, use it
instead. Fractional clocks are not currently supported, and will be
dealt with in the next commit.

[ marek: Ported from Linux kernel commit
         5114c3ee24875 ("usb: dwc3: Calculate REFCLKPER based on reference clock") ]

Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
2022-11-27 15:34:56 +01:00
Balaji Prakash J
57548e8bc7 usb: dwc3: reference clock period configuration
Set reference clock period when it differs from dwc3 default hardware
set.

We could calculate clock period based on reference clock frequency. But
this information is not always available. This is the case of PCI bus
attached USB host. For that reason we use a custom property.

Tested (USB2 only) on IPQ6010 SoC based board with 24 MHz reference
clock while hardware default is 19.2 MHz.

[ baruch: rewrite commit message; drop GFLADJ code; remove 'quirk-' from
  property name; mention tested hardware ]

[ marek: Ported from Linux kernel commit
         7bee318838890 ("usb: dwc3: reference clock period configuration") ]

Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
2022-11-27 15:34:56 +01:00
Marek Vasut
8ae84e6453 usb: dwc3: Cache ref_clk pointer in struct dwc3
Cache ref_clk clock pointer in struct dwc3 . This is a preparatory
patch for subsequent backports from Linux kernel which configure
GFLADJ register content based on the ref_clk rate and therefore need
access to the ref_clk pointer.

It is possible to extract the clock pointer from existing clk_bulk
list of already claimed clock, no need to call clk_get*() again.

Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2022-11-27 15:34:56 +01:00
Marek Vasut
55a95f8f58 usb: Expand buffer size in usb_find_and_bind_driver()
The "generic_bus_%x_dev_%x" string which is printed into this buffer
can be up to 34 characters long ("generic_bus_12345678_dev_12345678").
The buffer would be clipped by snprintf() if both %x were at maximum
range. Make sure the buffer is long enough to cover such possibility.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-27 12:04:36 +01:00
Tom Rini
27c415ae8b Merge branch '2022-11-23-assorted-fixes'
- Small ubifs updates, mkenvimage fix, ast2600 ram updates, update CI to
  make git happier, spelling fix in K3 code and fix dependencies in
  CMD_CLS
2022-11-24 16:31:02 -05:00
John Keeping
2fdc4c0c49 cmd: fix dependency for CMD_CLS
It seems this symbol was missed when renaming DM_VIDEO -> VIDEO.  Update
it.

Fixes: b86986c7b3 ("video: Rename CONFIG_DM_VIDEO to CONFIG_VIDEO")
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: John Keeping <john@metanate.com>
2022-11-24 16:26:03 -05:00
Bryan Brattlof
4c710fa828 arm: mach-k3: fix spelling mistake "entended" -> "extended"
the macro for the boot data location from rom is misspelled. fix it

Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-11-24 16:26:03 -05:00
Tom Rini
bd181a24c4 CI: Make more use of git safe.directory
We have a number of jobs that will have git complain about needing to
set safe.directory and this being untrue as a fatal error, but then
complete. Set this flag correctly now as it should be used, and may
prevent a future failure.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-24 16:26:03 -05:00
Dylan Hung
8c7b55724c ram: ast2600: Align the RL and WL setting
Use macro to represent the RL and WL setting to ensure the PHY and
controller setting are aligned.

Review-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-24 16:26:01 -05:00
Dylan Hung
bd1e195421 ram: ast2600: Improve ddr4 timing and signal quality
Adjust the following settings to get better timing and signal quality.

1. write DQS/DQ delay
- 1e6e2304[0]
- 1e6e2304[15:8]

2. read DQS/DQ delay
- 0x1e6e0298[0]
- 0x1e6e0298[15:8]

3. CLK/CA timing
- 0x1e6e01a8[31]

4. Read and write termination
- change RTT_ROM from 40 ohm to 48 ohm (MR1[10:8])
- change RTT_PARK from disable to 48 ohm (MR5[8:6])
- change RTT_WR from 120 ohm to disable (MR2[11:9])
- change PHY ODT from 40 ohm to 80 ohm (0x1e6e0130[10:8])

Note1: Both DDR-PHY and DDR controller have their own registers for DDR4
Mode Registers (MR0~MR6).  This patch introduces macros to synchronize
the MR value on both sides.

Note2: the waveform meansurement can be found in item #21 of Aspeed
AST26x0 Application note (AP note).

Review-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-24 16:25:58 -05:00
Dylan Hung
581df347db ram: ast2600: Fix incorrect statement of the register polling
The condition "~data" in the if-statement is a typo.  The original
intention is to poll if SDRAM_PHYCTRL0_INIT bit equals to 0. So use
"data == 0" for instead.

Besides, the bit[1] of "phy_status" register is hardwired to
SDRAM_PHYCTRL0_INIT (with inverse logic). Since SDRAM_PHYCTRL0_INIT has
already done, remove the unnecessary checking of phy_status[1].

Fixes: fde93143469f ("ram: aspeed: Add AST2600 DRAM control support")
Review-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-24 16:25:54 -05:00
Marek Vasut
c246d69f31 tools: mkenvimage: Drop duplicate crc header include
This header was already included just above version.h,
do not include it twice.

Fixes: 3db71108575 ("crc32: Use the crc.h header for crc functions")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-23 13:06:12 -05:00
Pali Rohár
1853811287 cmd: ubifs: Do not show usage when command fails
Return value -1 cause U-Boot to print usage message. Return value
1 (CMD_RET_FAILURE) indicates failure. So fix return value when ubifs
command starts it execution and fails.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
2022-11-23 13:06:12 -05:00
Pali Rohár
6b752c729e ubifs: Allow to silence debug dumps
Debug dump logs are not always required. Add a new config option
UBIFS_SILENCE_DEBUG_DUMP to silence all debug dumps. On powerpc/mpc85xx
when enabled this will decrease size of U-Boot binary by 11 kB.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
2022-11-23 13:06:12 -05:00
Tom Rini
d5d9f32579 - Implement setbrg op to meson serial device
- Re-add the old PHY reset binding for nanopi-k2
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Merge tag 'u-boot-amlogic-20221122' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- Implement setbrg op to meson serial device
- Re-add the old PHY reset binding for nanopi-k2
2022-11-23 10:05:26 -05:00
Tom Rini
19fb8d7945 buildman /binman improvements for handling missing blobs
fix for long-standing image.h warning
 minor fixes
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Merge tag 'dm-pull-22nov22' of https://source.denx.de/u-boot/custodians/u-boot-dm

buildman /binman improvements for handling missing blobs
fix for long-standing image.h warning
minor fixes
2022-11-22 22:14:06 -05:00
Simon Glass
b4574c0e75 test: Disable part of the setexpr test for now
This fails in CI for unknown reasons. Disable the last assert for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:14:25 -07:00
Marek Vasut
d83615bc34 test: cmd: fdt: Add fdt get value test case
Add test case for 'fdt get value' sub command.

The test case can be triggered using:
"
./u-boot -d u-boot.dtb -c 'ut fdt'
"

Acked-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2022-11-22 15:13:35 -07:00
Marek Vasut
7dfcf2a57f cmd: fdt: Fix iteration over elements above index 1 in fdt get
Always increment both the iterator and pointer into the string
property value by length of the current element + 1 (to cater
for the string delimiter), otherwise the element extracted from
the string property value would be extracted from an offset that
is multiple of the length of the first element, instead of sum
of element lengths until select index.

This fixes 'fdt get value' operation for index above 1 (counting
from index 0).

Acked-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Fixes: 13982ced2cc ("cmd: fdt: Add support for reading stringlist property values")
Signed-off-by: Marek Vasut <marex@denx.de>
2022-11-22 15:13:35 -07:00
Sughosh Ganu
0524bfc297 sandbox: Move the capsule GUID declarations to board file
The sandbox config file is to be removed. Move the GUID declarations
needed for capsule update functionality to the board file where they
are used.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:35 -07:00
Heinrich Schuchardt
b3a680a47a sandbox: check lseek return value in handle_ufi_command
Invoking lseek() may result in an error. Handle it.

Addresses-Coverity-ID: 376212 ("Error handling issues  (CHECKED_RETURN)")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-22 15:13:35 -07:00
Simon Glass
8dd0059f77 binman: Add documentation for the command line args
Add command-line documentation for binman.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:35 -07:00
Tom Rini
d7713ad36f buildman: Add --allow-missing flag to allow missing blobs
Add a new flag to buildman so that we will in turn pass
BINMAN_ALLOW_MISSING=1 to 'make'. Make use of this flag in CI.

Allow the settings file to control this.

Cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:35 -07:00
Simon Glass
5f319fa728 buildman: Reinstate removal of temp output dir in tests
This was dropped my mistake. Reinstate it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: d829f1217c6 ("bulidman: Add support for a simple build")
2022-11-22 15:13:35 -07:00
Simon Glass
301cd7431a buildman: Ensure config_fname is inited
Init this variable at the top level since it is a global.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:35 -07:00
Tom Rini
b144b93ea9 global: Do not default to faking missing binaries for buildman
While it is possible and documented on how to re-run buildman to replace
faked required binary files after the fact, this behavior ends up being
more confusing than helpful in practice. Switch to requiring
BINMAN_ALLOW_MISSING=1 to be passed on the 'make' line to enable this
behavior.

Cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:35 -07:00
Simon Glass
85760a690d binman: Add a separate section about environment variables
These are documented in various several sections. Add a new section that
mentions them all in one place so it is easier to see what environment
variables can be used to control U-Boot's use of binman.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2022-11-22 15:13:35 -07:00
Simon Glass
35b6e53d0d buildman: Detect binman reporting missing blobs
Buildman should consider a build as a success (with warnings) if missing
blobs have been dealt with by binman, even though buildman itself returns
and error code overall. This is how other warnings are dealt with.

We cannot easily access the 103 exit code, so detect the problem in the
output.

With this change, missing blobs result in an exit code of 101, although
they still indicate failure.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:35 -07:00
Simon Glass
cd6889d896 buildman: Drop mention of old architectures
Support for some architectures has been removed since buildman was first
written. Also all toolchains are now available at kernel.org so we don't
need the links, except for arc where the kernel.org toolchain fails to
build all boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:34 -07:00
Simon Glass
3da04ff1d3 buildman: Update the default settings file
The settings file omits a few lines which are useful for getting every
board building. Add these and update the documentation tool.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:34 -07:00
Simon Glass
ce59252df5 buildman: Update the arc toolchain
There is one on kernel.org but it does not build the hsdk_4xd board. Add
a link to one which does.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:34 -07:00
Simon Glass
274d05303d buildman: Drop mention of MAKEALL
This script was removed about 6 years ago so most people should be aware
that it is not needed anymore. Drop mention of it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:34 -07:00
Simon Glass
74df491051 buildman: Convert documentation to rST
Convert the buildman documentation to rST format and include it in the
'build' section.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Quentin Schulz <foss+uboot@0leil.net>
2022-11-22 15:13:34 -07:00
Simon Glass
b38da15a05 binman: Use an exit code when blobs are missing
At present binman returns success when told to handle missing/faked blobs
or missing bintools. This is confusing since in fact the resulting image
cannot work.

Use exit code 103 to signal this problem, with a -W option to convert
it to a warning.

Rename the flag to --ignore-missing since it controls bintools also.

Add documentation about exit codes while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:34 -07:00
Simon Glass
921b0a6ce2 doc: Correct the path to the Makefile documentation
This is out-of-date now. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:34 -07:00
Simon Glass
c39c7c62d6 Makefile: Correct the binman rule
This currently uses if_changed on a phony target. Use a real file as the
target and add FORCE at the end, as required. Drop the 'inputs' phony
since it is not needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:34 -07:00
Simon Glass
88ff7cb1c8 image: Correct strncpy() warning with image_set_name()
gcc 12 seems to warn on strncpy() as a matter of course. Rewrite the code
a different way to do the same thing, to avoid the warning.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:34 -07:00
Quentin Schulz
fb132b3727 Revert "binman: btool: gzip: fix packer name so that binary can be found"
This reverts commit daa2da754afe1bac777f6cb0f05233e0de7b325d.

This commit is not needed anymore since the btool_ prefix is
automatically stripped by bintool.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:34 -07:00
Quentin Schulz
478332a345 binman: bintool: remove btool_ prefix from btool names
The binary is looked on the system by the suffix of the packer class.
This means binman was looking for btool_gzip on the system and not gzip.

Since a btool can have its btool_ prefix missing but its module and
binary presence on the system appropriately found, there's no need to
actually keep this prefix after listing all possible btools, so let's
remove it.

This fixes gzip btool by letting Bintool.find_bintool_class handle the
missing prefix and still return the correct class which is then init
with gzip name instead of btool_gzip.

Additionally, there was an issue with the cached module global variable.
The variable only stores the module and not the associated class name
when calling find_bintool_class.
This means that when caching the module on the first call to
find_bintool_class, class_name would be set to Bintoolbtool_gzip but the
module_name gzip only, adding the module in the gzip key in the module
dictionary. When hitting the cache on next calls, the gzip key would be
found, so its value (the module) is used. However the default class_name
(Bintoolgzip) is used, failing the getattr call.

Instead, let's enforce the same class name: Bintool<packer>, whatever
the filename it is contained in.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-22 15:13:34 -07:00
Christian Hewitt
e0638f1d09 arm64: dts: meson: nanopi-k2: readd PHY reset properties
The sync of device-tree/bindings in 11a48a5a18c6 ("Linux 5.6-rc2") causes
Ethernet to break on some GXBB boards; the PHY seems to need proper reset
timing to function in u-boot and Linux. Re-add the old PHY reset binding
for dwmac until we support new bindings in the PHY node. This borrows the
same fix applied to the Odroid C2 board [0].

[0] https://lists.denx.de/pipermail/u-boot/2021-April/446658.html

Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Link: https://lore.kernel.org/r/20221025143205.14470-1-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2022-11-22 18:53:21 +01:00
Edoardo Tomelleri
66006f86e8 arm: amlogic: add setbrg op to serial device
Implement setbrg in amlogic/meson serial device with driver model
similar to how the meson_uart.c driver does it in Linux. Also
configure (probe) the serial device with the new reg5 register.

Signed-off-by: Edoardo Tomelleri <e.tomell@gmail.com>
Link: https://lore.kernel.org/r/20220918161701.572814-1-e.tomell@gmail.com
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2022-11-22 18:53:21 +01:00
Tom Rini
521277ec15 Xilinx changes for v2023.01-rc3
microblaze:
 - Enable 32 bit addressing mode for SPIs
 
 zynq:
 - Minor DT fixes (PL clock enabling)
 
 zynqmp:
 - Disable watchdog by default
 - Remove unused xlnx,eeprom chosen support
 - Add missing symlink for vck190 SC revB
 - Use mdio bus with ethernet-phy-id description
 
 versal:
 - Add mini qspi/ospi configuration
 
 versal-net:
 - Add soc driver
 - Fix Kconfig entry for SOC
 - Fix loading address location for MINI configuration
 - Disable LMB for mini configuration
 
 net:
 - Fix ethernet-phy-id usage in the code
 
 pinctrl:
 - Revert high impedance/output enable support
 
 timer:
 - Fix timer relocation for Microblaze
 - Fix timer wrap in 32bit Xilinx timer driver
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Merge tag 'xilinx-for-v2023.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.01-rc3

microblaze:
- Enable 32 bit addressing mode for SPIs

zynq:
- Minor DT fixes (PL clock enabling)

zynqmp:
- Disable watchdog by default
- Remove unused xlnx,eeprom chosen support
- Add missing symlink for vck190 SC revB
- Use mdio bus with ethernet-phy-id description

versal:
- Add mini qspi/ospi configuration

versal-net:
- Add soc driver
- Fix Kconfig entry for SOC
- Fix loading address location for MINI configuration
- Disable LMB for mini configuration

net:
- Fix ethernet-phy-id usage in the code

pinctrl:
- Revert high impedance/output enable support

timer:
- Fix timer relocation for Microblaze
- Fix timer wrap in 32bit Xilinx timer driver
2022-11-22 12:33:48 -05:00
Ashok Reddy Soma
3655dd22a4 arm64: versal: Add octal spi flash mini u-boot configuration
Add configuration file for mini u-boot configuration which runs on a
smaller footprint from on chip memory(OCM). This configuration has
required CONFIG's enabled to support octal spi flash and uses DCC terminal
for console output. Add required dts for octal spi flash mini u-boot
configuration.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20221116141155.14788-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Ashok Reddy Soma
ce8adf1a41 spi: cadence-qspi: Fix compilation error in mini u-boot flash reset
When cadence_qspi_versal_flash_reset() function is called in mini
u-boot where there is no firmware support, it is missing defines for
macro's BOOT_MODE_POR_0 & BOOT_MODE_POR_1. Remove them and replace with
already define macro's which have same values as these.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20221116141155.14788-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Ashok Reddy Soma
3c53ebdd5c arm64: versal: Add qspi flash mini u-boot configuration
Add configuration file for mini u-boot configuration which runs on a
smaller footprint from on chip memory(OCM). This configuration has
required CONFIG's enabled to support qspi flash and uses DCC terminal
for console output. Add required dts files for qspi mini configuration.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20221116141155.14788-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Ashok Reddy Soma
450d8eb54f qspi: versal-net: Add condition for tapdelay register
Add CONFIG_ARCH_VERSAL_NET to select tapdelay register for versal-net.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2500dd688214e2ec2d54ed3fabbfee0b1ca861a6.1668613229.git.michal.simek@amd.com
2022-11-22 15:02:07 +01:00
Michal Simek
64fc7fc887 soc: xilinx: versal-net: Add soc_xilinx_versal_net driver
Add soc_xilinx_versal_net driver to identify the family & revision of
versal-net SoC. Add Kconfig option CONFIG_SOC_XILINX_VERSAL_NET to
enable/disable this driver. To enable this driver by default, add this
config to xilinx_versal_net_virt_defconfig file. This driver will be
probed using platdata U_BOOT_DEVICE structure which is specified in
mach-versal-net/cpu.c.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/613d6bcffd9070f62cf348079ed16c120f8fc56f.1668612993.git.michal.simek@amd.com
2022-11-22 15:02:07 +01:00
Michal Simek
de4a22e703 xilinx: versal-net: Disable LMB for mini configuration
There is no reason to have LMB enabled on mini configuration because it is
only consuming space that's why disable it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/47067c87b6b2e7600d3c2808e7d0aa6fe82aa1fe.1668612795.git.michal.simek@amd.com
2022-11-22 15:02:07 +01:00
Michal Simek
38920451c7 arm64: zynqmp: Describe TI phy as ethernet-phy-id with reset on zcu106
zcu106 also connects ethernet phy reset via tca6416 chip as is done on
other evaluation boards. That's why describe this connection to make sure
that ethernet phy is reset before it's use.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/21ccd672b799b5858021f6059098a1247c311fae.1668596358.git.michal.simek@amd.com
2022-11-22 15:02:07 +01:00
Michal Simek
9dc51069f4 xilinx: versal-net: Fix SYS_LOAD_ADDR to point to OCM
Versal NET mini U-Boot configuration is used for memory testing that's why
load address can't be really placed in memory which doesn't need to work
that's why move it to start of OCM which is the same memory which U-Boot is
running from.

Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Michal Simek
6b067f4bfa xilinx: versal-net: Fix incorrect platform name in Kconfig
Fix incorrect name used in entry description.

Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Michal Simek
7ca9662d7f arm64: zynqmp: Create vck190 spl link for revB
vck190 system controller low level setup is the same for revB that's why
also create symlink to revA.

Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Michal Simek
2e9946aba8 net: phy: Fix ethernet-phy-id <dot> in the code
Use dot instead of comma. The fix doesn't affect anything but it is good to
be aligned with used pattern. The first is used only for string size
calculation and the second change is in the comment.

Fixes: db681d4929ca ("net: phy: Add new read ethernet phy id function")
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Christian Kohn
96dcde487e ARM: zynq: DT: Enable all FCLKs by default
The fclk-enable property is set to 0 which disables all FCLKs.
Enable all FCLKs so they can be used as clock sources in the
programmable logic.

Signed-off-by: Christian Kohn <christian.kohn@xilinx.com>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b1308dc1f14f8eb24662019f7376c959e5e763b8.1665567031.git.michal.simek@amd.com
2022-11-22 15:02:07 +01:00
Ovidiu Panait
b34bc22bd9 timer: xilinx-timer: use timer_conv_64() to fix timer wrap around
Current xilinx_timer_get_count() implementation does not take into account
the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter
register value. The roll-overs cause problems in the upper timer layers, as
generic timer code expects an incrementing 64-bit value from get_count() to
work correctly.

Add the missing 64-bit up-conversion to fix random hangs/delays in
__udelay().

Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver")
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221012053656.1492457-3-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Ovidiu Panait
8272d4cb89 timer-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOC
Relocate timer_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled.

The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done
logic works for drivers that use DM_FLAG_PRE_RELOC.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20221012053656.1492457-2-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Ovidiu Panait
1e766a04c7 timer-uclass: add timer_get_ops() macro
Align timer uclass with the other subsystems and provide a timer_get_ops()
convenience macro.

Using this instead of the generic device_get_ops() also prevents
-Wdiscarded-qualifiers warnings when used with non-const variables.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20221012053656.1492457-1-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Venkatesh Yadav Abbarapu
ba74bcf3e0 xilinx: common: Remove zynq_board_read_rom_ethaddr()
Removing the zynq_board_read_rom_ethaddr() function as
xlnx,eeprom is not used anymore. As all board dts to use
nvmem alias instead of xlnx,eeprom.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221017094818.17996-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22 15:02:07 +01:00
Michal Simek
716527299a Revert "pinctrl: zynqmp: Add support for output-enable and bias-high-impedance"
This reverts commit 123462e5e534d6e17b1b7d2006734bbe54b03e0a.

On systems with older PMUFW using these pinctrl properties can cause system
hang because there is missing feature autodetection.
When it is implemented support for these two properties should go back.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c2900319ea80484f21692997f296269aee701c1f.1665659138.git.michal.simek@amd.com
2022-11-22 15:02:07 +01:00
Michal Simek
7b84fe7684 arm64: zynqmp: Disable watchdog by default for virt platform
Disable watchdog based on request in past that not all Linux rootfs have
proper utilities ready to service it. Enable it if your rootfs have proper
watchdog handling.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/62dfc08f32635abee42feab26aaa9efed52134c0.1665567328.git.michal.simek@amd.com
2022-11-22 15:02:07 +01:00
T Karthik Reddy
fcabdf1e7c microblaze: Make extended addressing support default
Axi qspi controller supports 32-bit & 24-bit addressing modes
for micron, macronix & spansion flash parts. But for winbond
flashes it only supports 24-bit addressing mode.
Enable CONFIG_SPI_FLASH_BAR to use extended addressing mode
to make 32-bit addressing mode work on all flashes.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f3864966c8ddd766a1702ad61b0e008a1f57462f.1665565423.git.michal.simek@amd.com
2022-11-22 15:02:07 +01:00
Tom Rini
536c642ffe Pull request for efi-2023-01-rc2-2
UEFI:
 
 * add UEFI Secure Boot Key enrollment interface to eficonfig command
 * fix buffer underflow in FatToStr() implementation
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Merge tag 'efi-2023-01-rc2-2' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2023-01-rc2-2

UEFI:

* add UEFI Secure Boot Key enrollment interface to eficonfig command
* fix buffer underflow in FatToStr() implementation
2022-11-22 08:30:53 -05:00
Tom Rini
b94db9efe8 Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog
- watchdog: designware: make reset really optional (Quentin)
- watchdog: Drop GD_FLG_WDT_READY (Stefan)
2022-11-22 08:07:03 -05:00
Masahisa Kojima
d0f9ae35fb eficonfig: add "Show Signature Database" menu entry
This commit adds the menu-driven interface to show the
signature list content.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-11-22 12:00:45 +01:00
Masahisa Kojima
c3b5af63d1 eficonfig: add UEFI Secure Boot Key enrollment interface
This commit adds the menu-driven UEFI Secure Boot Key
enrollment interface. User can enroll PK, KEK, db
and dbx by selecting file.
Only the signed EFI Signature List(s) with an authenticated
header, typically '.auth' file, is accepted.

To clear the PK, KEK, db and dbx, user needs to enroll the null key
signed by PK or KEK.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-11-22 12:00:45 +01:00
Masahisa Kojima
21faf4ef67 eficonfig: use protocol interface for file selection
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL is not always provided
by U-Boot. Use protocol interface functions instead of
U-Boot internal functions.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
2022-11-22 12:00:44 +01:00
Masahisa Kojima
d656611310 eficonfig: expose eficonfig_create_device_path()
Following commits are adding support for UEFI variable management
via the eficonfig menu. Those functions needs to use
eficonfig_create_device_path() to construct the full device path
from device path of the volume and file path, so move it
out of their static declarations.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
2022-11-22 12:00:44 +01:00
Masahisa Kojima
d571f9b23e eficonfig: refactor change boot order implementation
All the eficonfig menus other than "Change Boot Order"
use 'eficonfig_entry' structure for each menu entry.
This commit refactors change boot order implementation
to use 'eficonfig_entry' structure same as other menus
to have consistent menu handling.

This commit also simplifies the data->active handling when
KEY_SPACE is pressed, and sizeof() parameter.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-11-22 12:00:44 +01:00
Masahisa Kojima
8961e93e16 eficonfig: expose append entry function
Following commits are adding support for UEFI variable management
via the eficonfig menu. Those functions needs to use
append_entry() and append_quit_entry() to construct the
menu, so move them out of their static declarations.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-11-22 12:00:44 +01:00
Masahisa Kojima
a84040ab46 eficonfig: refactor file selection handling
eficonfig_select_file_handler() is commonly used to select the
file. eficonfig_display_select_file_option() adds an additional
menu to clear the selected file.
eficonfig_display_select_file_option() is not always necessary
for the file selection process, so it must be outside of
eficonfig_select_file_handler().

This commit also renames the following functions to avoid confusion.
 eficonfig_select_file_handler() -> eficonfig_process_select_file()
 eficonfig_select_file() -> eficonfig_show_file_selection()
 eficonfig_display_select_file_option() -> eficonfig_process_show_file_option()

Finally, test_eficonfig.py need to be updated to get aligned with
the above modification.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-11-22 12:00:44 +01:00
Heinrich Schuchardt
a356b50fdf doc: in cmp man-page replace 'tuples' by 'values'
The word tuples might be misleading.

Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-22 12:00:01 +01:00
Heinrich Schuchardt
6717a03d30 efi_selftest: Improve the FatToStr() unit test
Add a test with a character >= 0x80.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-22 11:54:30 +01:00
Heinrich Schuchardt
caf29d1e64 efi_selftest: unsigned char parameter for efi_st_strcmp_16_8()
Use unsigned char for the parameter of efi_st_strcmp_16_8. This allows
comparing characters 0x80 - 0xff.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-22 11:54:30 +01:00
Mikhail Ilin
ae182a25f5 efi_loader: Fix buffer underflow
If the array index 'i' < 128, the 'codepage' array is accessed using
[-128...-1] in efi_unicode_collation.c:262. This can lead to a buffer
overflow.

    Negative index in efi_unicode_collation.c:262.

The index of the 'codepage' array should be c - 0x80 instead of i - 0x80.

Fixes: 0bc4b0da7b59 ("efi_loader: EFI_UNICODE_COLLATION_PROTOCOL")
Signed-off-by: Mikhail Ilin <ilin.mikhail.ol@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-22 11:54:30 +01:00
Stefan Roese
5cbd029539 watchdog: Drop GD_FLG_WDT_READY as it's not used any more
Since commit c2fd0ca1a822
("watchdog: Integrate watchdog triggering into the cyclic framework")
GD_FLG_WDT_READY has become write-only. This patch now removes this
flag completely.

The vacant spot in gd_flags is filled with the newly introduced
GD_FLG_CYCLIC_RUNNING flag.

Suggested-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
2022-11-22 08:56:26 +01:00
Quentin Schulz
dca313ff9d watchdog: designware: make reset really optional
Checking for DM_RESET is not enough since not all watchdog
implementations use a reset lane. Such is the case for Rockchip
implementation for example. Since reset_assert_bulk will only succeed if
the resets property exists in the watchdog DT node, it needs to be
called only if a reset property is present.

This adds a condition on the resets property presence in the watchdog DT
node before assuming a reset lane needs to be fetched with
reset_assert_bulk, by calling ofnode_read_prop.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2022-11-22 08:56:26 +01:00
Tom Rini
16e49a14b2 Prepare v2023.01-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-11-21 12:33:14 -05:00
Tom Rini
b871701ff1 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-11-21 11:58:53 -05:00
Tom Rini
347ed84822 Merge branch '2022-11-21-important-fixes'
- Several important fixes for the Nokia RX51 platform, and a few other
  fixes while we're at it.
2022-11-21 11:54:58 -05:00
Samuel Holland
4b0a1f5987 spl: Fix SPL_ATF and SPL_OPENSBI dependencies
The code for these two options depends on having the FIT loadables
recorded in the FDT. Thus, these options require the full version of
the SPL_LOAD_FIT code.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-11-21 09:23:00 -05:00
Alexandre Mergnat
758bff205f configs: mediatek: enable boot via extlinux
Enable FAT and SYSBOOT to use extlinux boot script

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Julien STEPHAN <jstephan@baylibre.com>
2022-11-21 09:23:00 -05:00
Venkatesh Yadav Abbarapu
fbce985e28 usb: gadget: dfu: Fix the unchecked length field
DFU implementation does not bound the length field in USB
DFU download setup packets, and it does not verify that
the transfer direction. Fixing the length and transfer
direction.

CVE-2022-2347

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2022-11-21 09:23:00 -05:00
Stefano Babic
8fc220d0a6 Revert "imx: imx8: apalis: switch to binman"
This reverts commit b8072ae848b73e89a73ba5b535324e4dc2793f37.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-21 09:23:00 -05:00
Pali Rohár
60d7820093 Revert "cli_readline: Only insert printable chars"
This reverts commit d2e64d29c44dee6d455f7705dd1cf1af8674ad9a.

This commit broke support for pound sign (£) and euro sign (€) keys on
Nokia N900 keypad.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-21 09:23:00 -05:00
Pali Rohár
9c41c06069 Nokia RX-51: Do not overwrite standard $loadaddr variable
Instead of overwriting $loadaddr variable, use custom temporary
$fileloadaddr variable. So scripts can access default/original address
stored in $loadaddr at build time.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-11-21 09:23:00 -05:00
Pali Rohár
9c2d4057e1 Nokia RX-51: Document debugging options and compile command
Add example command how to compile U-Boot and add new documentation section
describing how to enable early debug UART and verbose log output for N900.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-11-21 09:23:00 -05:00
Pali Rohár
04bb5e95be arm32: Fix relocation of env_addr if POSITION_INDEPENDENT=y
Apply commit 534f0fbd6520 ("arm64: Fix relocation of env_addr if
POSITION_INDEPENDENT=y") also for 32-bit ARM.

This change fixes crashing of U-Boot on ARMv7 (Omap3 / Cortex-A8) Nokia N900
phone (real HW). Note that qemu emulator of this board with same u-boot.bin
binary has not triggered this crash.

Crash happened after U-Boot printed following debug lines to serial console:

    initcall: 0001ea8c (relocated to 8fe0aa8c)
    Loading Environment from <NULL>... Using default environment
    Destroy Hash Table: 8fe25a98 table = 00000000
    Create Hash Table: N=387

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-11-21 09:23:00 -05:00
Pali Rohár
2827c2f07d Fix usage of CONFIG_PREBOOT
Due to usage of PREBOOT in Kconfig, macro CONFIG_PREBOOT is always defined
when CONFIG_USE_PREBOOT is enabled. In case CONFIG_PREBOOT is not
explicitly enabled it is set to empty C string and therefore
'#ifdef CONFIG_PREBOOT' guard does not work. Fix this issue by introducing
a new Kconfig symbol PREBOOT_DEFINED which cause to define new C macro
CONFIG_PREBOOT_DEFINED only when CONFIG_PREBOOT is really defined.

Change usage of '#ifdef CONFIG_PREBOOT' by '#ifdef CONFIG_USE_PREBOOT' for
code which checks if preboot code would be called and by
'#ifdef CONFIG_PREBOOT_DEFINED' for defining preboot code.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-11-21 09:23:00 -05:00
Tom Rini
bebb393b34 Pull request for efi-2023-01-rc2
Documentation:
 
 * fix building with Sphinx 5.0+
 * man-pages for cmp and bootd commands
 
 UEFI:
 
 * Avoid unaligned access in efi_file_from_path()
 * More bug fixes
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Merge tag 'efi-2023-01-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2023-01-rc2

Documentation:

* fix building with Sphinx 5.0+
* man-pages for cmp and bootd commands

UEFI:

* Avoid unaligned access in efi_file_from_path()
* More bug fixes
2022-11-16 11:08:51 -05:00
Tom Rini
d78cccb1ac Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- Fix and improve microchip's clock driver to allow sync'ing DTS with linux
- Improve the help message in "SBI_V02" Kconfig
- Improve DTS property "isa-string" parsing rule
2022-11-16 11:08:28 -05:00
Ilias Apalodimas
a930d69baa efi_loader: replace a u16_strdup with alloc + memcpy
Heinrich reports that on RISC-V unaligned access is emulated by OpenSBI
which is very slow.  Performance wise it's better if we skip the calls
to u16_strdup() -- which in turn calls u16_strsize() and just allocate/copy the
memory directly.  The access to dp.length may still be unaligned, but that's
way less than what u16_strsize() would do

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Use malloc() instead of calloc().
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-16 08:34:06 +01:00
Ilias Apalodimas
64012e0c52 efi_loader: add missing EFI_CALL when closing a file
Closing the files uses the EFI protocol and specifically it's .close
callback.  This needs to be wrapped on an EFI_CALL()

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-16 08:34:06 +01:00
Ilias Apalodimas
94a574d8f6 efi_loader: add comments on efi_file_from_path() regarding alignment
UEFI specification requires pointers that are passed to protocol member
functions to be aligned.  There's a u16_strdup in that function which
doesn't make sense otherwise  Add a comment so no one removes it
accidentally

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-16 08:34:06 +01:00
Masahisa Kojima
1167e88ab8 eficonfig: fix missing variable initialization
The 'ret' variable must be initialized before use
in eficonfig_delete_invalid_boot_option().

Fixes: c416f1c0bc ("bootmenu: add removable media entries")
Addresses-Coverity: 376207 ("Uninitialized variables")
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-11-16 08:34:06 +01:00
Heinrich Schuchardt
95d18c5ed0 efi_loader: improve description of efi_file_from_path()
Provide a description of the function's logic.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-11-16 08:34:06 +01:00
Heinrich Schuchardt
3d595ac5f5 cmd: remove superfluous if in eficonfig_edit_boot_option
Goto for an immediately succeeding label is superfluous.

Fixes: 87d791423ac6 ("eficonfig: menu-driven addition of UEFI boot option")
Addresses-Coverity: 376202 ("Identical code for different branches")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-11-16 08:34:06 +01:00
Heinrich Schuchardt
00ec77f2b0 MAINTAINERS: add UEFI commands to EFI PAYLOAD
Add the following files to EFI PAYLOAD:

- cmd/bootefi.c
- cmd/efidebug.c
- cmd/eficonfig.c
- cmd/nvedit_efi.c

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-11-16 08:34:06 +01:00
Ilias Apalodimas
9fb3269ab3 efi_loader: initialize return values in efi_uninstall_multiple_protocol_interfaces_int()
If the va_list we got handed over contains no protocols we must return
EFI_SUCCESS.  However in that case the current code just returns
an unintialized value.
Fix that by setting the return value in the variable definition

Addresses-Coverity: CID 376195:  ("Uninitialized variables  (UNINIT)")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-16 08:34:06 +01:00
Quentin Schulz
2b94359e9c doc: fix build with sphinx 5.0 and later.
Sphinx 5.0 and later fails to build when language is set to None:
Warning, treated as error:
Invalid configuration value found: 'language = None'. Update your configuration to a valid langauge code. Falling back to 'en' (English)

Let's set the language to English since it is the language used for the
documentation.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-16 08:34:06 +01:00
Heinrich Schuchardt
030c2d187e doc: add man-page for cmp command
Provide a man-page for the cmp command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-16 08:34:06 +01:00
Heinrich Schuchardt
5727f922ca Documentation: man-page for command bootd
Provide a man-page for the bootd command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 08:34:06 +01:00
Heinrich Schuchardt
dd706c83be sandbox: fix documentation of struct host_ops
The documentation of struct host_ops should be Sphinx compliant.

Fixes: 9bd1aa8af2ed ("dm: sandbox: Create a new HOST uclass")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-16 08:34:06 +01:00
Heinrich Schuchardt
a8a0fc4628 doc: fix documentation of enum gd_flags
Correct GD_FLG_CYCLIC_RUNNING documentation to match Sphinx style.

Fixes: d7de5ef62935 ("cyclic: use a flag in gd->flags for recursion protection")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-16 08:34:06 +01:00
Heinrich Schuchardt
591e0f8780 riscv: enable reset via SBI on PolarFire Icicle Kit
HSS 2022.10 provides support for resetting the board.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-15 15:37:17 +08:00
Heinrich Schuchardt
5c89467262 riscv: clarify meaning of CONFIG_SBI_V02
Describe that CONFIG_SBI_V02=y does not mean SBI specification v0.2
but v0.2 or later.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-15 15:37:17 +08:00
Yu Chien Peter Lin
c277c787a0 riscv: Fix detecting FPU support in standard extension
We should check the string until it hits underscore, in case it
searches multi-letter extensions. For example, "rv64imac_xandes"
will be treated as D extension support since there is a "d" in
"andes", resulting illegal instruction caused by initializing FCSR.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-11-15 15:37:17 +08:00
Conor Dooley
3f3527044d riscv: dts: fix the mpfs's reference clock frequency
The initial devicetree for PolarFire SoC incorrectly created a fixed
frequency clock in the devicetree to represent the msspll, but the
msspll is not a fixed frequency clock. The actual reference clock on a
board is either 125 or 100 MHz, 125 MHz in the case of the icicle kit.
Swap the incorrect representation of the msspll out for the actual
reference clock.

Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-15 15:37:17 +08:00
Conor Dooley
4e405c68fb clk: microchip: mpfs: fix criticality of peripheral clocks
Sync the critical clocks in the U-Boot driver with those marked as
critical in Linux. The Linux driver has an explanation of why each clock
is considered to be critical, so import that too.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-15 15:37:17 +08:00
Conor Dooley
88b697fb37 clk: microchip: mpfs: fix periph clk parentage
Not all "periph" clocks are children of the AHB clock, some have the AXI
clock as their parent & the mtimer clock is derived from the external
reference clock directly. Stop assuming the AHB clock to be the parent
of all "periph" clocks and define their correct parents instead.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-15 15:37:17 +08:00
Conor Dooley
32cfdd5163 clk: microchip: mpfs: fix reference clock handling
The original devicetrees for PolarFire SoC messed up & defined the
msspll's output as a fixed-frequency, 600 MHz clock & used that as the
input for the clock controller node. The msspll is not a fixed
frequency clock and later devicetrees handled this properly. Check the
devicetree & if it is one of the fixed ones, register the msspll.
Otherwise, skip registering it & pass the reference clock directly to
the cfg clock registration function so that existing devicetrees are
not broken by this change.

As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for
it, based on the one in Linux.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-15 15:37:17 +08:00
Conor Dooley
fb103971fe clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()
Currently the clock driver for PolarFire SoC takes a very naive approach
to the relationship between clocks. It reads the dt to get an input
clock, assumes that that is fixed frequency, reads the "clock-frequency"
property & uses that to set up both the "cfg" and "periph" clocks.

Simplifying for the sake of incremental fixes, the "correct" parentage for
the clocks currently supported in U-Boot is that the "cfg" clocks should
be children of the fixed frequency clock in the dt. The AHB clock is one
of these "cfg" clocks and is the parent of the "periph" clocks.

Instead of passing the clock rate of the fixed-frequency clock to the
"cfg" and "periph" registration functions and the name of the parents,
pass their actual parents & use clk_get_rate() to determine their parents
rates.

The "periph" clocks are purely gate clocks and should not be reading the
AHB clocks registers to determine their rates, as they can simply report
the output of clk_get_rate() on their parent.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-15 15:37:17 +08:00
Conor Dooley
540d02217f dt-bindings: clk: add missing clk ids for microchip mpfs
When this binding header was initally upstreamed, the PLL clocking the
microprocessor subsystem (MSS) and the RTC reference clocks were
omitted. Add them now, matching the IDs used in Linux.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-15 15:37:17 +08:00
Tom Rini
c4ee4fe92e For 2022.01
-----------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083
 
 - Fix UART
 - moved to binman (MX8 boards)
 - Toradex: sync DTS with Linux
 - Gateworks: fixes
 - New boards : MSC SM2S iMX8MP
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Merge tag 'u-boot-imx-20221114' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

For 2022.01
-----------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083

- Fix UART
- moved to binman (MX8 boards)
- Toradex: sync DTS with Linux
- Gateworks: fixes
- New boards : MSC SM2S iMX8MP
2022-11-14 09:33:36 -05:00
Tom Rini
fac432652f Merge tag 'for-v2023.01-rc2' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c Fixes for v2023.01-rc2

- i2c-gpio: add a missing new line in printed string
  detected and fixed by Sergei

- microchip i2c driver fixes from Conor
  - fix erroneous late ack send
  - fix ack sending logic
2022-11-14 07:29:30 -05:00
Sergei Antonov
b0c485fd38 i2c: i2c-gpio: add newline
Add newline at the end of the printed string.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-11-14 07:24:47 +01:00
Conor Dooley
6d133b3158 i2c: microchip: fix erroneous late ack send
A late ack is currently being sent at the end of a transfer due to
incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack
bit is being written to the controller's control reg after the last
byte has been received, causing it to sent another byte with the ack.
Instead, the AA flag should be written to the control register when
the penultimate byte is read so it is sent out for the last byte.

Reported-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Fixes: 0dc0d1e094 ("i2c: Add Microchip PolarFire SoC I2C driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

Removed Tag by hs: Fixes: 0190d48488 ("i2c: microchip: fix ack sending logic")
2022-11-14 07:21:58 +01:00
Conor Dooley
95b22bd6dc i2c: microchip: fix ack sending logic
"Master receive mode" was not correctly sending ACKs/NACKs in the
interrupt handler. Bring the handling of M_SLAR_ACK, M_RX_DATA_ACKED &
M_RX_DATA_NACKED in line with the Linux driver.

Fixes: 0dc0d1e094 ("i2c: Add Microchip PolarFire SoC I2C driver")
Reported-by: Shravan Chippa <shravan.chippa@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-11-14 07:20:10 +01:00
Fabio Estevam
fc1c1760de Revert "serial: mxc: have putc use the TXFIFO"
This reverts commit c7878a0483c59c48a730123bc0f4659fd40921bf.

Since commit c7878a0483c5 ("serial: mxc: have putc use the TXFIFO"),
serial console corruption can be seen when priting inside board_init().

Revert it to avoid the regression.

Reported-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2022-11-12 14:16:26 +01:00
Fabio Estevam
c9713c1551 imx8-u-boot: Fix SPL guard option
We should guard the SPL nodes against CONFIG_SPL_BUILD to fix
the following build error when the blobs are absent:

binman: Fail open first container file mx8qm-ahab-container.img

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-11-12 14:13:49 +01:00
Tom Rini
0cbeed4f66 Merge branch '2022-11-10-symbol-migrations'
- Migrate a number of CONFIG symbols to Kconfig and start migrating some
  symbol families from CONFIG to the CFG namespace.
2022-11-10 10:09:40 -05:00
Tom Rini
cc1159bbfa global: Migrate CONFIG_HPS* symbols to the CFG namespace
Migrate all of CONFIG_HPS* to the CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 10:08:55 -05:00
Tom Rini
6cc04547cb global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 10:08:55 -05:00
Tom Rini
5155207ae1 global: Migrate CONFIG_SYS_MPC8* symbols to the CFG_SYS namespace
Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-11-10 10:08:55 -05:00
Tom Rini
d236210c11 Convert CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 10:08:55 -05:00
Tom Rini
8c778f7834 Convert CONFIG_SYS_NONCACHED_MEMORY to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NONCACHED_MEMORY

To do this we introduce CONFIG_SYS_HAS_NONCACHED_MEMORY as a bool to
gate if we are going to have noncached_... functions available and then
continue to use CONFIG_SYS_NONCACHED_MEMORY to store the size of said
cache. We make this new option depend on both the architectures which
implement support and the drivers which make use of it.

Cc: Tom Warren <twarren@nvidia.com>
Cc: Mingming lee <mingming.lee@mediatek.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
Cc: Alban Bedel <alban.bedel@avionic-design.de>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 10:08:55 -05:00
Tom Rini
02f5a01441 SYS_NONCACHED_MEMORY: Correct comment in common/board_f.c
The comment block in reserve_noncached has a typo in one filename and
an incorrect filename in another function reference. Correct both of
these.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 10:08:55 -05:00
Tom Rini
15713fc855 mediatek: Include <linux/sizes.h> where needed
These files reference SZ_ macros without including <linux/sizes.h>,
correct this.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 10:08:55 -05:00
Tom Rini
08574ed339 Convert CONFIG_SYS_MONITOR_LEN to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_MONITOR_LEN

To do this, we set a default of 0 for everyone because there are a
number of cases where we define CONFIG_SYS_MONITOR_LEN but the only
impact is that we set TOTAL_MALLOC_LEN to be CONFIG_SYS_MALLOC_LEN +
CONFIG_ENV_SIZE, so we must continue to allow all boards to set this
value. Update the SPL code to use 200 KB as the default raw U-Boot size
directly, if we don't have a real CONFIG_SYS_MONITOR_LEN value.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 10:08:55 -05:00
Tom Rini
9ba938e744 Convert CONFIG_SYS_MMC_MAX_DEVICE to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_MMC_MAX_DEVICE

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-11-10 10:08:55 -05:00
Tom Rini
75fc79e530 Convert CONFIG_SYS_MMC_MAX_BLK_COUNT to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_MMC_MAX_BLK_COUNT

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-11-10 10:08:55 -05:00
Tom Rini
a918df21f0 Convert CONFIG_SYS_MAX_NAND_DEVICE to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_MAX_NAND_DEVICE

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 10:08:54 -05:00
Tom Rini
e28e0f47f3 rtc: Remove unused drivers
These drivers are not enabled anywhere, remove them.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 09:45:54 -05:00
Tom Rini
2c8d04dd17 Convert CONFIG_SYS_LOADS_BAUD_CHANGE et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_LOADS_BAUD_CHANGE
   CONFIG_LOADS_ECHO

As part of this, we move CMD_SAVES to be after CMD_LOADS as they are
logically related (load or save an s-record format file) and this makes
grouping of CONFIG_SYS_LOADS_BAUD_CHANGE easier.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 09:45:54 -05:00
Tom Rini
b85d75951f powerpc: Migrate SYS_L3_SIZE to Kconfig
Introduce three options, one for each observed L3 cache size, and have
the size select'd as needed.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 09:45:54 -05:00
Tom Rini
22a2283f2d powerpc: Migrate SYS_L2_SIZE to Kconfig
Introduce two options, one for each observed L2 cache size, and have the
size select'd as needed.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 09:45:54 -05:00
Tom Rini
3b677dcd9d fs: jffs2: Move SYS_JFFS2_SORT_FRAGMENTS to Kconfig
Move the symbol SYS_JFFS2_SORT_FRAGMENTS to Kconfig and use the only
remaining part of doc/README.JFFS2 that is still relevant and useful to
the help for this option.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 09:45:54 -05:00
Tom Rini
e020b974ce Remove unused symbols CONFIG_SYS_JFFS2_FIRST_BANK et al
This removes the following symbols:
   CONFIG_RTC_MCFRRTC
   CONFIG_SYS_JFFS2_FIRST_BANK
   CONFIG_SYS_JFFS2_FIRST_SECTOR
   CONFIG_SYS_JFFS2_NUM_BANKS
   CONFIG_SYS_LBC_CACHE_BASE
   CONFIG_SYS_LIME_SIZE
   CONFIG_SYS_MAMR
   CONFIG_SYS_MCFRRTC_BASE
   CONFIG_SYS_MONITOR_SEC

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 09:45:54 -05:00
Tom Rini
c56289ddaf Convert CONFIG_SYS_INTERLAKEN et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_INTERLAKEN
   CONFIG_SYS_ISA_IO
   CONFIG_SYS_ISA_IO_BASE_ADDRESS

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 09:45:54 -05:00
Tom Rini
14a5d3b50e Remove dead code
This header is unreferenced, remove.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 09:45:53 -05:00
Tom Rini
d3d0b5bb62 Convert CONFIG_SYS_INIT_RAM_LOCK to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_INIT_RAM_LOCK

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 09:45:53 -05:00
Tom Rini
9244b2fda9 Convert CONFIG_SYS_I2C_INIT_BOARD to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_I2C_INIT_BOARD

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 09:45:53 -05:00
Stefano Babic
cca660c2bd Convert mx8 u-boot.dtsi to CONFIG_TEXT_BASE
Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-11-09 17:12:32 +01:00
Oliver Graute
b8072ae848 imx: imx8: apalis: switch to binman
Switch to use binman to pack images

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09 17:12:32 +01:00
Oliver Graute
bdadc140a1 imx: imx8x: colibri: switch to binman
Switch to use binman to pack images

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09 17:12:32 +01:00
Oliver Graute
bc1d145eaf imx: imx8qxp: deneb switch to binman
Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-11-09 17:12:32 +01:00
Oliver Graute
dcbc4ae9d6 imx: imx8qxp: giedi switch to binman
Switch to use binman to pack images

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09 17:12:32 +01:00
Oliver Graute
4aa738823c imx: imx8qm: imx8qm_mek switch to binman
Switch to use binman to pack images

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09 17:12:32 +01:00
Oliver Graute
61c57b614e imx: imx8qxp: imx8qxp_mek switch to binman
Switch to use binman pack images

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-11-09 17:12:32 +01:00
Oliver Graute
5a878c9472 imx: imx8qm: cgtqmx8: switch to binman
Switch to use binman to pack images

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-11-09 17:12:32 +01:00
Oliver Graute
55be8433d5 imx: imx8qm-rom7720: switch to binman
Switch to use binman to pack images

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09 17:12:32 +01:00
Fabio Estevam
20cc70a84f wandboard: Select DM_SERIAL
The conversion to DM_SERIAL is mandatory, so select this
option.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-11-09 17:12:31 +01:00
Fabio Estevam
f827f84d3f wandboard: Pass mmc aliases
Originally, the mmc aliases node was present in imx6qdl-wandboard.dtsi.

After the sync with Linux in commit d0399a46e7cd ("imx6dl/imx6qdl:
synchronise device trees with linux"), the aliases node is gone as
the upstream version does not have it.

This causes a regression in which the SD card cannot be found anymore:

Since commit  the aliases node has been removed
U-Boot 2022.10-00999-gcca41ed3d63f-dirty (Nov 03 2022 - 22:07:38 -0300)

CPU:   Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: POR
DRAM:  2 GiB
Core:  62 devices, 17 uclasses, devicetree: separate
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... MMC: no card present
*** Warning - No block device, using default environment

Fix it by passing the alias node in the u-boot.dtsi file to
restore the original behaviour where the SD card (esdhc3) was
mapped to mmc0.

Fixes: d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with linux")
Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-11-09 17:12:31 +01:00
Adam Ford
f2fe18fa38 configs: imx8mn_beacon: Enable SPL_DM_PMIC_BD71837
To properly operate the Nano with LPDDR4 at 1.6GHz, the
voltage needs to be adjusted before DDR is initialized.
Enable the PMIC in SPL to do this.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-11-08 17:35:00 +01:00
Adam Ford
899f291bd1 configs: imx8mn_beacon: Re-align memory to standard imx8mn settings
The imx8mn_beacon board does not use the same memory map as the reference
design from NXP or other imx8mn boards.  As such, memory is more limited
in SPL.

Moving SPL_BSS_START_ADDR and SPL_STACK to default locations increases
the amount of available meory for the SPL stack.  Doing this allows
the board to no longer define CONFIG_MALLOC_F_ADDR.

Since SYS_LOAD_ADDR also does not align with other boards, move it too.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
dbd5ca2e46 imx8mm: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8m{m,n,p}-venice-*
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
f067b59743 imx8mn: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8m{m,n,p}-venice-*
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
0b42fdca2d imx8mp: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8m{m,n,p}-venice-*
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
cb9b70fd2f imx8mq: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
ed7bda5710 imx8ulp: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
62f96866d3 imxrt1050: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.

Note: Nowadays, the intent is for them regular device trees to just be
synchronised from them Linux kernel device trees and any and all U-Boot
specific changes need to go into the -u-boot.dtsi device tree include
files which BTW get included automatically by the U-Boot build system.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
59a4e7fd88 imxrt1020: migrate to build system included -u-boot.dtsi
Migrate to using automatic build system included -u-boot.dtsi device
tree include files.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Tested-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2022-11-08 17:35:00 +01:00
Marcel Ziswiler
05e22e2804 vf610: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-08 17:35:00 +01:00
Tim Harvey
4a71b9c286 configs: imx8m{m,n,p}_venice: disable autoload
disable network autoload

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-11-08 17:35:00 +01:00
Tim Harvey
765f6f1895 imx: imx8m{m,n,p}_venice: migrate to CONFIG_EXTRA_ENV_TEXT
Move the majority of the environment from the board headers to
a separate text file.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-11-08 17:35:00 +01:00
Tim Harvey
e9e03e7984 configs: imx8m{m, n}_venice: remove unneeded CONFIG_FEC_MXC_PHYADDR
The IMX8M based Venice boards all have device-tree fec nodes that
use proper dt with a phy-handle pointing to a phy with reg assigned
to the proper phy address.

There is no need to keep using the CONFIG_FEC_MXC_PHYADDR hack when
a proper dt is used - remove it.

This was previously done in commit 400eebf10d9b
("configs: imx8m{m, n}_venice: remove unneeded CONFIG_FEC_MXC_PHYADDR")
but got clobbered by commit 6889412ad5e7
("Convert CONFIG_SYS_BARGSIZE to Kconfig")

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-11-08 17:35:00 +01:00
Tim Harvey
37fa34f727 configs: imx8mn_venice.h: remove unused ifdef
remove unused ifdef left behind after commit ca3369df71d8
("configs: drop CONFIG_SPL_ABORT_ON_RAW_IMAGE")

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-11-08 17:35:00 +01:00
Tim Harvey
9414097ab7 configs: imx8mn_venice: fix include header protection
Fix typo in the include header protection.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-11-08 17:35:00 +01:00
Tim Harvey
630abef2f1 board: gateworks: venice: remove redundance adjustment of thermal trip points
commit 0543a1ed2787 ("imx8m: fixup thermal trips") moved updating the
thermal trip points to all IMX8M so we can remove it from our board
specific dt config.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-11-08 17:35:00 +01:00
Baruch Siach
cf8ffbe36f mx6cuboxi: migrate to DM_SERIAL
Add the needed DT overrides to enable UART in SPL.

Cc: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Tested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-11-08 17:35:00 +01:00
Marek Vasut
b177a2626e ARM: imx: Add version variable to DHSOM
Enable insertion of version variable into U-Boot environment on DHSOM,
to make it possible to check U-Boot version e.g. in U-Boot scripts.

Signed-off-by: Marek Vasut <marex@denx.de>
2022-11-08 17:35:00 +01:00
Martyn Welch
c8f3402ad2 arm: imx8mp: Initial MSC SM2S iMX8MP support
Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction
with the MSC SM2-MB-EP1 Mini-ITX Carrier Board.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-11-08 17:34:47 +01:00
Tom Rini
77b5cc2948 sandbox UCLASS_HOST
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Merge tag 'dm-pull-7nov22' of https://source.denx.de/u-boot/custodians/u-boot-dm

sandbox UCLASS_HOST
2022-11-08 09:45:10 -05:00
Michal Suchanek
168a0e45fc dm: blk: Add probe in blk_first_device/blk_next_device
The description claims that the device is probed but it isn't.

Add the device_probe() call.

Also consolidate the iteration into one function.

Fixes: 8a5cbc065d ("dm: blk: Use uclass_find_first/next_device() in blk_first/next_device()")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
2022-11-07 16:24:30 -07:00
Simon Glass
499503e157 dm: Add tests for the sandbox host driver
Add some unit tests for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
2851cc94f3 dm: Add documentation for host command and implementation
Document the 'host' command and also the internals of how it is
implemented.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
952018117a dm: sandbox: Switch over to using the new host uclass
Update the sandbox implementation to use UCLASS_HOST and adjust all
the pieces to continue to work:

- Update the 'host' command to use the new API
- Replace various uses of UCLASS_ROOT with UCLASS_HOST
- Disable test_eficonfig since it doesn't work (this should have a unit
  test to allow this to be debugged)
- Update the blk test to use the new API
- Drop the old header file

Unfortunately it does not seem to be possible to split this change up
further.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
10aae1145c dm: sandbox: Create a block driver
Create a block driver for the new HOST uclass. This handles attaching and
detaching host files.

For now the uclass is not used but this will be plumbed in with future
patches.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
9bd1aa8af2 dm: sandbox: Create a new HOST uclass
Sandbox supports block devices which can access files on the host machine.
At present there is no uclass for this. The devices are attached to the
root devic. The block-device type is therefore set to UCLASS_ROOT which
is confusing.

Block devices should be attached to a 'media' device instead, something
which handles access to the actual media and provides the block driver
for the block device.

Create a new uclass to handle this. It supports two operations, to attach
and detach a file on the host machine.

For now this is not fully plumbed in.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
41e751091d dm: blk: Tidy up obtaining a block device from its parent
This function now finds its block-device child by looking for a child
device of the correct uclass (UCLASS_BLK). It cannot produce a device of
any other type, so drop the superfluous check.

Provide a version which does not probe the device, since that is often
needed when setting up the device's platdata.

Also fix up the function's comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
d1b4659570 test: Add a way to detect a test that breaks another
When running unit tests, some may have side effects which cause a
subsequent test to break. This can sometimes be seen when using 'ut dm'
or similar.

Add a new argument which allows a particular (failing) test to be run
immediately after a certain number of tests have run. This allows the
test causing the failure to be determined.

Update the documentation also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
6580b61830 test: Allow showing basic information about tests
Add a 'ut info' command to show the number of suites and tests. This is
useful to get a feel for the scale of the tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
93e2673982 test: doc: Add documentation for ut command
Before adding more options, document this command.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
cdd964e380 test: Tidy up help for ut command
Sort this and put the command summary at the top instead of the bottom.

Adjust it so that the newlines are at the start of the strings, so that
there is not a blank line at the end.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
f7a68d2284 test: Drop an unused parameter to ut_run_test_live_flat()
The select_name parameter is not used anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
5ea894ac42 dm: test: Clear the block cache after running a test
Some tests access data in block devices and so cause the cache to fill
up. This results in memory being allocated.

Some tests check the malloc usage at the beginning and then again at the
end, to ensure there is no memory leak caused by the test. The block cache
makes this difficult, since the any test may cause entries to be allocated
or even freed, if the cache becomes full.

It is simpler to clear the block cache after each test. This ensures that
it will not introduce noise in tests which check malloc usage.

Add the logic to clear the cache, using the existing blkcache_invalidate()
function. Drop the duplicate code at the same time.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
fa1e420ab0 dm: test: Drop the special function for running DM tests
This is not needed since the flag takes care of all differences. Make use
of the common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
7cbb57321e test: Correct pylint warnings in fs_helper
Tidy this up so that pylint is happy. Use hex for the 1MB size and make
sure it is not a floating-point value.

Add a little main program to allow the code to be tried out, since at
present is only called from a long-running test.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
4349ba5977 test: Split out mk_fs function into a helper
This function is useful for other tests. Move it into common code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
6ca4d5b96b sandbox: Add missing comments for os_alarm()
Add the documentation to avoid a warning with 'make htmldocs'.

Fixes: 10107efedd5 ("sandbox: add SIGALRM-based watchdog device")

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Simon Glass
ff1f0e414a dm: sandbox: Drop non-BLK code from host implementation
This is not used anymore. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07 16:24:30 -07:00
Martyn Welch
e055457759 drivers: power: pmic: Enable use of rn5t567 PMIC in SPL
The support added later in this series tweaks the PMIC voltages in the
SPL. Enable support for the rn5t567 in SPL builds to allow this to be done
cleanly.

Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-11-07 22:45:05 +01:00
Martyn Welch
da470ddbb3 drivers: power: pmic: Add support for rn5t568 PMIC
Add support for the rn5t568 PMIC to the rn5t567 driver.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Jaehoon Chung <j80.chung@samsung.com>
2022-11-07 22:45:05 +01:00
Martyn Welch
c92c3a4453 ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MP
The i.MX8MP SoC contains 2 more i2c buses. Add support for the
configuration of these buses.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2022-11-07 22:45:05 +01:00
Martyn Welch
03a7a82970 imx8m: USDHC3 base address definition for i.MX8MP
The i.MX8MP also has USDHC3, allow access to the relvant base address
definition.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2022-11-07 22:45:05 +01:00
Adam Ford
78f34793ed imx: imx8mm-beacon: Move Environment to eMMC partition 2
The downstream U-Boot distributed by Beacon stores the environment
in the eMMC and the end of partition 2.  This allow the environment
to stay on the SOM regardless of the boot source.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-11-07 22:45:05 +01:00
Adam Ford
3a7943a90c imx: imx8mm-beacon: Enable USB booting via SDP
In order to boot over USB, the device tree needs to enable
a few extra nodes in SPL.  Since the USB driver has the
ability to detect host/device, the dr_mode can be removed
from the device tree since it needs to act as a device when
booting and OTG is the default mode.  Add USB boot support
to spl_board_boot_device and enable the corresponding config
options.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-11-07 22:45:05 +01:00
Adam Ford
b6c8a28090 imx: imx8mm_beacon: Eliminate a few extras to free up SPL space
There are a few functions which are not essential for use in
SPL, but they take up enough space to make other preferred
features not fit.  Remove the extras.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-11-07 22:45:05 +01:00
Adam Ford
a5685ea488 imx: imx8mn-beacon: Fix out of spec voltage
The DDR is configured for LPDDR4 running at 1.6GHz which requires
the voltage on the PMIC to rise a bit before initializing LPDDR4
or it will be running out of spec.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-11-07 22:45:04 +01:00
Adam Ford
4dbe07f275 regulator: bd718x7: Only bind children when PMIC_CHILDREN is enabled
If the bd718x7 is required, but PMIC_CHILDREN is disabled, this
driver throws a compile error.  Fix this by putting the function
to bind children into an if-statement checking for PMIC_CHILDREN.

Allowing PMIC_CHILDREN to be disabled in SPL saves some space and
still permits some read/write functions to access the PMIC in
early startup.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-11-07 22:45:04 +01:00
Matthias Schiffer
975f4117d5 ARM: mx7: psci: fix suspend/resume e10133 workaround
The e10133 workaround was broken in two places:

- The code intended to temporarily mask all interrupts in GPC_IMRx_CORE0.
  While the old register values were saved, the actual masking was
  missing.
- imx_udelay() expects the system counter to run at its base frequency,
  but the system counter is switched to a lower frequency earlier in
  psci_system_suspend(), leading to a much longer delay than intended.
  Replace the call with an equivalent loop (linux-imx 5.15 does the same)

This fixes the SoC hanging forever when there was already a wakeup IRQ
pending while suspending.

Fixes: 57b620255e ("imx: mx7: add system suspend/resume support")
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2022-11-07 22:45:04 +01:00
Loic Poulain
a887f2ac3e configs: imx8m: Enable CONFIG_ARMV8_CRYPTO support
This enables armv8 crypto extension usage for SHA1/SHA256.

Which speed up sha1/sha256 operations, about 10x faster with
a imx8mm evk for a 20MiB kernel hash verification (12ms vs 165ms).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-11-07 22:45:04 +01:00
Tom Rini
88bd8ee106 Prepare v2023.01-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-11-07 15:27:03 -05:00
Tom Rini
1bb3d8b201 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-11-07 11:58:57 -05:00
Tom Rini
6de63bd38b Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: Support for 98DX25xx/98DX35xx (AlleyCat5) (Chris)
- Makefile: Rename u-boot-spl.kwb to u-boot-with-spl.kwb (Pali)
- armada: dts: Add clock to armada-ap80x uart1 (Hamish)
2022-11-07 07:56:07 -05:00
Chris Packham
6cc8b5db40 arm: mvebu: Add RD-AC5X board
The RD-AC5X-32G16HVG6HLG-A0 development board main components and
features include:
* Main 12V/54V power supply
* 270 Gbps throughput packet processor on the main board
* DDR4:
  * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
  * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
  * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
* 16GB eMMC (Samsung KLMAG1JETD-B041006)
* 16MB SPI NOR(GD25Q127C)
* 32 x 1000 Base-T interfaces
* 16 x 2500 Base-T interfaces
  * SR1: 88E2540*4
  * SR2: 88E2580*1+88E2540*2
* Six (6) x 25G Base-R SFP28 interfaces
* One (1) x RJ-45 console connector, interfacing to the on board UART
* One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
* One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
* One (1) x RJ-45 1G Base-T Management port, interfacing to the host
  port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
* One (1) x Oculink port, interfacing to the PCIe port for external CPU
  connection
* POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
  Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
  solution)
* POE total power budget 780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2022-11-07 07:46:28 +01:00
Chris Packham
7d7bb99e22 arm: mvebu: Support for 98DX25xx/98DX35xx SoC
Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
an integrated CPU (referred to as the CnM block in Marvell's
documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support
has been ported from Marvell's SDK which is based on a much older
version of U-Boot.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2022-11-07 07:46:28 +01:00
Chris Packham
c249938214 pinctrl: mvebu: Add AlleyCat5 support
This uses the same IP block as the Armada-8K SoCs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-07 07:46:28 +01:00
Chris Packham
515fe1ee4e usb: ehci: ehci-marvell: Support for marvell,ac5-ehci
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-07 07:46:28 +01:00
Chris Packham
aaee5720f2 net: mvneta: Add support for AlleyCat5
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-07 07:46:28 +01:00
Chris Packham
3988e6d6b1 arm: mvebu: Don't use CONFIG_TIMER on ARM64
The 64-bit mvebu SoCs don't have a suitable timer driver so add a !ARM64
condition to the select.

Fixes: 7b530bb19e ("arm: mvebu: Use CONFIG_TIMER on all MVEBU & KIRKWOOD platforms")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-07 07:46:12 +01:00
Pali Rohár
87ac4b4b4c Makefile: Rename u-boot-spl.kwb to u-boot-with-spl.kwb
File name with pattern u-boot-spl* is used on all places except in kwb
image for binary with SPL-only code. Combined binary with both SPL and
proper U-Boot in other places has file name pattern u-boot-with-spl*.

Make it consistent also for kwb image and rename u-boot-spl.kwb to
u-boot-with-spl.kwb as this image contains both SPL and proper U-Boot code.

Also update documentation about file name changes.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-07 07:17:55 +01:00
Hamish Martin
497db3ad89 arm: armada: dts: Add clock to armada-ap80x uart1
The uart1 node was missing the 'clock-frequency' property. This meant
the driver for this device would fail at probe.
The clock for uart1 is fed from the same source as uart0 and is a fixed
200MHz clock. This is confirmed via documentation for the CN9130 SoC
and from the equivalent code in Linux at:
<linux>/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
where uart0 and uart1 share a common 'clocks' definition.

Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-07 07:17:55 +01:00
Tom Rini
d332cd59f7 Pull request for efi-2023-01-rc1-4
Documentation:
 
 * Provide a document about security issue handling.
 
 UEFI:
 
 * Let networking support depend on NETDEVICES.
 * Discover if no efi_system_partition is set.
 
 Other:
 
 * MAINTAINERS: add arch/arm/lib/*_efi.* to EFI_PAYLOAD.
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Merge tag 'efi-2023-01-rc1-4' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2023-01-rc1-4

Documentation:

* Provide a document about security issue handling.

UEFI:

* Let networking support depend on NETDEVICES.
* Discover if no efi_system_partition is set.

Other:

* MAINTAINERS: add arch/arm/lib/*_efi.* to EFI_PAYLOAD.
2022-11-06 07:51:44 -05:00
Heinrich Schuchardt
53def68df5 efi_loader: AllocateAddress requires page address
AllocatePages() can be called with Type=AllocateAddress. Such a call can
only succeed if *Memory points to the address of an unallocated page range.

A call with *Memory being an address that is not page aligned must not
succeed. The UEFI specification requires returning EFI_OUT_OF_RESOURCES
if the requested pages cannot be allocated.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-06 10:50:04 +01:00
Masahisa Kojima
0b4cbeba59 test/py: efi_secboot: Remove unnecessary cert-to-efi-hash-list option
'cert-to-efi-hash-list -t 0' does not work as expected, it produces
indeterminate timestamp.

  $ cert-to-efi-hash-list -t 0 -s 256 db.crt dbx_hash.crl
  TimeOfRevocation is 0-113-0 00:00:255

If we need the CRL revoked for all the time, just don't specify
'-t' option.

  $ cert-to-efi-hash-list -s 256 db.crt dbx_hash.crl
  TimeOfRevocation is 0-0-0 00:00:00

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-11-06 10:50:04 +01:00
Heinrich Schuchardt
2b55ad304d efi_loader: discover if no efi_system_partition is set
Variable efi_system_partition holds the efi_system_partition. Currently it
is initialized as:

    {
      .uclass_id = 0 = UCLASS_ROOT,
      .denum = 0,
      .part = 0,
    }

This indicates that host 0:0 is the efi_system_partition and we see output
like:

    => bootefi hello
    ** Bad device specification host 0 **
    Couldn't find partition host 0:0

To identify that no EFI system partition has been set use UCLASS_INVALID.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-11-06 10:50:04 +01:00
AKASHI Takahiro
023d9c9393 efi_loader: remove CONFIG_EFI_SETUP_EARLY
Since the commit a9bf024b2933 ("efi_loader: disk: a helper function to
create efi_disk objects from udevice"), CONFIG_EFI_SETUP_EARLY option is
by default on and will never be turned off.

So just remove this option.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-11-06 10:50:04 +01:00
Jan Kiszka
77b5c4a5b1 efi_loader: Let networking support depend on NETDEVICES
CONFIG_NET does not imply that there are actually network devices
available, only CONFIG_NETDEVICES does. Changing to this dependency
obsoletes the check in Kconfig because NETDEVICES means DM_ETH.

Fixes: 0efe1bcf5c2c ("efi_loader: Add network access support")
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2022-11-06 10:50:04 +01:00
Heinrich Schuchardt
607566d010 MAINTAINERS: add arch/arm/lib/*_efi.* to EFI_PAYLOAD
The files arch/arm/lib/*_efi.* are only relevant for the UEFI sub-system.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-06 10:50:04 +01:00
Tom Rini
541e68d0ee docs: Add a basic security document
Based loosely on the Linux kernel
Documentation/admin-guide/security-bugs.rst file, create a basic
security document for U-Boot.  In sum, security issues should be
disclosed in public on the mailing list if at all possible as an initial
position.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-06 10:50:04 +01:00
Heinrich Schuchardt
f67cc2f056 doc: update sbi command example
The output of the sbi command has been changed since the last release of
the man-page. Update the example.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-06 10:50:04 +01:00
Tom Rini
898bd53e6a Merge https://source.denx.de/u-boot/custodians/u-boot-usb
- 3 important fixes
2022-11-04 11:19:58 -04:00
Janne Grunau
04448899de usb: storage: continue probe on "Invalid device"
Fixes a crash during probing of sd card readers without medium present.
Seen with the device below but reported for many other devices.

  idVendor           0x0bda Realtek Semiconductor Corp.
  idProduct          0x0326 Card reader
  bcdDevice           11.24
  iManufacturer           1 Realtek
  iProduct                2 USB3.0 Card Reader
  iSerial                 3 201404081410

Link: https://github.com/AsahiLinux/linux/issues/44
Link: https://lists.denx.de/pipermail/u-boot/2022-July/489717.html

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
2022-11-04 12:22:45 +01:00
Tom Rini
45fc699cc5 - MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig
- MIPS: mtmips: fix incorrectly converted default value for CONFIG_SPL_PAD_TO
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Merge tag 'mips-pull-2022-11-03' of https://source.denx.de/u-boot/custodians/u-boot-mips

- MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig
- MIPS: mtmips: fix incorrectly converted default value for CONFIG_SPL_PAD_TO
2022-11-03 20:23:27 -04:00
Marek Vasut
3406e9d8af usb: Add 1ms delay after first Get Descriptor request
Logitech Unifying Receiver 046d:c52b bcdDevice 12.10 seems
sensitive about the first Get Descriptor request. If there
are any other requests in the same microframe, the device
reports bogus data, first of the descriptor parts is not
sent to the host. Wait over one microframe duration before
issuing subsequent requests to avoid probe failure with
this device, since it can be used to connect USB keyboards.

Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Janne Grunau <j@jannau.net>
2022-11-03 23:36:48 +01:00
Samuel Holland
f4917b4933 usb: ohci: Use a flexible array member for portstatus
The struct is only used to overlay the MMIO region, so the behavior is
the same. This obsoletes the Kconfig option for the number of ports.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-11-03 23:24:09 +01:00
Tom Rini
36bc9b6113 Merge branch '2022-11-02-assorted-updates'
- Improve arm semihosting, NPCM8xx pinctrl driver, SP804 uclass timer
  driver (and enable on relevant platforms), pvblock cleanup, eeprom cmd
  bugfix, add RTI watchdog nodes to k3-am64-main, evb-ast2500 config
  updates.
2022-11-03 08:29:10 -04:00
Tom Rini
c07babda65 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv 2022-11-03 08:27:44 -04:00
Padmarao Begari
7321bad25f riscv: Update Microchip MPFS Icicle Kit support
This patch updates Microchip MPFS Icicle Kit support. For now,
add Microchip QSPI driver and a small 4MB reservation is
made at the end of 32-bit DDR to provide some memory for
the HSS to use.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-03 13:27:56 +08:00
Padmarao Begari
eac3bbe5d8 spi: Add Microchip PolarFire SoC QSPI driver
Add QSPI driver code for the Microchip PolarFire SoC.
This driver supports the QSPI standard, dual and quad
mode interfaces.

Co-developed-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-03 13:27:56 +08:00
Padmarao Begari
0b8e6f8411 riscv: dts: Add QSPI NAND device node
Add QSPI NAND device node to the Microchip PolarFire SoC
Icicle kit device tree.

The Winbond NAND flash memory can be connected to the
Icicle Kit by using the Mikroe Flash 5 click board and
the Pi 3 Click shield.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-03 13:27:56 +08:00
Padmarao Begari
ab1644bdc4 riscv: dts: Update memory configuration
In the v2022.10 Icicle reference design, the seg registers have been
changed, resulting in a required change to the memory map.
A small 4MB reservation is made at the end of 32-bit DDR to provide some
memory for the HSS to use, so that it can cache its payload between
reboots of a specific context.

Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-03 13:27:56 +08:00
Yu Chien Peter Lin
a5dfa3b8a0 riscv: Rename Andes PLIC to PLICSW
As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-03 13:27:56 +08:00
Stefan Roese
8450b97bf4 mips: mtmips: spl/Kconfig: Set CONFIG_SPL_PAD_TO to 0x0 for ARCH_MTMIPS
It was noticed that while converting CONFIG_SPL_PAD_TO to Kconfig its
value for the MIPS MT762x/8x targets got not ported correctly. Its
default is not 0x10000 instead of 0x0. This patch fixes this issue.

Fixes: ca8a329a1b7f ("Convert CONFIG_SPL_PAD_TO et al to Kconfig")
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Ruben Winters <Ruben.Winters@gooiland-elektro.nl>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2022-11-02 21:54:26 +01:00
Daniel Schwierzeck
a29491ade0 MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig
This converts the following to Kconfig:
    CONFIG_SYS_MIPS_TIMER_REQ

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-02 21:42:32 +01:00
Daniel Schwierzeck
ea24b0eacf MIPS: mscc: remove unused CPU_CLOCK_RATE
CPU_CLOCK_RATE is just used once for CONFIG_SYS_MIPS_TIMER_FREQ
which is migrated to Kconfig in the next patch.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-02 21:42:32 +01:00
Daniel Schwierzeck
e9dcd5b402 MIPS: remove CONFIG_SYS_MHZ
Resolve all uses of CONFIG_SYS_MHZ with the currently defined value.
Remove code which depends on CONFIG_SYS_MHZ but where no board configs
actually use that code.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-02 21:42:32 +01:00
Daniel Schwierzeck
ac14db1ca9 MIPS: remove deprecated TARGET_VCT option
This board has been removed a long time ago.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-02 21:42:32 +01:00
Nylon Chen
3708739ef2 led: led_pwm: typo 'iverted' on code comment
change iverted to inverted.

Signed-off-by: Nylon Chen <nylon.chen@sifive.com>
2022-11-02 13:58:17 -04:00
Cédric Le Goater
0954bc2f89 configs: evb-ast2500: Set environment in SPI flash
We now have a SPI flash driver. Let's use it.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
2022-11-02 13:58:17 -04:00
Cédric Le Goater
18a5db3a81 configs: evb-ast2500: Add support for FIT format
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
2022-11-02 13:58:17 -04:00
Cédric Le Goater
2cede90c4b configs: evb-ast2500: Adjust boot command
Loading a kernel image is enough.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
2022-11-02 13:58:17 -04:00
Cédric Le Goater
60ecf059cc configs: evb-ast2500: Remove MMC support from default settings
This saves ~50K in the resulting u-boot.bin file which is important to
fit in the U-Boot partition defined in the flash layout of upstream Linux.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-11-02 13:58:17 -04:00
Christian Gmeiner
dcbc95c23c arm: dts: ti: k3-am64-main: Add RTI watchdog nodes
Add the needed bus mappings for the two main RTI memory ranges and
the required device tree nodes in the main domain.

Same as kernel commit 6dd8457dc20693e2ba9054c171499b22664fd4e7

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-11-02 13:58:17 -04:00
Bin Meng
ea253ad7b5 treewide: Remove the unnecessary space before semicolon
%s/return ;/return;

Signed-off-by: Bin Meng <bmeng@tinylab.org>
2022-11-02 13:58:17 -04:00
Baruch Siach
aa59c1bec7 cmd: eeprom: don't truncate target address at 32-bit
On 64-bit platforms where int is 32-bit wide, the eeprom command
parse_numeric_param() routine truncates the memory address parameter to
the lower 32-bit. Make parse_numeric_param() return long to allow
read/write of addresses beyond the lower 4GB.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-02 13:58:17 -04:00
Michal Suchanek
0b999d2082 xen: pvblock: Use uclass_probe_all
Also eliminate useless code and variables.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-02 13:58:17 -04:00
Andre Przywara
44b7abf8dc highbank: switch to use the Arm SP804 DM_TIMER driver
So far the Calxeda machines were using the CONFIG_SYS_TIMER_* macros to
simply hardcode the address of the counter register of the SP804 timer.
This method is deprecated and scheduled for removal.

Use the newly introduced SP804 DM_TIMER driver to provide timer
functionality on Highbank and Midway machines. The base address and base
frequency are taken from the devicetree.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-11-02 13:58:17 -04:00
Andre Przywara
4849e2edf4 highbank: scan into hb_sregs DT subnodes
The DT used for Calxeda Highbank and Midway systems exposes a "system
registers" block, modeled as a DT subnode.
This includes several clocks, including the two fixed clocks for the
main oscillator and timer.

So far U-Boot was ignorant of this special construct (a "clocks" node
within the "hb-sregs" node), as it didn't need the PLL clocks in there.
But that also meant we lost the fixed clocks, which form the base for
the UART baudrate generator and also the SP804 timer.

To allow the generic PL011 and SP804 driver to read the clock rate,
add a simple bus driver, which triggers the DT node discovery inside this
special node. As we only care about the fixed clocks (we don't have
drivers for the PLLs anyway), just ignore the address translation (for
now).

The binding is described in bindings/arm/calxeda/hb-sregs.yaml, the DT
snippet in question looks like:

=======================
	sregs@fff3c000 {
		compatible = "calxeda,hb-sregs";
		reg = <0xfff3c000 0x1000>;

		clocks {
			#address-cells = <1>;
			#size-cells = <0>;

			osc: oscillator {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <33333000>;
			};
			....
		};
	};
=======================

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-11-02 13:58:17 -04:00
Andre Przywara
731d108dd0 timer: add SP804 UCLASS timer driver
The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down
timer IP with interrupt functionality, and is used in some SoCs from
various vendors.

Add a simple DM compliant timer driver, to allow users of the SP804 to
switch to DM_TIMER.

This relies on the input clock to be accessible via the DM clock
framework, which should be fine as we probably look at fixed-clock's
here anyway.
We re-program the control register in the probe() function, but keep
the divider in place, in case this has been set to something on purpose
before.

The TRM for the timer IP can be found here:
https://developer.arm.com/documentation/ddi0271/latest

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-11-02 13:58:17 -04:00
Jim Liu
1c1036499f pinctrl: nuvoton: Add NPCM8xx pinctrl driver
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
2022-11-02 13:31:40 -04:00
Andre Przywara
2e32930087 arm: smh: Allow semihosting trap calls to be inlined
Currently our semihosting trap function is somewhat fragile: we rely
on the current compiler behaviour to assign the second inline assembly
argument to the next free register (r1/x1), which happens to be the
"addr" argument to the smh_trap() function (per the calling convention).
I guess this is also the reason for the noinline attribute.

Make it explicit what we want: the "addr" argument needs to go into r1,
so we add another register variable. This allows to drop the "noinline"
attribute, so now the compiler beautifully inlines just the trap
instruction directly into the calling function.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-11-02 13:31:40 -04:00
Andre Przywara
d660a82934 arm: smh: Make semihosting trap calls more robust
Commit f4b540e25c5c("arm: smh: Fix uninitialized parameters with newer
GCCs") added a memory clobber to the semihosting inline assembly trap
calls, to avoid too eager GCC optimisation: when passing a pointer, newer
compilers couldn't be bothered to actually fill in the structure that it
pointed to, as this data would seemingly never be used (at least from the
compiler's point of view).
But instead of the memory clobber we need to tell the compiler that we are
passing an *array* instead of some generic pointer, this forces the
compiler to actually populate the data structure.
This involves some rather hideous cast, which is best hidden in a macro.

But regardless of that, we actually need the memory clobber, but for two
different reasons: explain them in comments.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-11-02 13:31:40 -04:00
Andre Przywara
30b315b48d arm: smh: specify Thumb trap instruction
The ARM semihosting interface uses different trap instructions for
different architectures and instruction sets. So far we were using
AArch64 and ARMv7-M, and had an untested v7-A entry. The latter does
not work when building for Thumb, as can be verified by using
qemu_arm_defconfig, then enabling SEMIHOSTING and SYS_THUMB_BUILD:
==========
{standard input}:35: Error: invalid swi expression
{standard input}:35: Error: value of 1193046 too large for field of 2 bytes at 0
==========

Fix this by providing the recommended instruction[1] for Thumb, and
using the ARM instruction only when not building for Thumb. This also
removes some comment, as QEMU for ARM allows to now test this case.
Also use the opportunity to clean up the inline assembly, and just define
the actual trap instruction inside #ifdef's, to improve readability.

[1] https://developer.arm.com/documentation/dui0471/g/Semihosting/The-semihosting-interface?lang=en

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-11-02 13:31:40 -04:00
Tom Rini
cca41ed3d6 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-watchdog
- cyclic: get rid of (the need for) cyclic_init() (Rasmus)
2022-11-02 09:10:30 -04:00
Tom Rini
ec5b8804de Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi.git
- NPCM PSPI controller (Jim)
2022-11-02 09:09:57 -04:00
Rasmus Villemoes
50128aeb0f cyclic: get rid of cyclic_init()
Currently, we must call cyclic_init() at some point before
cyclic_register() becomes possible. That turns out to be somewhat
awkward, especially with SPL, and has resulted in a watchdog callback
not being registered, thus causing the board to prematurely reset.

We already rely on gd->cyclic reliably being set to NULL by the asm
code that clears all of gd. Now that the cyclic list is a hlist, and
thus an empty list is represented by a NULL head pointer, and struct
cyclic_drv has no other members, we can just as well drop a level of
indirection and put the hlist_head directly in struct
global_data. This doesn't increase the size of struct global_data,
gets rid of an early malloc(), and generates slightly smaller code.

But primarily, this avoids having to call cyclic_init() early; the cyclic
infrastructure is simply ready to register callbacks as soon as we
enter C code.

We can still end up with schedule() being called from asm very early,
so we still need to check that gd itself has been properly initialized
[*], but once it has, gd->cyclic_list is perfectly fine to access, and
will just be an empty list.

As for cyclic_uninit(), it was never really the opposite of
cyclic_init() since it didn't free the struct cyclic_drv nor set
gd->cyclic to NULL. Rename it to cyclic_unregister_all() and use that
in test/, and also insert a call at the end of the board_init_f
sequence so that gd->cyclic_list is a fresh empty list before we enter
board_init_r().

A small piece of ugliness is that I had to add a cast in
cyclic_get_list() to silence a "discards 'volatile' qualifier"
warning, but that is completely equivalent to the existing handling of
the uclass_root_s list_head member.

[*] I'm not really sure where we guarantee that the register used for
gd contains 0 until it gets explicitly initialized, but that must be
the case, otherwise testing gd for being NULL would not make much sense.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
2022-11-02 08:42:03 +01:00
Rasmus Villemoes
2896839483 cyclic: switch to using hlist instead of list
A hlist is headed by just a single pointer, so can only be traversed
forwards, and insertions can only happen at the head (or before/after
an existing list member). But each list node still consists of two
pointers, so arbitrary elements can still be removed in O(1).

This is precisely what we need for the cyclic_list - we never need to
traverse it backwards, and the order the callbacks appear in the list
should really not matter.

One advantage, and the main reason for doing this switch, is that an
empty list is represented by a NULL head pointer, so unlike a
list_head, it does not need separate C code to initialize - a
memset(,0,) of the containing structure is sufficient.

This is mostly mechanical:

- The iterators are updated with an h prefix, and the type of the
  temporary variable changed to struct hlist_node*.

- Adding/removing is now just hlist_add_head (and not tail) and
  hlist_del().

- struct members and function return values updated.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
2022-11-02 08:41:55 +01:00
Rasmus Villemoes
2399b628f4 list.h: synchronize hlist_for_each_entry* iterators with linux
All the way back in 2013, the linux kernel updated the four
hlist_for_each_entry* iterators to require one less auxiliary
variable:

  commit b67bfe0d42cac56c512dd5da4b1b347a23f4b70a
  Author: Sasha Levin <sasha.levin@oracle.com>
  Date:   Wed Feb 27 17:06:00 2013 -0800

      hlist: drop the node parameter from iterators

Currently, there is only one "user" of any of these, namely in
fs/ubifs/super.c, but that actually uses the "new-style" form, and
is (obviously, or it wouldn't have built) inside #ifndef __UBOOT__.

Before adding actual users of these, import the version as of linux
v6.1-rc1, including the hlist_entry_safe() helper used by the new
versions.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
2022-11-02 08:41:49 +01:00
Rasmus Villemoes
6b84b1db2d cyclic: drop redundant cyclic_ready flag
We're already relying on gd->cyclic being NULL before cyclic_init() is
called - i.e., we're relying on all of gd being zeroed before entering
any C code. And when we do populate gd->cyclic, its ->cyclic_ready
member is automatically set to true. So we can actually just rely on
testing gd->cyclic itself.

The only wrinkle is that cyclic_uninit() actually did set
->cyclic_ready to false. However, since it doesn't free gd->cyclic,
the cyclic infrastructure is actually still ready (i.e., the list_head
is properly initialized as an empty list).

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
2022-11-02 08:41:42 +01:00
Rasmus Villemoes
d7de5ef629 cyclic: use a flag in gd->flags for recursion protection
As a preparation for future patches, use a flag in gd->flags rather
than a separate member in (the singleton) struct cyclic_drv to keep
track of whether we're already inside cyclic_run().

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
2022-11-02 08:41:20 +01:00
Tom Rini
c8d9ff634f Merge branch '2022-10-31-FWU-add-FWU-multi-bank-update-feature-support'
To quote the author:
The patchset adds support for the FWU Multi Bank Update[1]
feature. Certain aspects of the Dependable Boot[2] specification have
also been implemented.

The FWU multi bank update feature is used for supporting multiple
sets(also called banks) of firmware image(s), allowing the platform to
boot from a different bank, in case it fails to boot from the active
bank. This functionality is supported by keeping the relevant
information in a structure called metadata, which provides information
on the images. Among other parameters, the metadata structure contains
information on the currect active bank that is being used to boot
image(s).

Functionality is being added to work with the UEFI capsule driver in
u-boot. The metadata is read to gather information on the update bank,
which is the bank to which the firmware images would be flashed to. On
a successful completion of the update of all components, the active
bank field in the metadata is updated, to reflect the bank from which
the platform will boot on the subsequent boots.

Currently, the feature is being enabled on the STM32MP157C-DK2 and
Synquacer boards. The DK2 board boots a FIP image from a uSD card
partitioned with the GPT partioning scheme, while the Synquacer board
boots a FIP image from a MTD partitioned SPI NOR flash device.

This feature also requires changes in a previous stage of
bootloader, which parses the metadata and selects the bank to boot the
image(s) from. Support has being added in tf-a(BL2 stage) for the
STM32MP157C-DK2 board to boot the active bank images. These changes
have been merged to the upstream tf-a repository.

The patch for adding a python test for the feature has been developed,
and was sent in the version 5 of the patches[3]. However, the test
script depends on adding support for the feature on MTD SPI NOR
devices, and that is being done as part of the Synquacer
patches. Hence these set of patches do not have the test script for
the feature. That will be added through the patches for adding support
for the feauture on Synquacer platform.

[1] - https://developer.arm.com/documentation/den0118/a
[2] - https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24e18d4319e108a758d02e/mbfw.pdf
[3] - https://lists.denx.de/pipermail/u-boot/2022-June/485992.html
2022-11-01 09:32:21 -04:00
Sughosh Ganu
75f11c3bfd FWU: doc: Add documentation for the FWU feature
Add documentation for the FWU Multi Bank Update feature. The document
describes the steps needed for setting up the platform for the
feature, as well as steps for enabling the feature on the platform.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-10-31 14:47:33 -04:00
Sughosh Ganu
f65ee99b9d mkeficapsule: Add support for setting OEM flags in capsule header
Add support for setting OEM flags in the capsule header. As per the
UEFI specification, bits 0-15 of the flags member of the capsule
header can be defined per capsule GUID.

The oemflags will be used for the FWU Multi Bank update feature, as
specified by the Dependable Boot specification[1]. Bit
15 of the flags member will be used to determine if the
acceptance/rejection of the updated images is to be done by the
firmware or an external component like the OS.

[1] - https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24e18d4319e108a758d02e/mbfw.pdf

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-10-31 14:47:33 -04:00
Sughosh Ganu
6da9271af1 mkeficapsule: Add support for generating empty capsules
The Dependable Boot specification[1] describes the structure of the
firmware accept and revert capsules. These are empty capsules which
are used for signalling the acceptance or rejection of the updated
firmware by the OS. Add support for generating these empty capsules.

[1] - https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24e18d4319e108a758d02e/mbfw.pdf

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-10-31 14:47:33 -04:00
Sughosh Ganu
873cf8ac70 test: dm: Add test cases for FWU Metadata uclass
Add test cases for accessing the FWU Metadata on the sandbox
platform. The sandbox platform also uses the metadata access driver
for GPT partitioned block devices.

The FWU feature will be tested on the sandbox64 variant with a raw
capsule. Remove the FIT capsule testing from sandbox64 defconfig --
the FIT capsule test will be run on the sandbox_flattree variant.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-10-31 14:47:33 -04:00
Sughosh Ganu
e68c03be46 FWU: cmd: Add a command to read FWU metadata
Add a command to read the metadata as specified in the FWU
specification and print the fields of the metadata.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-10-31 14:47:33 -04:00
Sughosh Ganu
8679405241 FWU: Add support for the FWU Multi Bank Update feature
The FWU Multi Bank Update feature supports updating firmware images
to one of multiple sets(also called banks) of images. The firmware
images are clubbed together in banks, with the system booting images
from the active bank. Information on the images such as which bank
they belong to is stored as part of the metadata structure, which is
stored on the same storage media as the firmware images on a dedicated
partition.

At the time of update, the metadata is read to identify the bank to
which the images need to be flashed(update bank). On a successful
update, the metadata is modified to set the updated bank as active
bank to subsequently boot from.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-10-31 14:47:32 -04:00
Sughosh Ganu
7e9814cc6c FWU: Add boot time checks as highlighted by the FWU specification
The FWU Multi Bank Update specification requires the Update Agent to
carry out certain checks at the time of platform boot. The Update
Agent is the component which is responsible for updating the firmware
components and maintaining and keeping the metadata in sync.

The spec requires that the Update Agent perform the following checks
at the time of boot
* Sanity check of both the metadata copies maintained by the platform.
* Get the boot index passed to U-Boot by the prior stage bootloader
  and use this value for metadata bookkeeping.
* Check if the system is booting in Trial State. If the system boots
  in the Trial State for more than a specified number of boot counts,
  change the Active Bank to be booting the platform from.

Call these checks through the main loop event at the time of platform
boot.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-10-31 14:47:32 -04:00
Sughosh Ganu
467bad5e36 event: Add an event for main_loop
Add an event type EVT_MAIN_LOOP that can be used for registering
events that need to be run after the platform has been initialised and
before the main_loop function is called.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-10-31 14:47:32 -04:00
Sughosh Ganu
95b5a7de30 FWU: STM32MP1: Add support to read boot index from backup register
The FWU Multi Bank Update feature allows the platform to boot the
firmware images from one of the partitions(banks). The first stage
bootloader(fsbl) passes the value of the boot index, i.e. the bank
from which the firmware images were booted from to U-Boot. On the
STM32MP157C-DK2 board, this value is passed through one of the SoC's
backup register. Add a function to read the boot index value from the
backup register.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-10-31 14:47:32 -04:00
Sughosh Ganu
7d6e2c54b7 FWU: Add helper functions for accessing FWU metadata
Add weak functions for getting the update index value and dfu
alternate number needed for FWU Multi Bank update
functionality.

The current implementation for getting the update index value is for
platforms with 2 banks. If a platform supports more than 2 banks, it
can implement it's own function. The function to get the dfu alternate
number has been added for platforms with GPT partitioned storage
devices. Platforms with other storage partition scheme need to
implement their own function.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-10-31 14:47:32 -04:00
Sughosh Ganu
d70c4a0a20 stm32mp1: Add image information for capsule updates
Enabling capsule update functionality on the platform requires
populating information on the images that are to be updated using the
functionality. Do so for the DK2 board.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-10-31 14:47:32 -04:00
Sughosh Ganu
a402adc664 stm32mp1: Add a node for the FWU metadata device
The FWU metadata structure is accessed through the driver model
interface. On the stm32mp157c dk2 and ev1 boards, the FWU metadata is
stored on the uSD card. Add the fwu-mdata node on the u-boot specifc
dtsi file for accessing the metadata structure.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-10-31 14:47:32 -04:00
Sughosh Ganu
554b38f7a5 FWU: Add FWU metadata access driver for GPT partitioned block devices
In the FWU Multi Bank Update feature, the information about the
updatable images is stored as part of the metadata, on a separate
partition. Add a driver for reading from and writing to the metadata
when the updatable images and the metadata are stored on a block
device which is formatted with GPT based partition scheme.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-10-31 14:47:32 -04:00
Sughosh Ganu
2eaedc9516 FWU: Add FWU metadata structure and driver for accessing metadata
In the FWU Multi Bank Update feature, the information about the
updatable images is stored as part of the metadata, which is stored on
a dedicated partition. Add the metadata structure, and a driver model
uclass which provides functions to access the metadata. These are
generic API's, and implementations can be added based on parameters
like how the metadata partition is accessed and what type of storage
device houses the metadata.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-10-31 14:47:32 -04:00
Sughosh Ganu
73981390df dt/bindings: Add bindings for GPT based FWU Metadata storage device
Add bindings needed for accessing the FWU metadata partitions. These
include the compatible string which point to the access method and the
actual device which stores the FWU metadata.

The current patch adds basic bindings needed for accessing the
metadata structure on GPT partitioned block devices.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-10-31 14:47:32 -04:00
Jim Liu
c1dc8473fa spi: nuvoton: add NPCM PSPI controller driver
Add Nuvoton NPCM BMC Peripheral SPI controller driver.
NPCM750 include two general-purpose SPI interface.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-10-27 12:41:36 +05:30
3790 changed files with 156400 additions and 47736 deletions

View File

@ -2,7 +2,7 @@ variables:
windows_vm: windows-2019 windows_vm: windows-2019
ubuntu_vm: ubuntu-22.04 ubuntu_vm: ubuntu-22.04
macos_vm: macOS-12 macos_vm: macOS-12
ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20221003-17Oct2022 ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20221130-11Jan2023
# Add '-u 0' options for Azure pipelines, otherwise we get "permission # Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root. # since our $(ci_runner_image) user is not root.
@ -30,7 +30,7 @@ stages:
%CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel" %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel"
displayName: 'Install Toolchain' displayName: 'Install Toolchain'
- script: | - script: |
echo make tools-only_defconfig tools-only NO_SDL=1 > build-tools.sh echo make tools-only_defconfig tools-only > build-tools.sh
%CD:~0,2%\msys64\usr\bin\bash -lc "bash build-tools.sh" %CD:~0,2%\msys64\usr\bin\bash -lc "bash build-tools.sh"
displayName: 'Build Host Tools' displayName: 'Build Host Tools'
env: env:
@ -47,43 +47,24 @@ stages:
- script: brew install make ossp-uuid - script: brew install make ossp-uuid
displayName: Brew install dependencies displayName: Brew install dependencies
- script: | - script: |
gmake tools-only_config tools-only NO_SDL=1 \ gmake tools-only_config tools-only \
HOSTCFLAGS="-I/usr/local/opt/openssl@1.1/include" \ HOSTCFLAGS="-I/usr/local/opt/openssl@1.1/include" \
HOSTLDFLAGS="-L/usr/local/opt/openssl@1.1/lib" \ HOSTLDFLAGS="-L/usr/local/opt/openssl@1.1/lib" \
-j$(sysctl -n hw.logicalcpu) -j$(sysctl -n hw.logicalcpu)
displayName: 'Perform tools-only build' displayName: 'Perform tools-only build'
- job: check_for_migrated_symbols_in_board_header - job: check_for_new_CONFIG_symbols_outside_Kconfig
displayName: 'Check for migrated symbols in board header' displayName: 'Check for new CONFIG symbols outside Kconfig'
pool: pool:
vmImage: $(ubuntu_vm) vmImage: $(ubuntu_vm)
container: container:
image: $(ci_runner_image) image: $(ci_runner_image)
options: $(container_option) options: $(container_option)
steps: steps:
- script: | # If grep succeeds and finds a match the test fails as we should
KSYMLST=`mktemp` # have no matches.
KUSEDLST=`mktemp` - script: git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
RET=0 include/configs `find arch -name config.h` && exit 1 || exit 0
cat `find . -name "Kconfig*"` | \
sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
| sort -u > $KSYMLST
for CFG in `find include/configs -name "*.h"`; do
(grep '#define[[:blank:]]CONFIG_' $CFG | \
sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' ; \
grep '#undef[[:blank:]]CONFIG_' $CFG | \
sed -n 's/#undef.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p') | \
sort -u > ${KUSEDLST} || true
NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} | \
cut -d , -f 3`
if [[ $NUM -ne 0 ]]; then
echo "Unmigrated symbols found in $CFG:"
comm -12 ${KSYMLST} ${KUSEDLST}
RET=1
fi
done
exit $RET
- job: cppcheck - job: cppcheck
displayName: 'Static code analysis with cppcheck' displayName: 'Static code analysis with cppcheck'
@ -95,8 +76,8 @@ stages:
steps: steps:
- script: cppcheck -j$(nproc) --force --quiet --inline-suppr . - script: cppcheck -j$(nproc) --force --quiet --inline-suppr .
- job: htmldocs - job: docs
displayName: 'Build HTML documentation' displayName: 'Build documentation'
pool: pool:
vmImage: $(ubuntu_vm) vmImage: $(ubuntu_vm)
container: container:
@ -108,6 +89,7 @@ stages:
. /tmp/venvhtml/bin/activate . /tmp/venvhtml/bin/activate
pip install -r doc/sphinx/requirements.txt pip install -r doc/sphinx/requirements.txt
make htmldocs make htmldocs
make infodocs
- job: todo - job: todo
displayName: 'Search for TODO within source tree' displayName: 'Search for TODO within source tree'
@ -204,7 +186,7 @@ stages:
options: $(container_option) options: $(container_option)
steps: steps:
- script: | - script: |
export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH export PATH=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin:$PATH
test/nokia_rx51_test.sh test/nokia_rx51_test.sh
- job: pylint - job: pylint
@ -242,7 +224,7 @@ stages:
TEST_PY_BD: "sandbox" TEST_PY_BD: "sandbox"
sandbox_clang: sandbox_clang:
TEST_PY_BD: "sandbox" TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-13" OVERRIDE: "-O clang-14"
sandbox_nolto: sandbox_nolto:
TEST_PY_BD: "sandbox" TEST_PY_BD: "sandbox"
BUILD_ENV: "NO_LTO=1" BUILD_ENV: "NO_LTO=1"
@ -362,6 +344,7 @@ stages:
cat << "EOF" >> test.sh cat << "EOF" >> test.sh
# the below corresponds to .gitlab-ci.yml "before_script" # the below corresponds to .gitlab-ci.yml "before_script"
cd ${WORK_DIR} cd ${WORK_DIR}
git config --global --add safe.directory ${WORK_DIR}
git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname` ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname` ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
@ -446,6 +429,8 @@ stages:
matrix: matrix:
arc_microblaze_xtensa: arc_microblaze_xtensa:
BUILDMAN: "arc microblaze xtensa" BUILDMAN: "arc microblaze xtensa"
amlogic:
BUILDMAN: "amlogic"
arm11_arm7_arm920t_arm946es: arm11_arm7_arm920t_arm946es:
BUILDMAN: "arm11 arm7 arm920t arm946es" BUILDMAN: "arm11 arm7 arm920t arm946es"
arm926ejs: arm926ejs:
@ -475,9 +460,9 @@ stages:
imx6: imx6:
BUILDMAN: "mx6 -x boundary,engicam,freescale,technexion,toradex" BUILDMAN: "mx6 -x boundary,engicam,freescale,technexion,toradex"
imx: imx:
BUILDMAN: "mx -x mx6,freescale,technexion,toradex" BUILDMAN: "mx -x mx6,imx8,freescale,technexion,toradex"
imx8: imx8_imx9:
BUILDMAN: "imx8" BUILDMAN: "imx8 imx9"
keystone2_keystone3: keystone2_keystone3:
BUILDMAN: "k2 k3" BUILDMAN: "k2 k3"
sandbox_asan: sandbox_asan:
@ -485,7 +470,7 @@ stages:
OVERRIDE: "-a ASAN" OVERRIDE: "-a ASAN"
sandbox_clang_asan: sandbox_clang_asan:
BUILDMAN: "sandbox" BUILDMAN: "sandbox"
OVERRIDE: "-O clang-13 -a ASAN" OVERRIDE: "-O clang-14 -a ASAN"
samsung_socfpga: samsung_socfpga:
BUILDMAN: "samsung socfpga" BUILDMAN: "samsung socfpga"
sun4i: sun4i:
@ -531,9 +516,11 @@ stages:
uniphier: uniphier:
BUILDMAN: "uniphier" BUILDMAN: "uniphier"
aarch64_catch_all: aarch64_catch_all:
BUILDMAN: "aarch64 -x bcm,imx8,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,renesas,sunxi,samsung,socfpga,rk,versal,zynq" BUILDMAN: "aarch64 -x amlogic,bcm,imx8,imx9,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,renesas,sunxi,samsung,socfpga,rk,versal,zynq"
rockchip: rockchip_32bit:
BUILDMAN: "rk" BUILDMAN: "rk -x aarch64"
rockchip_64bit:
BUILDMAN: "rk&aarch64"
renesas: renesas:
BUILDMAN: "renesas" BUILDMAN: "renesas"
zynq: zynq:
@ -549,11 +536,12 @@ stages:
cd ${WORK_DIR} cd ${WORK_DIR}
# make environment variables available as tests are running inside a container # make environment variables available as tests are running inside a container
export BUILDMAN="${BUILDMAN}" export BUILDMAN="${BUILDMAN}"
git config --global --add safe.directory ${WORK_DIR}
EOF EOF
cat << "EOF" >> build.sh cat << "EOF" >> build.sh
if [[ "${BUILDMAN}" != "" ]]; then if [[ "${BUILDMAN}" != "" ]]; then
ret=0; ret=0;
tools/buildman/buildman -o /tmp -P -E -W ${BUILDMAN} ${OVERRIDE} || ret=$?; tools/buildman/buildman -o /tmp -PEWM ${BUILDMAN} ${OVERRIDE} || ret=$?;
if [[ $ret -ne 0 ]]; then if [[ $ret -ne 0 ]]; then
tools/buildman/buildman -o /tmp -seP ${BUILDMAN}; tools/buildman/buildman -o /tmp -seP ${BUILDMAN};
exit $ret; exit $ret;

View File

@ -4,7 +4,7 @@
# Temporary for false positive in checkpatch # Temporary for false positive in checkpatch
--ignore COMPLEX_MACRO --ignore COMPLEX_MACRO
# For CONFIG_SYS_I2C_NOPROBES # For CFG_SYS_I2C_NOPROBES
--ignore MULTISTATEMENT_MACRO_USE_DO_WHILE --ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
# For simple_strtoul # For simple_strtoul

View File

@ -2,7 +2,7 @@
# Grab our configured image. The source for this is found # Grab our configured image. The source for this is found
# in the u-boot tree at tools/docker/Dockerfile # in the u-boot tree at tools/docker/Dockerfile
image: trini/u-boot-gitlab-ci-runner:jammy-20221003-17Oct2022 image: trini/u-boot-gitlab-ci-runner:jammy-20221130-11Jan2023
# We run some tests in different order, to catch some failures quicker. # We run some tests in different order, to catch some failures quicker.
stages: stages:
@ -14,6 +14,7 @@ stages:
stage: test.py stage: test.py
before_script: before_script:
# Clone uboot-test-hooks # Clone uboot-test-hooks
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
- git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks - git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
- ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname` - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname` - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
@ -81,7 +82,8 @@ build all 32bit ARM platforms:
stage: world build stage: world build
script: script:
- ret=0; - ret=0;
./tools/buildman/buildman -o /tmp -P -E -W arm -x aarch64 || ret=$?; git config --global --add safe.directory "${CI_PROJECT_DIR}";
./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 || ret=$?;
if [[ $ret -ne 0 ]]; then if [[ $ret -ne 0 ]]; then
./tools/buildman/buildman -o /tmp -seP; ./tools/buildman/buildman -o /tmp -seP;
exit $ret; exit $ret;
@ -93,7 +95,8 @@ build all 64bit ARM platforms:
- virtualenv -p /usr/bin/python3 /tmp/venv - virtualenv -p /usr/bin/python3 /tmp/venv
- . /tmp/venv/bin/activate - . /tmp/venv/bin/activate
- ret=0; - ret=0;
./tools/buildman/buildman -o /tmp -P -E -W aarch64 || ret=$?; git config --global --add safe.directory "${CI_PROJECT_DIR}";
./tools/buildman/buildman -o /tmp -PEWM aarch64 || ret=$?;
if [[ $ret -ne 0 ]]; then if [[ $ret -ne 0 ]]; then
./tools/buildman/buildman -o /tmp -seP; ./tools/buildman/buildman -o /tmp -seP;
exit $ret; exit $ret;
@ -103,6 +106,7 @@ build all PowerPC platforms:
stage: world build stage: world build
script: script:
- ret=0; - ret=0;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
./tools/buildman/buildman -o /tmp -P -E -W powerpc || ret=$?; ./tools/buildman/buildman -o /tmp -P -E -W powerpc || ret=$?;
if [[ $ret -ne 0 ]]; then if [[ $ret -ne 0 ]]; then
./tools/buildman/buildman -o /tmp -seP; ./tools/buildman/buildman -o /tmp -seP;
@ -113,37 +117,21 @@ build all other platforms:
stage: world build stage: world build
script: script:
- ret=0; - ret=0;
./tools/buildman/buildman -o /tmp -P -E -W -x arm,powerpc || ret=$?; git config --global --add safe.directory "${CI_PROJECT_DIR}";
./tools/buildman/buildman -o /tmp -PEWM -x arm,powerpc || ret=$?;
if [[ $ret -ne 0 ]]; then if [[ $ret -ne 0 ]]; then
./tools/buildman/buildman -o /tmp -seP; ./tools/buildman/buildman -o /tmp -seP;
exit $ret; exit $ret;
fi; fi;
check for migrated symbols in board header: check for new CONFIG symbols outside Kconfig:
stage: testsuites stage: testsuites
script: script:
- KSYMLST=`mktemp`; - git config --global --add safe.directory "${CI_PROJECT_DIR}"
KUSEDLST=`mktemp`; # If grep succeeds and finds a match the test fails as we should
RET=0; # have no matches.
cat `find . -name "Kconfig*"` | - git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' include/configs `find arch -name config.h` && exit 1 || exit 0
-e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
| sort -u > $KSYMLST;
for CFG in `find include/configs -name "*.h"`; do
(grep '#define[[:blank:]]CONFIG_' $CFG |
sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' ;
grep '#undef[[:blank:]]CONFIG_' $CFG |
sed -n 's/#undef.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p') |
sort -u > ${KUSEDLST} || true;
NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} |
cut -d , -f 3`;
if [[ $NUM -ne 0 ]]; then
echo "Unmigrated symbols found in $CFG:";
comm -12 ${KSYMLST} ${KUSEDLST};
RET=1;
fi;
done;
exit $RET
# QA jobs for code analytics # QA jobs for code analytics
# static code analysis with cppcheck (we can add --enable=all later) # static code analysis with cppcheck (we can add --enable=all later)
@ -161,14 +149,15 @@ grep TODO/FIXME/HACK:
# search for HACK within source tree and ignore HACKKIT board # search for HACK within source tree and ignore HACKKIT board
- grep -r HACK . | grep -v HACKKIT - grep -r HACK . | grep -v HACKKIT
# build HTML documentation # build documentation
htmldocs: docs:
stage: testsuites stage: testsuites
script: script:
- virtualenv -p /usr/bin/python3 /tmp/venvhtml - virtualenv -p /usr/bin/python3 /tmp/venvhtml
- . /tmp/venvhtml/bin/activate - . /tmp/venvhtml/bin/activate
- pip install -r doc/sphinx/requirements.txt - pip install -r doc/sphinx/requirements.txt
- make htmldocs - make htmldocs
- make infodocs
# some statistics about the code base # some statistics about the code base
sloccount: sloccount:
@ -220,7 +209,7 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites:
Run tests for Nokia RX-51 (aka N900): Run tests for Nokia RX-51 (aka N900):
stage: testsuites stage: testsuites
script: script:
- export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH; - export PATH=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin:$PATH;
test/nokia_rx51_test.sh test/nokia_rx51_test.sh
# Check for any pylint regressions # Check for any pylint regressions
@ -251,7 +240,7 @@ sandbox test.py:
sandbox with clang test.py: sandbox with clang test.py:
variables: variables:
TEST_PY_BD: "sandbox" TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-13" OVERRIDE: "-O clang-14"
<<: *buildman_and_testpy_dfn <<: *buildman_and_testpy_dfn
sandbox without LTO test.py: sandbox without LTO test.py:

28
Kconfig
View File

@ -264,8 +264,8 @@ config HAS_CUSTOM_SYS_INIT_SP_ADDR
default y if TFABOOT default y if TFABOOT
help help
Typically, we use an initial stack pointer address that is calculated Typically, we use an initial stack pointer address that is calculated
by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the by taking the statically defined CFG_SYS_INIT_RAM_ADDR, adding the
statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the statically defined CFG_SYS_INIT_RAM_SIZE and then subtracting the
build-time constant of GENERATED_GBL_DATA_SIZE. On MIPS a different build-time constant of GENERATED_GBL_DATA_SIZE. On MIPS a different
but statica calculation is performed. However, some platforms will but statica calculation is performed. However, some platforms will
take a different approach. Say Y here to define the address statically take a different approach. Say Y here to define the address statically
@ -333,7 +333,7 @@ config SPL_SYS_MALLOC_F_LEN
particular needs this to operate, so that it can allocate the particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed. initial serial device and any others that are needed.
It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new It is possible to enable CFG_SYS_SPL_MALLOC_START to start a new
malloc() region in SDRAM once it is inited. malloc() region in SDRAM once it is inited.
config TPL_SYS_MALLOC_F_LEN config TPL_SYS_MALLOC_F_LEN
@ -456,11 +456,12 @@ config BUILD_TARGET
string "Build target special images" string "Build target special images"
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10 default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5 default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL default "u-boot-with-spl.kwb" if ARMADA_32BIT && SPL
default "u-boot-elf.srec" if RCAR_GEN3 default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \ default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
RISCV || ARCH_ZYNQMP) ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
default "u-boot.kwb" if ARCH_KIRKWOOD default "u-boot.kwb" if (ARCH_KIRKWOOD || ARMADA_32BIT) && !SPL
default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "u-boot-with-spl.imx" if ARCH_MX6 && SPL default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
help help
@ -508,6 +509,9 @@ config SYS_LOAD_ADDR
hex "Address in memory to use by default" hex "Address in memory to use by default"
default 0x01000000 if ARCH_SOCFPGA default 0x01000000 if ARCH_SOCFPGA
default 0x02000000 if PPC || X86 default 0x02000000 if PPC || X86
default 0x81000000 if MACH_SUNIV
default 0x22000000 if MACH_SUN9I
default 0x42000000 if ARCH_SUNXI
default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3 default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL) default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL)
default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL) default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL)
@ -580,6 +584,18 @@ config SYS_SRAM_SIZE
default 0x10000 if TARGET_TRICORDER default 0x10000 if TARGET_TRICORDER
default 0x0 default 0x0
config SYS_MONITOR_LEN
int "Maximum size in bytes reserved for U-Boot in memory"
default 1048576 if X86
default 786432 if ARCH_SUNXI
default 0
help
Size of memory reserved for monitor code, used to determine
_at_compile_time_ (!) if the environment is embedded within the
U-Boot image, or in a separate flash sector, among other uses where
we need to set a maximum size of the U-Boot binary itself that will
be loaded.
config MP config MP
bool "Support for multiprocessor" bool "Support for multiprocessor"
help help

View File

@ -192,6 +192,7 @@ N: aspeed
ARM BROADCOM BCM283X / BCM27XX ARM BROADCOM BCM283X / BCM27XX
M: Matthias Brugger <mbrugger@suse.com> M: Matthias Brugger <mbrugger@suse.com>
M: Peter Robinson <pbrobinson@gmail.com>
S: Maintained S: Maintained
F: arch/arm/dts/bcm283* F: arch/arm/dts/bcm283*
F: arch/arm/mach-bcm283x/ F: arch/arm/mach-bcm283x/
@ -408,11 +409,21 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-atmel.git
F: arch/arm/mach-at91/ F: arch/arm/mach-at91/
F: board/atmel/ F: board/atmel/
F: drivers/cpu/at91_cpu.c F: drivers/cpu/at91_cpu.c
F: drivers/memory/atmel-ebi.c
F: drivers/misc/microchip_flexcom.c F: drivers/misc/microchip_flexcom.c
F: drivers/timer/atmel_tcb_timer.c F: drivers/timer/atmel_tcb_timer.c
F: include/dt-bindings/mfd/atmel-flexcom.h F: include/dt-bindings/mfd/atmel-flexcom.h
F: drivers/timer/mchp-pit64b-timer.c F: drivers/timer/mchp-pit64b-timer.c
ARM MSC SM2S IMX8MP SOM
M: Martyn Welch <martyn.welch@collabora.com>
M: Ian Ray <ian.ray@ge.com>
S: Maintained
F: arch/arm/dts/imx8mp-msc-sm2s*
F: board/msc/sm2s_imx8mp/
F: configs/msc_sm2s_imx8mp_defconfig
F: include/configs/msc_sm2s_imx8mp.h
ARM NEXELL S5P4418 ARM NEXELL S5P4418
M: Stefan Bosch <stefan_b@posteo.net> M: Stefan Bosch <stefan_b@posteo.net>
S: Maintained S: Maintained
@ -426,6 +437,7 @@ F: drivers/gpio/nx_gpio.c
F: drivers/i2c/nx_i2c.c F: drivers/i2c/nx_i2c.c
F: drivers/mmc/nexell_dw_mmc_dm.c F: drivers/mmc/nexell_dw_mmc_dm.c
F: drivers/pinctrl/nexell/ F: drivers/pinctrl/nexell/
F: drivers/serial/serial_s5p4418_pl011.c
F: drivers/video/nexell/ F: drivers/video/nexell/
F: drivers/video/nexell_display.c F: drivers/video/nexell_display.c
F: include/configs/s5p4418_nanopi2.h F: include/configs/s5p4418_nanopi2.h
@ -485,6 +497,12 @@ F: arch/arm/mach-exynos/
F: arch/arm/mach-s5pc1xx/ F: arch/arm/mach-s5pc1xx/
F: arch/arm/cpu/armv7/s5p-common/ F: arch/arm/cpu/armv7/s5p-common/
ARM SANCLOUD
M: Paul Barker <paul.barker@sancloud.com>
R: Marc Murphy <marc.murphy@sancloud.com>
S: Supported
F: arch/arm/dts/am335x-sancloud*
ARM SNAPDRAGON ARM SNAPDRAGON
M: Ramon Fried <rfried.dev@gmail.com> M: Ramon Fried <rfried.dev@gmail.com>
S: Maintained S: Maintained
@ -552,10 +570,9 @@ F: drivers/spi/stm32_spi.c
F: drivers/video/stm32/stm32_ltdc.c F: drivers/video/stm32/stm32_ltdc.c
F: drivers/watchdog/stm32mp_wdt.c F: drivers/watchdog/stm32mp_wdt.c
F: include/dt-bindings/clock/stm32fx-clock.h F: include/dt-bindings/clock/stm32fx-clock.h
F: include/dt-bindings/clock/stm32mp1-clks.h F: include/dt-bindings/clock/stm32mp*
F: include/dt-bindings/clock/stm32mp1-clksrc.h
F: include/dt-bindings/pinctrl/stm32-pinfunc.h F: include/dt-bindings/pinctrl/stm32-pinfunc.h
F: include/dt-bindings/reset/stm32mp1-resets.h F: include/dt-bindings/reset/stm32mp*
F: include/stm32_rcc.h F: include/stm32_rcc.h
F: tools/stm32image.c F: tools/stm32image.c
N: stm N: stm
@ -655,6 +672,7 @@ M: Michal Simek <michal.simek@amd.com>
S: Maintained S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-versal-net/ F: arch/arm/mach-versal-net/
F: drivers/soc/soc_xilinx_versal_net.c
N: (?<!uni)versal-net N: (?<!uni)versal-net
ARM VERSAL ARM VERSAL
@ -844,7 +862,6 @@ F: cmd/dfu.c
F: cmd/usb_*.c F: cmd/usb_*.c
F: common/dfu.c F: common/dfu.c
F: common/update.c F: common/update.c
F: common/usb_storage.c
F: doc/api/dfu.rst F: doc/api/dfu.rst
F: doc/usage/dfu.rst F: doc/usage/dfu.rst
F: drivers/dfu/ F: drivers/dfu/
@ -879,6 +896,11 @@ M: Heinrich Schuchardt <xypron.glpk@gmx.de>
M: Ilias Apalodimas <ilias.apalodimas@linaro.org> M: Ilias Apalodimas <ilias.apalodimas@linaro.org>
S: Maintained S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-efi.git T: git https://source.denx.de/u-boot/custodians/u-boot-efi.git
F: arch/arm/lib/*_efi.*
F: cmd/bootefi.c
F: cmd/eficonfig.c
F: cmd/efidebug.c
F: cmd/nvedit_efi.c
F: doc/api/efi.rst F: doc/api/efi.rst
F: doc/develop/uefi/* F: doc/develop/uefi/*
F: doc/mkeficapsule.1 F: doc/mkeficapsule.1
@ -1176,6 +1198,7 @@ M: Sean Anderson <seanga2@gmail.com>
S: Maintained S: Maintained
F: doc/api/nvmem.rst F: doc/api/nvmem.rst
F: drivers/misc/nvmem.c F: drivers/misc/nvmem.c
F: drivers/reboot-mode/reboot-mode-nvmem.c
F: include/nvmem.h F: include/nvmem.h
NXP C45 TJA11XX PHY DRIVER NXP C45 TJA11XX PHY DRIVER
@ -1467,6 +1490,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-usb.git
F: drivers/usb/ F: drivers/usb/
F: common/usb.c F: common/usb.c
F: common/usb_kbd.c F: common/usb_kbd.c
F: common/usb_storage.c
F: include/usb.h F: include/usb.h
USB xHCI USB xHCI

View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+ # SPDX-License-Identifier: GPL-2.0+
VERSION = 2022 VERSION = 2023
PATCHLEVEL = 10 PATCHLEVEL = 01
SUBLEVEL = SUBLEVEL =
EXTRAVERSION = EXTRAVERSION =
NAME = NAME =
@ -761,10 +761,10 @@ KBUILD_CFLAGS += $(call cc-disable-warning, maybe-uninitialized)
# change __FILE__ to the relative path from the srctree # change __FILE__ to the relative path from the srctree
KBUILD_CFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=) KBUILD_CFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
KBUILD_CFLAGS += -g KBUILD_CFLAGS += -gdwarf-4
# $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format> # $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
# option to the assembler. # option to the assembler.
KBUILD_AFLAGS += -g KBUILD_AFLAGS += -gdwarf-4
# Report stack usage if supported # Report stack usage if supported
# ARC tools based on GCC 7.1 has an issue with stack usage # ARC tools based on GCC 7.1 has an issue with stack usage
@ -806,6 +806,8 @@ KBUILD_CPPFLAGS += $(KCPPFLAGS)
KBUILD_AFLAGS += $(KAFLAGS) KBUILD_AFLAGS += $(KAFLAGS)
KBUILD_CFLAGS += $(KCFLAGS) KBUILD_CFLAGS += $(KCFLAGS)
KBUILD_LDFLAGS += $(call ld-option,--no-warn-rwx-segments)
KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g) KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g)
# Use UBOOTINCLUDE when you must reference the include/ directory. # Use UBOOTINCLUDE when you must reference the include/ directory.
@ -1013,23 +1015,6 @@ INPUTS-y += u-boot.img
endif endif
endif endif
ifeq ($(CONFIG_MACH_SUN8I_H3)$(CONFIG_ARMV7_PSCI),yy)
INPUTS-$(CONFIG_ARMV7_PSCI) += u-boot-resume.img
MKIMAGEFLAGS_u-boot-resume.img := -B 0x400 -T sunxi_egon
u-boot-resume.img: u-boot-resume.bin
$(call if_changed,mkimage)
OBJCOPYFLAGS_u-boot-resume.bin := -O binary
u-boot-resume.bin: u-boot-resume.o
$(call if_changed,objcopy)
u-boot-resume.S: u-boot
@sed -En 's/(0x[[:xdigit:]]+) +psci_cpu_entry/ldr pc, =\1/p' $<.map > $@
endif
INPUTS-$(CONFIG_X86) += u-boot-x86-start16.bin u-boot-x86-reset16.bin \ INPUTS-$(CONFIG_X86) += u-boot-x86-start16.bin u-boot-x86-reset16.bin \
$(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \ $(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
$(if $(CONFIG_TPL_X86_16BIT_INIT),tpl/u-boot-tpl.bin) $(if $(CONFIG_TPL_X86_16BIT_INIT),tpl/u-boot-tpl.bin)
@ -1090,10 +1075,6 @@ cmd_lzma = lzma -c -z -k -9 $< > $@
cfg: u-boot.cfg cfg: u-boot.cfg
quiet_cmd_cfgcheck = CFGCHK $2
cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
$(srctree)/scripts/config_whitelist.txt $(srctree)
quiet_cmd_ofcheck = OFCHK $2 quiet_cmd_ofcheck = OFCHK $2
cmd_ofcheck = $(srctree)/scripts/check-of.sh $2 \ cmd_ofcheck = $(srctree)/scripts/check-of.sh $2 \
$(srctree)/scripts/of_allowlist.txt $(srctree)/scripts/of_allowlist.txt
@ -1125,18 +1106,15 @@ define deprecated
endef endef
PHONY += inputs # Timestamp file to make sure that binman always runs
inputs: $(INPUTS-y) .binman_stamp: $(INPUTS-y) FORCE
all: .binman_stamp inputs
ifeq ($(CONFIG_BINMAN),y) ifeq ($(CONFIG_BINMAN),y)
$(call if_changed,binman) $(call if_changed,binman)
endif endif
# Timestamp file to make sure that binman always runs
.binman_stamp: FORCE
@touch $@ @touch $@
all: .binman_stamp
ifeq ($(CONFIG_DEPRECATED),y) ifeq ($(CONFIG_DEPRECATED),y)
$(warning "You have deprecated configuration options enabled in your .config! Please check your configuration.") $(warning "You have deprecated configuration options enabled in your .config! Please check your configuration.")
endif endif
@ -1158,16 +1136,12 @@ endif
$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\ $(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG)) $(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
$(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY)) $(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY))
@# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which @# CFG_SYS_TIMER_RATE has brackets in it for some boards which
@# confuses this rule. Use if() to send just a single character which @# confuses this rule. Use if() to send just a single character which
@# is enable to tell 'deprecated' that one of these symbols exists @# is enable to tell 'deprecated' that one of these symbols exists
$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CONFIG_SYS_TIMER_RATE)$(CONFIG_SYS_TIMER_COUNTER)),x)) $(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x))
$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL)) $(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
$(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI)) $(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
@# Check that this build does not use CONFIG options that we do not
@# know about unless they are in Kconfig. All the existing CONFIG
@# options are whitelisted, so new ones should not be added.
$(call cmd,cfgcheck,u-boot.cfg)
@# Check that this build does not override OF_HAS_PRIOR_STAGE by @# Check that this build does not override OF_HAS_PRIOR_STAGE by
@# disabling OF_BOARD. @# disabling OF_BOARD.
$(call cmd,ofcheck,$(KCONFIG_CONFIG)) $(call cmd,ofcheck,$(KCONFIG_CONFIG))
@ -1353,8 +1327,8 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
$(foreach f,$(BINMAN_TOOLPATHS),--toolpath $(f)) \ $(foreach f,$(BINMAN_TOOLPATHS),--toolpath $(f)) \
--toolpath $(objtree)/tools \ --toolpath $(objtree)/tools \
$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \ $(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
build -u -d u-boot.dtb -O . -m --allow-missing \ build -u -d u-boot.dtb -O . -m \
--fake-ext-blobs \ $(if $(BINMAN_ALLOW_MISSING),--allow-missing --ignore-missing) \
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \ -I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \ -I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
$(foreach f,$(BINMAN_INDIRS),-I $(f)) \ $(foreach f,$(BINMAN_INDIRS),-I $(f)) \
@ -1381,8 +1355,8 @@ u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
# U-Boot entry point, needed for booting of full-blown U-Boot # U-Boot entry point, needed for booting of full-blown U-Boot
# from the SPL U-Boot version. # from the SPL U-Boot version.
# #
ifndef CONFIG_SYS_UBOOT_START ifndef CFG_SYS_UBOOT_START
CONFIG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE) CFG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
endif endif
# Boards with more complex image requirements can provide an .its source file # Boards with more complex image requirements can provide an .its source file
@ -1407,7 +1381,7 @@ endif
ifdef CONFIG_SPL_LOAD_FIT ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-p $(CONFIG_FIT_EXTERNAL_OFFSET) \ -p $(CONFIG_FIT_EXTERNAL_OFFSET) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \
@ -1415,10 +1389,10 @@ MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST))) $(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST)))
else else
MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \ MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \ MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
endif endif
@ -1439,7 +1413,7 @@ KWD_CONFIG_FILE = $(shell \
MKIMAGEFLAGS_u-boot.kwb = -n $(KWD_CONFIG_FILE) \ MKIMAGEFLAGS_u-boot.kwb = -n $(KWD_CONFIG_FILE) \
-T kwbimage -a $(CONFIG_TEXT_BASE) -e $(CONFIG_TEXT_BASE) -T kwbimage -a $(CONFIG_TEXT_BASE) -e $(CONFIG_TEXT_BASE)
MKIMAGEFLAGS_u-boot-spl.kwb = -n $(KWD_CONFIG_FILE) \ MKIMAGEFLAGS_u-boot-with-spl.kwb = -n $(KWD_CONFIG_FILE) \
-T kwbimage -a $(CONFIG_TEXT_BASE) -e $(CONFIG_TEXT_BASE) \ -T kwbimage -a $(CONFIG_TEXT_BASE) -e $(CONFIG_TEXT_BASE) \
$(if $(KEYDIR),-k $(KEYDIR)) $(if $(KEYDIR),-k $(KEYDIR))
@ -1449,7 +1423,7 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
UBOOT_BIN := u-boot.bin UBOOT_BIN := u-boot.bin
MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \ MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \
-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
u-boot.bin.lzma: u-boot.bin FORCE u-boot.bin.lzma: u-boot.bin FORCE
@ -1480,7 +1454,7 @@ u-boot.itb: u-boot-nodtb.bin \
$(BOARD_SIZE_CHECK) $(BOARD_SIZE_CHECK)
endif endif
u-boot-spl.kwb: u-boot.bin spl/u-boot-spl.bin FORCE u-boot-with-spl.kwb: u-boot.bin spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage) $(call if_changed,mkimage)
$(BOARD_SIZE_CHECK) $(BOARD_SIZE_CHECK)
@ -2392,7 +2366,7 @@ tcheck:
# Documentation targets # Documentation targets
# --------------------------------------------------------------------------- # ---------------------------------------------------------------------------
DOC_TARGETS := xmldocs latexdocs pdfdocs htmldocs epubdocs cleandocs \ DOC_TARGETS := xmldocs latexdocs pdfdocs htmldocs epubdocs cleandocs \
linkcheckdocs dochelp refcheckdocs linkcheckdocs dochelp refcheckdocs texinfodocs infodocs
PHONY += $(DOC_TARGETS) PHONY += $(DOC_TARGETS)
$(DOC_TARGETS): scripts_basic FORCE $(DOC_TARGETS): scripts_basic FORCE
$(Q)$(MAKE) $(build)=doc $@ $(Q)$(MAKE) $(build)=doc $@
@ -2459,11 +2433,13 @@ endif
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
quiet_cmd_genenv = GENENV $@ quiet_cmd_genenv = GENENV $@
cmd_genenv = $(OBJCOPY) --dump-section .rodata.default_environment=$@ env/common.o; \ cmd_genenv = \
sed --in-place -e 's/\x00/\x0A/g' $@; sed --in-place -e '/^\s*$$/d' $@; \ $(objtree)/tools/printinitialenv | \
sort --field-separator== -k1,1 --stable $@ -o $@ sed -e '/^\s*$$/d' | \
sort --field-separator== -k1,1 --stable -o $@
u-boot-initial-env: u-boot.bin u-boot-initial-env: $(env_h) FORCE
$(Q)$(MAKE) $(build)=tools $(objtree)/tools/printinitialenv
$(call if_changed,genenv) $(call if_changed,genenv)
# Consistency checks # Consistency checks

341
README
View File

@ -298,7 +298,7 @@ The following options need to be configured:
Enables a workaround for erratum A004510. If set, Enables a workaround for erratum A004510. If set,
then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set. CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional) CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
@ -314,7 +314,7 @@ The following options need to be configured:
See Freescale App Note 4493 for more information about See Freescale App Note 4493 for more information about
this erratum. this erratum.
CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
This is the value to write into CCSR offset 0x18600 This is the value to write into CCSR offset 0x18600
according to the A004510 workaround. according to the A004510 workaround.
@ -330,7 +330,7 @@ The following options need to be configured:
Freescale DDR driver in use. This type of DDR controller is Freescale DDR driver in use. This type of DDR controller is
found in mpc83xx, mpc85xx as well as some ARM core SoCs. found in mpc83xx, mpc85xx as well as some ARM core SoCs.
CONFIG_SYS_FSL_DDR_ADDR CFG_SYS_FSL_DDR_ADDR
Freescale DDR memory-mapped register base. Freescale DDR memory-mapped register base.
CONFIG_SYS_FSL_IFC_CLK_DIV CONFIG_SYS_FSL_IFC_CLK_DIV
@ -339,9 +339,9 @@ The following options need to be configured:
CONFIG_SYS_FSL_LBC_CLK_DIV CONFIG_SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to eLBC controller). Defines divider of platform clock(clock input to eLBC controller).
CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
Physical address from the view of DDR controllers. It is the Physical address from the view of DDR controllers. It is the
same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But same as CFG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
it could be different for ARM SoCs. it could be different for ARM SoCs.
- MIPS CPU options: - MIPS CPU options:
@ -352,7 +352,7 @@ The following options need to be configured:
be swapped if a flash programmer is used. be swapped if a flash programmer is used.
- ARM options: - ARM options:
CONFIG_SYS_EXCEPTION_VECTORS_HIGH CFG_SYS_EXCEPTION_VECTORS_HIGH
Select high exception vectors of the ARM core, e.g., do not Select high exception vectors of the ARM core, e.g., do not
clear the V bit of the c1 register of CP15. clear the V bit of the c1 register of CP15.
@ -373,12 +373,6 @@ The following options need to be configured:
such as ARM architectural timer initialization. such as ARM architectural timer initialization.
- Linux Kernel Interface: - Linux Kernel Interface:
CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only]
When transferring memsize parameter to Linux, some versions
expect it to be in bytes, others in MB.
Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
CONFIG_OF_LIBFDT CONFIG_OF_LIBFDT
New kernel versions are expecting firmware settings to be New kernel versions are expecting firmware settings to be
@ -415,16 +409,16 @@ The following options need to be configured:
the defaults discussed just above. the defaults discussed just above.
- Cache Configuration for ARM: - Cache Configuration for ARM:
CONFIG_SYS_PL310_BASE - Physical base address of PL310 CFG_SYS_PL310_BASE - Physical base address of PL310
controller register space controller register space
- Serial Ports: - Serial Ports:
CONFIG_PL011_CLOCK CFG_PL011_CLOCK
If you have Amba PrimeCell PL011 UARTs, set this variable to If you have Amba PrimeCell PL011 UARTs, set this variable to
the clock speed of the UARTs. the clock speed of the UARTs.
CONFIG_PL01x_PORTS CFG_PL01x_PORTS
If you have Amba PrimeCell PL010 or PL011 UARTs on your board, If you have Amba PrimeCell PL010 or PL011 UARTs on your board,
define this to a list of base addresses for each (supported) define this to a list of base addresses for each (supported)
@ -435,15 +429,6 @@ The following options need to be configured:
Define this variable to enable hw flow control in serial driver. Define this variable to enable hw flow control in serial driver.
Current user of this option is drivers/serial/nsl16550.c driver Current user of this option is drivers/serial/nsl16550.c driver
- Serial Download Echo Mode:
CONFIG_LOADS_ECHO
If defined to 1, all characters received during a
serial download (using the "loads" command) are
echoed back. This might be needed by some terminal
emulations (like "cu"), but may as well just take
time on others. This setting #define's the initial
value of the "loads_echo" environment variable.
- Removal of commands - Removal of commands
If no commands are needed to boot, you can disable If no commands are needed to boot, you can disable
CONFIG_CMDLINE to remove them. In this case, the command line CONFIG_CMDLINE to remove them. In this case, the command line
@ -469,33 +454,8 @@ The following options need to be configured:
to 0 disables calling WATCHDOG_RESET() from the timer to 0 disables calling WATCHDOG_RESET() from the timer
interrupt. interrupt.
- Real-Time Clock:
When CONFIG_CMD_DATE is selected, the type of the RTC
has to be selected, too. Define exactly one of the
following options:
CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC
CONFIG_RTC_MC13XXX - use MC13783 or MC13892 RTC
CONFIG_RTC_MC146818 - use MC146818 RTC
CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC
CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC
CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC
CONFIG_RTC_DS1339 - use Maxim, Inc. DS1339 RTC
CONFIG_RTC_DS164x - use Dallas DS164x RTC
CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC
CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC
CONFIG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337
CONFIG_SYS_RV3029_TCR - enable trickle charger on
RV3029 RTC.
Note that if the RTC uses I2C, then the I2C interface
must also be configured. See I2C Support, below.
- GPIO Support: - GPIO Support:
CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of
The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
chip-ngpio pairs that tell the PCA953X driver the number of chip-ngpio pairs that tell the PCA953X driver the number of
pins supported by a particular chip. pins supported by a particular chip.
@ -581,13 +541,13 @@ The following options need to be configured:
CONFIG_SH_ETHER CONFIG_SH_ETHER
Support for Renesas on-chip Ethernet controller Support for Renesas on-chip Ethernet controller
CONFIG_SH_ETHER_USE_PORT CFG_SH_ETHER_USE_PORT
Define the number of ports to be used Define the number of ports to be used
CONFIG_SH_ETHER_PHY_ADDR CFG_SH_ETHER_PHY_ADDR
Define the ETH PHY's address Define the ETH PHY's address
CONFIG_SH_ETHER_CACHE_WRITEBACK CFG_SH_ETHER_CACHE_WRITEBACK
If this option is set, the driver enables cache flush. If this option is set, the driver enables cache flush.
- TPM Support: - TPM Support:
@ -619,11 +579,6 @@ The following options need to be configured:
Support for generic parallel port TPM devices. Only one device Support for generic parallel port TPM devices. Only one device
per system is supported at this time. per system is supported at this time.
CONFIG_TPM_TIS_BASE_ADDRESS
Base address where the generic TPM device is mapped
to. Contemporary x86 systems usually map it at
0xfed40000.
CONFIG_TPM CONFIG_TPM
Define this to enable the TPM support library which provides Define this to enable the TPM support library which provides
functional interfaces to some TPM commands. functional interfaces to some TPM commands.
@ -663,21 +618,6 @@ The following options need to be configured:
variable usbtty to be cdc_acm should suffice. The following variable usbtty to be cdc_acm should suffice. The following
might be defined in YourBoardName.h might be defined in YourBoardName.h
CONFIG_USB_DEVICE
Define this to build a UDC device
CONFIG_USB_TTY
Define this to have a tty type of device available to
talk to the UDC device
CONFIG_USBD_HS
Define this to enable the high speed support for usb
device and usbtty. If this feature is enabled, a routine
int is_usbd_high_speed(void)
also needs to be defined by the driver to dynamically poll
whether the enumeration has succeded at high speed or full
speed.
If you have a USB-IF assigned VendorID then you may wish to If you have a USB-IF assigned VendorID then you may wish to
define your own vendor specific values either in BoardName.h define your own vendor specific values either in BoardName.h
or directly in usbd_vendor_info.h. If you don't define or directly in usbd_vendor_info.h. If you don't define
@ -762,11 +702,6 @@ The following options need to be configured:
entering dfuMANIFEST state. Host waits this timeout, before entering dfuMANIFEST state. Host waits this timeout, before
sending again an USB request to the device. sending again an USB request to the device.
- Journaling Flash filesystem support:
CONFIG_SYS_JFFS2_FIRST_SECTOR,
CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
Define these for a default partition on a NOR device
- Keyboard Support: - Keyboard Support:
See Kconfig help for available keyboard drivers. See Kconfig help for available keyboard drivers.
@ -780,38 +715,6 @@ The following options need to be configured:
Some PHY like Intel LXT971A need extra delay after Some PHY like Intel LXT971A need extra delay after
command issued before MII status register can be read command issued before MII status register can be read
- IP address:
CONFIG_IPADDR
Define a default value for the IP address to use for
the default Ethernet interface, in case this is not
determined through e.g. bootp.
(Environment variable "ipaddr")
- Server IP address:
CONFIG_SERVERIP
Defines a default value for the IP address of a TFTP
server to contact when using the "tftboot" command.
(Environment variable "serverip")
- Gateway IP address:
CONFIG_GATEWAYIP
Defines a default value for the IP address of the
default router where packets to other networks are
sent to.
(Environment variable "gatewayip")
- Subnet mask:
CONFIG_NETMASK
Defines a default value for the subnet mask (or
routing prefix) which is used to determine if an IP
address belongs to the local subnet or needs to be
forwarded through a router.
(Environment variable "netmask")
- BOOTP Recovery Mode: - BOOTP Recovery Mode:
CONFIG_BOOTP_RANDOM_DELAY CONFIG_BOOTP_RANDOM_DELAY
@ -937,26 +840,26 @@ The following options need to be configured:
with a list of GPIO LEDs that have inverted polarity. with a list of GPIO LEDs that have inverted polarity.
- I2C Support: - I2C Support:
CONFIG_SYS_NUM_I2C_BUSES CFG_SYS_NUM_I2C_BUSES
Hold the number of i2c buses you want to use. Hold the number of i2c buses you want to use.
CONFIG_SYS_I2C_DIRECT_BUS CFG_SYS_I2C_DIRECT_BUS
define this, if you don't use i2c muxes on your hardware. define this, if you don't use i2c muxes on your hardware.
if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
omit this define. omit this define.
CONFIG_SYS_I2C_MAX_HOPS CFG_SYS_I2C_MAX_HOPS
define how many muxes are maximal consecutively connected define how many muxes are maximal consecutively connected
on one i2c bus. If you not use i2c muxes, omit this on one i2c bus. If you not use i2c muxes, omit this
define. define.
CONFIG_SYS_I2C_BUSES CFG_SYS_I2C_BUSES
hold a list of buses you want to use, only used if hold a list of buses you want to use, only used if
CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example CFG_SYS_I2C_DIRECT_BUS is not defined, for example
a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and a board with CFG_SYS_I2C_MAX_HOPS = 1 and
CONFIG_SYS_NUM_I2C_BUSES = 9: CFG_SYS_NUM_I2C_BUSES = 9:
CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \ CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
@ -1052,43 +955,24 @@ The following options need to be configured:
You should define these to the GPIO value as given directly to You should define these to the GPIO value as given directly to
the generic GPIO functions. the generic GPIO functions.
CONFIG_SYS_I2C_INIT_BOARD CFG_I2C_MULTI_BUS
When a board is reset during an i2c bus transfer
chips might think that the current transfer is still
in progress. On some boards it is possible to access
the i2c SCLK line directly, either by using the
processor pin as a GPIO or by having a second pin
connected to the bus. If this option is defined a
custom i2c_init_board() routine in boards/xxx/board.c
is run early in the boot sequence.
CONFIG_I2C_MULTI_BUS
This option allows the use of multiple I2C buses, each of which This option allows the use of multiple I2C buses, each of which
must have a controller. At any point in time, only one bus is must have a controller. At any point in time, only one bus is
active. To switch to a different bus, use the 'i2c dev' command. active. To switch to a different bus, use the 'i2c dev' command.
Note that bus numbering is zero-based. Note that bus numbering is zero-based.
CONFIG_SYS_I2C_NOPROBES CFG_SYS_I2C_NOPROBES
This option specifies a list of I2C devices that will be skipped This option specifies a list of I2C devices that will be skipped
when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS when the 'i2c probe' command is issued.
is set, specify a list of bus-device pairs. Otherwise, specify
a 1D array of device addresses
e.g. e.g.
#undef CONFIG_I2C_MULTI_BUS #define CFG_SYS_I2C_NOPROBES {0x50,0x68}
#define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
will skip addresses 0x50 and 0x68 on a board with one I2C bus will skip addresses 0x50 and 0x68 on a board with one I2C bus
#define CONFIG_I2C_MULTI_BUS CFG_SYS_RTC_BUS_NUM
#define CONFIG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
CONFIG_SYS_RTC_BUS_NUM
If defined, then this indicates the I2C bus number for the RTC. If defined, then this indicates the I2C bus number for the RTC.
If not defined, then U-Boot assumes that RTC is on I2C bus 0. If not defined, then U-Boot assumes that RTC is on I2C bus 0.
@ -1134,7 +1018,7 @@ The following options need to be configured:
will require a board or device specific function to will require a board or device specific function to
be written. be written.
CONFIG_FPGA_DELAY CFG_FPGA_DELAY
If defined, a function that provides delays in the FPGA If defined, a function that provides delays in the FPGA
configuration driver. configuration driver.
@ -1146,19 +1030,19 @@ The following options need to be configured:
configuration if the INIT_B line goes low (which configuration if the INIT_B line goes low (which
indicated a CRC error). indicated a CRC error).
CONFIG_SYS_FPGA_WAIT_INIT CFG_SYS_FPGA_WAIT_INIT
Maximum time to wait for the INIT_B line to de-assert Maximum time to wait for the INIT_B line to de-assert
after PROB_B has been de-asserted during a Virtex II after PROB_B has been de-asserted during a Virtex II
FPGA configuration sequence. The default time is 500 FPGA configuration sequence. The default time is 500
ms. ms.
CONFIG_SYS_FPGA_WAIT_BUSY CFG_SYS_FPGA_WAIT_BUSY
Maximum time to wait for BUSY to de-assert during Maximum time to wait for BUSY to de-assert during
Virtex II FPGA configuration. The default is 5 ms. Virtex II FPGA configuration. The default is 5 ms.
CONFIG_SYS_FPGA_WAIT_CONFIG CFG_SYS_FPGA_WAIT_CONFIG
Time to wait after FPGA configuration. The default is Time to wait after FPGA configuration. The default is
200 ms. 200 ms.
@ -1179,24 +1063,17 @@ The following options need to be configured:
completely disabled. Anybody can change or delete completely disabled. Anybody can change or delete
these parameters. these parameters.
Alternatively, if you define _both_ an ethaddr in the
default env _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
Ethernet address is installed in the environment,
which can be changed exactly ONCE by the user. [The
serial# is unaffected by this, i. e. it remains
read-only.]
The same can be accomplished in a more flexible way The same can be accomplished in a more flexible way
for any variable by configuring the type of access for any variable by configuring the type of access
to allow for those variables in the ".flags" variable to allow for those variables in the ".flags" variable
or define CONFIG_ENV_FLAGS_LIST_STATIC. or define CFG_ENV_FLAGS_LIST_STATIC.
- Protected RAM: - Protected RAM:
CONFIG_PRAM CFG_PRAM
Define this variable to enable the reservation of Define this variable to enable the reservation of
"protected RAM", i. e. RAM which is not overwritten "protected RAM", i. e. RAM which is not overwritten
by U-Boot. Define CONFIG_PRAM to hold the number of by U-Boot. Define CFG_PRAM to hold the number of
kB you want to reserve for pRAM. You can overwrite kB you want to reserve for pRAM. You can overwrite
this default value by defining an environment this default value by defining an environment
variable "pram" to the number of kB you want to variable "pram" to the number of kB you want to
@ -1247,7 +1124,7 @@ The following options need to be configured:
symbols. symbols.
- Default Environment: - Default Environment:
CONFIG_EXTRA_ENV_SETTINGS CFG_EXTRA_ENV_SETTINGS
Define this to contain any number of null terminated Define this to contain any number of null terminated
strings (variable = value pairs) that will be part of strings (variable = value pairs) that will be part of
@ -1256,7 +1133,7 @@ The following options need to be configured:
For example, place something like this in your For example, place something like this in your
board's config file: board's config file:
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CFG_EXTRA_ENV_SETTINGS \
"myvar1=value1\0" \ "myvar1=value1\0" \
"myvar2=value2\0" "myvar2=value2\0"
@ -1281,13 +1158,6 @@ The following options need to be configured:
this is instead controlled by the value of this is instead controlled by the value of
/config/load-environment. /config/load-environment.
CONFIG_STANDALONE_LOAD_ADDR
This option defines a board specific value for the
address where standalone program gets loaded, thus
overwriting the architecture dependent default
settings.
- Automatic software updates via TFTP server - Automatic software updates via TFTP server
CONFIG_UPDATE_TFTP CONFIG_UPDATE_TFTP
CONFIG_UPDATE_TFTP_CNT_MAX CONFIG_UPDATE_TFTP_CNT_MAX
@ -1389,24 +1259,20 @@ The following options need to be configured:
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT, CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS, CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE, CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
CONFIG_SYS_NAND_ECCBYTES CFG_SYS_NAND_ECCBYTES
Defines the size and behavior of the NAND that SPL uses Defines the size and behavior of the NAND that SPL uses
to read U-Boot to read U-Boot
CONFIG_SYS_NAND_U_BOOT_DST CFG_SYS_NAND_U_BOOT_DST
Location in memory to load U-Boot to Location in memory to load U-Boot to
CONFIG_SYS_NAND_U_BOOT_SIZE CFG_SYS_NAND_U_BOOT_SIZE
Size of image to load Size of image to load
CONFIG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_START
Entry point in loaded image to jump to Entry point in loaded image to jump to
CONFIG_SYS_NAND_HW_ECC_OOBFIRST
Define this if you need to first read the OOB and then the
data. This is used, for example, on davinci platforms.
CONFIG_SPL_RAM_DEVICE CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary Support for running image already present in ram, in SPL binary
@ -1459,33 +1325,24 @@ Configuration Settings:
- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to - CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
prompt for user input. prompt for user input.
- CONFIG_SYS_BAUDRATE_TABLE: - CFG_SYS_BAUDRATE_TABLE:
List of legal baudrate settings for this board. List of legal baudrate settings for this board.
- CONFIG_SYS_MEM_RESERVE_SECURE - CFG_SYS_MEM_RESERVE_SECURE
Only implemented for ARMv8 for now. Only implemented for ARMv8 for now.
If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory If defined, the size of CFG_SYS_MEM_RESERVE_SECURE memory
is substracted from total RAM and won't be reported to OS. is substracted from total RAM and won't be reported to OS.
This memory can be used as secure memory. A variable This memory can be used as secure memory. A variable
gd->arch.secure_ram is used to track the location. In systems gd->arch.secure_ram is used to track the location. In systems
the RAM base is not zero, or RAM is divided into banks, the RAM base is not zero, or RAM is divided into banks,
this variable needs to be recalcuated to get the address. this variable needs to be recalcuated to get the address.
- CONFIG_SYS_LOADS_BAUD_CHANGE: - CFG_SYS_SDRAM_BASE:
Enable temporary baudrate change while serial download
- CONFIG_SYS_SDRAM_BASE:
Physical start address of SDRAM. _Must_ be 0 here. Physical start address of SDRAM. _Must_ be 0 here.
- CONFIG_SYS_FLASH_BASE: - CFG_SYS_FLASH_BASE:
Physical start address of Flash memory. Physical start address of Flash memory.
- CONFIG_SYS_MONITOR_LEN:
Size of memory reserved for monitor code, used to
determine _at_compile_time_ (!) if the environment is
embedded within the U-Boot image, or in a separate
flash sector.
- CONFIG_SYS_MALLOC_LEN: - CONFIG_SYS_MALLOC_LEN:
Size of DRAM reserved for malloc() use. Size of DRAM reserved for malloc() use.
@ -1507,35 +1364,16 @@ Configuration Settings:
boards which do not use the full malloc in SPL (which is boards which do not use the full malloc in SPL (which is
enabled with CONFIG_SYS_SPL_MALLOC). enabled with CONFIG_SYS_SPL_MALLOC).
- CONFIG_SYS_NONCACHED_MEMORY: - CFG_SYS_BOOTMAPSZ:
Size of non-cached memory area. This area of memory will be
typically located right below the malloc() area and mapped
uncached in the MMU. This is useful for drivers that would
otherwise require a lot of explicit cache maintenance. For
some drivers it's also impossible to properly maintain the
cache. For example if the regions that need to be flushed
are not a multiple of the cache-line size, *and* padding
cannot be allocated between the regions to align them (i.e.
if the HW requires a contiguous array of regions, and the
size of each region is not cache-aligned), then a flush of
one region may result in overwriting data that hardware has
written to another region in the same cache-line. This can
happen for example in network drivers where descriptors for
buffers are typically smaller than the CPU cache-line (e.g.
16 bytes vs. 32 or 64 bytes).
Non-cached memory is only supported on 32-bit ARM at present.
- CONFIG_SYS_BOOTMAPSZ:
Maximum size of memory mapped by the startup code of Maximum size of memory mapped by the startup code of
the Linux kernel; all data that must be processed by the Linux kernel; all data that must be processed by
the Linux kernel (bd_info, boot arguments, FDT blob if the Linux kernel (bd_info, boot arguments, FDT blob if
used) must be put below this limit, unless "bootm_low" used) must be put below this limit, unless "bootm_low"
environment variable is defined and non-zero. In such case environment variable is defined and non-zero. In such case
all data for the Linux kernel must be between "bootm_low" all data for the Linux kernel must be between "bootm_low"
and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment and "bootm_low" + CFG_SYS_BOOTMAPSZ. The environment
variable "bootm_mapsize" will override the value of variable "bootm_mapsize" will override the value of
CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined, CFG_SYS_BOOTMAPSZ. If CFG_SYS_BOOTMAPSZ is undefined,
then the value in "bootm_size" will be used instead. then the value in "bootm_size" will be used instead.
- CONFIG_SYS_BOOT_GET_CMDLINE: - CONFIG_SYS_BOOT_GET_CMDLINE:
@ -1566,26 +1404,8 @@ Configuration Settings:
- CONFIG_SYS_FLASH_USE_BUFFER_WRITE - CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Use buffered writes to flash. Use buffered writes to flash.
- CONFIG_FLASH_SPANSION_S29WS_N
s29ws-n MirrorBit flash has non-standard addresses for buffered
write commands.
- CONFIG_FLASH_SHOW_PROGRESS
If defined (must be an integer), print out countdown
digits and dots. Recommended value: 45 (9..1) for 80
column displays, 15 (3..1) for 40 column displays.
- CONFIG_FLASH_VERIFY
If defined, the content of the flash (destination) is compared
against the source after the write operation. An error message
will be printed when the contents are not identical.
Please note that this option is useless in nearly all cases,
since such flash programming errors usually are detected earlier
while unprotecting/erasing/programming. Please only enable
this option if you really know what you are doing.
- CONFIG_ENV_FLAGS_LIST_DEFAULT - CONFIG_ENV_FLAGS_LIST_DEFAULT
- CONFIG_ENV_FLAGS_LIST_STATIC - CFG_ENV_FLAGS_LIST_STATIC
Enable validation of the values given to environment variables when Enable validation of the values given to environment variables when
calling env set. Variables can be restricted to only decimal, calling env set. Variables can be restricted to only decimal,
hexadecimal, or boolean. If CONFIG_CMD_NET is also defined, hexadecimal, or boolean. If CONFIG_CMD_NET is also defined,
@ -1616,7 +1436,7 @@ Configuration Settings:
Define this to a list (string) to define the ".flags" Define this to a list (string) to define the ".flags"
environment variable in the default or embedded environment. environment variable in the default or embedded environment.
- CONFIG_ENV_FLAGS_LIST_STATIC - CFG_ENV_FLAGS_LIST_STATIC
Define this to a list (string) to define validation that Define this to a list (string) to define validation that
should be done if an entry is not found in the ".flags" should be done if an entry is not found in the ".flags"
environment variable. To override a setting in the static environment variable. To override a setting in the static
@ -1631,11 +1451,6 @@ The following definitions that deal with the placement and management
of environment data (variable area); in general, we support the of environment data (variable area); in general, we support the
following configurations: following configurations:
- CONFIG_BUILD_ENVCRC:
Builds up envcrc with the target environment so that external utils
may easily extract it and embed it in final U-Boot images.
BE CAREFUL! The first access to the environment happens quite early BE CAREFUL! The first access to the environment happens quite early
in U-Boot initialization (when we try to get the setting of for the in U-Boot initialization (when we try to get the setting of for the
console baudrate). You *MUST* have mapped your NVRAM area then, or console baudrate). You *MUST* have mapped your NVRAM area then, or
@ -1676,13 +1491,6 @@ use the "saveenv" command to store a valid environment.
- CONFIG_SYS_FAULT_MII_ADDR: - CONFIG_SYS_FAULT_MII_ADDR:
MII address of the PHY to check for the Ethernet link state. MII address of the PHY to check for the Ethernet link state.
- CONFIG_NS16550_MIN_FUNCTIONS:
Define this if you desire to only have use of the NS16550_init
and NS16550_putc functions for the serial driver located at
drivers/serial/ns16550.c. This option is useful for saving
space for already greatly restricted images, including but not
limited to NAND_SPL configurations.
- CONFIG_DISPLAY_BOARDINFO - CONFIG_DISPLAY_BOARDINFO
Display information about the board that U-Boot is running on Display information about the board that U-Boot is running on
when U-Boot starts up. The board function checkboard() is called when U-Boot starts up. The board function checkboard() is called
@ -1703,11 +1511,11 @@ Low Level (hardware related) configuration options:
Default (power-on reset) physical address of CCSR on Freescale Default (power-on reset) physical address of CCSR on Freescale
PowerPC SOCs. PowerPC SOCs.
- CONFIG_SYS_CCSRBAR: - CFG_SYS_CCSRBAR:
Virtual address of CCSR. On a 32-bit build, this is typically Virtual address of CCSR. On a 32-bit build, this is typically
the same value as CONFIG_SYS_CCSRBAR_DEFAULT. the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
- CONFIG_SYS_CCSRBAR_PHYS: - CFG_SYS_CCSRBAR_PHYS:
Physical address of CCSR. CCSR can be relocated to a new Physical address of CCSR. CCSR can be relocated to a new
physical address, if desired. In this case, this macro should physical address, if desired. In this case, this macro should
be set to that address. Otherwise, it should be set to the be set to that address. Otherwise, it should be set to the
@ -1715,17 +1523,17 @@ Low Level (hardware related) configuration options:
is typically relocated on 36-bit builds. It is recommended is typically relocated on 36-bit builds. It is recommended
that this macro be defined via the _HIGH and _LOW macros: that this macro be defined via the _HIGH and _LOW macros:
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH #define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH
* 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW) * 1ull) << 32 | CFG_SYS_CCSRBAR_PHYS_LOW)
- CONFIG_SYS_CCSRBAR_PHYS_HIGH: - CFG_SYS_CCSRBAR_PHYS_HIGH:
Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically Bits 33-36 of CFG_SYS_CCSRBAR_PHYS. This value is typically
either 0 (32-bit build) or 0xF (36-bit build). This macro is either 0 (32-bit build) or 0xF (36-bit build). This macro is
used in assembly code, so it must not contain typecasts or used in assembly code, so it must not contain typecasts or
integer size suffixes (e.g. "ULL"). integer size suffixes (e.g. "ULL").
- CONFIG_SYS_CCSRBAR_PHYS_LOW: - CFG_SYS_CCSRBAR_PHYS_LOW:
Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is Lower 32-bits of CFG_SYS_CCSRBAR_PHYS. This macro is
used in assembly code, so it must not contain typecasts or used in assembly code, so it must not contain typecasts or
integer size suffixes (e.g. "ULL"). integer size suffixes (e.g. "ULL").
@ -1733,7 +1541,7 @@ Low Level (hardware related) configuration options:
DO NOT CHANGE unless you know exactly what you're DO NOT CHANGE unless you know exactly what you're
doing! (11-4) [MPC8xx systems only] doing! (11-4) [MPC8xx systems only]
- CONFIG_SYS_INIT_RAM_ADDR: - CFG_SYS_INIT_RAM_ADDR:
Start address of memory area that can be used for Start address of memory area that can be used for
initial data and stack; please note that this must be initial data and stack; please note that this must be
@ -1751,21 +1559,6 @@ Low Level (hardware related) configuration options:
- CONFIG_SYS_OR_TIMING_SDRAM: - CONFIG_SYS_OR_TIMING_SDRAM:
SDRAM timing SDRAM timing
- CONFIG_SYS_MAMR_PTA:
periodic timer for refresh
- CONFIG_SYS_SRIO:
Chip has SRIO or not
- CONFIG_SRIO1:
Board has SRIO 1 port available
- CONFIG_SRIO2:
Board has SRIO 2 port available
- CONFIG_SRIO_PCIE_BOOT_MASTER
Board can support master function for Boot from SRIO and PCIE
- CONFIG_SYS_SRIOn_MEM_VIRT: - CONFIG_SYS_SRIOn_MEM_VIRT:
Virtual Address of SRIO port 'n' memory region Virtual Address of SRIO port 'n' memory region
@ -1787,13 +1580,6 @@ Low Level (hardware related) configuration options:
Sets the EBC0_CFG register for the NDFC. If not defined Sets the EBC0_CFG register for the NDFC. If not defined
a default value will be used. a default value will be used.
- CONFIG_SPD_EEPROM
Get DDR timing information from an I2C EEPROM. Common
with pluggable memory modules such as SODIMMs
SPD_EEPROM_ADDRESS
I2C address of the SPD EEPROM
- CONFIG_SYS_SPD_BUS_NUM - CONFIG_SYS_SPD_BUS_NUM
If SPD EEPROM is on an I2C bus other than the first If SPD EEPROM is on an I2C bus other than the first
one, specify here. Note that the value must resolve one, specify here. Note that the value must resolve
@ -1866,11 +1652,6 @@ Low Level (hardware related) configuration options:
If defined, the x86 reset vector code is included. This is not If defined, the x86 reset vector code is included. This is not
needed when U-Boot is running from Coreboot. needed when U-Boot is running from Coreboot.
- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Option to disable subpage write in NAND driver
driver that uses this:
drivers/mtd/nand/raw/davinci_nand.c
Freescale QE/FMAN Firmware Support: Freescale QE/FMAN Firmware Support:
----------------------------------- -----------------------------------
@ -2822,7 +2603,7 @@ locked as (mis-) used as memory, etc.
cause you grief during the initial boot! It is frequently not cause you grief during the initial boot! It is frequently not
used. used.
CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere CFG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
with your processor/board/system design. The default value with your processor/board/system design. The default value
you will find in any recent u-boot distribution in you will find in any recent u-boot distribution in
walnut.h should work for you. I'd set it to a value larger walnut.h should work for you. I'd set it to a value larger

View File

@ -5,4 +5,28 @@ config API
help help
This option enables the U-Boot API. See api/README for more information. This option enables the U-Boot API. See api/README for more information.
config SYS_MMC_MAX_DEVICE
int "Maximum number of MMC devices exposed via the API"
depends on API
default 1
endmenu endmenu
config STANDALONE_LOAD_ADDR
hex "Address in memory to link standalone applications to"
default 0xffffffff80200000 if MIPS && 64BIT
default 0x8c000000 if SH
default 0x82000000 if ARC
default 0x80f00000 if MICROBLAZE
default 0x80300000 if ARCH_OMAP2PLUS || FSL_LSCH2 || FSL_LSCH3
default 0x80200000 if MIPS && 32BIT
default 0x0c100000 if ARM
default 0x02000000 if NIOS2
default 0x00040000 if PPC || X86
default 0x00020000 if M68K
default 0x0 if RISCV
default SYS_LOAD_ADDR
help
This option defines a board specific value for the address where
standalone program gets loaded, thus overwriting the architecture
dependent default settings.

View File

@ -44,10 +44,6 @@ struct stor_spec {
static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, }; static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };
#ifndef CONFIG_SYS_MMC_MAX_DEVICE
#define CONFIG_SYS_MMC_MAX_DEVICE 1
#endif
void dev_stor_init(void) void dev_stor_init(void)
{ {
#if defined(CONFIG_IDE) #if defined(CONFIG_IDE)

View File

@ -111,9 +111,8 @@ config RISCV
select SUPPORT_OF_CONTROL select SUPPORT_OF_CONTROL
select OF_CONTROL select OF_CONTROL
select DM select DM
select SPL_SEPARATE_BSS if SPL imply SPL_SEPARATE_BSS if SPL
imply DM_SERIAL imply DM_SERIAL
imply DM_ETH
imply DM_EVENT imply DM_EVENT
imply DM_MMC imply DM_MMC
imply DM_SPI imply DM_SPI
@ -146,6 +145,7 @@ config SANDBOX
select DM_SPI select DM_SPI
select DM_SPI_FLASH select DM_SPI_FLASH
select GZIP_COMPRESSED select GZIP_COMPRESSED
select IO_TRACE
select LZO select LZO
select OF_BOARD_SETUP select OF_BOARD_SETUP
select PCI_ENDPOINT select PCI_ENDPOINT
@ -240,7 +240,6 @@ config X86
imply CMD_SF imply CMD_SF
imply CMD_SF_TEST imply CMD_SF_TEST
imply CMD_ZBOOT imply CMD_ZBOOT
imply DM_ETH
imply DM_EVENT imply DM_EVENT
imply DM_GPIO imply DM_GPIO
imply DM_KEYBOARD imply DM_KEYBOARD
@ -381,9 +380,15 @@ config SYS_IMMR
Address for the Internal Memory-Mapped Registers (IMMR) window used Address for the Internal Memory-Mapped Registers (IMMR) window used
to configure the features of many Freescale / NXP SoCs. to configure the features of many Freescale / NXP SoCs.
config SKIP_LOWLEVEL_INIT config MONITOR_IS_IN_RAM
bool "Skip the calls to certain low level initialization functions" bool "U-Boot is loaded in to RAM by a pre-loader"
depends on M68K || NIOS2
menu "Skipping low level initialization functions"
depends on ARM || MIPS || RISCV depends on ARM || MIPS || RISCV
config SKIP_LOWLEVEL_INIT
bool "Skip calls to certain low level initialization functions"
help help
If enabled, then certain low level initializations (like setting up If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate the memory controller) are omitted and/or U-Boot does not relocate
@ -393,8 +398,8 @@ config SKIP_LOWLEVEL_INIT
debugger which performs these initializations itself. debugger which performs these initializations itself.
config SPL_SKIP_LOWLEVEL_INIT config SPL_SKIP_LOWLEVEL_INIT
bool "Skip the calls to certain low level initialization functions" bool "Skip calls to certain low level initialization functions in SPL"
depends on SPL && (ARM || MIPS || RISCV) depends on SPL
help help
If enabled, then certain low level initializations (like setting up If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate the memory controller) are omitted and/or U-Boot does not relocate
@ -404,7 +409,7 @@ config SPL_SKIP_LOWLEVEL_INIT
debugger which performs these initializations itself. debugger which performs these initializations itself.
config TPL_SKIP_LOWLEVEL_INIT config TPL_SKIP_LOWLEVEL_INIT
bool "Skip the calls to certain low level initialization functions" bool "Skip calls to certain low level initialization functions in TPL"
depends on SPL && ARM depends on SPL && ARM
help help
If enabled, then certain low level initializations (like setting up If enabled, then certain low level initializations (like setting up
@ -415,7 +420,7 @@ config TPL_SKIP_LOWLEVEL_INIT
debugger which performs these initializations itself. debugger which performs these initializations itself.
config SKIP_LOWLEVEL_INIT_ONLY config SKIP_LOWLEVEL_INIT_ONLY
bool "Skip the call to lowlevel_init during early boot ONLY" bool "Skip call to lowlevel_init during early boot ONLY"
depends on ARM depends on ARM
help help
This allows just the call to lowlevel_init() to be skipped. The This allows just the call to lowlevel_init() to be skipped. The
@ -423,7 +428,7 @@ config SKIP_LOWLEVEL_INIT_ONLY
performed. performed.
config SPL_SKIP_LOWLEVEL_INIT_ONLY config SPL_SKIP_LOWLEVEL_INIT_ONLY
bool "Skip the call to lowlevel_init during early boot ONLY" bool "Skip call to lowlevel_init during early SPL boot ONLY"
depends on SPL && ARM depends on SPL && ARM
help help
This allows just the call to lowlevel_init() to be skipped. The This allows just the call to lowlevel_init() to be skipped. The
@ -431,13 +436,39 @@ config SPL_SKIP_LOWLEVEL_INIT_ONLY
performed. performed.
config TPL_SKIP_LOWLEVEL_INIT_ONLY config TPL_SKIP_LOWLEVEL_INIT_ONLY
bool "Skip the call to lowlevel_init during early boot ONLY" bool "Skip call to lowlevel_init during early TPL boot ONLY"
depends on TPL && ARM depends on TPL && ARM
help help
This allows just the call to lowlevel_init() to be skipped. The This allows just the call to lowlevel_init() to be skipped. The
normal CP15 init (such as enabling the instruction cache) is still normal CP15 init (such as enabling the instruction cache) is still
performed. performed.
endmenu
config SYS_HAS_NONCACHED_MEMORY
bool "Enable reserving a non-cached memory area for drivers"
depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
help
This is useful for drivers that would otherwise require a lot of
explicit cache maintenance. For some drivers it's also impossible to
properly maintain the cache. For example if the regions that need to
be flushed are not a multiple of the cache-line size, *and* padding
cannot be allocated between the regions to align them (i.e. if the
HW requires a contiguous array of regions, and the size of each
region is not cache-aligned), then a flush of one region may result
in overwriting data that hardware has written to another region in
the same cache-line. This can happen for example in network drivers
where descriptors for buffers are typically smaller than the CPU
cache-line (e.g. 16 bytes vs. 32 or 64 bytes).
config SYS_NONCACHED_MEMORY
hex "Size in bytes of the non-cached memory area"
depends on SYS_HAS_NONCACHED_MEMORY
default 0x100000
help
Size of non-cached memory area. This area of memory will be typically
located right below the malloc() area and mapped uncached in the MMU.
source "arch/arc/Kconfig" source "arch/arc/Kconfig"
source "arch/arm/Kconfig" source "arch/arm/Kconfig"
source "arch/m68k/Kconfig" source "arch/m68k/Kconfig"
@ -458,7 +489,6 @@ source "arch/Kconfig.nxp"
endif endif
source "board/keymile/Kconfig" source "board/keymile/Kconfig"
source "board/sunxi/Kconfig"
if MIPS || MICROBLAZE if MIPS || MICROBLAZE

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@ -1,5 +1,12 @@
menu "Functionality shared between NXP SoCs"
config FSL_TRUST_ARCH_v1
bool
config NXP_ESBC config NXP_ESBC
bool "NXP ESBC (secure boot) functionality" bool "NXP ESBC (secure boot) functionality"
select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
ARCH_P5040 || ARCH_P2041
help help
Enable Freescale Secure Boot feature. Normally selected by defconfig. Enable Freescale Secure Boot feature. Normally selected by defconfig.
If unsure, do not change. If unsure, do not change.
@ -10,6 +17,7 @@ menu "Chain of trust / secure boot options"
config CHAIN_OF_TRUST config CHAIN_OF_TRUST
select FSL_CAAM select FSL_CAAM
select ARCH_MISC_INIT select ARCH_MISC_INIT
select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT
select FSL_SEC_MON select FSL_SEC_MON
select SPL_BOARD_INIT if (ARM && SPL) select SPL_BOARD_INIT if (ARM && SPL)
select SPL_HASH if (ARM && SPL) select SPL_HASH if (ARM && SPL)
@ -41,6 +49,17 @@ config ESBC_ADDR_64BIT
help help
For Layerscape based platforms, ESBC image Address in Header is 64bit. For Layerscape based platforms, ESBC image Address in Header is 64bit.
config FSL_ISBC_KEY_EXT
bool
help
The key used for verification of next level images is picked up from
an Extension Table which has been verified by the ISBC (Internal
Secure boot Code) in boot ROM of the SoC. The feature is only
applicable in case of NOR boot and is not applicable in case of
RAMBOOT (NAND, SD, SPI). For Layerscape, this feature is available
for all device if IE Table is copied to XIP memory Also, for
Layerscape, ISBC doesn't verify this table.
config SYS_FSL_SFP_BE config SYS_FSL_SFP_BE
def_bool y def_bool y
depends on PPC || FSL_LSCH2 || ARCH_LS1021A depends on PPC || FSL_LSCH2 || ARCH_LS1021A
@ -125,8 +144,6 @@ config KEY_REVOCATION
endmenu endmenu
comment "Other functionality shared between NXP SoCs"
config DEEP_SLEEP config DEEP_SLEEP
bool "Enable SoC deep sleep feature" bool "Enable SoC deep sleep feature"
depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
@ -251,3 +268,8 @@ config QIXIS_I2C_ACCESS
config HAS_FSL_DR_USB config HAS_FSL_DR_USB
def_bool y def_bool y
depends on USB_EHCI_HCD && PPC depends on USB_EHCI_HCD && PPC
config SYS_DPAA_FMAN
bool
endmenu

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@ -21,6 +21,3 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -fno-common
# Needed for relocation # Needed for relocation
LDFLAGS_FINAL += -pie --gc-sections LDFLAGS_FINAL += -pie --gc-sections
# Load address for standalone apps
CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000

View File

@ -476,9 +476,9 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
static void arc_ioc_setup(void) static void arc_ioc_setup(void)
{ {
/* IOC Aperture start is equal to DDR start */ /* IOC Aperture start is equal to DDR start */
unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; unsigned int ap_base = CFG_SYS_SDRAM_BASE;
/* IOC Aperture size is equal to DDR size */ /* IOC Aperture size is equal to DDR size */
long ap_size = CONFIG_SYS_SDRAM_SIZE; long ap_size = CFG_SYS_SDRAM_SIZE;
/* Unsupported configuration. See [ NOTE 2 ] for more details. */ /* Unsupported configuration. See [ NOTE 2 ] for more details. */
if (!slc_exists()) if (!slc_exists())

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@ -20,7 +20,7 @@ int arch_cpu_init(void)
timer_init(); timer_init();
gd->cpu_clk = get_board_sys_clk(); gd->cpu_clk = get_board_sys_clk();
gd->ram_size = CONFIG_SYS_SDRAM_SIZE; gd->ram_size = CFG_SYS_SDRAM_SIZE;
cache_init(); cache_init();

View File

@ -413,52 +413,6 @@ config ARM_SMCCC
This should be enabled if U-Boot needs to communicate with system This should be enabled if U-Boot needs to communicate with system
firmware (for example, PSCI) according to SMCCC. firmware (for example, PSCI) according to SMCCC.
config SEMIHOSTING
bool "Support ARM semihosting"
help
Semihosting is a method for a target to communicate with a host
debugger. It uses special instructions which the debugger will trap
on and interpret. This allows U-Boot to read/write files, print to
the console, and execute arbitrary commands on the host system.
Enabling this option will add support for reading and writing files
on the host system. If you don't have a debugger attached then trying
to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
config SEMIHOSTING_FALLBACK
bool "Recover gracefully when semihosting fails"
depends on SEMIHOSTING && ARM64
default y
help
Normally, if U-Boot makes a semihosting call and no debugger is
attached, then it will panic due to a synchronous abort
exception. This config adds an exception handler which will allow
U-Boot to recover. Say 'y' if unsure.
config SPL_SEMIHOSTING
bool "Support ARM semihosting in SPL"
depends on SPL
help
Semihosting is a method for a target to communicate with a host
debugger. It uses special instructions which the debugger will trap
on and interpret. This allows U-Boot to read/write files, print to
the console, and execute arbitrary commands on the host system.
Enabling this option will add support for reading and writing files
on the host system. If you don't have a debugger attached then trying
to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
config SPL_SEMIHOSTING_FALLBACK
bool "Recover gracefully when semihosting fails in SPL"
depends on SPL_SEMIHOSTING && ARM64
select ARMV8_SPL_EXCEPTION_VECTORS
default y
help
Normally, if U-Boot makes a semihosting call and no debugger is
attached, then it will panic due to a synchronous abort
exception. This config adds an exception handler which will allow
U-Boot to recover. Say 'y' if unsure.
config SYS_THUMB_BUILD config SYS_THUMB_BUILD
bool "Build U-Boot using the Thumb instruction set" bool "Build U-Boot using the Thumb instruction set"
depends on !ARM64 depends on !ARM64
@ -599,6 +553,9 @@ config ARM64_SUPPORT_AARCH32
help help
This ARM64 system supports AArch32 execution state. This ARM64 system supports AArch32 execution state.
config IPROC
bool
config S5P config S5P
def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
@ -632,7 +589,6 @@ config ARCH_KIRKWOOD
config ARCH_MVEBU config ARCH_MVEBU
bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)" bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
select DM select DM
select DM_ETH
select DM_SERIAL select DM_SERIAL
select DM_SPI select DM_SPI
select DM_SPI_FLASH select DM_SPI_FLASH
@ -640,7 +596,7 @@ config ARCH_MVEBU
select SPL_DM_SPI if SPL select SPL_DM_SPI if SPL
select SPL_DM_SPI_FLASH if SPL select SPL_DM_SPI_FLASH if SPL
select SPL_TIMER if SPL select SPL_TIMER if SPL
select TIMER select TIMER if !ARM64
select OF_CONTROL select OF_CONTROL
select OF_SEPARATE select OF_SEPARATE
select SPI select SPI
@ -705,6 +661,7 @@ config TARGET_BCMCYGNUS
bool "Support bcmcygnus" bool "Support bcmcygnus"
select CPU_V7A select CPU_V7A
select GPIO_EXTRA_HEADER select GPIO_EXTRA_HEADER
select IPROC
imply BCM_SF2_ETH imply BCM_SF2_ETH
imply BCM_SF2_ETH_GMAC imply BCM_SF2_ETH_GMAC
imply CMD_HASH imply CMD_HASH
@ -736,7 +693,6 @@ config ARCH_EXYNOS
select DM select DM
select DM_GPIO select DM_GPIO
select DM_I2C select DM_I2C
select DM_ETH
select DM_KEYBOARD select DM_KEYBOARD
select DM_SERIAL select DM_SERIAL
select DM_SPI select DM_SPI
@ -767,8 +723,9 @@ config ARCH_HIGHBANK
select CLK select CLK
select CLK_CCF select CLK_CCF
select AHCI select AHCI
select DM_ETH
select PHYS_64BIT select PHYS_64BIT
select TIMER
select SP804_TIMER
imply OF_HAS_PRIOR_STAGE imply OF_HAS_PRIOR_STAGE
config ARCH_INTEGRATOR config ARCH_INTEGRATOR
@ -962,6 +919,7 @@ config ARCH_MX7
select CPU_V7A select CPU_V7A
select GPIO_EXTRA_HEADER select GPIO_EXTRA_HEADER
select MACH_IMX select MACH_IMX
select MXC_GPT_HCLK
select SYS_FSL_HAS_SEC select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE select SYS_FSL_SEC_LE
@ -975,6 +933,7 @@ config ARCH_MX6
select CPU_V7A select CPU_V7A
select GPIO_EXTRA_HEADER select GPIO_EXTRA_HEADER
select MACH_IMX select MACH_IMX
select MXC_GPT_HCLK
select SYS_FSL_HAS_SEC select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE select SYS_FSL_SEC_LE
@ -1039,7 +998,6 @@ config ARCH_APPLE
config ARCH_OWL config ARCH_OWL
bool "Actions Semi OWL SoCs" bool "Actions Semi OWL SoCs"
select DM select DM
select DM_ETH
select DM_SERIAL select DM_SERIAL
select GPIO_EXTRA_HEADER select GPIO_EXTRA_HEADER
select OWL_SERIAL select OWL_SERIAL
@ -1133,17 +1091,59 @@ config ARCH_SOCFPGA
config ARCH_SUNXI config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs" bool "Support sunxi (Allwinner) SoCs"
select BOARD_SUNXI select BINMAN
select CMD_GPIO
select CMD_MMC if MMC
select CMD_USB if DISTRO_DEFAULTS && USB_HOST
select CLK
select DM
select DM_GPIO
select DM_I2C if I2C
select DM_SPI if SPI
select DM_SPI_FLASH if SPI
select DM_KEYBOARD
select DM_MMC if MMC
select DM_SCSI if SCSI
select DM_SERIAL
select GPIO_EXTRA_HEADER select GPIO_EXTRA_HEADER
select OF_BOARD_SETUP
select OF_CONTROL select OF_CONTROL
select OF_SEPARATE select OF_SEPARATE
select SPECIFY_CONSOLE_INDEX if SERIAL select PINCTRL
select SPECIFY_CONSOLE_INDEX
select SPL_SEPARATE_BSS if SPL
select SPL_STACK_R if SPL select SPL_STACK_R if SPL
select SPL_SYS_MALLOC_SIMPLE if SPL select SPL_SYS_MALLOC_SIMPLE if SPL
select SPL_SYS_THUMB_BUILD if !ARM64 select SPL_SYS_THUMB_BUILD if !ARM64
select SUNXI_GPIO
select SYS_NS16550
select SYS_THUMB_BUILD if !ARM64 select SYS_THUMB_BUILD if !ARM64
select USB if DISTRO_DEFAULTS
select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
select SPL_USE_TINY_PRINTF select SPL_USE_TINY_PRINTF
imply SPL_LOAD_FIT select USE_PREBOOT
select SYS_RELOC_GD_ENV_ADDR
imply BOARD_LATE_INIT
imply CMD_DM
imply CMD_GPT
imply CMD_UBI if MTD_RAW_NAND
imply DISTRO_DEFAULTS
imply FAT_WRITE
imply FIT
imply OF_LIBFDT_OVERLAY
imply PRE_CONSOLE_BUFFER
imply SPL_GPIO
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_MMC if MMC
imply SPL_POWER
imply SPL_SERIAL
imply SYSRESET
imply SYSRESET_WATCHDOG
imply SYSRESET_WATCHDOG_AUTO
imply USB_GADGET
imply WDT
config ARCH_U8500 config ARCH_U8500
bool "ST-Ericsson U8500 Series" bool "ST-Ericsson U8500 Series"
@ -1175,7 +1175,6 @@ config ARCH_VERSAL
select ARM64 select ARM64
select CLK select CLK
select DM select DM
select DM_ETH if NET
select DM_MMC if MMC select DM_MMC if MMC
select DM_SERIAL select DM_SERIAL
select GICV3 select GICV3
@ -1185,11 +1184,10 @@ config ARCH_VERSAL
imply ENV_VARS_UBOOT_RUNTIME_CONFIG imply ENV_VARS_UBOOT_RUNTIME_CONFIG
config ARCH_VERSAL_NET config ARCH_VERSAL_NET
bool "Support Xilinx Keystone Platform" bool "Support Xilinx Versal NET Platform"
select ARM64 select ARM64
select CLK select CLK
select DM select DM
select DM_ETH if NET
select DM_MMC if MMC select DM_MMC if MMC
select DM_SERIAL select DM_SERIAL
select OF_CONTROL select OF_CONTROL
@ -1200,6 +1198,7 @@ config ARCH_VF610
bool "Freescale Vybrid" bool "Freescale Vybrid"
select CPU_V7A select CPU_V7A
select GPIO_EXTRA_HEADER select GPIO_EXTRA_HEADER
select IOMUX_SHARE_CONF_REG
select MACH_IMX select MACH_IMX
select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_ESDHC111
imply CMD_MTDPARTS imply CMD_MTDPARTS
@ -1213,7 +1212,6 @@ config ARCH_ZYNQ
select CPU_V7A select CPU_V7A
select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
select DM select DM
select DM_ETH if NET
select DM_MMC if MMC select DM_MMC if MMC
select DM_SERIAL select DM_SERIAL
select DM_SPI select DM_SPI
@ -1243,7 +1241,6 @@ config ARCH_ZYNQMP_R5
select CLK select CLK
select CPU_V7R select CPU_V7R
select DM select DM
select DM_ETH if NET
select DM_MMC if MMC select DM_MMC if MMC
select DM_SERIAL select DM_SERIAL
select OF_CONTROL select OF_CONTROL
@ -1256,8 +1253,7 @@ config ARCH_ZYNQMP
select CLK select CLK
select DM select DM
select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
select DM_ETH if NET imply DM_MAILBOX
select DM_MAILBOX
select DM_MMC if MMC select DM_MMC if MMC
select DM_SERIAL select DM_SERIAL
select DM_SPI if SPI select DM_SPI if SPI
@ -1274,7 +1270,7 @@ config ARCH_ZYNQMP
imply SPL_FIRMWARE if SPL imply SPL_FIRMWARE if SPL
select SPL_SEPARATE_BSS if SPL select SPL_SEPARATE_BSS if SPL
select SUPPORT_SPL select SUPPORT_SPL
select ZYNQMP_IPI imply ZYNQMP_IPI if DM_MAILBOX
select SOC_DEVICE select SOC_DEVICE
imply BOARD_LATE_INIT imply BOARD_LATE_INIT
imply CMD_DM imply CMD_DM
@ -1607,6 +1603,7 @@ config TARGET_LS1021AQDS
select CPU_V7_HAS_NONSEC select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT select CPU_V7_HAS_VIRT
select LS1_DEEP_SLEEP select LS1_DEEP_SLEEP
select PEN_ADDR_BIG_ENDIAN
select SUPPORT_SPL select SUPPORT_SPL
select SYS_FSL_DDR select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE select FSL_DDR_INTERACTIVE
@ -1625,6 +1622,7 @@ config TARGET_LS1021ATWR
select CPU_V7_HAS_NONSEC select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT select CPU_V7_HAS_VIRT
select LS1_DEEP_SLEEP select LS1_DEEP_SLEEP
select PEN_ADDR_BIG_ENDIAN
select SUPPORT_SPL select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
select GPIO_EXTRA_HEADER select GPIO_EXTRA_HEADER
@ -1689,6 +1687,7 @@ config TARGET_LS1021AIOT
select CPU_V7A select CPU_V7A
select CPU_V7_HAS_NONSEC select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT select CPU_V7_HAS_VIRT
select PEN_ADDR_BIG_ENDIAN
select SUPPORT_SPL select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
select GPIO_EXTRA_HEADER select GPIO_EXTRA_HEADER
@ -1803,7 +1802,6 @@ config TARGET_SL28
select DM_I2C select DM_I2C
select DM_MMC select DM_MMC
select DM_SPI_FLASH select DM_SPI_FLASH
select DM_ETH
select DM_MDIO select DM_MDIO
select PCI select PCI
select DM_RNG select DM_RNG
@ -1840,7 +1838,6 @@ config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs" bool "Socionext UniPhier SoCs"
select BOARD_LATE_INIT select BOARD_LATE_INIT
select DM select DM
select DM_ETH
select DM_GPIO select DM_GPIO
select DM_I2C select DM_I2C
select DM_MMC select DM_MMC
@ -2026,7 +2023,6 @@ config TARGET_POMELO
select SCSI select SCSI
select DM_SCSI select DM_SCSI
select DM_SERIAL select DM_SERIAL
select DM_ETH if NET
imply CMD_PCI imply CMD_PCI
help help
Support for pomelo platform. Support for pomelo platform.
@ -2296,6 +2292,7 @@ source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig" source "board/isee/igep003x/Kconfig"
source "board/kontron/sl28/Kconfig" source "board/kontron/sl28/Kconfig"
source "board/myir/mys_6ulx/Kconfig" source "board/myir/mys_6ulx/Kconfig"
source "board/samsung/common/Kconfig"
source "board/siemens/common/Kconfig" source "board/siemens/common/Kconfig"
source "board/seeed/npi_imx6ull/Kconfig" source "board/seeed/npi_imx6ull/Kconfig"
source "board/socionext/developerbox/Kconfig" source "board/socionext/developerbox/Kconfig"

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@ -3,14 +3,6 @@
# (C) Copyright 2000-2002 # (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de. # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifndef CONFIG_STANDALONE_LOAD_ADDR
ifneq ($(CONFIG_ARCH_OMAP2PLUS),)
CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
else
CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
endif
endif
CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \ CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
-fstack-protector-strong -fstack-protector-strong
CFLAGS_EFI := -fpic -fshort-wchar CFLAGS_EFI := -fpic -fshort-wchar

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@ -18,7 +18,7 @@
#include <linux/linkage.h> #include <linux/linkage.h>
#ifndef CONFIG_SYS_PHY_UBOOT_BASE #ifndef CONFIG_SYS_PHY_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE #define CONFIG_SYS_PHY_UBOOT_BASE CFG_SYS_UBOOT_BASE
#endif #endif
/* /*

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@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += generic.o
obj-y += speed.o
obj-y += timer.o

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@ -1,76 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* arch/arm/mach-imx/generic.c
*
* author: Sascha Hauer
* Created: april 20th, 2004
* Copyright: Synertronixx GmbH
*
* Common code for i.MX machines
*/
#include <common.h>
#ifdef CONFIG_IMX
#include <asm/arch/imx-regs.h>
void imx_gpio_mode(int gpio_mode)
{
unsigned int pin = gpio_mode & GPIO_PIN_MASK;
unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5;
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10;
unsigned int tmp;
/* Pullup enable */
if(gpio_mode & GPIO_PUEN)
PUEN(port) |= (1<<pin);
else
PUEN(port) &= ~(1<<pin);
/* Data direction */
if(gpio_mode & GPIO_OUT)
DDIR(port) |= 1<<pin;
else
DDIR(port) &= ~(1<<pin);
/* Primary / alternate function */
if(gpio_mode & GPIO_AF)
GPR(port) |= (1<<pin);
else
GPR(port) &= ~(1<<pin);
/* use as gpio? */
if( ocr == 3 )
GIUS(port) |= (1<<pin);
else
GIUS(port) &= ~(1<<pin);
/* Output / input configuration */
/* FIXME: I'm not very sure about OCR and ICONF, someone
* should have a look over it
*/
if(pin<16) {
tmp = OCR1(port);
tmp &= ~( 3<<(pin*2));
tmp |= (ocr << (pin*2));
OCR1(port) = tmp;
if( gpio_mode & GPIO_AOUT )
ICONFA1(port) &= ~( 3<<(pin*2));
if( gpio_mode & GPIO_BOUT )
ICONFB1(port) &= ~( 3<<(pin*2));
} else {
tmp = OCR2(port);
tmp &= ~( 3<<((pin-16)*2));
tmp |= (ocr << ((pin-16)*2));
OCR2(port) = tmp;
if( gpio_mode & GPIO_AOUT )
ICONFA2(port) &= ~( 3<<((pin-16)*2));
if( gpio_mode & GPIO_BOUT )
ICONFB2(port) &= ~( 3<<((pin-16)*2));
}
}
#endif /* CONFIG_IMX */

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@ -1,86 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
*
* (c) 2004 Sascha Hauer <sascha@saschahauer.de>
*/
#include <common.h>
#if defined (CONFIG_IMX)
#include <clock_legacy.h>
#include <asm/arch/imx-regs.h>
/* ------------------------------------------------------------------------- */
/* NOTE: This describes the proper use of this file.
*
* get_board_sys_clk() should be defined as the input frequency of the PLL.
* SH FIXME: 16780000 in our case
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
*/
/* ------------------------------------------------------------------------- */
ulong get_systemPLLCLK(void)
{
/* FIXME: We assume System_SEL = 0 here */
u32 spctl0 = SPCTL0;
u32 mfi = (spctl0 >> 10) & 0xf;
u32 mfn = spctl0 & 0x3f;
u32 mfd = (spctl0 >> 16) & 0x3f;
u32 pd = (spctl0 >> 26) & 0xf;
mfi = mfi<=5 ? 5 : mfi;
return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
}
ulong get_mcuPLLCLK(void)
{
/* FIXME: We assume System_SEL = 0 here */
u32 mpctl0 = MPCTL0;
u32 mfi = (mpctl0 >> 10) & 0xf;
u32 mfn = mpctl0 & 0x3f;
u32 mfd = (mpctl0 >> 16) & 0x3f;
u32 pd = (mpctl0 >> 26) & 0xf;
mfi = mfi<=5 ? 5 : mfi;
return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
}
ulong get_FCLK(void)
{
return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK();
}
/* return HCLK frequency */
ulong get_HCLK(void)
{
u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
printf("bclkdiv: %d\n", bclkdiv);
return get_systemPLLCLK() / bclkdiv;
}
/* return BCLK frequency */
ulong get_BCLK(void)
{
return get_HCLK();
}
ulong get_PERCLK1(void)
{
return get_systemPLLCLK() / (((PCDR) & 0xf)+1);
}
ulong get_PERCLK2(void)
{
return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1);
}
ulong get_PERCLK3(void)
{
return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1);
}
#endif /* defined (CONFIG_IMX) */

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@ -1,100 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*/
#include <common.h>
#include <cpu_func.h>
#include <time.h>
#if defined (CONFIG_IMX)
#include <asm/arch/imx-regs.h>
#include <linux/delay.h>
int timer_init (void)
{
int i;
/* setup GP Timer 1 */
TCTL1 = TCTL_SWR;
for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
/* Reset the timer */
TCTL1 &= ~TCTL_TEN;
TCTL1 |= TCTL_TEN; /* Enable timer */
return (0);
}
/*
* timer without interrupts
*/
static ulong get_timer_masked (void)
{
return TCN1;
}
ulong get_timer (ulong base)
{
return get_timer_masked() - base;
}
void __udelay(unsigned long usec)
{
ulong endtime = get_timer_masked() + usec;
signed long diff;
do {
ulong now = get_timer_masked ();
diff = endtime - now;
} while (diff >= 0);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}
/*
* Reset the cpu by setting up the watchdog timer and let him time out
*/
void reset_cpu(void)
{
/* Disable watchdog and set Time-Out field to 0 */
WCR = 0x00000000;
/* Write Service Sequence */
WSR = 0x00005555;
WSR = 0x0000AAAA;
/* Enable watchdog */
WCR = 0x00000001;
while (1);
/*NOTREACHED*/
}
#endif /* defined (CONFIG_IMX) */

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@ -12,7 +12,6 @@ extra-y :=
endif endif
endif endif
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(if $(filter spear,$(SOC)),y) += spear/ obj-$(if $(filter spear,$(SOC)),y) += spear/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/

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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
obj-y += generic.o timer.o reset.o relocate.o

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@ -1,378 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
*/
#include <common.h>
#include <div64.h>
#include <net.h>
#include <netdev.h>
#include <vsprintf.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/mach-imx/sys_proto.h>
#ifdef CONFIG_MMC_MXC
#include <asm/arch/mxcmmc.h>
#endif
/*
* get the system pll clock in Hz
*
* mfi + mfn / (mfd +1)
* f = 2 * f_ref * --------------------
* pd + 1
*/
static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
{
unsigned int mfi = (pll >> 10) & 0xf;
unsigned int mfn = pll & 0x3ff;
unsigned int mfd = (pll >> 16) & 0x3ff;
unsigned int pd = (pll >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi;
return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
(mfd + 1) * (pd + 1));
}
static ulong clk_in_32k(void)
{
return 1024 * CONFIG_MX27_CLK32;
}
static ulong clk_in_26m(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
/* divide by 1.5 */
return 26000000 * 2 / 3;
} else {
return 26000000;
}
}
static ulong imx_get_mpllclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref;
if (cscr & CSCR_MCU_SEL)
fref = clk_in_26m();
else
fref = clk_in_32k();
return imx_decode_pll(readl(&pll->mpctl0), fref);
}
static ulong imx_get_armclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref = imx_get_mpllclk();
ulong div;
if (!(cscr & CSCR_ARM_SRC_MPLL))
fref = lldiv((fref * 2), 3);
div = ((cscr >> 12) & 0x3) + 1;
return lldiv(fref, div);
}
static ulong imx_get_ahbclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref = imx_get_mpllclk();
ulong div;
div = ((cscr >> 8) & 0x3) + 1;
return lldiv(fref * 2, 3 * div);
}
static __attribute__((unused)) ulong imx_get_spllclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref;
if (cscr & CSCR_SP_SEL)
fref = clk_in_26m();
else
fref = clk_in_32k();
return imx_decode_pll(readl(&pll->spctl0), fref);
}
static ulong imx_decode_perclk(ulong div)
{
return lldiv((imx_get_mpllclk() * 2), (div * 3));
}
static ulong imx_get_perclk1(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
}
static ulong imx_get_perclk2(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
}
static __attribute__((unused)) ulong imx_get_perclk3(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
}
static __attribute__((unused)) ulong imx_get_perclk4(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ARM_CLK:
return imx_get_armclk();
case MXC_I2C_CLK:
return imx_get_ahbclk()/2;
case MXC_UART_CLK:
return imx_get_perclk1();
case MXC_FEC_CLK:
return imx_get_ahbclk();
case MXC_ESDHC_CLK:
return imx_get_perclk2();
}
return -1;
}
u32 get_cpu_rev(void)
{
return MXC_CPU_MX27 << 12;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
char buf[32];
printf("CPU: Freescale i.MX27 at %s MHz\n\n",
strmhz(buf, imx_get_mpllclk()));
return 0;
}
#endif
int cpu_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_FEC_MXC)
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
/* enable FEC clock */
writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
return fecmxc_initialize(bis);
#else
return 0;
#endif
}
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(struct bd_info *bis)
{
#ifdef CONFIG_MMC_MXC
return mxc_mmc_init(bis);
#else
return 0;
#endif
}
void imx_gpio_mode(int gpio_mode)
{
struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
unsigned int pin = gpio_mode & GPIO_PIN_MASK;
unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
unsigned int tmp;
/* Pullup enable */
if (gpio_mode & GPIO_PUEN) {
writel(readl(&regs->port[port].puen) | (1 << pin),
&regs->port[port].puen);
} else {
writel(readl(&regs->port[port].puen) & ~(1 << pin),
&regs->port[port].puen);
}
/* Data direction */
if (gpio_mode & GPIO_OUT) {
writel(readl(&regs->port[port].gpio_dir) | 1 << pin,
&regs->port[port].gpio_dir);
} else {
writel(readl(&regs->port[port].gpio_dir) & ~(1 << pin),
&regs->port[port].gpio_dir);
}
/* Primary / alternate function */
if (gpio_mode & GPIO_AF) {
writel(readl(&regs->port[port].gpr) | (1 << pin),
&regs->port[port].gpr);
} else {
writel(readl(&regs->port[port].gpr) & ~(1 << pin),
&regs->port[port].gpr);
}
/* use as gpio? */
if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
writel(readl(&regs->port[port].gius) | (1 << pin),
&regs->port[port].gius);
} else {
writel(readl(&regs->port[port].gius) & ~(1 << pin),
&regs->port[port].gius);
}
/* Output / input configuration */
if (pin < 16) {
tmp = readl(&regs->port[port].ocr1);
tmp &= ~(3 << (pin * 2));
tmp |= (ocr << (pin * 2));
writel(tmp, &regs->port[port].ocr1);
writel(readl(&regs->port[port].iconfa1) & ~(3 << (pin * 2)),
&regs->port[port].iconfa1);
writel(readl(&regs->port[port].iconfa1) | aout << (pin * 2),
&regs->port[port].iconfa1);
writel(readl(&regs->port[port].iconfb1) & ~(3 << (pin * 2)),
&regs->port[port].iconfb1);
writel(readl(&regs->port[port].iconfb1) | bout << (pin * 2),
&regs->port[port].iconfb1);
} else {
pin -= 16;
tmp = readl(&regs->port[port].ocr2);
tmp &= ~(3 << (pin * 2));
tmp |= (ocr << (pin * 2));
writel(tmp, &regs->port[port].ocr2);
writel(readl(&regs->port[port].iconfa2) & ~(3 << (pin * 2)),
&regs->port[port].iconfa2);
writel(readl(&regs->port[port].iconfa2) | aout << (pin * 2),
&regs->port[port].iconfa2);
writel(readl(&regs->port[port].iconfb2) & ~(3 << (pin * 2)),
&regs->port[port].iconfb2);
writel(readl(&regs->port[port].iconfb2) | bout << (pin * 2),
&regs->port[port].iconfb2);
}
}
#ifdef CONFIG_MXC_UART
void mx27_uart1_init_pins(void)
{
int i;
unsigned int mode[] = {
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
#endif /* CONFIG_MXC_UART */
#ifdef CONFIG_FEC_MXC
void mx27_fec_init_pins(void)
{
int i;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_CLR,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
int i;
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
struct fuse_bank *bank = &iim->bank[0];
struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;
for (i = 0; i < 6; i++)
mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
}
#endif /* CONFIG_FEC_MXC */
#ifdef CONFIG_MMC_MXC
void mx27_sd1_init_pins(void)
{
int i;
unsigned int mode[] = {
PE18_PF_SD1_D0,
PE19_PF_SD1_D1,
PE20_PF_SD1_D2,
PE21_PF_SD1_D3,
PE22_PF_SD1_CMD,
PE23_PF_SD1_CLK,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
void mx27_sd2_init_pins(void)
{
int i;
unsigned int mode[] = {
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
PB6_PF_SD2_D2,
PB7_PF_SD2_D3,
PB8_PF_SD2_CMD,
PB9_PF_SD2_CLK,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
#endif /* CONFIG_MMC_MXC */

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@ -1,50 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - i.MX27-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
/*
* The i.MX27 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM. Therefore, vectors cannot be changed at all.
*
* However, these ROM-based vectors actually just perform indirect
* calls through pointers located in RAM at SoC-specific addresses,
* as follows:
*
* Offset Exception Use by ROM code
* 0x00000000 reset indirect branch to [0x00000014]
* 0x00000004 undefined instruction indirect branch to [0xfffffef0]
* 0x00000008 software interrupt indirect branch to [0xfffffef4]
* 0x0000000c prefetch abort indirect branch to [0xfffffef8]
* 0x00000010 data abort indirect branch to [0xfffffefc]
* 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000
* 0x00000018 IRQ indirect branch to [0xffffff00]
* 0x0000001c FIQ indirect branch to [0xffffff04]
*
* In order to initialize exceptions on i.MX27, we must copy U-Boot's
* indirect (not exception!) vector table into 0xfffffef0..0xffffff04
* taking care not to copy vectors number 5 (reserved exception).
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
ldr r1, =32 /* size of vector table */
add r0, r0, r1 /* skip to indirect table */
ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */
ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */
stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */
bx lr
ENDPROC(relocate_vectors)

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@ -1,41 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
void reset_cpu(void)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
writew(0x0000, &regs->wcr);
/* Write Service Sequence */
writew(0x5555, &regs->wsr);
writew(0xAAAA, &regs->wsr);
/* Enable watchdog */
writew(WCR_WDE, &regs->wcr);
while (1);
/*NOTREACHED*/
}

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@ -1,166 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*/
#include <common.h>
#include <div64.h>
#include <init.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/ptrace.h>
#include <linux/delay.h>
/* General purpose timers bitfields */
#define GPTCR_SWR (1 << 15) /* Software reset */
#define GPTCR_FRR (1 << 8) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
DECLARE_GLOBAL_DATA_PTR;
#define timestamp (gd->arch.tbl)
#define lastinc (gd->arch.lastinc)
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
* "tick" is internal timer period
*/
#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
/* ~0.4% error - measured with stop-watch on 100s boot-delay */
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, CONFIG_MX27_CLK32);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
time *= CONFIG_MX27_CLK32;
do_div(time, CONFIG_SYS_HZ);
return time;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us = us * CONFIG_MX27_CLK32 + 999999;
do_div(us, 1000000);
return us;
}
#else
/* ~2% error */
#define TICK_PER_TIME ((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \
CONFIG_SYS_HZ)
#define US_PER_TICK (1000000 / CONFIG_MX27_CLK32)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
do_div(tick, TICK_PER_TIME);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
return time * TICK_PER_TIME;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us += US_PER_TICK - 1;
do_div(us, US_PER_TICK);
return us;
}
#endif
/* nothing really to do with interrupts, just starts up a counter. */
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int timer_init(void)
{
int i;
struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
/* setup GP Timer 1 */
writel(GPTCR_SWR, &regs->gpt_tctl);
writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0);
writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1);
for (i = 0; i < 100; i++)
writel(0, &regs->gpt_tctl); /* We have no udelay by now */
writel(0, &regs->gpt_tprer); /* 32Khz */
/* Freerun Mode, PERCLK1 input */
writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
&regs->gpt_tctl);
writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl);
return 0;
}
unsigned long long get_ticks(void)
{
struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
ulong now = readl(&regs->gpt_tcn); /* current tick value */
if (now >= lastinc) {
/*
* normal mode (non roll)
* move stamp forward with absolut diff ticks
*/
timestamp += (now - lastinc);
} else {
/* we have rollover of incrementer */
timestamp += (0xFFFFFFFF - lastinc) + now;
}
lastinc = now;
return timestamp;
}
static ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
return tick_to_time(get_ticks());
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
/* delay x useconds AND preserve advance timstamp value */
void __udelay(unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
tmo = us_to_tick(usec);
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
ulong get_tbclk(void)
{
return CONFIG_MX27_CLK32;
}

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@ -95,7 +95,7 @@ flush_dcache:
mrc p15, 0, r0, c1, c0, 0 mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH #ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH
orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
#else #else
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */

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@ -75,15 +75,11 @@ config ARMV7_PSCI
choice choice
prompt "Supported PSCI version" prompt "Supported PSCI version"
depends on ARMV7_PSCI depends on ARMV7_PSCI
default ARMV7_PSCI_1_1 if MACH_SUN8I_A33 || MACH_SUN8I_H3
default ARMV7_PSCI_0_1 if ARCH_SUNXI default ARMV7_PSCI_0_1 if ARCH_SUNXI
default ARMV7_PSCI_1_0 default ARMV7_PSCI_1_0
help help
Select the supported PSCI version. Select the supported PSCI version.
config ARMV7_PSCI_1_1
bool "PSCI V1.1"
config ARMV7_PSCI_1_0 config ARMV7_PSCI_1_0
bool "PSCI V1.0" bool "PSCI V1.0"

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@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_HZ_CLOCK #ifndef CFG_SYS_HZ_CLOCK
static inline u32 read_cntfrq(void) static inline u32 read_cntfrq(void)
{ {
u32 frq; u32 frq;
@ -29,8 +29,8 @@ int timer_init(void)
gd->arch.tbl = 0; gd->arch.tbl = 0;
gd->arch.tbu = 0; gd->arch.tbu = 0;
#ifdef CONFIG_SYS_HZ_CLOCK #ifdef CFG_SYS_HZ_CLOCK
gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
#else #else
gd->arch.timer_rate_hz = read_cntfrq(); gd->arch.timer_rate_hz = read_cntfrq();
#endif #endif

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@ -1,6 +1,8 @@
config ARCH_LS1021A config ARCH_LS1021A
bool bool
select FSL_DEVICE_DISABLE
select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
select LS102XA_STREAM_ID
select SYS_FSL_DDR_BE if SYS_FSL_DDR select SYS_FSL_DDR_BE if SYS_FSL_DDR
select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
select SYS_FSL_IFC_BE select SYS_FSL_IFC_BE
@ -30,9 +32,15 @@ config ARCH_LS1021A
menu "LS102xA architecture" menu "LS102xA architecture"
depends on ARCH_LS1021A depends on ARCH_LS1021A
config FSL_DEVICE_DISABLE
bool
config LS1_DEEP_SLEEP config LS1_DEEP_SLEEP
bool "Deep sleep" bool "Deep sleep"
config LS102XA_STREAM_ID
bool
config MAX_CPUS config MAX_CPUS
int "Maximum number of CPUs permitted for LS102xA" int "Maximum number of CPUs permitted for LS102xA"
default 2 default 2
@ -43,6 +51,9 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores. in spin table to properly handle all cores.
config PEN_ADDR_BIG_ENDIAN
bool
config SYS_CCI400_OFFSET config SYS_CCI400_OFFSET
hex "Offset for CCI400 base" hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400 depends on SYS_FSL_HAS_CCI400

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@ -15,8 +15,8 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(struct sys_info *sys_info) void get_sys_info(struct sys_info *sys_info)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR); struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_LS1_CLK_ADDR);
unsigned int cpu; unsigned int cpu;
const u8 core_cplx_pll[6] = { const u8 core_cplx_pll[6] = {
[0] = 0, /* CC1 PPL / 1 */ [0] = 0, /* CC1 PPL / 1 */

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@ -168,18 +168,18 @@ static void mmu_setup(void)
/* Level 1 has 512 entries */ /* Level 1 has 512 entries */
for (i = 0; i < 512; i++) { for (i = 0; i < 512; i++) {
/* Mapping for PCIe 1 */ /* Mapping for PCIe 1 */
if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR && if (va_start >= CFG_SYS_PCIE1_VIRT_ADDR &&
va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR + va_start < (CFG_SYS_PCIE1_VIRT_ADDR +
CONFIG_SYS_PCIE_MMAP_SIZE)) CFG_SYS_PCIE_MMAP_SIZE))
set_pgsection(level1_table, i, set_pgsection(level1_table, i,
CONFIG_SYS_PCIE1_PHYS_BASE + va_start, CFG_SYS_PCIE1_PHYS_BASE + va_start,
MT_DEVICE_MEM); MT_DEVICE_MEM);
/* Mapping for PCIe 2 */ /* Mapping for PCIe 2 */
else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR && else if (va_start >= CFG_SYS_PCIE2_VIRT_ADDR &&
va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR + va_start < (CFG_SYS_PCIE2_VIRT_ADDR +
CONFIG_SYS_PCIE_MMAP_SIZE)) CFG_SYS_PCIE_MMAP_SIZE))
set_pgsection(level1_table, i, set_pgsection(level1_table, i,
CONFIG_SYS_PCIE2_PHYS_BASE + va_start, CFG_SYS_PCIE2_PHYS_BASE + va_start,
MT_DEVICE_MEM); MT_DEVICE_MEM);
else else
set_pgsection(level1_table, i, set_pgsection(level1_table, i,
@ -228,7 +228,7 @@ void enable_caches(void)
uint get_svr(void) uint get_svr(void)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
return in_be32(&gur->svr); return in_be32(&gur->svr);
} }
@ -237,7 +237,7 @@ uint get_svr(void)
int print_cpuinfo(void) int print_cpuinfo(void)
{ {
char buf1[32], buf2[32]; char buf1[32], buf2[32];
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr, major, minor, ver, i; unsigned int svr, major, minor, ver, i;
svr = in_be32(&gur->svr); svr = in_be32(&gur->svr);
@ -302,21 +302,12 @@ int cpu_mmc_init(struct bd_info *bis)
} }
#endif #endif
int cpu_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
tsec_standard_init(bis);
#endif
return 0;
}
int arch_cpu_init(void) int arch_cpu_init(void)
{ {
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base = void *rcpm2_base =
(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); (void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
u32 state; u32 state;
icache_enable(); icache_enable();
@ -355,7 +346,7 @@ int arch_cpu_init(void)
/* Set the address at which the secondary core starts from.*/ /* Set the address at which the secondary core starts from.*/
void smp_set_core_boot_addr(unsigned long addr, int corenr) void smp_set_core_boot_addr(unsigned long addr, int corenr)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->scratchrw[0], addr); out_be32(&gur->scratchrw[0], addr);
} }
@ -363,7 +354,7 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr)
/* Release the secondary core from holdoff state and kick it */ /* Release the secondary core from holdoff state and kick it */
void smp_kick_all_cpus(void) void smp_kick_all_cpus(void)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->brrl, 0x2); out_be32(&gur->brrl, 0x2);

View File

@ -92,7 +92,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
int off; int off;
int val; int val;
const char *sysclk_path; const char *sysclk_path;
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr; unsigned int svr;
svr = in_be32(&gur->svr); svr = in_be32(&gur->svr);
@ -105,7 +105,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
else { else {
ccsr_sec_t __iomem *sec; ccsr_sec_t __iomem *sec;
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
} }
#endif #endif
@ -125,7 +125,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_SYS_NS16550 #ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64", do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1); "clock-frequency", CFG_SYS_NS16550_CLK, 1);
#endif #endif
sysclk_path = fdt_get_alias(blob, "sysclk"); sysclk_path = fdt_get_alias(blob, "sysclk");
@ -183,7 +183,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
CONFIG_SYS_IFC_ADDR); CFG_SYS_IFC_ADDR);
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
#else #else
off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT, off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,

View File

@ -39,7 +39,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device) int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = in_be32(&gur->rcwsr[4]); u32 cfg = in_be32(&gur->rcwsr[4]);
int i; int i;
@ -74,7 +74,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u64 serdes_prtcl_map = 0; u64 serdes_prtcl_map = 0;
u32 cfg; u32 cfg;
int lane; int lane;
@ -103,14 +103,14 @@ void fsl_serdes_init(void)
#ifdef CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_SYS_FSL_SRDS_1
if (!(serdes1_prtcl_map & (1ULL << NONE))) if (!(serdes1_prtcl_map & (1ULL << NONE)))
serdes1_prtcl_map = serdes_init(FSL_SRDS_1, serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_SERDES_ADDR, CFG_SYS_FSL_SERDES_ADDR,
RCWSR4_SRDS1_PRTCL_MASK, RCWSR4_SRDS1_PRTCL_MASK,
RCWSR4_SRDS1_PRTCL_SHIFT); RCWSR4_SRDS1_PRTCL_SHIFT);
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_2 #ifdef CONFIG_SYS_FSL_SRDS_2
if (!(serdes2_prtcl_map & (1ULL << NONE))) if (!(serdes2_prtcl_map & (1ULL << NONE)))
serdes2_prtcl_map = serdes_init(FSL_SRDS_2, serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_SERDES_ADDR + CFG_SYS_FSL_SERDES_ADDR +
FSL_SRDS_2 * 0x1000, FSL_SRDS_2 * 0x1000,
RCWSR4_SRDS2_PRTCL_MASK, RCWSR4_SRDS2_PRTCL_MASK,
RCWSR4_SRDS2_PRTCL_SHIFT); RCWSR4_SRDS2_PRTCL_SHIFT);

View File

@ -29,9 +29,9 @@
*/ */
static void __secure ls1_save_ddr_head(void) static void __secure ls1_save_ddr_head(void)
{ {
const char *src = (const char *)CONFIG_SYS_SDRAM_BASE; const char *src = (const char *)CFG_SYS_SDRAM_BASE;
char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN); char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i; int i;
out_le32(&scfg->sparecr[2], dest); out_le32(&scfg->sparecr[2], dest);
@ -42,7 +42,7 @@ static void __secure ls1_save_ddr_head(void)
static void __secure ls1_fsm_setup(void) static void __secure ls1_fsm_setup(void)
{ {
void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR; void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001); out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
@ -57,8 +57,8 @@ static void __secure ls1_fsm_setup(void)
static void __secure ls1_deepsleep_irq_cfg(void) static void __secure ls1_deepsleep_irq_cfg(void)
{ {
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0; u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
/* Mask interrupts from GIC */ /* Mask interrupts from GIC */
@ -118,10 +118,10 @@ static void __secure ls1_delay(unsigned int loop)
static void __secure ls1_start_fsm(void) static void __secure ls1_start_fsm(void)
{ {
void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR; void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* Set HRSTCR */ /* Set HRSTCR */
setbits_be32(&scfg->hrstcr, 0x80000000); setbits_be32(&scfg->hrstcr, 0x80000000);
@ -155,9 +155,9 @@ static void __secure ls1_start_fsm(void)
static void __secure ls1_deep_sleep(u32 entry_point) static void __secure ls1_deep_sleep(u32 entry_point)
{ {
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE #ifdef QIXIS_BASE
u32 tmp; u32 tmp;
void *qixis_base = (void *)QIXIS_BASE; void *qixis_base = (void *)QIXIS_BASE;
@ -213,8 +213,8 @@ static void __secure ls1_deep_sleep(u32 entry_point)
#else #else
static void __secure ls1_sleep(void) static void __secure ls1_sleep(void)
{ {
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE #ifdef QIXIS_BASE
u32 tmp; u32 tmp;

View File

@ -129,8 +129,8 @@ psci_cpu_on:
mov r1, r4 mov r1, r4
@ Get DCFG base address @ Get DCFG base address
movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff) movw r4, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16) movt r4, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
@ Detect target CPU state @ Detect target CPU state
ldr r2, [r4, #DCFG_CCSR_BRR] ldr r2, [r4, #DCFG_CCSR_BRR]
@ -141,8 +141,8 @@ psci_cpu_on:
@ Reset target CPU @ Reset target CPU
@ Get SCFG base address @ Get SCFG base address
movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff) movw r0, #(CFG_SYS_FSL_SCFG_ADDR & 0xffff)
movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16) movt r0, #(CFG_SYS_FSL_SCFG_ADDR >> 16)
@ Enable CORE Soft Reset @ Enable CORE Soft Reset
movw r5, #0 movw r5, #0
@ -216,8 +216,8 @@ psci_affinity_info:
mov r1, r4 mov r1, r4
@ Get RCPM base address @ Get RCPM base address
movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff) movw r4, #(CFG_SYS_FSL_RCPM_ADDR & 0xffff)
movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16) movt r4, #(CFG_SYS_FSL_RCPM_ADDR >> 16)
mov r0, #PSCI_AFFINITY_LEVEL_ON mov r0, #PSCI_AFFINITY_LEVEL_ON
@ -236,8 +236,8 @@ out_affinity_info:
.globl psci_system_reset .globl psci_system_reset
psci_system_reset: psci_system_reset:
@ Get DCFG base address @ Get DCFG base address
movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff) movw r1, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16) movt r1, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
mov r2, #DCFG_CCSR_RSTCR_RESET_REQ mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
rev r2, r2 rev r2, r2

View File

@ -54,7 +54,7 @@ struct smmu_stream_id dev_stream_id[] = {
unsigned int get_soc_major_rev(void) unsigned int get_soc_major_rev(void)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr, major; unsigned int svr, major;
svr = in_be32(&gur->svr); svr = in_be32(&gur->svr);
@ -113,7 +113,7 @@ static void erratum_a008850_early(void)
/* part 1 of 2 */ /* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET); CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* disables propagation of barrier transactions to DDRC from CCI400 */ /* disables propagation of barrier transactions to DDRC from CCI400 */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
@ -129,7 +129,7 @@ void erratum_a008850_post(void)
/* part 2 of 2 */ /* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET); CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp; u32 tmp;
/* enable propagation of barrier transactions to DDRC from CCI400 */ /* enable propagation of barrier transactions to DDRC from CCI400 */
@ -161,7 +161,7 @@ void erratum_a010315(void)
int arch_soc_init(void) int arch_soc_init(void)
{ {
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET); CONFIG_SYS_CCI400_OFFSET);
unsigned int major; unsigned int major;

View File

@ -112,8 +112,8 @@ ENTRY(_do_nonsec_entry)
ENDPROC(_do_nonsec_entry) ENDPROC(_do_nonsec_entry)
.macro get_cbar_addr addr .macro get_cbar_addr addr
#ifdef CONFIG_ARM_GIC_BASE_ADDRESS #ifdef CFG_ARM_GIC_BASE_ADDRESS
ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS ldr \addr, =CFG_ARM_GIC_BASE_ADDRESS
#else #else
mrc p15, 4, \addr, c15, c0, 0 @ read CBAR mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
bfc \addr, #0, #15 @ clear reserved bits bfc \addr, #0, #15 @ clear reserved bits
@ -205,11 +205,11 @@ ENTRY(_nonsec_init)
bx lr bx lr
ENDPROC(_nonsec_init) ENDPROC(_nonsec_init)
#ifdef CONFIG_SMP_PEN_ADDR #ifdef CFG_SMP_PEN_ADDR
/* void __weak smp_waitloop(unsigned previous_address); */ /* void __weak smp_waitloop(unsigned previous_address); */
ENTRY(smp_waitloop) WEAK(smp_waitloop)
wfi wfi
ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address ldr r1, =CFG_SMP_PEN_ADDR @ load start address
ldr r1, [r1] ldr r1, [r1]
#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN #ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
rev r1, r1 rev r1, r1
@ -219,7 +219,6 @@ ENTRY(smp_waitloop)
mov r0, r1 mov r0, r1
b _do_nonsec_entry b _do_nonsec_entry
ENDPROC(smp_waitloop) ENDPROC(smp_waitloop)
.weak smp_waitloop
#endif #endif
.popsection .popsection

View File

@ -36,34 +36,32 @@ _psci_vectors:
b default_psci_vector @ irq b default_psci_vector @ irq
b psci_fiq_enter @ fiq b psci_fiq_enter @ fiq
ENTRY(psci_fiq_enter) WEAK(psci_fiq_enter)
movs pc, lr movs pc, lr
ENDPROC(psci_fiq_enter) ENDPROC(psci_fiq_enter)
.weak psci_fiq_enter
ENTRY(default_psci_vector) WEAK(default_psci_vector)
movs pc, lr movs pc, lr
ENDPROC(default_psci_vector) ENDPROC(default_psci_vector)
.weak default_psci_vector
ENTRY(psci_version) WEAK(psci_version)
ENTRY(psci_cpu_suspend) WEAK(psci_cpu_suspend)
ENTRY(psci_cpu_off) WEAK(psci_cpu_off)
ENTRY(psci_cpu_on) WEAK(psci_cpu_on)
ENTRY(psci_affinity_info) WEAK(psci_affinity_info)
ENTRY(psci_migrate) WEAK(psci_migrate)
ENTRY(psci_migrate_info_type) WEAK(psci_migrate_info_type)
ENTRY(psci_migrate_info_up_cpu) WEAK(psci_migrate_info_up_cpu)
ENTRY(psci_system_off) WEAK(psci_system_off)
ENTRY(psci_system_reset) WEAK(psci_system_reset)
ENTRY(psci_features) WEAK(psci_features)
ENTRY(psci_cpu_freeze) WEAK(psci_cpu_freeze)
ENTRY(psci_cpu_default_suspend) WEAK(psci_cpu_default_suspend)
ENTRY(psci_node_hw_state) WEAK(psci_node_hw_state)
ENTRY(psci_system_suspend) WEAK(psci_system_suspend)
ENTRY(psci_set_suspend_mode) WEAK(psci_set_suspend_mode)
ENTRY(psi_stat_residency) WEAK(psi_stat_residency)
ENTRY(psci_stat_count) WEAK(psci_stat_count)
mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented) mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented)
mov pc, lr mov pc, lr
ENDPROC(psci_stat_count) ENDPROC(psci_stat_count)
@ -84,24 +82,6 @@ ENDPROC(psci_cpu_on)
ENDPROC(psci_cpu_off) ENDPROC(psci_cpu_off)
ENDPROC(psci_cpu_suspend) ENDPROC(psci_cpu_suspend)
ENDPROC(psci_version) ENDPROC(psci_version)
.weak psci_version
.weak psci_cpu_suspend
.weak psci_cpu_off
.weak psci_cpu_on
.weak psci_affinity_info
.weak psci_migrate
.weak psci_migrate_info_type
.weak psci_migrate_info_up_cpu
.weak psci_system_off
.weak psci_system_reset
.weak psci_features
.weak psci_cpu_freeze
.weak psci_cpu_default_suspend
.weak psci_node_hw_state
.weak psci_system_suspend
.weak psci_set_suspend_mode
.weak psi_stat_residency
.weak psci_stat_count
_psci_table: _psci_table:
.word ARM_PSCI_FN_CPU_SUSPEND .word ARM_PSCI_FN_CPU_SUSPEND
@ -179,12 +159,11 @@ _smc_psci:
movs pc, lr @ Return to the kernel movs pc, lr @ Return to the kernel
@ Requires dense and single-cluster CPU ID space @ Requires dense and single-cluster CPU ID space
ENTRY(psci_get_cpu_id) WEAK(psci_get_cpu_id)
mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */ mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
and r0, r0, #0xff /* return CPU ID in cluster */ and r0, r0, #0xff /* return CPU ID in cluster */
bx lr bx lr
ENDPROC(psci_get_cpu_id) ENDPROC(psci_get_cpu_id)
.weak psci_get_cpu_id
/* Imported from Linux kernel */ /* Imported from Linux kernel */
ENTRY(psci_v7_flush_dcache_all) ENTRY(psci_v7_flush_dcache_all)
@ -236,7 +215,7 @@ finished:
bx lr bx lr
ENDPROC(psci_v7_flush_dcache_all) ENDPROC(psci_v7_flush_dcache_all)
ENTRY(psci_disable_smp) WEAK(psci_disable_smp)
mrc p15, 0, r0, c1, c0, 1 @ ACTLR mrc p15, 0, r0, c1, c0, 1 @ ACTLR
bic r0, r0, #(1 << 6) @ Clear SMP bit bic r0, r0, #(1 << 6) @ Clear SMP bit
mcr p15, 0, r0, c1, c0, 1 @ ACTLR mcr p15, 0, r0, c1, c0, 1 @ ACTLR
@ -244,16 +223,14 @@ ENTRY(psci_disable_smp)
dsb dsb
bx lr bx lr
ENDPROC(psci_disable_smp) ENDPROC(psci_disable_smp)
.weak psci_disable_smp
ENTRY(psci_enable_smp) WEAK(psci_enable_smp)
mrc p15, 0, r0, c1, c0, 1 @ ACTLR mrc p15, 0, r0, c1, c0, 1 @ ACTLR
orr r0, r0, #(1 << 6) @ Set SMP bit orr r0, r0, #(1 << 6) @ Set SMP bit
mcr p15, 0, r0, c1, c0, 1 @ ACTLR mcr p15, 0, r0, c1, c0, 1 @ ACTLR
isb isb
bx lr bx lr
ENDPROC(psci_enable_smp) ENDPROC(psci_enable_smp)
.weak psci_enable_smp
ENTRY(psci_cpu_off_common) ENTRY(psci_cpu_off_common)
push {lr} push {lr}
@ -316,15 +293,13 @@ ENTRY(psci_stack_setup)
bx r6 bx r6
ENDPROC(psci_stack_setup) ENDPROC(psci_stack_setup)
ENTRY(psci_arch_init) WEAK(psci_arch_init)
mov pc, lr mov pc, lr
ENDPROC(psci_arch_init) ENDPROC(psci_arch_init)
.weak psci_arch_init
ENTRY(psci_arch_cpu_entry) WEAK(psci_arch_cpu_entry)
mov pc, lr mov pc, lr
ENDPROC(psci_arch_cpu_entry) ENDPROC(psci_arch_cpu_entry)
.weak psci_arch_cpu_entry
ENTRY(psci_cpu_entry) ENTRY(psci_cpu_entry)
bl psci_enable_smp bl psci_enable_smp

View File

@ -7,12 +7,11 @@
#include <common.h> #include <common.h>
#include <errno.h> #include <errno.h>
#include <pwm.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/pwm.h> #include <asm/arch/pwm.h>
#include <asm/arch/clk.h> #include <asm/arch/clk.h>
int pwm_enable(int pwm_id) int s5p_pwm_enable(int pwm_id)
{ {
const struct s5p_timer *pwm = const struct s5p_timer *pwm =
#if defined(CONFIG_ARCH_NEXELL) #if defined(CONFIG_ARCH_NEXELL)
@ -30,7 +29,7 @@ int pwm_enable(int pwm_id)
return 0; return 0;
} }
void pwm_disable(int pwm_id) void s5p_pwm_disable(int pwm_id)
{ {
const struct s5p_timer *pwm = const struct s5p_timer *pwm =
#if defined(CONFIG_ARCH_NEXELL) #if defined(CONFIG_ARCH_NEXELL)
@ -92,7 +91,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
#define NS_IN_SEC 1000000000UL #define NS_IN_SEC 1000000000UL
int pwm_config(int pwm_id, int duty_ns, int period_ns) int s5p_pwm_config(int pwm_id, int duty_ns, int period_ns)
{ {
const struct s5p_timer *pwm = const struct s5p_timer *pwm =
#if defined(CONFIG_ARCH_NEXELL) #if defined(CONFIG_ARCH_NEXELL)
@ -157,7 +156,7 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns)
return 0; return 0;
} }
int pwm_init(int pwm_id, int div, int invert) int s5p_pwm_init(int pwm_id, int div, int invert)
{ {
u32 val; u32 val;
const struct s5p_timer *pwm = const struct s5p_timer *pwm =
@ -219,7 +218,7 @@ int pwm_init(int pwm_id, int div, int invert)
val |= TCON_INVERTER(pwm_id); val |= TCON_INVERTER(pwm_id);
writel(val, &pwm->tcon); writel(val, &pwm->tcon);
pwm_enable(pwm_id); s5p_pwm_enable(pwm_id);
return 0; return 0;
} }

View File

@ -16,10 +16,6 @@
#include <asm/arch/clk.h> #include <asm/arch/clk.h>
#include <linux/delay.h> #include <linux/delay.h>
/* Use the old PWM interface for now */
#undef CONFIG_DM_PWM
#include <pwm.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
unsigned long get_current_tick(void); unsigned long get_current_tick(void);
@ -49,9 +45,9 @@ static unsigned long timer_get_us_down(void)
int timer_init(void) int timer_init(void)
{ {
/* PWM Timer 4 */ /* PWM Timer 4 */
pwm_init(4, MUX_DIV_4, 0); s5p_pwm_init(4, MUX_DIV_4, 0);
pwm_config(4, 100000, 100000); s5p_pwm_config(4, 100000, 100000);
pwm_enable(4); s5p_pwm_enable(4);
/* Use this as the current monotonic time in us */ /* Use this as the current monotonic time in us */
gd->arch.timer_reset_value = 0; gd->arch.timer_reset_value = 0;

View File

@ -13,10 +13,8 @@
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/nexell.h> #include <asm/arch/nexell.h>
#include <asm/arch/clk.h> #include <asm/arch/clk.h>
#include <asm/arch/reset.h>
#include <asm/arch/tieoff.h> #include <asm/arch/tieoff.h>
#include <cpu_func.h> #include <cpu_func.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -45,39 +43,12 @@ static void cpu_soc_init(void)
nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1); nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1);
} }
#ifdef CONFIG_PL011_SERIAL
static void serial_device_init(void)
{
char dev[10];
int id;
sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX);
id = RESET_ID_UART0 + CONFIG_CONS_INDEX;
struct clk *clk = clk_get((const char *)dev);
/* reset control: Low active ___|--- */
nx_rstcon_setrst(id, RSTCON_ASSERT);
udelay(10);
nx_rstcon_setrst(id, RSTCON_NEGATE);
udelay(10);
/* set clock */
clk_disable(clk);
clk_set_rate(clk, CONFIG_PL011_CLOCK);
clk_enable(clk);
}
#endif
int arch_cpu_init(void) int arch_cpu_init(void)
{ {
flush_dcache_all(); flush_dcache_all();
cpu_soc_init(); cpu_soc_init();
clk_init(); clk_init();
if (IS_ENABLED(CONFIG_PL011_SERIAL))
serial_device_init();
return 0; return 0;
} }

View File

@ -151,16 +151,14 @@ ENDPROC(c_runtime_cpu_setup)
* Don't save anything to stack even if compiled with -O0 * Don't save anything to stack even if compiled with -O0
* *
*************************************************************************/ *************************************************************************/
ENTRY(save_boot_params) WEAK(save_boot_params)
b save_boot_params_ret @ back to my caller b save_boot_params_ret @ back to my caller
ENDPROC(save_boot_params) ENDPROC(save_boot_params)
.weak save_boot_params
#ifdef CONFIG_ARMV7_LPAE #ifdef CONFIG_ARMV7_LPAE
ENTRY(switch_to_hypervisor) WEAK(switch_to_hypervisor)
b switch_to_hypervisor_ret b switch_to_hypervisor_ret
ENDPROC(switch_to_hypervisor) ENDPROC(switch_to_hypervisor)
.weak switch_to_hypervisor
#endif #endif
/************************************************************************* /*************************************************************************

View File

@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR); (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) #define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) #define GPT_RESOLUTION (CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -67,7 +67,7 @@ void __udelay(unsigned long usec)
{ {
ulong tmo; ulong tmo;
ulong start = get_timer_masked(); ulong start = get_timer_masked();
ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100); ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100);
ulong rndoff; ulong rndoff;
rndoff = (usec % 10) ? 1 : 0; rndoff = (usec % 10) ? 1 : 0;

View File

@ -13,12 +13,8 @@ obj-$(CONFIG_MACH_SUN6I) += sram.o
obj-$(CONFIG_MACH_SUN8I) += sram.o obj-$(CONFIG_MACH_SUN8I) += sram.o
ifndef CONFIG_SPL_BUILD ifndef CONFIG_SPL_BUILD
ifneq ($(CONFIG_MACH_SUN8I_A33)$(CONFIG_MACH_SUN8I_H3),)
obj-$(CONFIG_ARMV7_PSCI) += psci-scpi.o
else
obj-$(CONFIG_ARMV7_PSCI) += psci.o obj-$(CONFIG_ARMV7_PSCI) += psci.o
endif endif
endif
ifdef CONFIG_SPL_BUILD ifdef CONFIG_SPL_BUILD
obj-y += fel_utils.o obj-y += fel_utils.o

View File

@ -1,455 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
* Copyright (C) 2018-2021 Samuel Holland <samuel@sholland.org>
*/
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/cpucfg.h>
#include <asm/armv7.h>
#include <asm/gic.h>
#include <asm/io.h>
#include <asm/psci.h>
#include <asm/secure.h>
#include <asm/system.h>
#define GICD_BASE (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
#define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
#define HW_ON 0
#define HW_OFF 1
#define HW_STANDBY 2
#define MPIDR_AFFLVL0(mpidr) (mpidr & 0xf)
#define MPIDR_AFFLVL1(mpidr) (mpidr >> 8 & 0xf)
#if defined(CONFIG_MACH_SUN8I_H3)
#define SCPI_SHMEM_BASE 0x0004be00
#else
#define SCPI_SHMEM_BASE 0x00053e00
#endif
#define SCPI_SHMEM ((struct scpi_shmem *)SCPI_SHMEM_BASE)
#define SCPI_RX_CHANNEL 1
#define SCPI_TX_CHANNEL 0
#define SCPI_VIRTUAL_CHANNEL BIT(0)
#define SCPI_MESSAGE_SIZE 0x100
#define SCPI_PAYLOAD_SIZE (SCPI_MESSAGE_SIZE - sizeof(struct scpi_header))
#define SUNXI_MSGBOX_BASE 0x01c17000
#define REMOTE_IRQ_STAT_REG (SUNXI_MSGBOX_BASE + 0x0050)
#define LOCAL_IRQ_STAT_REG (SUNXI_MSGBOX_BASE + 0x0070)
#define MSG_STAT_REG(n) (SUNXI_MSGBOX_BASE + 0x0140 + 0x4 * (n))
#define MSG_DATA_REG(n) (SUNXI_MSGBOX_BASE + 0x0180 + 0x4 * (n))
#define RX_IRQ(n) BIT(0 + 2 * (n))
#define TX_IRQ(n) BIT(1 + 2 * (n))
enum {
CORE_POWER_LEVEL = 0,
CLUSTER_POWER_LEVEL = 1,
CSS_POWER_LEVEL = 2,
};
enum {
SCPI_CMD_SCP_READY = 0x01,
SCPI_CMD_SET_CSS_POWER_STATE = 0x03,
SCPI_CMD_GET_CSS_POWER_STATE = 0x04,
SCPI_CMD_SET_SYS_POWER_STATE = 0x05,
};
enum {
SCPI_E_OK = 0,
SCPI_E_PARAM = 1,
SCPI_E_ALIGN = 2,
SCPI_E_SIZE = 3,
SCPI_E_HANDLER = 4,
SCPI_E_ACCESS = 5,
SCPI_E_RANGE = 6,
SCPI_E_TIMEOUT = 7,
SCPI_E_NOMEM = 8,
SCPI_E_PWRSTATE = 9,
SCPI_E_SUPPORT = 10,
SCPI_E_DEVICE = 11,
SCPI_E_BUSY = 12,
SCPI_E_OS = 13,
SCPI_E_DATA = 14,
SCPI_E_STATE = 15,
};
enum {
SCPI_POWER_ON = 0x00,
SCPI_POWER_RETENTION = 0x01,
SCPI_POWER_OFF = 0x03,
};
enum {
SCPI_SYSTEM_SHUTDOWN = 0x00,
SCPI_SYSTEM_REBOOT = 0x01,
SCPI_SYSTEM_RESET = 0x02,
};
struct scpi_header {
u8 command;
u8 sender;
u16 size;
u32 status;
};
struct scpi_message {
struct scpi_header header;
u8 payload[SCPI_PAYLOAD_SIZE];
};
struct scpi_shmem {
struct scpi_message rx;
struct scpi_message tx;
};
static bool __secure_data gic_dist_init;
static u32 __secure_data lock;
static inline u32 __secure read_mpidr(void)
{
u32 val;
asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
return val;
}
static void __secure scpi_begin_command(void)
{
u32 mpidr = read_mpidr();
do {
while (readl(&lock));
writel(mpidr, &lock);
dsb();
} while (readl(&lock) != mpidr);
while (readl(REMOTE_IRQ_STAT_REG) & RX_IRQ(SCPI_TX_CHANNEL));
}
static void __secure scpi_send_command(void)
{
writel(SCPI_VIRTUAL_CHANNEL, MSG_DATA_REG(SCPI_TX_CHANNEL));
}
static void __secure scpi_wait_response(void)
{
while (!readl(MSG_STAT_REG(SCPI_RX_CHANNEL)));
}
static void __secure scpi_end_command(void)
{
while (readl(MSG_STAT_REG(SCPI_RX_CHANNEL)))
readl(MSG_DATA_REG(SCPI_RX_CHANNEL));
writel(RX_IRQ(SCPI_RX_CHANNEL), LOCAL_IRQ_STAT_REG);
writel(0, &lock);
}
static void __secure scpi_set_css_power_state(u32 target_cpu, u32 core_state,
u32 cluster_state, u32 css_state)
{
struct scpi_shmem *shmem = SCPI_SHMEM;
scpi_begin_command();
shmem->tx.header.command = SCPI_CMD_SET_CSS_POWER_STATE;
shmem->tx.header.size = 4;
shmem->tx.payload[0] = target_cpu >> 4 | target_cpu;
shmem->tx.payload[1] = cluster_state << 4 | core_state;
shmem->tx.payload[2] = css_state;
shmem->tx.payload[3] = 0;
scpi_send_command();
scpi_end_command();
}
static s32 __secure scpi_get_css_power_state(u32 target_cpu, u8 *core_states,
u8 *cluster_state)
{
struct scpi_shmem *shmem = SCPI_SHMEM;
u32 cluster = MPIDR_AFFLVL1(target_cpu);
u32 offset;
s32 ret;
scpi_begin_command();
shmem->tx.header.command = SCPI_CMD_GET_CSS_POWER_STATE;
shmem->tx.header.size = 0;
scpi_send_command();
scpi_wait_response();
for (offset = 0; offset < shmem->rx.header.size; offset += 2) {
if ((shmem->rx.payload[offset] & 0xf) == cluster) {
*cluster_state = shmem->rx.payload[offset+0] >> 4;
*core_states = shmem->rx.payload[offset+1];
break;
}
}
ret = shmem->rx.header.status;
scpi_end_command();
return ret;
}
static s32 __secure scpi_set_sys_power_state(u32 sys_state)
{
struct scpi_shmem *shmem = SCPI_SHMEM;
s32 ret;
scpi_begin_command();
shmem->tx.header.command = SCPI_CMD_SET_SYS_POWER_STATE;
shmem->tx.header.size = 1;
shmem->tx.payload[0] = sys_state;
scpi_send_command();
scpi_wait_response();
ret = shmem->rx.header.status;
scpi_end_command();
return ret;
}
void psci_enable_smp(void);
static s32 __secure psci_suspend_common(u32 pc, u32 context_id, u32 core_state,
u32 cluster_state, u32 css_state)
{
u32 target_cpu = read_mpidr();
if (core_state == SCPI_POWER_OFF)
psci_save(MPIDR_AFFLVL0(target_cpu), pc, context_id);
if (css_state == SCPI_POWER_OFF)
gic_dist_init = true;
scpi_set_css_power_state(target_cpu, core_state,
cluster_state, css_state);
psci_cpu_off_common();
wfi();
psci_enable_smp();
return ARM_PSCI_RET_SUCCESS;
}
u32 __secure psci_version(void)
{
return ARM_PSCI_VER_1_1;
}
s32 __secure psci_cpu_suspend(u32 __always_unused function_id,
u32 power_state, u32 pc, u32 context_id)
{
return psci_suspend_common(pc, context_id,
power_state >> 0 & 0xf,
power_state >> 4 & 0xf,
power_state >> 8 & 0xf);
}
s32 __secure psci_cpu_off(void)
{
u32 pc = 0, context_id = 0;
return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
SCPI_POWER_OFF, SCPI_POWER_ON);
}
s32 __secure psci_cpu_on(u32 __always_unused function_id,
u32 target_cpu, u32 pc, u32 context_id)
{
psci_save(MPIDR_AFFLVL0(target_cpu), pc, context_id);
scpi_set_css_power_state(target_cpu, SCPI_POWER_ON,
SCPI_POWER_ON, SCPI_POWER_ON);
return ARM_PSCI_RET_SUCCESS;
}
s32 __secure psci_affinity_info(u32 function_id,
u32 target_cpu, u32 power_level)
{
if (power_level != CORE_POWER_LEVEL)
return ARM_PSCI_RET_INVAL;
/* This happens to have the same HW_ON/HW_OFF encoding. */
return psci_node_hw_state(function_id, target_cpu, power_level);
}
void __secure psci_system_off(void)
{
scpi_set_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
/* Wait to be turned off. */
for (;;) wfi();
}
void __secure psci_system_reset(void)
{
scpi_set_sys_power_state(SCPI_SYSTEM_REBOOT);
/* Wait to be turned off. */
for (;;) wfi();
}
s32 __secure psci_features(u32 __always_unused function_id,
u32 psci_fid)
{
switch (psci_fid) {
case ARM_PSCI_0_2_FN_PSCI_VERSION:
case ARM_PSCI_0_2_FN_CPU_SUSPEND:
case ARM_PSCI_0_2_FN_CPU_OFF:
case ARM_PSCI_0_2_FN_CPU_ON:
case ARM_PSCI_0_2_FN_AFFINITY_INFO:
case ARM_PSCI_0_2_FN_SYSTEM_OFF:
case ARM_PSCI_0_2_FN_SYSTEM_RESET:
case ARM_PSCI_1_0_FN_PSCI_FEATURES:
case ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND:
case ARM_PSCI_1_0_FN_NODE_HW_STATE:
case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND:
case ARM_PSCI_1_1_FN_SYSTEM_RESET2:
return ARM_PSCI_RET_SUCCESS;
default:
return ARM_PSCI_RET_NI;
}
}
s32 __secure psci_cpu_default_suspend(u32 __always_unused function_id,
u32 pc, u32 context_id)
{
return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
SCPI_POWER_OFF, SCPI_POWER_RETENTION);
}
s32 __secure psci_node_hw_state(u32 __always_unused function_id,
u32 target_cpu, u32 power_level)
{
u32 core = MPIDR_AFFLVL0(target_cpu);
u8 core_states, cluster_state;
if (power_level >= CSS_POWER_LEVEL)
return HW_ON;
if (scpi_get_css_power_state(target_cpu, &core_states, &cluster_state))
return ARM_PSCI_RET_NI;
if (power_level == CLUSTER_POWER_LEVEL) {
if (cluster_state == SCPI_POWER_ON)
return HW_ON;
if (cluster_state < SCPI_POWER_OFF)
return HW_STANDBY;
return HW_OFF;
}
return (core_states & BIT(core)) ? HW_ON : HW_OFF;
}
s32 __secure psci_system_suspend(u32 __always_unused function_id,
u32 pc, u32 context_id)
{
return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
SCPI_POWER_OFF, SCPI_POWER_OFF);
}
s32 __secure psci_system_reset2(u32 __always_unused function_id,
u32 reset_type, u32 cookie)
{
s32 ret;
if (reset_type)
return ARM_PSCI_RET_INVAL;
ret = scpi_set_sys_power_state(SCPI_SYSTEM_RESET);
if (ret)
return ARM_PSCI_RET_INVAL;
/* Wait to be turned off. */
for (;;) wfi();
}
/*
* R40 is different from other single cluster SoCs. The secondary core
* entry address register is in the SRAM controller address range.
*/
#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
#ifdef CONFIG_MACH_SUN8I_R40
/* secondary core entry address is programmed differently on R40 */
static void __secure sunxi_set_entry_address(void *entry)
{
writel((u32)entry,
SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
}
#else
static void __secure sunxi_set_entry_address(void *entry)
{
struct sunxi_cpucfg_reg *cpucfg =
(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
writel((u32)entry, &cpucfg->priv0);
#ifdef CONFIG_MACH_SUN8I_H3
/* Redirect CPU 0 to the secure monitor via the resume shim. */
writel(0x16aaefe8, &cpucfg->super_standy_flag);
writel(0xaa16efe8, &cpucfg->super_standy_flag);
writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
#endif
}
#endif
void __secure psci_arch_init(void)
{
static bool __secure_data one_time_init = true;
if (one_time_init) {
/* Set secondary core power-on PC. */
sunxi_set_entry_address(psci_cpu_entry);
/* Wait for the SCP firmware to boot. */
scpi_begin_command();
scpi_wait_response();
scpi_end_command();
one_time_init = false;
}
/*
* Copied from arch/arm/cpu/armv7/virt-v7.c
* See also gic_resume() in arch/arm/mach-imx/mx7/psci-mx7.c
*/
if (gic_dist_init) {
u32 i, itlinesnr;
/* enable the GIC distributor */
writel(readl(GICD_BASE + GICD_CTLR) | 0x03, GICD_BASE + GICD_CTLR);
/* TYPER[4:0] contains an encoded number of available interrupts */
itlinesnr = readl(GICD_BASE + GICD_TYPER) & 0x1f;
/* set all bits in the GIC group registers to one to allow access
* from non-secure state. The first 32 interrupts are private per
* CPU and will be set later when enabling the GIC for each core
*/
for (i = 1; i <= itlinesnr; i++)
writel((unsigned)-1, GICD_BASE + GICD_IGROUPRn + 4 * i);
gic_dist_init = false;
}
/* Be cool with non-secure. */
writel(0xff, GICC_BASE + GICC_PMR);
}

View File

@ -10,7 +10,6 @@
#include <common.h> #include <common.h>
#include <asm/cache.h> #include <asm/cache.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h> #include <asm/arch/cpu.h>
#include <asm/arch/cpucfg.h> #include <asm/arch/cpucfg.h>
#include <asm/arch/prcm.h> #include <asm/arch/prcm.h>
@ -39,15 +38,6 @@
#define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4) #define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4)
#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc) #define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
static inline u32 __secure cp15_read_mpidr(void)
{
u32 val;
asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
return val;
}
static void __secure cp15_write_cntp_tval(u32 tval) static void __secure cp15_write_cntp_tval(u32 tval)
{ {
asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval)); asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
@ -142,13 +132,6 @@ static void __secure sunxi_set_entry_address(void *entry)
(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
writel((u32)entry, &cpucfg->priv0); writel((u32)entry, &cpucfg->priv0);
#ifdef CONFIG_MACH_SUN8I_H3
/* Redirect CPU 0 to the secure monitor via the resume shim. */
writel(0x16aaefe8, &cpucfg->super_standy_flag);
writel(0xaa16efe8, &cpucfg->super_standy_flag);
writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
#endif
} }
#endif #endif
@ -263,12 +246,9 @@ out:
int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc, int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
u32 context_id) u32 context_id)
{ {
struct sunxi_ccm_reg *ccu = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_cpucfg_reg *cpucfg = struct sunxi_cpucfg_reg *cpucfg =
(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
u32 cpu = (mpidr & 0x3); u32 cpu = (mpidr & 0x3);
u32 cpu_clk;
u32 bus_clk;
/* store target PC and context id */ /* store target PC and context id */
psci_save(cpu, pc, context_id); psci_save(cpu, pc, context_id);
@ -285,32 +265,12 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
/* Lock CPU (Disable external debug access) */ /* Lock CPU (Disable external debug access) */
clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
/* Save registers that will be clobbered by the BROM. */
cpu_clk = readl(&ccu->cpu_axi_cfg);
bus_clk = readl(&ccu->ahb1_apb1_div);
/* Bypass PLL_PERIPH0 so AHB1 frequency does not spike. */
setbits_le32(&ccu->pll6_cfg, BIT(25));
}
/* Power up target CPU */ /* Power up target CPU */
sunxi_cpu_set_power(cpu, true); sunxi_cpu_set_power(cpu, true);
/* De-assert reset on target CPU */ /* De-assert reset on target CPU */
writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst); writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
/* Spin until the BROM has clobbered the clock registers. */
while (readl(&ccu->ahb1_apb1_div) != 0x00001100);
/* Restore the registers and turn off PLL_PERIPH0 bypass. */
writel(cpu_clk, &ccu->cpu_axi_cfg);
writel(bus_clk, &ccu->ahb1_apb1_div);
clrbits_le32(&ccu->pll6_cfg, BIT(25));
}
/* Unlock CPU (Disable external debug access) */ /* Unlock CPU (Disable external debug access) */
setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
@ -321,14 +281,9 @@ s32 __secure psci_cpu_off(void)
{ {
psci_cpu_off_common(); psci_cpu_off_common();
if (cp15_read_mpidr() & 3) {
/* Ask CPU0 via SGI15 to pull the rug... */ /* Ask CPU0 via SGI15 to pull the rug... */
writel(BIT(16) | 15, GICD_BASE + GICD_SGIR); writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
dsb(); dsb();
} else {
/* Unmask FIQs to service SGI15. */
asm volatile ("cpsie f");
}
/* Wait to be turned off */ /* Wait to be turned off */
while (1) while (1)

View File

@ -26,8 +26,8 @@ static unsigned int read_id_pfr1(void)
static unsigned long get_gicd_base_address(void) static unsigned long get_gicd_base_address(void)
{ {
#ifdef CONFIG_ARM_GIC_BASE_ADDRESS #ifdef CFG_ARM_GIC_BASE_ADDRESS
return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; return CFG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
#else #else
unsigned periphbase; unsigned periphbase;

View File

@ -18,7 +18,7 @@
* The number of reference clock ticks that correspond to 10ms is normally * The number of reference clock ticks that correspond to 10ms is normally
* defined in the SysTick Calibration register's TENMS field. However, on some * defined in the SysTick Calibration register's TENMS field. However, on some
* devices this is wrong, so this driver allows the clock rate to be defined * devices this is wrong, so this driver allows the clock rate to be defined
* using CONFIG_SYS_HZ_CLOCK. * using CFG_SYS_HZ_CLOCK.
*/ */
#include <common.h> #include <common.h>
@ -76,10 +76,10 @@ int timer_init(void)
/* /*
* If the TENMS field is inexact or wrong, specify the clock rate using * If the TENMS field is inexact or wrong, specify the clock rate using
* CONFIG_SYS_HZ_CLOCK. * CFG_SYS_HZ_CLOCK.
*/ */
#if defined(CONFIG_SYS_HZ_CLOCK) #if defined(CFG_SYS_HZ_CLOCK)
gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
#else #else
gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100; gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100;
#endif #endif

View File

@ -29,6 +29,7 @@ config ARCH_LS1028A
select ESBC_HDR_LS if CHAIN_OF_TRUST select ESBC_HDR_LS if CHAIN_OF_TRUST
select FSL_LAYERSCAPE select FSL_LAYERSCAPE
select FSL_LSCH3 select FSL_LSCH3
select FSL_TZASC_400
select GICV3 select GICV3
select NXP_LSCH3_2 select NXP_LSCH3_2
select SYS_FSL_HAS_CCI400 select SYS_FSL_HAS_CCI400
@ -69,6 +70,7 @@ config ARCH_LS1043A
select GICV2 select GICV2
select HAS_FSL_XHCI_USB if USB_HOST select HAS_FSL_XHCI_USB if USB_HOST
select SKIP_LOWLEVEL_INIT select SKIP_LOWLEVEL_INIT
select SYS_DPAA_FMAN
select SYS_FSL_SRDS_1 select SYS_FSL_SRDS_1
select SYS_HAS_SERDES select SYS_HAS_SERDES
select SYS_FSL_DDR select SYS_FSL_DDR
@ -106,6 +108,7 @@ config ARCH_LS1046A
select GICV2 select GICV2
select HAS_FSL_XHCI_USB if USB_HOST select HAS_FSL_XHCI_USB if USB_HOST
select SKIP_LOWLEVEL_INIT select SKIP_LOWLEVEL_INIT
select SYS_DPAA_FMAN
select SYS_FSL_SRDS_1 select SYS_FSL_SRDS_1
select SYS_HAS_SERDES select SYS_HAS_SERDES
select SYS_FSL_DDR select SYS_FSL_DDR

View File

@ -96,11 +96,11 @@ static struct mm_region early_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE, SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
}, },
{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, { CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1, CONFIG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
#ifdef CONFIG_FSL_IFC #ifdef CONFIG_FSL_IFC
@ -114,7 +114,7 @@ static struct mm_region early_map[] = {
CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
}, },
{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, { CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
CONFIG_SYS_FSL_IFC_SIZE1, CONFIG_SYS_FSL_IFC_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
}, },
@ -130,9 +130,9 @@ static struct mm_region early_map[] = {
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
}, },
#ifdef CONFIG_FSL_IFC #ifdef CONFIG_FSL_IFC
/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ /* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
}, },
#endif #endif
@ -159,7 +159,7 @@ static struct mm_region early_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE, SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
}, },
@ -168,7 +168,7 @@ static struct mm_region early_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, { CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_FSL_QSPI_SIZE, CONFIG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
}, },
@ -204,7 +204,7 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE, SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
}, },
@ -213,12 +213,12 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
}, },
{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, { CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1, CONFIG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, { CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2,
CONFIG_SYS_FSL_QSPI_SIZE2, CONFIG_SYS_FSL_QSPI_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
@ -257,26 +257,26 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
CONFIG_SYS_PCIE1_PHYS_SIZE, CFG_SYS_PCIE1_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
CONFIG_SYS_PCIE2_PHYS_SIZE, CFG_SYS_PCIE2_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR #ifdef CFG_SYS_PCIE3_PHYS_ADDR
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
CONFIG_SYS_PCIE3_PHYS_SIZE, CFG_SYS_PCIE3_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
#endif #endif
#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR #ifdef CFG_SYS_PCIE4_PHYS_ADDR
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, { CFG_SYS_PCIE4_PHYS_ADDR, CFG_SYS_PCIE4_PHYS_ADDR,
CONFIG_SYS_PCIE4_PHYS_SIZE, CFG_SYS_PCIE4_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
@ -333,7 +333,7 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE, SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
}, },
@ -342,7 +342,7 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, { CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_FSL_QSPI_SIZE, CONFIG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
@ -368,19 +368,19 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
}, },
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
CONFIG_SYS_PCIE1_PHYS_SIZE, CFG_SYS_PCIE1_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
CONFIG_SYS_PCIE2_PHYS_SIZE, CFG_SYS_PCIE2_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR #ifdef CFG_SYS_PCIE3_PHYS_ADDR
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
CONFIG_SYS_PCIE3_PHYS_SIZE, CFG_SYS_PCIE3_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, },
@ -391,7 +391,7 @@ static struct mm_region final_map[] = {
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
}, },
#endif #endif
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CFG_SYS_MEM_RESERVE_SECURE
{}, /* space holder for secure mem */ {}, /* space holder for secure mem */
#endif #endif
{}, {},
@ -401,7 +401,7 @@ struct mm_region *mem_map = early_map;
void cpu_name(char *name) void cpu_name(char *name)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int i, svr, ver; unsigned int i, svr, ver;
svr = gur_in32(&gur->svr); svr = gur_in32(&gur->svr);
@ -430,7 +430,7 @@ void cpu_name(char *name)
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/* /*
* To start MMU before DDR is available, we create MMU table in SRAM. * To start MMU before DDR is available, we create MMU table in SRAM.
* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three * The base address of SRAM is CFG_SYS_FSL_OCRAM_BASE. We use three
* levels of translation tables here to cover 40-bit address space. * levels of translation tables here to cover 40-bit address space.
* We use 4KB granule size, with 40 bits physical address, T0SZ=24 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
* Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose. * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
@ -443,9 +443,9 @@ static inline void early_mmu_setup(void)
/* global data is already setup, no allocation yet */ /* global data is already setup, no allocation yet */
if (el == 3) if (el == 3)
gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
else else
gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE;
gd->arch.tlb_fillptr = gd->arch.tlb_addr; gd->arch.tlb_fillptr = gd->arch.tlb_addr;
gd->arch.tlb_size = EARLY_PGTABLE_SIZE; gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
@ -466,7 +466,7 @@ static void fix_pcie_mmu_map(void)
#ifdef CONFIG_ARCH_LS2080A #ifdef CONFIG_ARCH_LS2080A
unsigned int i; unsigned int i;
u32 svr, ver; u32 svr, ver;
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
svr = gur_in32(&gur->svr); svr = gur_in32(&gur->svr);
ver = SVR_SOC_VER(svr); ver = SVR_SOC_VER(svr);
@ -477,25 +477,25 @@ static void fix_pcie_mmu_map(void)
(ver == SVR_LS2081A) || (ver == SVR_LS2041A)) { (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
for (i = 0; i < ARRAY_SIZE(final_map); i++) { for (i = 0; i < ARRAY_SIZE(final_map); i++) {
switch (final_map[i].phys) { switch (final_map[i].phys) {
case CONFIG_SYS_PCIE1_PHYS_ADDR: case CFG_SYS_PCIE1_PHYS_ADDR:
final_map[i].phys = 0x2000000000ULL; final_map[i].phys = 0x2000000000ULL;
final_map[i].virt = 0x2000000000ULL; final_map[i].virt = 0x2000000000ULL;
final_map[i].size = 0x800000000ULL; final_map[i].size = 0x800000000ULL;
break; break;
case CONFIG_SYS_PCIE2_PHYS_ADDR: case CFG_SYS_PCIE2_PHYS_ADDR:
final_map[i].phys = 0x2800000000ULL; final_map[i].phys = 0x2800000000ULL;
final_map[i].virt = 0x2800000000ULL; final_map[i].virt = 0x2800000000ULL;
final_map[i].size = 0x800000000ULL; final_map[i].size = 0x800000000ULL;
break; break;
#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR #ifdef CFG_SYS_PCIE3_PHYS_ADDR
case CONFIG_SYS_PCIE3_PHYS_ADDR: case CFG_SYS_PCIE3_PHYS_ADDR:
final_map[i].phys = 0x3000000000ULL; final_map[i].phys = 0x3000000000ULL;
final_map[i].virt = 0x3000000000ULL; final_map[i].virt = 0x3000000000ULL;
final_map[i].size = 0x800000000ULL; final_map[i].size = 0x800000000ULL;
break; break;
#endif #endif
#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR #ifdef CFG_SYS_PCIE4_PHYS_ADDR
case CONFIG_SYS_PCIE4_PHYS_ADDR: case CFG_SYS_PCIE4_PHYS_ADDR:
final_map[i].phys = 0x3800000000ULL; final_map[i].phys = 0x3800000000ULL;
final_map[i].virt = 0x3800000000ULL; final_map[i].virt = 0x3800000000ULL;
final_map[i].size = 0x800000000ULL; final_map[i].size = 0x800000000ULL;
@ -568,7 +568,7 @@ static inline void final_mmu_setup(void)
} }
} }
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
if (el == 3) { if (el == 3) {
/* /*
@ -580,7 +580,7 @@ static inline void final_mmu_setup(void)
gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
final_map[index].virt = gd->arch.secure_ram & ~0x3; final_map[index].virt = gd->arch.secure_ram & ~0x3;
final_map[index].phys = final_map[index].virt; final_map[index].phys = final_map[index].virt;
final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE; final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE;
final_map[index].attrs = PTE_BLOCK_OUTER_SHARE; final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
tlb_addr_save = gd->arch.tlb_addr; tlb_addr_save = gd->arch.tlb_addr;
@ -775,7 +775,7 @@ enum boot_src get_boot_src(void)
#if defined(CONFIG_FSL_LSCH3) #if defined(CONFIG_FSL_LSCH3)
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
#elif defined(CONFIG_FSL_LSCH2) #elif defined(CONFIG_FSL_LSCH2)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
#endif #endif
if (current_el() == 2) { if (current_el() == 2) {
@ -863,7 +863,7 @@ enum env_location arch_env_get_location(enum env_operation op, int prio)
u32 initiator_type(u32 cluster, int init_id) u32 initiator_type(u32 cluster, int init_id)
{ {
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
u32 type = 0; u32 type = 0;
@ -876,7 +876,7 @@ u32 initiator_type(u32 cluster, int init_id)
u32 cpu_pos_mask(void) u32 cpu_pos_mask(void)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0; int i = 0;
u32 cluster, type, mask = 0; u32 cluster, type, mask = 0;
@ -897,7 +897,7 @@ u32 cpu_pos_mask(void)
u32 cpu_mask(void) u32 cpu_mask(void)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0; int i = 0, count = 0;
u32 cluster, type, mask = 0; u32 cluster, type, mask = 0;
@ -930,7 +930,7 @@ int cpu_numcores(void)
int fsl_qoriq_core_to_cluster(unsigned int core) int fsl_qoriq_core_to_cluster(unsigned int core)
{ {
struct ccsr_gur __iomem *gur = struct ccsr_gur __iomem *gur =
(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); (void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0; int i = 0, count = 0;
u32 cluster; u32 cluster;
@ -954,7 +954,7 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
u32 fsl_qoriq_core_to_type(unsigned int core) u32 fsl_qoriq_core_to_type(unsigned int core)
{ {
struct ccsr_gur __iomem *gur = struct ccsr_gur __iomem *gur =
(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); (void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0; int i = 0, count = 0;
u32 cluster, type; u32 cluster, type;
@ -979,7 +979,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
#ifndef CONFIG_FSL_LSCH3 #ifndef CONFIG_FSL_LSCH3
uint get_svr(void) uint get_svr(void)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
return gur_in32(&gur->svr); return gur_in32(&gur->svr);
} }
@ -988,7 +988,7 @@ uint get_svr(void)
#ifdef CONFIG_DISPLAY_CPUINFO #ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void) int print_cpuinfo(void)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct sys_info sysinfo; struct sys_info sysinfo;
char buf[32]; char buf[32];
unsigned int i, core; unsigned int i, core;
@ -1057,9 +1057,6 @@ int cpu_eth_init(struct bd_info *bis)
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
error = fsl_mc_ldpaa_init(bis); error = fsl_mc_ldpaa_init(bis);
#endif
#ifdef CONFIG_FMAN_ENET
fm_standard_init(bis);
#endif #endif
return error; return error;
} }
@ -1179,9 +1176,9 @@ int arch_early_init_r(void)
int timer_init(void) int timer_init(void)
{ {
u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_FSL_LSCH3 #ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; u32 __iomem *cltbenr = (u32 *)CFG_SYS_FSL_PMU_CLTBENR;
#endif #endif
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
defined(CONFIG_ARCH_LS1028A) defined(CONFIG_ARCH_LS1028A)
@ -1230,7 +1227,7 @@ int timer_init(void)
} }
#if !CONFIG_IS_ENABLED(SYSRESET) #if !CONFIG_IS_ENABLED(SYSRESET)
__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; __efi_runtime_data u32 __iomem *rstcr = (u32 *)CFG_SYS_FSL_RST_ADDR;
void __efi_runtime reset_cpu(void) void __efi_runtime reset_cpu(void)
{ {
@ -1311,22 +1308,22 @@ phys_size_t get_effective_memsize(void)
* allocated from first region. If the memory extends to the second * allocated from first region. If the memory extends to the second
* region (or the third region if applicable), Management Complex (MC) * region (or the third region if applicable), Management Complex (MC)
* memory should be put into the highest region, i.e. the end of DDR * memory should be put into the highest region, i.e. the end of DDR
* memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so * memory. CFG_MAX_MEM_MAPPED is set to the size of first region so
* U-Boot doesn't relocate itself into higher address. Should DDR be * U-Boot doesn't relocate itself into higher address. Should DDR be
* configured to skip the first region, this function needs to be * configured to skip the first region, this function needs to be
* adjusted. * adjusted.
*/ */
if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
ea_size = CONFIG_MAX_MEM_MAPPED; ea_size = CFG_MAX_MEM_MAPPED;
rem = gd->ram_size - ea_size; rem = gd->ram_size - ea_size;
} else { } else {
ea_size = gd->ram_size; ea_size = gd->ram_size;
} }
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CFG_SYS_MEM_RESERVE_SECURE
/* Check if we have enough space for secure memory */ /* Check if we have enough space for secure memory */
if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) if (ea_size > CFG_SYS_MEM_RESERVE_SECURE)
ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE; ea_size -= CFG_SYS_MEM_RESERVE_SECURE;
else else
printf("Error: No enough space for secure memory.\n"); printf("Error: No enough space for secure memory.\n");
#endif #endif
@ -1433,7 +1430,7 @@ int dram_init_banksize(void)
* gd->arch.secure_ram should be done to avoid running it repeatedly. * gd->arch.secure_ram should be done to avoid running it repeatedly.
*/ */
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
debug("No need to run again, skip %s\n", __func__); debug("No need to run again, skip %s\n", __func__);
@ -1441,12 +1438,12 @@ int dram_init_banksize(void)
} }
#endif #endif
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
gd->bd->bi_dram[1].size = gd->ram_size - gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE; CFG_SYS_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
@ -1458,17 +1455,17 @@ int dram_init_banksize(void)
} else { } else {
gd->bd->bi_dram[0].size = gd->ram_size; gd->bd->bi_dram[0].size = gd->ram_size;
} }
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->bd->bi_dram[0].size > if (gd->bd->bi_dram[0].size >
CONFIG_SYS_MEM_RESERVE_SECURE) { CFG_SYS_MEM_RESERVE_SECURE) {
gd->bd->bi_dram[0].size -= gd->bd->bi_dram[0].size -=
CONFIG_SYS_MEM_RESERVE_SECURE; CFG_SYS_MEM_RESERVE_SECURE;
gd->arch.secure_ram = gd->bd->bi_dram[0].start + gd->arch.secure_ram = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size; gd->bd->bi_dram[0].size;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
} }
#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ #endif /* CFG_SYS_MEM_RESERVE_SECURE */
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
/* Assign memory for MC */ /* Assign memory for MC */
@ -1520,7 +1517,7 @@ int dram_init_banksize(void)
} }
#endif #endif
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CFG_SYS_MEM_RESERVE_SECURE
debug("%s is called. gd->ram_size is reduced to %lu\n", debug("%s is called. gd->ram_size is reduced to %lu\n",
__func__, (ulong)gd->ram_size); __func__, (ulong)gd->ram_size);
#endif #endif
@ -1571,7 +1568,7 @@ void update_early_mmu_table(void)
if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
mmu_change_region_attr( mmu_change_region_attr(
CONFIG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_BASE,
gd->ram_size, gd->ram_size,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_OUTER_SHARE |
@ -1579,8 +1576,8 @@ void update_early_mmu_table(void)
PTE_TYPE_VALID); PTE_TYPE_VALID);
} else { } else {
mmu_change_region_attr( mmu_change_region_attr(
CONFIG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_BASE,
CONFIG_SYS_DDR_BLOCK1_SIZE, CFG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS | PTE_BLOCK_NS |
@ -1589,10 +1586,10 @@ void update_early_mmu_table(void)
#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
#endif #endif
if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE > if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE >
CONFIG_SYS_DDR_BLOCK2_SIZE) { CONFIG_SYS_DDR_BLOCK2_SIZE) {
mmu_change_region_attr( mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK2_BASE, CFG_SYS_DDR_BLOCK2_BASE,
CONFIG_SYS_DDR_BLOCK2_SIZE, CONFIG_SYS_DDR_BLOCK2_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_OUTER_SHARE |
@ -1601,7 +1598,7 @@ void update_early_mmu_table(void)
mmu_change_region_attr( mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK3_BASE, CONFIG_SYS_DDR_BLOCK3_BASE,
gd->ram_size - gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE - CFG_SYS_DDR_BLOCK1_SIZE -
CONFIG_SYS_DDR_BLOCK2_SIZE, CONFIG_SYS_DDR_BLOCK2_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_OUTER_SHARE |
@ -1611,9 +1608,9 @@ void update_early_mmu_table(void)
#endif #endif
{ {
mmu_change_region_attr( mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK2_BASE, CFG_SYS_DDR_BLOCK2_BASE,
gd->ram_size - gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE, CFG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS | PTE_BLOCK_NS |

View File

@ -116,10 +116,10 @@ Flash Layout
Environment Variables Environment Variables
===================== =====================
mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
mcmemsize: MC DRAM block size in hex. If this variable is not defined, the value mcmemsize: MC DRAM block size in hex. If this variable is not defined, the value
CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
mcinitcmd: This environment variable is defined to initiate MC and DPL deployment mcinitcmd: This environment variable is defined to initiate MC and DPL deployment
from the location where it is stored(NOR, NAND, SD, SATA, USB)during from the location where it is stored(NOR, NAND, SD, SATA, USB)during

View File

@ -171,9 +171,9 @@ static void fdt_fixup_gic(void *blob)
{ {
int offset, err; int offset, err;
u64 reg[8]; u64 reg[8];
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int val; unsigned int val;
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int align_64k = 0; int align_64k = 0;
val = gur_in32(&gur->svr); val = gur_in32(&gur->svr);
@ -355,7 +355,7 @@ static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
static void fdt_fixup_msi(void *blob) static void fdt_fixup_msi(void *blob)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int rev; unsigned int rev;
rev = gur_in32(&gur->svr); rev = gur_in32(&gur->svr);
@ -620,7 +620,7 @@ void fdt_fixup_pfe_firmware(void *blob)
void ft_cpu_setup(void *blob, struct bd_info *bd) void ft_cpu_setup(void *blob, struct bd_info *bd)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr = gur_in32(&gur->svr); unsigned int svr = gur_in32(&gur->svr);
/* delete crypto node if not on an E-processor */ /* delete crypto node if not on an E-processor */
@ -635,7 +635,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
fdt_fixup_kaslr(blob); fdt_fixup_kaslr(blob);
#endif #endif
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
} }
#endif #endif
@ -646,7 +646,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_SYS_NS16550 #ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "fsl,ns16550", do_fixup_by_compat_u32(blob, "fsl,ns16550",
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1); "clock-frequency", CFG_SYS_NS16550_CLK, 1);
#endif #endif
do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",

View File

@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device) int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = gur_in32(&gur->rcwsr[4]); u32 cfg = gur_in32(&gur->rcwsr[4]);
int i; int i;
@ -76,7 +76,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
int get_serdes_protocol(void) int get_serdes_protocol(void)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = gur_in32(&gur->rcwsr[4]) & u32 cfg = gur_in32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
@ -101,7 +101,7 @@ const char *serdes_clock_to_string(u32 clock)
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg; u32 cfg;
int lane; int lane;
@ -142,7 +142,7 @@ __weak int set_serdes_volt(int svdd)
int setup_serdes_volt(u32 svdd) int setup_serdes_volt(u32 svdd)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_serdes *serdes1_base; struct ccsr_serdes *serdes1_base;
#ifdef CONFIG_SYS_FSL_SRDS_2 #ifdef CONFIG_SYS_FSL_SRDS_2
struct ccsr_serdes *serdes2_base; struct ccsr_serdes *serdes2_base;
@ -168,7 +168,7 @@ int setup_serdes_volt(u32 svdd)
if (svdd_cur == svdd_tar) if (svdd_cur == svdd_tar)
return 0; return 0;
serdes1_base = (void *)CONFIG_SYS_FSL_SERDES_ADDR; serdes1_base = (void *)CFG_SYS_FSL_SERDES_ADDR;
#ifdef CONFIG_SYS_FSL_SRDS_2 #ifdef CONFIG_SYS_FSL_SRDS_2
serdes2_base = (void *)serdes1_base + 0x10000; serdes2_base = (void *)serdes1_base + 0x10000;
#endif #endif
@ -406,14 +406,14 @@ void fsl_serdes_init(void)
{ {
#ifdef CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1, serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_SERDES_ADDR, CFG_SYS_FSL_SERDES_ADDR,
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK, FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT, FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map); serdes1_prtcl_map);
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_2 #ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2, serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_SERDES_ADDR, CFG_SYS_FSL_SERDES_ADDR,
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK, FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT, FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map); serdes2_prtcl_map);

View File

@ -20,16 +20,12 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(struct sys_info *sys_info) void get_sys_info(struct sys_info *sys_info)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
/* rcw_tmp is needed to get FMAN clock, or to get cluster group A /* rcw_tmp is needed to get FMAN clock, or to get cluster group A
* mux 2 clock for LS1043A/LS1046A. * mux 2 clock for LS1043A/LS1046A.
*/ */
#if defined(CONFIG_SYS_DPAA_FMAN) || \ __maybe_unused u32 rcw_tmp;
defined(CONFIG_ARCH_LS1046A) || \ struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR);
defined(CONFIG_ARCH_LS1043A)
u32 rcw_tmp;
#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
unsigned int cpu; unsigned int cpu;
const u8 core_cplx_pll[8] = { const u8 core_cplx_pll[8] = {
[0] = 0, /* CC1 PPL / 1 */ [0] = 0, /* CC1 PPL / 1 */
@ -96,7 +92,7 @@ void get_sys_info(struct sys_info *sys_info)
#define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SEL 0xe0000000
#define HWA_CGA_M1_CLK_SHIFT 29 #define HWA_CGA_M1_CLK_SHIFT 29
#ifdef CONFIG_SYS_DPAA_FMAN #if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
rcw_tmp = in_be32(&gur->rcwsr[7]); rcw_tmp = in_be32(&gur->rcwsr[7]);
switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) { switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
case 2: case 2:

View File

@ -86,7 +86,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device) int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = 0; u32 cfg = 0;
int i; int i;
@ -134,7 +134,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg; u32 cfg;
int lane; int lane;
@ -399,18 +399,18 @@ static void do_pll_lock(u32 cfg,
int setup_serdes_volt(u32 svdd) int setup_serdes_volt(u32 svdd)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_serdes __iomem *serdes1_base = struct ccsr_serdes __iomem *serdes1_base =
(void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR; (void *)CFG_SYS_FSL_LSCH3_SERDES_ADDR;
u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
#ifdef CONFIG_SYS_FSL_SRDS_2 #ifdef CONFIG_SYS_FSL_SRDS_2
struct ccsr_serdes __iomem *serdes2_base = struct ccsr_serdes __iomem *serdes2_base =
(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000); (void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
#endif #endif
#ifdef CONFIG_SYS_NXP_SRDS_3 #ifdef CONFIG_SYS_NXP_SRDS_3
struct ccsr_serdes __iomem *serdes3_base = struct ccsr_serdes __iomem *serdes3_base =
(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000); (void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]); u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
#endif #endif
u32 cfg_tmp; u32 cfg_tmp;
@ -585,7 +585,7 @@ void fsl_serdes_init(void)
#ifdef CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1, serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, CFG_SYS_FSL_LSCH3_SERDES_ADDR,
FSL_CHASSIS3_SRDS1_REGSR, FSL_CHASSIS3_SRDS1_REGSR,
FSL_CHASSIS3_SRDS1_PRTCL_MASK, FSL_CHASSIS3_SRDS1_PRTCL_MASK,
FSL_CHASSIS3_SRDS1_PRTCL_SHIFT, FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
@ -593,7 +593,7 @@ void fsl_serdes_init(void)
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_2 #ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2, serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, CFG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
FSL_CHASSIS3_SRDS2_REGSR, FSL_CHASSIS3_SRDS2_REGSR,
FSL_CHASSIS3_SRDS2_PRTCL_MASK, FSL_CHASSIS3_SRDS2_PRTCL_MASK,
FSL_CHASSIS3_SRDS2_PRTCL_SHIFT, FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
@ -601,7 +601,7 @@ void fsl_serdes_init(void)
#endif #endif
#ifdef CONFIG_SYS_NXP_SRDS_3 #ifdef CONFIG_SYS_NXP_SRDS_3
serdes_init(NXP_SRDS_3, serdes_init(NXP_SRDS_3,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000, CFG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
FSL_CHASSIS3_SRDS3_REGSR, FSL_CHASSIS3_SRDS3_REGSR,
FSL_CHASSIS3_SRDS3_PRTCL_MASK, FSL_CHASSIS3_SRDS3_PRTCL_MASK,
FSL_CHASSIS3_SRDS3_PRTCL_SHIFT, FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
@ -611,7 +611,7 @@ void fsl_serdes_init(void)
int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift) int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
char scfg[16], snum[16]; char scfg[16], snum[16];
int cfgr = 0; int cfgr = 0;
u32 cfg; u32 cfg;

View File

@ -23,13 +23,13 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(struct sys_info *sys_info) void get_sys_info(struct sys_info *sys_info)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_clk_cluster_group __iomem *clk_grp[2] = { struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR), (void *)(CFG_SYS_FSL_CH3_CLK_GRPA_ADDR),
(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR) (void *)(CFG_SYS_FSL_CH3_CLK_GRPB_ADDR)
}; };
struct ccsr_clk_ctrl __iomem *clk_ctrl = struct ccsr_clk_ctrl __iomem *clk_ctrl =
(void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR); (void *)(CFG_SYS_FSL_CH3_CLK_CTRL_ADDR);
unsigned int cpu; unsigned int cpu;
const u8 core_cplx_pll[16] = { const u8 core_cplx_pll[16] = {
[0] = 0, /* CC1 PPL / 1 */ [0] = 0, /* CC1 PPL / 1 */
@ -68,7 +68,7 @@ void get_sys_info(struct sys_info *sys_info)
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = get_board_sys_clk(); unsigned long sysclk = get_board_sys_clk();
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
u32 c_pll_sel, cplx_pll; u32 c_pll_sel, cplx_pll;
void *offset; void *offset;

View File

@ -27,7 +27,7 @@ static void set_icid(struct icid_id_table *tbl, int size)
void set_fman_icids(struct fman_icid_id_table *tbl, int size) void set_fman_icids(struct fman_icid_id_table *tbl, int size)
{ {
int i; int i;
ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR; ccsr_fman_t *fm = (void *)CFG_SYS_FSL_FM1_ADDR;
for (i = 0; i < size; i++) { for (i = 0; i < size; i++) {
out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1], out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1],
@ -41,7 +41,7 @@ void set_icids(void)
/* setup general icid offsets */ /* setup general icid offsets */
set_icid(icid_tbl, icid_tbl_sz); set_icid(icid_tbl, icid_tbl_sz);
#ifdef CONFIG_SYS_DPAA_FMAN #if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz); set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
#endif #endif
} }

View File

@ -325,8 +325,8 @@ ENDPROC(fsl_ocram_init)
ENTRY(fsl_clear_ocram) ENTRY(fsl_clear_ocram)
/* Clear OCRAM */ /* Clear OCRAM */
ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE ldr x0, =CFG_SYS_FSL_OCRAM_BASE
ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE) ldr x1, =(CFG_SYS_FSL_OCRAM_BASE + CFG_SYS_FSL_OCRAM_SIZE)
mov x2, #0 mov x2, #0
clear_loop: clear_loop:
str x2, [x0] str x2, [x0]

View File

@ -10,7 +10,7 @@
#include <fsl_sec.h> #include <fsl_sec.h>
#ifdef CONFIG_SYS_DPAA_QBMAN #ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
@ -59,7 +59,7 @@ struct icid_id_table icid_tbl[] = {
int icid_tbl_sz = ARRAY_SIZE(icid_tbl); int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
#ifdef CONFIG_SYS_DPAA_FMAN #if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
struct fman_icid_id_table fman_icid_tbl[] = { struct fman_icid_id_table fman_icid_tbl[] = {
/* port id, icid */ /* port id, icid */
SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),

View File

@ -9,7 +9,7 @@
#include <asm/arch-fsl-layerscape/fsl_portals.h> #include <asm/arch-fsl-layerscape/fsl_portals.h>
#ifdef CONFIG_SYS_DPAA_QBMAN #ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
@ -58,7 +58,7 @@ struct icid_id_table icid_tbl[] = {
int icid_tbl_sz = ARRAY_SIZE(icid_tbl); int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
#ifdef CONFIG_SYS_DPAA_FMAN #if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
struct fman_icid_id_table fman_icid_tbl[] = { struct fman_icid_id_table fman_icid_tbl[] = {
/* port id, icid */ /* port id, icid */
SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),

View File

@ -53,7 +53,7 @@ static struct serdes_config *serdes_cfg_tbl[] = {
bool soc_has_mac1(void) bool soc_has_mac1(void)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr = gur_in32(&gur->svr); unsigned int svr = gur_in32(&gur->svr);
unsigned int version = SVR_SOC_VER(svr); unsigned int version = SVR_SOC_VER(svr);

View File

@ -48,8 +48,8 @@ void update_os_arch_secondary_cores(uint8_t os_arch)
#ifdef CONFIG_FSL_LSCH3 #ifdef CONFIG_FSL_LSCH3
static void wake_secondary_core_n(int cluster, int core, int cluster_cores) static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
u32 mpidr = 0; u32 mpidr = 0;
mpidr = ((cluster << 8) | core); mpidr = ((cluster << 8) | core);
@ -73,13 +73,13 @@ static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
int fsl_layerscape_wake_seconday_cores(void) int fsl_layerscape_wake_seconday_cores(void)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
#ifdef CONFIG_FSL_LSCH3 #ifdef CONFIG_FSL_LSCH3
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
u32 svr, ver, cluster, type; u32 svr, ver, cluster, type;
int j = 0, cluster_cores = 0; int j = 0, cluster_cores = 0;
#elif defined(CONFIG_FSL_LSCH2) #elif defined(CONFIG_FSL_LSCH2)
struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR); struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
#endif #endif
u32 cores, cpu_up_mask = 1; u32 cores, cpu_up_mask = 1;
int i, timeout = 10; int i, timeout = 10;

View File

@ -253,7 +253,7 @@ int ppa_init(void)
#endif #endif
#ifdef CONFIG_FSL_LSCH3 #ifdef CONFIG_FSL_LSCH3
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
boot_loc_ptr_l = &gur->bootlocptrl; boot_loc_ptr_l = &gur->bootlocptrl;
boot_loc_ptr_h = &gur->bootlocptrh; boot_loc_ptr_h = &gur->bootlocptrh;
@ -261,7 +261,7 @@ int ppa_init(void)
loadable_l = &gur->scratchrw[4]; loadable_l = &gur->scratchrw[4];
loadable_h = &gur->scratchrw[5]; loadable_h = &gur->scratchrw[5];
#elif defined(CONFIG_FSL_LSCH2) #elif defined(CONFIG_FSL_LSCH2)
struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR); struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
boot_loc_ptr_l = &scfg->scratchrw[1]; boot_loc_ptr_l = &scfg->scratchrw[1];
boot_loc_ptr_h = &scfg->scratchrw[0]; boot_loc_ptr_h = &scfg->scratchrw[0];

View File

@ -80,7 +80,7 @@ int ls_gic_rd_tables_init(void *blob)
bool soc_has_dp_ddr(void) bool soc_has_dp_ddr(void)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr); u32 svr = gur_in32(&gur->svr);
/* LS2085A, LS2088A, LS2048A has DP_DDR */ /* LS2085A, LS2088A, LS2048A has DP_DDR */
@ -94,7 +94,7 @@ bool soc_has_dp_ddr(void)
bool soc_has_aiop(void) bool soc_has_aiop(void)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr); u32 svr = gur_in32(&gur->svr);
/* LS2085A has AIOP */ /* LS2085A has AIOP */
@ -249,13 +249,13 @@ static void erratum_a008336(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
u32 *eddrtqcr1; u32 *eddrtqcr1;
#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR #ifdef CFG_SYS_FSL_DCSR_DDR_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
if (fsl_ddr_get_version(0) == 0x50200) if (fsl_ddr_get_version(0) == 0x50200)
out_le32(eddrtqcr1, 0x63b30002); out_le32(eddrtqcr1, 0x63b30002);
#endif #endif
#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR #ifdef CFG_SYS_FSL_DCSR_DDR2_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
if (fsl_ddr_get_version(0) == 0x50200) if (fsl_ddr_get_version(0) == 0x50200)
out_le32(eddrtqcr1, 0x63b30002); out_le32(eddrtqcr1, 0x63b30002);
#endif #endif
@ -271,8 +271,8 @@ static void erratum_a008514(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
u32 *eddrtqcr1; u32 *eddrtqcr1;
#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR #ifdef CFG_SYS_FSL_DCSR_DDR3_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
out_le32(eddrtqcr1, 0x63b20002); out_le32(eddrtqcr1, 0x63b20002);
#endif #endif
#endif #endif
@ -412,7 +412,7 @@ void fsl_lsch3_early_init_f(void)
/* Get VDD in the unit mV from voltage ID */ /* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void) int get_core_volt_from_fuse(void)
{ {
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int vdd; int vdd;
u32 fusesr; u32 fusesr;
u8 vid; u8 vid;
@ -462,7 +462,7 @@ int get_core_volt_from_fuse(void)
static void erratum_a009660(void) static void erratum_a009660(void)
{ {
#ifdef CONFIG_SYS_FSL_ERRATUM_A009660 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; u32 *eddrtqcr1 = (void *)CFG_SYS_FSL_SCFG_ADDR + 0x20c;
out_be32(eddrtqcr1, 0x63b20042); out_be32(eddrtqcr1, 0x63b20042);
#endif #endif
} }
@ -473,7 +473,7 @@ static void erratum_a008850_early(void)
/* part 1 of 2 */ /* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET); CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* Skip if running at lower exception level */ /* Skip if running at lower exception level */
if (current_el() < 3) if (current_el() < 3)
@ -493,7 +493,7 @@ void erratum_a008850_post(void)
/* part 2 of 2 */ /* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET); CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp; u32 tmp;
/* Skip if running at lower exception level */ /* Skip if running at lower exception level */
@ -526,21 +526,21 @@ void erratum_a010315(void)
static void erratum_a010539(void) static void erratum_a010539(void)
{ {
#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT) #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 porsr1; u32 porsr1;
porsr1 = in_be32(&gur->porsr1); porsr1 = in_be32(&gur->porsr1);
porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
porsr1); porsr1);
out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
#endif #endif
} }
/* Get VDD in the unit mV from voltage ID */ /* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void) int get_core_volt_from_fuse(void)
{ {
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int vdd; int vdd;
u32 fusesr; u32 fusesr;
u8 vid; u8 vid;
@ -588,7 +588,7 @@ static int setup_core_volt(u32 vdd)
#ifdef CONFIG_SYS_FSL_DDR #ifdef CONFIG_SYS_FSL_DDR
static void ddr_enable_0v9_volt(bool en) static void ddr_enable_0v9_volt(bool en)
{ {
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp; u32 tmp;
tmp = ddr_in32(&ddr->ddr_cdr1); tmp = ddr_in32(&ddr->ddr_cdr1);
@ -629,7 +629,7 @@ int setup_chip_volt(void)
#ifdef CONFIG_FSL_PFE #ifdef CONFIG_FSL_PFE
void init_pfe_scfg_dcfg_regs(void) void init_pfe_scfg_dcfg_regs(void)
{ {
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 ecccr2; u32 ecccr2;
out_be32(&scfg->pfeasbcr, out_be32(&scfg->pfeasbcr,
@ -643,8 +643,8 @@ void init_pfe_scfg_dcfg_regs(void)
out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
| SCFG_RD_QOS1_PFE2_QOS)); | SCFG_RD_QOS1_PFE2_QOS));
ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
ecccr2 | (unsigned int)DISABLE_PFE_ECC); ecccr2 | (unsigned int)DISABLE_PFE_ECC);
} }
#endif #endif
@ -653,7 +653,7 @@ void fsl_lsch2_early_init_f(void)
{ {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET); CONFIG_SYS_CCI400_OFFSET);
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT) #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
enum boot_src src; enum boot_src src;
#endif #endif

View File

@ -116,7 +116,7 @@ void board_init_f(ulong dummy)
#endif #endif
dram_init(); dram_init();
#ifdef CONFIG_SPL_FSL_LS_PPA #ifdef CONFIG_SPL_FSL_LS_PPA
#ifndef CONFIG_SYS_MEM_RESERVE_SECURE #ifndef CFG_SYS_MEM_RESERVE_SECURE
#error Need secure RAM for PPA #error Need secure RAM for PPA
#endif #endif
/* /*

View File

@ -103,7 +103,7 @@ void __noreturn psci_system_reset2(u32 reset_level, u32 cookie)
{ {
struct pt_regs regs; struct pt_regs regs;
regs.regs[0] = ARM_PSCI_1_1_FN64_SYSTEM_RESET2; regs.regs[0] = ARM_PSCI_0_2_FN64_SYSTEM_RESET2;
regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level; regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level;
regs.regs[2] = cookie; regs.regs[2] = cookie;
if (use_smc_for_psci) if (use_smc_for_psci)

View File

@ -12,11 +12,10 @@
/* Default PSCI function, return -1, Not Implemented */ /* Default PSCI function, return -1, Not Implemented */
#define PSCI_DEFAULT(__fn) \ #define PSCI_DEFAULT(__fn) \
ENTRY(__fn); \ WEAK(__fn); \
mov w0, #ARM_PSCI_RET_NI; \ mov w0, #ARM_PSCI_RET_NI; \
ret; \ ret; \
ENDPROC(__fn); \ ENDPROC(__fn); \
.weak __fn
/* PSCI function and ID table definition*/ /* PSCI function and ID table definition*/
#define PSCI_TABLE(__id, __fn) \ #define PSCI_TABLE(__id, __fn) \
@ -207,7 +206,7 @@ handle_smc64:
* used for the return value, while in this PSCI environment, X0 usually holds * used for the return value, while in this PSCI environment, X0 usually holds
* the SMC function identifier, so X0 should be saved by caller function. * the SMC function identifier, so X0 should be saved by caller function.
*/ */
ENTRY(psci_get_cpu_id) WEAK(psci_get_cpu_id)
#ifdef CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER #ifdef CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
mrs x9, MPIDR_EL1 mrs x9, MPIDR_EL1
ubfx x9, x9, #8, #8 ubfx x9, x9, #8, #8
@ -221,7 +220,6 @@ ENTRY(psci_get_cpu_id)
add x0, x10, x9 add x0, x10, x9
ret ret
ENDPROC(psci_get_cpu_id) ENDPROC(psci_get_cpu_id)
.weak psci_get_cpu_id
/* CPU ID input in x0, stack top output in x0*/ /* CPU ID input in x0, stack top output in x0*/
LENTRY(psci_get_cpu_stack_top) LENTRY(psci_get_cpu_stack_top)
@ -261,10 +259,9 @@ handle_sync:
* Override this function if custom error handling is * Override this function if custom error handling is
* needed for asynchronous aborts * needed for asynchronous aborts
*/ */
ENTRY(plat_error_handler) WEAK(plat_error_handler)
ret ret
ENDPROC(plat_error_handler) ENDPROC(plat_error_handler)
.weak plat_error_handler
handle_error: handle_error:
bl psci_get_cpu_id bl psci_get_cpu_id
@ -323,9 +320,8 @@ ENTRY(psci_setup_vectors)
ret ret
ENDPROC(psci_setup_vectors) ENDPROC(psci_setup_vectors)
ENTRY(psci_arch_init) WEAK(psci_arch_init)
ret ret
ENDPROC(psci_arch_init) ENDPROC(psci_arch_init)
.weak psci_arch_init
.popsection .popsection

View File

@ -198,7 +198,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img,
goto out; goto out;
} }
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE #ifdef CFG_SYS_MEM_RESERVE_SECURE
/* /*
* The SEC Firmware must be stored in secure memory. * The SEC Firmware must be stored in secure memory.
* Append SEC Firmware to secure mmu table. * Append SEC Firmware to secure mmu table.
@ -211,7 +211,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img,
sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) + sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) +
gd->arch.tlb_size; gd->arch.tlb_size;
#else #else
#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support" #error "The CFG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
#endif #endif
/* Align SEC Firmware base address to 4K */ /* Align SEC Firmware base address to 4K */

View File

@ -278,7 +278,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
cn9132-db-A.dtb \ cn9132-db-A.dtb \
cn9132-db-B.dtb \ cn9132-db-B.dtb \
cn9130-crb-A.dtb \ cn9130-crb-A.dtb \
cn9130-crb-B.dtb cn9130-crb-B.dtb \
ac5-98dx35xx-rd.dtb
endif endif
dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
@ -382,6 +383,8 @@ dtb-$(CONFIG_ARCH_VERSAL) += \
versal-mini.dtb \ versal-mini.dtb \
versal-mini-emmc0.dtb \ versal-mini-emmc0.dtb \
versal-mini-emmc1.dtb \ versal-mini-emmc1.dtb \
versal-mini-ospi-single.dtb \
versal-mini-qspi-single.dtb \
xilinx-versal-virt.dtb xilinx-versal-virt.dtb
dtb-$(CONFIG_ARCH_VERSAL_NET) += \ dtb-$(CONFIG_ARCH_VERSAL_NET) += \
versal-net-mini.dtb \ versal-net-mini.dtb \
@ -641,7 +644,6 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-et-q8-v1.6.dtb \ sun8i-a33-et-q8-v1.6.dtb \
sun8i-a33-ga10h-v1.1.dtb \ sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-inet-d978-rev2.dtb \ sun8i-a33-inet-d978-rev2.dtb \
sun8i-a33-inet-u70b-rev1.dtb \
sun8i-a33-ippo-q8h-v1.2.dtb \ sun8i-a33-ippo-q8h-v1.2.dtb \
sun8i-a33-olinuxino.dtb \ sun8i-a33-olinuxino.dtb \
sun8i-a33-q8-tablet.dtb \ sun8i-a33-q8-tablet.dtb \
@ -979,6 +981,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-dhcom-pdk2.dtb \ imx8mp-dhcom-pdk2.dtb \
imx8mp-evk.dtb \ imx8mp-evk.dtb \
imx8mp-icore-mx8mp-edimm2.2.dtb \ imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-msc-sm2s.dtb \
imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-venice.dtb \ imx8mp-venice.dtb \
imx8mp-venice-gw74xx.dtb \ imx8mp-venice-gw74xx.dtb \
@ -1256,6 +1259,9 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
k3-am625-r5-sk.dtb k3-am625-r5-sk.dtb
dtb-$(CONFIG_SOC_K3_AM625) += k3-am62a7-sk.dtb \
k3-am62a7-r5-sk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \ mt7622-rfb.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \

View File

@ -0,0 +1,277 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree For AC5.
*
* Copyright (C) 2021 Marvell
* Copyright (C) 2022 Allied Telesis Labs
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Marvell AC5 SoC";
compatible = "marvell,ac5";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges;
internal-regs@7f000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
/* 16M internal register @ 0x7f00_0000 */
ranges = <0x0 0x0 0x7f000000 0x1000000>;
dma-coherent;
uart0: serial@12000 {
compatible = "snps,dw-apb-uart";
reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&cnm_clock>;
status = "okay";
};
uart1: serial@12100 {
compatible = "snps,dw-apb-uart";
reg = <0x12100 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&cnm_clock>;
status = "disabled";
};
uart2: serial@12200 {
compatible = "snps,dw-apb-uart";
reg = <0x12200 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&cnm_clock>;
status = "disabled";
};
uart3: serial@12300 {
compatible = "snps,dw-apb-uart";
reg = <0x12300 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&cnm_clock>;
status = "disabled";
};
mdio: mdio@22004 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x22004 0x4>;
clocks = <&cnm_clock>;
};
i2c0: i2c@11000 {
compatible = "marvell,mv78230-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cnm_clock>;
clock-names = "core";
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency=<100000>;
status = "disabled";
};
i2c1: i2c@11100 {
compatible = "marvell,mv78230-i2c";
reg = <0x11100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cnm_clock>;
clock-names = "core";
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency=<100000>;
status = "disabled";
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
status = "okay";
};
gpio1: gpio@18140 {
reg = <0x18140 0x40>;
compatible = "marvell,orion-gpio";
ngpios = <14>;
gpio-controller;
#gpio-cells = <2>;
status = "okay";
};
};
/*
* Dedicated section for devices behind 32bit controllers so we
* can configure specific DMA mapping for them
*/
behind-32bit-controller@7f000000 {
compatible = "simple-bus";
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
/* Host phy ram starts at 0x200M */
dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
dma-coherent;
eth0: ethernet@20000 {
compatible = "marvell,armada-ac5-neta";
reg = <0x0 0x20000 0x0 0x4000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cnm_clock>;
phy-mode = "sgmii";
status = "disabled";
};
eth1: ethernet@24000 {
compatible = "marvell,armada-ac5-neta";
reg = <0x0 0x24000 0x0 0x4000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cnm_clock>;
phy-mode = "sgmii";
status = "disabled";
};
usb0: usb@80000 {
compatible = "marvell,ac5-ehci";
reg = <0x0 0x80000 0x0 0x500>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
usb1: usb@a0000 {
compatible = "marvell,ac5-ehci";
reg = <0x0 0xa0000 0x0 0x500>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
pinctrl0: pinctrl@80020100 {
compatible = "marvell,mvebu-pinctrl";
reg = <0 0x80020100 0 0x20>;
pin-count = <46>;
max-func = <0xf>;
status = "okay";
};
spi0: spi@805a0000 {
compatible = "marvell,armada-3700-spi";
reg = <0x0 0x805a0000 0x0 0x50>;
#address-cells = <0x1>;
#size-cells = <0x0>;
clocks = <&spi_clock>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <1>;
status = "disabled";
};
spi1: spi@805a8000 {
compatible = "marvell,armada-3700-spi";
reg = <0x0 0x805a8000 0x0 0x50>;
#address-cells = <0x1>;
#size-cells = <0x0>;
clocks = <&spi_clock>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <1>;
status = "disabled";
};
gic: interrupt-controller@80600000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
<0x0 0x80660000 0x0 0x40000>; /* GICR */
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
};
};
clocks {
cnm_clock: cnm-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <328000000>;
};
spi_clock: spi-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
};
};

View File

@ -0,0 +1,129 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree For RD-AC5X.
*
* Copyright (C) 2021 Marvell
* Copyright (C) 2022 Allied Telesis Labs
*/
/*
* Device Tree file for Marvell Alleycat 5X development board
* This board file supports the B configuration of the board
*/
/dts-v1/;
#include "ac5-98dx35xx.dtsi"
/ {
model = "Marvell RD-AC5X Board";
compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
aliases {
serial0 = &uart0;
spiflash0 = &spiflash0;
gpio0 = &gpio0;
gpio1 = &gpio1;
ethernet0 = &eth0;
ethernet1 = &eth1;
spi0 = &spi0;
i2c0 = &i2c0;
i2c1 = &i2c1;
usb0 = &usb0;
usb1 = &usb1;
pinctrl0 = &pinctrl0;
sar-reg0 = "/config-space/sar-reg";
};
usb1phy: usb-phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
&mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&eth0 {
status = "okay";
phy-handle = <&phy0>;
};
/* USB0 is a host USB */
&usb0 {
status = "okay";
};
/* USB1 is a peripheral USB */
&usb1 {
status = "okay";
phys = <&usb1phy>;
phy-names = "usb-phy";
dr_mode = "peripheral";
};
&spi0 {
status = "okay";
spiflash0: flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&pinctrl0 {
/*
* MPP Bus: MPP# mode#
* eMMC [0-11] 0x1
* SPI[0] [12-17] 0x1
* TSEN_INT [18] 0x1
* DEV_INIT [19] 0x1
* SPI[1] [20-23] 0x3
* UART[1] [24-25] 0x3
* I2C[0] [26-27] 0x1
* XSMI[0] [28-29] 0x1 // SCH use SMI[0], reversed due to CPSS problem
* SMI[1] [30-31] 0x2 // SCH use XSMI[1], reversed due to CPSS problem
* UART[0] [32-33] 0x1
* OOB_SMI [34-35] 0x1
* PTP_CLK0_OUT [36] 0x1
* PTP_PULSE_OUT [37] 0x1
* RCVR_CLK_OUT [38] 0x1
* GPIO(in/out) [39] 0x0
* GPIO(in/out) [40] 0x0
* PTP_REF_CLK [41] 0x1
* PTP_CLK0 [42] 0x1
* LED0_CLK [43] 0x1
* LED0_STB [44] 0x1
* LED0_DATA [45] 0x1
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
3 3 3 3 3 3 1 1 1 1
2 2 1 1 1 1 1 1 1 0
0 1 1 1 1 1 >;
};

View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree For AC5X.
*
* Copyright (C) 2022 Allied Telesis Labs
*/
#include "ac5-98dx25xx.dtsi"
/ {
model = "Marvell AC5X SoC";
compatible = "marvell,ac5x", "marvell,ac5";
};
&cnm_clock {
clock-frequency = <325000000>;
};

View File

@ -6,9 +6,9 @@
#include "am33xx-u-boot.dtsi" #include "am33xx-u-boot.dtsi"
&l4_per { &l4_per {
u-boot,dm-pre-reloc;
segment@300000 { segment@300000 {
u-boot,dm-pre-reloc;
target-module@e000 { target-module@e000 {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
@ -26,3 +26,29 @@
&usb0 { &usb0 {
dr_mode = "peripheral"; dr_mode = "peripheral";
}; };
&i2c0 {
u-boot,dm-pre-reloc;
};
&l4_wkup {
u-boot,dm-pre-reloc;
segment@200000 {
u-boot,dm-pre-reloc;
target-module@9000 {
u-boot,dm-pre-reloc;
};
};
};
&uart0 {
u-boot,dm-pre-reloc;
};
&mmc1 {
u-boot,dm-pre-reloc;
};
&mmc2 {
u-boot,dm-pre-reloc;
};

View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2021 SanCloud Ltd
*/
#include "am335x-sancloud-bbe-u-boot.dtsi"
&l4_wkup {
segment@200000 {
target-module@0 {
u-boot,dm-pre-reloc;
};
};
};
&prcm {
u-boot,dm-pre-reloc;
};
&per_cm {
u-boot,dm-pre-reloc;
};
&l4ls_clkctrl {
u-boot,dm-pre-reloc;
};
&l4_per {
u-boot,dm-pre-reloc;
segment@0 {
u-boot,dm-pre-reloc;
target-module@30000 {
u-boot,dm-pre-reloc;
};
};
};
&spi0 {
u-boot,dm-pre-reloc;
channel@0 {
u-boot,dm-pre-reloc;
};
};

View File

@ -41,7 +41,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "micron,spi-authenta"; compatible = "micron,spi-authenta", "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <16000000>; spi-max-frequency = <16000000>;

View File

@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022 SanCloud Ltd
*/
#include "am335x-evm-u-boot.dtsi"

View File

@ -181,7 +181,7 @@
reg-io-width = <1>; reg-io-width = <1>;
clocks = <&ap_syscon 3>; clocks = <&ap_syscon 3>;
status = "disabled"; status = "disabled";
clock-frequency = <200000000>;
}; };
watchdog: watchdog@610000 { watchdog: watchdog@610000 {

View File

@ -49,6 +49,13 @@
atmel,pins = atmel,pins =
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
}; };
usb1 {
pinctrl_usb_default: usb_default {
atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
}; };
}; };
}; };
@ -89,3 +96,17 @@
phy-mode = "rmii"; phy-mode = "rmii";
status = "okay"; status = "okay";
}; };
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioD 15 GPIO_ACTIVE_HIGH
&pioD 18 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
&usb2 {
status = "okay";
};

View File

@ -143,7 +143,32 @@
pinmux = <PIN_PC9__GPIO>; pinmux = <PIN_PC9__GPIO>;
bias-pull-up; bias-pull-up;
}; };
pinctrl_usb_default: usb_default {
pinmux = <PIN_PA10__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PA16__GPIO>;
bias-disable;
};
}; };
}; };
}; };
}; };
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioA PIN_PA10 GPIO_ACTIVE_HIGH
0
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
&usb2 {
status = "okay";
};

View File

@ -154,7 +154,29 @@
<PIN_PA13__SDMMC0_CD>; <PIN_PA13__SDMMC0_CD>;
bias-disable; bias-disable;
}; };
pinctrl_usb_default: usb_default {
pinmux = <PIN_PC17__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PD23__GPIO>;
bias-disable;
};
}; };
}; };
}; };
}; };
&usb1 {
num-ports = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
&usb2 {
phy_type = "hsic";
status = "okay";
};

View File

@ -10,13 +10,88 @@
* *
*/ */
#include "sama7g5-pinfunc.h"
#include <dt-bindings/reset/sama7g5-reset.h>
#include <dt-bindings/clock/at91.h>
/ { / {
chosen { chosen {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
utmi {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
usb_phy0: phy@0 {
compatible = "microchip,sama7g5-usb-phy";
sfr-phandle = <&sfr>;
reg = <0>;
clocks = <&utmi_clk USB_UTMI1>;
clock-names = "utmi_clk";
status = "disabled";
#phy-cells = <0>;
};
usb_phy1: phy@1 {
compatible = "microchip,sama7g5-usb-phy";
sfr-phandle = <&sfr>;
reg = <1>;
clocks = <&utmi_clk USB_UTMI2>;
clock-names = "utmi_clk";
status = "disabled";
#phy-cells = <0>;
};
usb_phy2: phy@2 {
compatible = "microchip,sama7g5-usb-phy";
sfr-phandle = <&sfr>;
reg = <2>;
clocks = <&utmi_clk USB_UTMI3>;
clock-names = "utmi_clk";
status = "disabled";
#phy-cells = <0>;
};
};
utmi_clk: utmi-clk {
compatible = "microchip,sama7g5-utmi-clk";
sfr-phandle = <&sfr>;
#clock-cells = <1>;
clocks = <&pmc PMC_TYPE_CORE 27>;
clock-names = "utmi_clk";
resets = <&reset_controller SAMA7G5_RESET_USB_PHY1>,
<&reset_controller SAMA7G5_RESET_USB_PHY2>,
<&reset_controller SAMA7G5_RESET_USB_PHY3>;
reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
};
soc { soc {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
usb2: usb@400000 {
compatible = "microchip,sama7g5-ohci", "usb-ohci";
reg = <0x00400000 0x100000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 106>, <&utmi_clk USB_UTMI1>, <&usb_clk>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
usb3: usb@500000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00500000 0x100000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_clk>, <&pmc PMC_TYPE_PERIPHERAL 106>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
sfr: sfr@e1624000 {
compatible = "microchip,sama7g5-sfr", "syscon";
reg = <0xe1624000 0x4000>;
};
}; };
}; };
@ -38,6 +113,11 @@
&pioA { &pioA {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
pinctrl_usb_default: usb_default {
pinmux = <PIN_PC6__GPIO>;
bias-disable;
};
}; };
&pit64b0 { &pit64b0 {
@ -60,3 +140,31 @@
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
&usb2 {
num-ports = <3>;
atmel,vbus-gpio = <0
0
&pioA PIN_PC6 GPIO_ACTIVE_HIGH
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
phys = <&usb_phy2>;
phy-names = "usb";
status = "okay";
};
&usb3 {
status = "okay";
};
&usb_phy0 {
status = "okay";
};
&usb_phy1 {
status = "okay";
};
&usb_phy2 {
status = "okay";
};

View File

@ -45,13 +45,13 @@
}; };
}; };
gpio_keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>; pinctrl-0 = <&pinctrl_key_gpio_default>;
bp1 { button {
label = "PB_USER"; label = "PB_USER";
gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>; gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>; linux,code = <KEY_PROG1>;
@ -244,8 +244,8 @@
regulators { regulators {
vdd_3v3: VDD_IO { vdd_3v3: VDD_IO {
regulator-name = "VDD_IO"; regulator-name = "VDD_IO";
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3700000>; regulator-max-microvolt = <3300000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-always-on; regulator-always-on;
@ -264,8 +264,8 @@
vddioddr: VDD_DDR { vddioddr: VDD_DDR {
regulator-name = "VDD_DDR"; regulator-name = "VDD_DDR";
regulator-min-microvolt = <1300000>; regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1450000>; regulator-max-microvolt = <1350000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-always-on; regulator-always-on;
@ -285,8 +285,8 @@
vddcore: VDD_CORE { vddcore: VDD_CORE {
regulator-name = "VDD_CORE"; regulator-name = "VDD_CORE";
regulator-min-microvolt = <1100000>; regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1850000>; regulator-max-microvolt = <1150000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-always-on; regulator-always-on;
@ -306,7 +306,7 @@
vddcpu: VDD_OTHER { vddcpu: VDD_OTHER {
regulator-name = "VDD_OTHER"; regulator-name = "VDD_OTHER";
regulator-min-microvolt = <1050000>; regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1850000>; regulator-max-microvolt = <1250000>;
regulator-initial-mode = <2>; regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>; regulator-allowed-modes = <2>, <4>;
regulator-ramp-delay = <3125>; regulator-ramp-delay = <3125>;
@ -326,8 +326,8 @@
vldo1: LDO1 { vldo1: LDO1 {
regulator-name = "LDO1"; regulator-name = "LDO1";
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3700000>; regulator-max-microvolt = <1800000>;
regulator-always-on; regulator-always-on;
regulator-state-standby { regulator-state-standby {
@ -707,7 +707,6 @@
ck_cd_rstn_vddsel { ck_cd_rstn_vddsel {
pinmux = <PIN_PA0__SDMMC0_CK>, pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA2__SDMMC0_RSTN>, <PIN_PA2__SDMMC0_RSTN>,
<PIN_PA14__SDMMC0_CD>,
<PIN_PA11__SDMMC0_DS>; <PIN_PA11__SDMMC0_DS>;
slew-rate = <0>; slew-rate = <0>;
bias-pull-up; bias-pull-up;

View File

@ -67,12 +67,6 @@
status = "disabled"; status = "disabled";
}; };
axp_gpio: gpio {
compatible = "x-powers,axp221-gpio";
gpio-controller;
#gpio-cells = <2>;
};
regulators { regulators {
/* Default work frequency for buck regulators */ /* Default work frequency for buck regulators */
x-powers,dcdc-freq = <3000>; x-powers,dcdc-freq = <3000>;

View File

@ -50,11 +50,4 @@
compatible = "x-powers,axp809"; compatible = "x-powers,axp809";
interrupt-controller; interrupt-controller;
#interrupt-cells = <1>; #interrupt-cells = <1>;
axp_gpio: gpio {
compatible = "x-powers,axp809-gpio",
"x-powers,axp221-gpio";
gpio-controller;
#gpio-cells = <2>;
};
}; };

View File

@ -3,6 +3,8 @@
* Copyright 2018, 2021 NXP * Copyright 2018, 2021 NXP
*/ */
#include "imx8qm-u-boot.dtsi"
&{/imx8qm-pm} { &{/imx8qm-pm} {
u-boot,dm-spl; u-boot,dm-spl;

View File

@ -3,6 +3,8 @@
* Copyright 2019 Toradex AG * Copyright 2019 Toradex AG
*/ */
#include "imx8qxp-u-boot.dtsi"
&{/imx8qx-pm} { &{/imx8qx-pm} {
u-boot,dm-pre-proper; u-boot,dm-pre-proper;

View File

@ -3,6 +3,8 @@
* Copyright 2018, 2021 NXP * Copyright 2018, 2021 NXP
*/ */
#include "imx8qxp-u-boot.dtsi"
&{/imx8qx-pm} { &{/imx8qx-pm} {
u-boot,dm-spl; u-boot,dm-spl;

View File

@ -0,0 +1 @@
#include "imx6qdl-wandboard-u-boot.dtsi"

View File

@ -0,0 +1 @@
#include "imx6qdl-wandboard-u-boot.dtsi"

View File

@ -15,6 +15,22 @@
}; };
}; };
&soc {
u-boot,dm-pre-reloc;
};
&aips1 {
u-boot,dm-pre-reloc;
};
&pinctrl_microsom_uart1 {
u-boot,dm-pre-reloc;
};
&uart1 {
u-boot,dm-pre-reloc;
};
&gpio2 { &gpio2 {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };

View File

@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
#include "imx6qdl-u-boot.dtsi"
/ {
aliases {
mmc0 = &usdhc3;
};
};

View File

@ -0,0 +1 @@
#include "imx6qdl-wandboard-u-boot.dtsi"

View File

@ -285,14 +285,14 @@
&usbotg1 { &usbotg1 {
vbus-supply = <&reg_usbotg1>; vbus-supply = <&reg_usbotg1>;
disable-over-current; disable-over-current;
dr_mode="otg"; dr_mode = "otg";
status = "okay"; status = "okay";
}; };
&usbotg2 { &usbotg2 {
pinctrl-names = "default"; pinctrl-names = "default";
disable-over-current; disable-over-current;
dr_mode="host"; dr_mode = "host";
status = "okay"; status = "okay";
}; };

View File

@ -13,6 +13,10 @@
}; };
}; };
&aips4 {
u-boot,dm-spl;
};
&reg_usdhc2_vmmc { &reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>; u-boot,off-on-delay-us = <20000>;
}; };
@ -77,12 +81,24 @@
u-boot,dm-spl; u-boot,dm-spl;
}; };
&reg_usbotg1 {
};
&uart2 { &uart2 {
u-boot,dm-spl; u-boot,dm-spl;
}; };
&usbmisc1 {
u-boot,dm-spl;
};
&usbotg1 { &usbotg1 {
dr_mode="host"; u-boot,dm-spl;
};
&usbphynop1 {
u-boot,dm-spl;
}; };
&usdhc2 { &usdhc2 {

View File

@ -75,6 +75,11 @@
linux,autosuspend-period = <125>; linux,autosuspend-period = <125>;
}; };
audio_codec_bt_sco: audio-codec-bt-sco {
compatible = "linux,bt-sco";
#sound-dai-cells = <1>;
};
wm8524: audio-codec { wm8524: audio-codec {
#sound-dai-cells = <0>; #sound-dai-cells = <0>;
compatible = "wlf,wm8524"; compatible = "wlf,wm8524";
@ -83,6 +88,25 @@
wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
}; };
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,name = "bt-sco-audio";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion;
simple-audio-card,frame-master = <&btcpu>;
simple-audio-card,bitclock-master = <&btcpu>;
btcpu: simple-audio-card,cpu {
sound-dai = <&sai2>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
simple-audio-card,codec {
sound-dai = <&audio_codec_bt_sco 1>;
};
};
sound-wm8524 { sound-wm8524 {
compatible = "simple-audio-card"; compatible = "simple-audio-card";
simple-audio-card,name = "wm8524-audio"; simple-audio-card,name = "wm8524-audio";
@ -346,6 +370,16 @@
status = "okay"; status = "okay";
}; };
&sai2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&sai3 { &sai3 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>; pinctrl-0 = <&pinctrl_sai3>;
@ -494,6 +528,15 @@
>; >;
}; };
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
>;
};
pinctrl_sai3: sai3grp { pinctrl_sai3: sai3grp {
fsl,pins = < fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6

View File

@ -2,7 +2,7 @@
/* /*
* Copyright (c) 2018 NXP * Copyright (c) 2018 NXP
* Copyright (c) 2019 Engicam srl * Copyright (c) 2019 Engicam srl
* Copyright (c) 2020 Amarula Solutons(India) * Copyright (c) 2020 Amarula Solutions(India)
*/ */
/ { / {

View File

@ -20,13 +20,13 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>; pinctrl-0 = <&pinctrl_led>;
user1 { led-1 {
label = "TestLed601"; label = "TestLed601";
gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0"; linux,default-trigger = "mmc0";
}; };
user2 { led-2 {
label = "TestLed602"; label = "TestLed602";
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
@ -152,11 +152,11 @@
* CPLD_reset is RESET_SOFT in schematic * CPLD_reset is RESET_SOFT in schematic
*/ */
gpio-line-names = gpio-line-names =
"CPLD_D[1]", "CPLD_int", "CPLD_reset", "", "CPLD_D[6]", "CPLD_int", "CPLD_reset", "",
"", "CPLD_D[0]", "", "", "", "CPLD_D[7]", "", "",
"", "", "", "CPLD_D[2]", "", "", "", "CPLD_D[5]",
"CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]", "CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]",
"CPLD_D[7]", "", "", "", "CPLD_D[0]", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "KBD_intK", "", "", "", "KBD_intK",
"", "", "", ""; "", "", "", "";

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