sunxi: Work around lack of Linux MBUS driver

Signed-off-by: Samuel Holland <samuel@sholland.org>

.azure-pipelines.yml

@@ -1,8 +1,8 @@
 variables:
   windows_vm: windows-2019
-  ubuntu_vm: ubuntu-22.04
-  macos_vm: macOS-12
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20221003-17Oct2022
+  ubuntu_vm: ubuntu-18.04
+  macos_vm: macOS-10.15
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20220302-15Mar2022
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
   # since our $(ci_runner_image) user is not root.
@@ -22,9 +22,8 @@ stages:
         displayName: 'Install MSYS2'
       - script: |
           sfx.exe -y -o%CD:~0,2%\
-          %CD:~0,2%\msys64\usr\bin\bash -lc " "
-          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syuu"
-          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syuu"
+          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syyuu"
+          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Su"
         displayName: 'Update MSYS2'
       - script: |
           %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel"
@@ -64,7 +63,6 @@ stages:
       - script: |
           KSYMLST=`mktemp`
           KUSEDLST=`mktemp`
-          RET=0
           cat `find . -name "Kconfig*"` | \
              sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
              -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
@@ -78,12 +76,10 @@ stages:
              NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} | \
                 cut -d , -f 3`
              if [[ $NUM -ne 0 ]]; then
-                echo "Unmigrated symbols found in $CFG:"
-                comm -12 ${KSYMLST} ${KUSEDLST}
-                RET=1
+                echo "Unmigrated symbols found in $CFG"
+                exit 1
              fi
           done
-          exit $RET
 
   - job: cppcheck
     displayName: 'Static code analysis with cppcheck'
@@ -140,7 +136,7 @@ stages:
       options: $(container_option)
     steps:
       - script: |
-          ./tools/buildman/buildman -R
+          if [ `./tools/genboardscfg.py -f 2>&1 | wc -l` -ne 0 ]; then exit 1; fi
 
   - job: tools_only
     displayName: 'Ensure host tools build'
@@ -170,11 +166,13 @@ stages:
       vmImage: $(ubuntu_vm)
     steps:
       - script: |
-          cat << "EOF" > build.sh
-          cd $(work_dir)
+          cat << EOF > build.sh
+          set -ex
+          cd ${WORK_DIR}
+          EOF
+          cat << "EOF" >> build.sh
           git config --global user.name "Azure Pipelines"
           git config --global user.email bmeng.cn@gmail.com
-          git config --global --add safe.directory $(work_dir)
           export USER=azure
           virtualenv -p /usr/bin/python3 /tmp/venv
           . /tmp/venv/bin/activate
@@ -183,7 +181,6 @@ stages:
           export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
           export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
           ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl
-          set -ex
           ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test
           ./tools/buildman/buildman -t
           ./tools/dtoc/dtoc -t
@@ -216,7 +213,7 @@ stages:
       options: $(container_option)
     steps:
       - script: |
-          git config --global --add safe.directory $(work_dir)
+          cd ${WORK_DIR}
           export USER=azure
           pip install -r test/py/requirements.txt
           pip install asteval pylint==2.12.2 pyopenssl
@@ -225,7 +222,6 @@ stages:
           echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
           export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
           ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl
-          set -ex
           pylint --version
           export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
           make pylint_err
@@ -243,15 +239,9 @@ stages:
         sandbox_clang:
           TEST_PY_BD: "sandbox"
           OVERRIDE: "-O clang-13"
-        sandbox_nolto:
-          TEST_PY_BD: "sandbox"
-          BUILD_ENV: "NO_LTO=1"
         sandbox_spl:
           TEST_PY_BD: "sandbox_spl"
           TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
-        sandbox_vpl:
-          TEST_PY_BD: "sandbox_vpl"
-          TEST_PY_TEST_SPEC: "test_vpl_help or test_spl"
         sandbox_noinst:
           TEST_PY_BD: "sandbox_noinst"
           TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
@@ -264,9 +254,6 @@ stages:
         evb_ast2500:
           TEST_PY_BD: "evb-ast2500"
           TEST_PY_ID: "--id qemu"
-        evb_ast2600:
-          TEST_PY_BD: "evb-ast2600"
-          TEST_PY_ID: "--id qemu"
         vexpress_ca9x4:
           TEST_PY_BD: "vexpress_ca9x4"
           TEST_PY_ID: "--id qemu"
@@ -357,7 +344,6 @@ stages:
           export TEST_PY_ID="${TEST_PY_ID}"
           export TEST_PY_TEST_SPEC="${TEST_PY_TEST_SPEC}"
           export OVERRIDE="${OVERRIDE}"
-          export BUILD_ENV="${BUILD_ENV}"
           EOF
           cat << "EOF" >> test.sh
           # the below corresponds to .gitlab-ci.yml "before_script"
@@ -442,10 +428,10 @@ stages:
       vmImage: $(ubuntu_vm)
     strategy:
       # Use almost the same target division in .travis.yml, only merged
-      # 3 small build jobs (arc/microblaze/xtensa) into one.
+      # 4 small build jobs (arc/microblaze/nds32/xtensa) into one.
       matrix:
-        arc_microblaze_xtensa:
-          BUILDMAN: "arc microblaze xtensa"
+        arc_microblaze_nds32_xtensa:
+          BUILDMAN: "arc microblaze nds32 xtensa"
         arm11_arm7_arm920t_arm946es:
           BUILDMAN: "arm11 arm7 arm920t arm946es"
         arm926ejs:
@@ -480,12 +466,6 @@ stages:
           BUILDMAN: "imx8"
         keystone2_keystone3:
           BUILDMAN: "k2 k3"
-        sandbox_asan:
-          BUILDMAN: "sandbox"
-          OVERRIDE: "-a ASAN"
-        sandbox_clang_asan:
-          BUILDMAN: "sandbox"
-          OVERRIDE: "-O clang-13 -a ASAN"
         samsung_socfpga:
           BUILDMAN: "samsung socfpga"
         sun4i:
@@ -518,8 +498,20 @@ stages:
           BUILDMAN: "m68k"
         mips:
           BUILDMAN: "mips"
-        powerpc:
-          BUILDMAN: "powerpc"
+        non_fsl_ppc:
+          BUILDMAN: "powerpc -x freescale"
+        mpc85xx_freescale:
+          BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x bsc91*"
+        t208xrdb_corenet_ds:
+          BUILDMAN: "t208xrdb corenet_ds"
+        fsl_ppc:
+          BUILDMAN: "mpc83xx&freescale"
+        t102x:
+          BUILDMAN: "t102*"
+        p1_p2_rdb_pc:
+          BUILDMAN: "p1_p2_rdb_pc"
+        p1010rdb_bsc91:
+          BUILDMAN: "p1010rdb bsc91"
         siemens:
           BUILDMAN: "siemens"
         tegra:

.github/pull_request_template.md

@@ -1,6 +1,6 @@
 Please do not submit a Pull Request via github.  Our project makes use of
 mailing lists for patch submission and review.  For more details please
-see https://u-boot.readthedocs.io/en/latest/develop/sending_patches.html
+see https://www.denx.de/wiki/U-Boot/Patches
 
 The only exception to this is in order to trigger a CI loop on Azure prior
 to posting of patches.

.gitignore

@@ -10,7 +10,6 @@
 *.asn1.[ch]
 *.bin
 *.cfgout
-*.cover
 *.dtb
 *.dtbo
 *.dtb.S
@@ -23,7 +22,6 @@
 *.lex.c
 *.lst
 *.mod.c
-*.mbx
 *.o
 *.o.*
 *.order

.gitlab-ci.yml

@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-# Grab our configured image.  The source for this is found
-# in the u-boot tree at tools/docker/Dockerfile
-image: trini/u-boot-gitlab-ci-runner:jammy-20221003-17Oct2022
+# Grab our configured image.  The source for this is found at:
+# https://source.denx.de/u-boot/gitlab-ci-runner
+image: trini/u-boot-gitlab-ci-runner:focal-20220302-15Mar2022
 
 # We run some tests in different order, to catch some failures quicker.
 stages:
@@ -33,7 +33,6 @@ stages:
   script:
     # If we've been asked to use clang only do one configuration.
     - export UBOOT_TRAVIS_BUILD_DIR=/tmp/${TEST_PY_BD}
-    - echo BUILD_ENV ${BUILD_ENV}
     - tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e
         --board ${TEST_PY_BD} ${OVERRIDE}
     - cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/
@@ -92,6 +91,7 @@ build all 64bit ARM platforms:
   script:
     - virtualenv -p /usr/bin/python3 /tmp/venv
     - . /tmp/venv/bin/activate
+    - pip install pyelftools
     - ret=0;
       ./tools/buildman/buildman -o /tmp -P -E -W aarch64 || ret=$?;
       if [[ $ret -ne 0 ]]; then
@@ -124,7 +124,6 @@ check for migrated symbols in board header:
   script:
     - KSYMLST=`mktemp`;
       KUSEDLST=`mktemp`;
-      RET=0;
       cat `find . -name "Kconfig*"` |
          sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
          -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
@@ -138,12 +137,10 @@ check for migrated symbols in board header:
          NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} |
             cut -d , -f 3`;
          if [[ $NUM -ne 0 ]]; then
-            echo "Unmigrated symbols found in $CFG:";
-            comm -12 ${KSYMLST} ${KUSEDLST};
-            RET=1;
+            echo "Unmigrated symbols found in $CFG";
+            exit 1;
          fi;
-      done;
-      exit $RET
+      done
 
 # QA jobs for code analytics
 # static code analysis with cppcheck (we can add --enable=all later)
@@ -180,7 +177,7 @@ sloccount:
 Check for configs without MAINTAINERS entry:
   stage: testsuites
   script:
-    - ./tools/buildman/buildman -R
+    - if [ `./tools/genboardscfg.py -f 2>&1 | wc -l` -ne 0 ]; then exit 1; fi
 
 # Ensure host tools build
 Build tools-only:
@@ -199,7 +196,6 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites:
   script:
     - git config --global user.name "GitLab CI Runner";
       git config --global user.email trini@konsulko.com;
-      git config --global --add safe.directory "${CI_PROJECT_DIR}";
       export USER=gitlab;
       virtualenv -p /usr/bin/python3 /tmp/venv;
       . /tmp/venv/bin/activate;
@@ -207,10 +203,8 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites:
       export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl;
       export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
       export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
-      set +e;
       ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
         --board sandbox_spl;
-      set -e;
       ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
       ./tools/buildman/buildman -t;
       ./tools/dtoc/dtoc -t;
@@ -227,17 +221,14 @@ Run tests for Nokia RX-51 (aka N900):
 Run pylint:
   stage: testsuites
   script:
-    - git config --global --add safe.directory "${CI_PROJECT_DIR}"
     - pip install -r test/py/requirements.txt
     - pip install asteval pylint==2.12.2 pyopenssl
     - export PATH=${PATH}:~/.local/bin
     - echo "[MASTER]" >> .pylintrc
     - echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
     - export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
-    - set +e
     - ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
         --board sandbox_spl
-    - set -e
     - pylint --version
     - export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
     - make pylint_err
@@ -254,12 +245,6 @@ sandbox with clang test.py:
     OVERRIDE: "-O clang-13"
   <<: *buildman_and_testpy_dfn
 
-sandbox without LTO test.py:
-  variables:
-    TEST_PY_BD: "sandbox"
-    BUILD_ENV: "NO_LTO=1"
-  <<: *buildman_and_testpy_dfn
-
 sandbox_spl test.py:
   variables:
     TEST_PY_BD: "sandbox_spl"
@@ -272,24 +257,12 @@ sandbox_noinst_test.py:
     TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
   <<: *buildman_and_testpy_dfn
 
-sandbox_vpl test.py:
-  variables:
-    TEST_PY_BD: "sandbox_vpl"
-    TEST_PY_TEST_SPEC: "test_vpl_help or test_spl"
-  <<: *buildman_and_testpy_dfn
-
 evb-ast2500 test.py:
   variables:
     TEST_PY_BD: "evb-ast2500"
     TEST_PY_ID: "--id qemu"
   <<: *buildman_and_testpy_dfn
 
-evb-ast2600 test.py:
-  variables:
-    TEST_PY_BD: "evb-ast2600"
-    TEST_PY_ID: "--id qemu"
-  <<: *buildman_and_testpy_dfn
-
 sandbox_flattree test.py:
   variables:
     TEST_PY_BD: "sandbox_flattree"

.mailmap

@@ -37,19 +37,15 @@ Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
 Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
 Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
 Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
-Marek Behún <kabel@kernel.org> <marek.behun@nic.cz>
-Marek Behún <kabel@kernel.org> Marek Behun <marek.behun@nic.cz>
 Marek Vasut <marex@denx.de> <marek.vasut+renesas@gmail.com>
 Marek Vasut <marex@denx.de> <marek.vasut@gmail.com>
 Marek Vasut <marex@denx.de> <marex at denx.de>
 Markus Klotzbuecher <mk@denx.de>
 Masahiro Yamada <yamada.masahiro@socionext.com> <yamada.m@jp.panasonic.com>
 Masahiro Yamada <yamada.masahiro@socionext.com> <masahiroy@kernel.org>
-Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com>
 Michal Simek <michal.simek@xilinx.com> <monstr@monstr.eu>
 Michal Simek <michal.simek@xilinx.com> <Monstr@seznam.cz>
 Michal Simek <michal.simek@xilinx.com> <root@monstr.eu>
-Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com>
 Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
 Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
 Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>

Kconfig

@@ -12,6 +12,8 @@ source "scripts/Kconfig.include"
 # Allow defaults in arch-specific code to override any given here
 source "arch/Kconfig"
 
+source "board/sunxi/Kconfig"
+
 menu "General setup"
 
 config BROKEN
@@ -154,22 +156,6 @@ config CC_COVERAGE
 	  Enabling this option will pass "--coverage" to gcc to compile
 	  and link code instrumented for coverage analysis.
 
-config ASAN
-	bool "Enable AddressSanitizer"
-	depends on SANDBOX
-	help
-	  Enables AddressSanitizer to discover out-of-bounds accesses,
-	  use-after-free, double-free and memory leaks.
-
-config FUZZ
-	bool "Enable fuzzing"
-	depends on CC_IS_CLANG
-	depends on DM_FUZZING_ENGINE
-	select ASAN
-	help
-	  Enables the fuzzing infrastructure to generate fuzzing data and run
-          fuzz tests.
-
 config CC_HAS_ASM_INLINE
 	def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC) -x c - -c -o /dev/null)
 
@@ -244,38 +230,12 @@ config SYS_BOOT_GET_CMDLINE
 	  Enables allocating and saving kernel cmdline in space between
 	  "bootm_low" and "bootm_low" + BOOTMAPSZ.
 
-config SYS_BARGSIZE
-	int "Size of kernel command line buffer in bytes"
-	depends on SYS_BOOT_GET_CMDLINE
-	default 512
-	help
-	  Buffer size for Boot Arguments which are passed to the application
-	  (usually a Linux kernel) when it is booted
-
 config SYS_BOOT_GET_KBD
 	bool "Enable kernel board information setup"
 	help
 	  Enables allocating and saving a kernel copy of the bd_info in
 	  space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
 
-config HAS_CUSTOM_SYS_INIT_SP_ADDR
-	bool "Use a custom location for the initial stack pointer address"
-	depends on ARC || (ARM && !INIT_SP_RELATIVE) || MIPS || PPC || RISCV
-	default y if TFABOOT
-	help
-	  Typically, we use an initial stack pointer address that is calculated
-	  by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the
-	  statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the
-	  build-time constant of GENERATED_GBL_DATA_SIZE.  On MIPS a different
-	  but statica calculation is performed.  However, some platforms will
-	  take a different approach.  Say Y here to define the address statically
-	  instead.
-
-config CUSTOM_SYS_INIT_SP_ADDR
-	hex "Static location for the initial stack pointer"
-	depends on HAS_CUSTOM_SYS_INIT_SP_ADDR
-	default TEXT_BASE if TFABOOT
-
 config SYS_MALLOC_F
 	bool "Enable malloc() pool before relocation"
 	default y if DM
@@ -289,18 +249,13 @@ config SYS_MALLOC_F
 config SYS_MALLOC_F_LEN
 	hex "Size of malloc() pool before relocation"
 	depends on SYS_MALLOC_F
-	default 0x400 if M68K || PPC || ROCKCHIP_PX30 || ROCKCHIP_RK3036 || \
-			 ROCKCHIP_RK3308 || ROCKCHIP_RV1108
-	default 0x600 if ARCH_ZYNQMP_R5 || ARCH_ZYNQMP
-	default 0x800 if ARCH_ZYNQ || ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \
-			 ROCKCHIP_RK322X || X86
-	default 0x1000 if ARCH_MESON || ARCH_BMIPS || ARCH_MTMIPS
-	default 0x1800 if ARCH_TEGRA
-	default 0x4000 if SANDBOX || RISCV || ARCH_APPLE || ROCKCHIP_RK3368 || \
-			  ROCKCHIP_RK3399
-	default 0x8000 if RCAR_GEN3
-	default 0x10000 if ARCH_IMX8 || ARCH_IMX8M
-	default 0x2000
+	default 0x1000 if AM33XX
+	default 0x4000 if SANDBOX
+	default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \
+			   ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \
+			   ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \
+			   ARCH_LS1046A || ARCH_QEMU || ARCH_SUNXI || ARCH_OWL || TARGET_SUNXI)
+	default 0x400
 	help
 	  Before relocation, memory is very limited on many platforms. Still,
 	  we can provide a small malloc() pool if needed. Driver model in
@@ -309,12 +264,11 @@ config SYS_MALLOC_F_LEN
 
 config SYS_MALLOC_LEN
 	hex "Define memory for Dynamic allocation"
-	default 0x4000000 if SANDBOX
 	default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
 	default 0x200000 if ARCH_BMIPS || X86
-	default 0x4020000 if SUNXI_MINIMUM_DRAM_MB >= 256
-	default 0x220000 if SUNXI_MINIMUM_DRAM_MB >= 64
-	default 0x120000 if SUNXI_MINIMUM_DRAM_MB >= 32
+	default 0x120000 if MACH_SUNIV
+	default 0x220000 if MACH_SUN8I_V3S
+	default 0x4020000 if ARCH_SUNXI
 	default 0x400000
 	help
 	  This defines memory to be allocated for Dynamic allocation
@@ -323,9 +277,7 @@ config SYS_MALLOC_LEN
 config SPL_SYS_MALLOC_F_LEN
 	hex "Size of malloc() pool in SPL"
 	depends on SYS_MALLOC_F && SPL
-	default 0 if !SPL_FRAMEWORK
 	default 0x2800 if RCAR_GEN3
-	default 0x2000 if IMX8MQ
 	default SYS_MALLOC_F_LEN
 	help
 	  In SPL memory is very limited on many platforms. Still,
@@ -346,31 +298,6 @@ config TPL_SYS_MALLOC_F_LEN
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.
 
-config VALGRIND
-	bool "Inform valgrind about memory allocations"
-	depends on !RISCV
-	help
-	  Valgrind is an instrumentation framework for building dynamic analysis
-	  tools. In particular, it may be used to detect memory management bugs
-	  in U-Boot. It relies on knowing when heap blocks are allocated in
-	  order to give accurate results. This happens automatically for
-	  standard allocator functions provided by the host OS. However, this
-	  doesn't automatically happen for U-Boot's malloc implementation.
-
-	  Enable this option to annotate U-Boot's malloc implementation so that
-	  it can be handled accurately by Valgrind. If you aren't planning on
-	  using valgrind to debug U-Boot, say 'n'.
-
-config VPL_SYS_MALLOC_F_LEN
-	hex "Size of malloc() pool in VPL before relocation"
-	depends on SYS_MALLOC_F && VPL
-	default SYS_MALLOC_F_LEN
-	help
-	  Before relocation, memory is very limited on many platforms. Still,
-	  we can provide a small malloc() pool if needed. Driver model in
-	  particular needs this to operate, so that it can allocate the
-	  initial serial device and any others that are needed.
-
 menuconfig EXPERT
 	bool "Configure standard U-Boot features (expert users)"
 	default y
@@ -470,23 +397,6 @@ config BUILD_TARGET
 	  special image will be automatically built upon calling
 	  make / buildman.
 
-config HAS_BOARD_SIZE_LIMIT
-	bool "Define a maximum size for the U-Boot image"
-	default y if RCAR_GEN3
-	help
-	  In some cases, we need to enforce a hard limit on how big the U-Boot
-	  image itself can be.
-
-config BOARD_SIZE_LIMIT
-	int "Maximum size of the U-Boot image in bytes"
-	default 1048576 if RCAR_GEN3
-	depends on HAS_BOARD_SIZE_LIMIT
-	help
-	  Maximum size of the U-Boot image. When defined, the build system
-	  checks that the actual size does not exceed it.  This does not
-	  include SPL nor TPL, on platforms that use that functionality, they
-	  have a separate option to restict size.
-
 config SYS_CUSTOM_LDSCRIPT
 	bool "Use a custom location for the U-Boot linker script"
 	help
@@ -508,6 +418,9 @@ config SYS_LOAD_ADDR
 	hex "Address in memory to use by default"
 	default 0x01000000 if ARCH_SOCFPGA
 	default 0x02000000 if PPC || X86
+	default 0x81000000 if MACH_SUNIV
+	default 0x22000000 if MACH_SUN9I
+	default 0x42000000 if ARCH_SUNXI
 	default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
 	default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
 	default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
@@ -537,7 +450,7 @@ config PLATFORM_ELFENTRY
 
 config STACK_SIZE
 	hex "Define max stack size that can be used by U-Boot"
-	default 0x4000000 if ARCH_VERSAL_NET || ARCH_VERSAL || ARCH_ZYNQMP
+	default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
 	default 0x200000 if MICROBLAZE
 	default 0x1000000
 	help
@@ -545,17 +458,6 @@ config STACK_SIZE
 	  by the UEFI sub-system. On some boards initrd_high is calculated as
 	  base stack pointer minus this stack size.
 
-config SYS_MEM_TOP_HIDE
-	hex "Exclude some memory from U-Boot / OS information"
-	default 0x0
-	help
-	  If set, this specified memory area will get subtracted from the top
-	  (end) of RAM and won't get "touched" at all by U-Boot. By fixing up
-	  gd->ram_size the OS / next stage should gets passed the now
-	  "corrected" memory size and won't touch it either.
-	  WARNING: Please make sure that this value is a multiple of the OS
-	  page size.
-
 config SYS_HAS_SRAM
 	bool
 	default y if TARGET_PIC32MZDASK

Licenses/Exceptions

@@ -7,13 +7,9 @@ use U-Boot services by means of the jump table provided by U-Boot
 exactly for this purpose - this is merely considered normal use of
 U-Boot, and does *not* fall under the heading of "derived work".
 
-The following files define interfaces to U-Boot:
-  * include/image.h
-  * include/export.h
-  * arch/*/include/asm/u-boot.h
-  * examples/standalone/stubs.c
-
-Including these (unmodified) files in another file is considered normal
-use of U-Boot, and does *not* fall under the heading of "derived work".
+  The header files "include/image.h" and "arch/*/include/asm/u-boot.h"
+define interfaces to U-Boot.  Including these (unmodified) header
+files in another file is considered normal use of U-Boot, and does
+*not* fall under the heading of "derived work".
 -- Wolfgang Denk
 

Licenses/README

@@ -139,7 +139,6 @@ License identifier syntax
 
 Full name					SPDX Identifier	OSI Approved	File name		URI
 =======================================================================================================================================
-bzip2 and libbzip2 License v1.0.6		bzip2-1.0.6			bzip2-1.0.6.txt		https://spdx.org/licenses/bzip2-1.0.6.html
 GNU General Public License v2.0 only		GPL-2.0		Y		gpl-2.0.txt		http://www.gnu.org/licenses/gpl-2.0.txt
 GNU General Public License v2.0 or later	GPL-2.0+	Y		gpl-2.0.txt		http://www.gnu.org/licenses/gpl-2.0.txt
 GNU Library General Public License v2 or later	LGPL-2.0+	Y		lgpl-2.0.txt		http://www.gnu.org/licenses/old-licenses/lgpl-2.0.txt

Licenses/bzip2-1.0.6.txt

@@ -1,30 +0,0 @@
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-
-2. The origin of this software must not be misrepresented; you must 
-   not claim that you wrote the original software.  If you use this 
-   software in a product, an acknowledgment in the product 
-   documentation would be appreciated but is not required.
-
-3. Altered source versions must be plainly marked as such, and must
-   not be misrepresented as being the original software.
-
-4. The name of the author may not be used to endorse or promote 
-   products derived from this software without specific prior written 
-   permission.
-
-THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
-OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

MAINTAINERS

@@ -121,7 +121,6 @@ F:	arch/arm/include/asm/arch-m1/
 F:	arch/arm/mach-apple/
 F:	configs/apple_m1_defconfig
 F:	drivers/iommu/apple_dart.c
-F:	drivers/nvme/nvme_apple.c
 F:	drivers/pinctrl/pinctrl-apple.c
 F:	drivers/watchdog/apple_wdt.c
 F:	include/configs/apple.h
@@ -143,7 +142,7 @@ F:	arch/arm/mach-socfpga/
 F:	drivers/sysreset/sysreset_socfpga*
 
 ARM AMLOGIC SOC SUPPORT
-M:	Neil Armstrong <neil.armstrong@linaro.org>
+M:	Neil Armstrong <narmstrong@baylibre.com>
 S:	Maintained
 L:	u-boot-amlogic@groups.io
 T:	git https://source.denx.de/u-boot/custodians/u-boot-amlogic.git
@@ -161,7 +160,6 @@ F:	drivers/spi/meson_spifc.c
 F:	drivers/pinctrl/meson/
 F:	drivers/power/domain/meson-gx-pwrc-vpu.c
 F:	drivers/video/meson/
-F:	drivers/watchdog/meson_gxbb_wdt.c
 F:	include/configs/meson64.h
 F:	include/configs/meson64_android.h
 F:	doc/board/amlogic/
@@ -171,23 +169,12 @@ ARM ASPEED
 M:	Ryan Chen <ryan_chen@aspeedtech.com>
 M:	Chia-Wei Wang <chiawei_wang@aspeedtech.com>
 R:	Aspeed BMC SW team <BMC-SW@aspeedtech.com>
-R:	Joel Stanley <joel@jms.id.au>
 S:	Maintained
 F:	arch/arm/mach-aspeed/
 F:	arch/arm/include/asm/arch-aspeed/
 F:	board/aspeed/
 F:	drivers/clk/aspeed/
-F:	drivers/crypto/aspeed/
-F:	drivers/gpio/gpio-aspeed.c
-F:	drivers/i2c/ast_i2c.[ch]
-F:	drivers/mmc/aspeed_sdhci.c
-F:	drivers/net/aspeed_mdio.c
-F:	drivers/net/ftgmac100.[ch]
 F:	drivers/pinctrl/aspeed/
-F:	drivers/pwm/pwm-aspeed.c
-F:	drivers/ram/aspeed/
-F:	drivers/reset/reset-ast2500.c
-F:	drivers/watchdog/ast_wdt.c
 N:	aspeed
 
 ARM BROADCOM BCM283X / BCM27XX
@@ -208,32 +195,6 @@ F:	drivers/pinctrl/broadcom/
 F:	configs/rpi_*
 T:	git https://source.denx.de/u-boot/custodians/u-boot-arm.git
 
-ARM BROADCOM BCMBCA
-M:	Anand Gore <anand.gore@broadcom.com>
-M:	William Zhang <william.zhang@broadcom.com>
-M:	Kursad Oney <kursad.oney@broadcom.com>
-M:	Joel Peshkin <joel.peshkin@broadcom.com>
-M:	Philippe Reynes <philippe.reynes@softathome.com>
-S:	Maintained
-F:	arch/arm/mach-bcmbca/
-F:	board/broadcom/bcmbca/
-N:	bcmbca
-N:	bcm[9]?47622
-N:	bcm[9]?4908
-N:	bcm[9]?4912
-N:	bcm[9]?63138
-N:	bcm[9]?63146
-N:	bcm[9]?63148
-N:	bcm[9]?63158
-N:	bcm[9]?63178
-N:	bcm[9]?6756
-N:	bcm[9]?6813
-N:	bcm[9]?6846
-N:	bcm[9]?6855
-N:	bcm[9]?6856
-N:	bcm[9]?6858
-N:	bcm[9]?6878
-
 ARM BROADCOM BCMSTB
 M:	Thomas Fitzsimmons <fitzsim@fitzsim.org>
 S:	Maintained
@@ -263,6 +224,14 @@ F:	drivers/net/cortina_ni.h
 F:	drivers/net/phy/ca_phy.c
 F:	configs/cortina_presidio-asic-pnand_defconfig
 
+ARM/CZ.NIC TURRIS MOX SUPPORT
+M:	Marek Behun <marek.behun@nic.cz>
+S:	Maintained
+F:	arch/arm/dts/armada-3720-turris-mox.dts
+F:	board/CZ.NIC/
+F:	configs/turris_*_defconfig
+F:	include/configs/turris_*.h
+
 ARM FREESCALE IMX
 M:	Stefano Babic <sbabic@denx.de>
 M:	Fabio Estevam <festevam@gmail.com>
@@ -274,12 +243,11 @@ F:	arch/arm/cpu/arm926ejs/mx*/
 F:	arch/arm/cpu/armv7/vf610/
 F:	arch/arm/dts/*imx*
 F:	arch/arm/mach-imx/
-F:	arch/arm/include/asm/arch-imx*/
+F:	arch/arm/include/asm/arch-imx/
 F:	arch/arm/include/asm/arch-mx*/
 F:	arch/arm/include/asm/arch-vf610/
 F:	arch/arm/include/asm/mach-imx/
 F:	board/freescale/*mx*/
-F:	drivers/serial/serial_mxc.c
 
 ARM HISILICON
 M:	Peter Griffin <peter.griffin@linaro.org>
@@ -289,19 +257,6 @@ F:	arch/arm/cpu/armv8/hisilicon
 F:	arch/arm/include/asm/arch-hi6220/
 F:	arch/arm/include/asm/arch-hi3660/
 
-ARM HPE GXP ARCHITECTURE
-M:	Jean-Marie Verdun <verdun@hpe.com>
-M:	Nick Hawkins <nick.hawkins@hpe.com>
-S:	Maintained
-F:	arch/arm/dts/hpe-bmc*
-F:	arch/arm/dts/hpe-gxp*
-F:	arch/arm/mach-hpe/
-F:	board/hpe/
-F:	configs/gxp_defconfig
-F:	doc/device-tree-bindings/spi/hpe,gxp-spi.yaml
-F:	drivers/timer/gxp-timer.c
-F:	drivers/spi/gxp_spi.c
-
 ARM IPQ40XX
 M:	Robert Marko <robert.marko@sartura.hr>
 M:	Luka Kovacic <luka.kovacic@sartura.hr>
@@ -316,11 +271,6 @@ F:	drivers/spi/spi-qup.c
 F:	drivers/net/mdio-ipq4019.c
 F:	drivers/rng/msm_rng.c
 
-ARM LAYERSCAPE SFP
-M:	Sean Anderson <sean.anderson@seco.com>
-S:	Maintained
-F:	drivers/misc/ls2_sfp.c
-
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
@@ -358,6 +308,13 @@ S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
 F:	drivers/serial/serial_mvebu_a3700.c
 
+ARM MARVELL PXA
+M:	Marek Vasut <marex@denx.de>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/custodians/u-boot-pxa.git
+F:	arch/arm/cpu/pxa/
+F:	arch/arm/include/asm/arch-pxa/
+
 ARM MEDIATEK
 M:	Ryder Lee <ryder.lee@mediatek.com>
 M:	Weijie Gao <weijie.gao@mediatek.com>
@@ -371,36 +328,22 @@ F:	doc/device-tree-bindings/phy/phy-mtk-*
 F:	doc/device-tree-bindings/usb/mediatek,*
 F:	doc/README.mediatek
 F:	drivers/clk/mediatek/
-F:	drivers/cpu/mtk_cpu.c
-F:	drivers/i2c/mtk_i2c.c
 F:	drivers/mmc/mtk-sd.c
 F:	drivers/phy/phy-mtk-*
 F:	drivers/pinctrl/mediatek/
 F:	drivers/power/domain/mtk-power-domain.c
 F:	drivers/ram/mediatek/
 F:	drivers/spi/mtk_snfi_spi.c
-F:	drivers/spi/mtk_spim.c
 F:	drivers/timer/mtk_timer.c
 F:	drivers/usb/host/xhci-mtk.c
 F:	drivers/usb/mtu3/
 F:	drivers/watchdog/mtk_wdt.c
 F:	drivers/net/mtk_eth.c
-F:	drivers/net/mtk_eth.h
 F:	drivers/reset/reset-mediatek.c
 F:	tools/mtk_image.c
 F:	tools/mtk_image.h
-F:	tools/mtk_nand_headers.c
-F:	tools/mtk_nand_headers.h
 N:	mediatek
 
-ARM METHODE SUPPORT
-M:	Robert Marko <robert.marko@sartura.hr>
-S:	Maintained
-F:	arch/arm/dts/armada-3720-eDPU*
-F:	arch/arm/dts/armada-3720-uDPU*
-F:	configs/eDPU_defconfig
-F:	configs/uDPU_defconfig
-
 ARM MICROCHIP/ATMEL AT91
 M:	Eugen Hristev <eugen.hristev@microchip.com>
 S:	Maintained
@@ -510,7 +453,7 @@ F:	drivers/mmc/sti_sdhci.c
 F:	drivers/reset/sti-reset.c
 F:	drivers/serial/serial_sti_asc.c
 F:	drivers/sysreset/sysreset_sti.c
-F:	drivers/timer/arm_global_timer.c
+F:	drivers/timer/sti-timer.c
 F:	drivers/usb/host/dwc3-sti-glue.c
 F:	include/dwc3-sti-glue.h
 F:	include/dt-bindings/clock/stih407-clks.h
@@ -526,7 +469,7 @@ S:	Maintained
 F:	arch/arm/mach-stm32mp/
 F:	doc/board/st/
 F:	drivers/adc/stm32-adc*
-F:	drivers/clk/stm32/
+F:	drivers/clk/clk_stm32mp1.c
 F:	drivers/gpio/stm32_gpio.c
 F:	drivers/hwspinlock/stm32_hwspinlock.c
 F:	drivers/i2c/stm32f7_i2c.c
@@ -543,7 +486,6 @@ F:	drivers/power/regulator/stpmic1.c
 F:	drivers/ram/stm32mp1/
 F:	drivers/remoteproc/stm32_copro.c
 F:	drivers/reset/stm32-reset.c
-F:	drivers/rng/optee_rng.c
 F:	drivers/rng/stm32mp1_rng.c
 F:	drivers/rtc/stm32_rtc.c
 F:	drivers/serial/serial_stm32.*
@@ -650,21 +592,13 @@ F:	arch/arm/mach-uniphier/
 F:	configs/uniphier_*_defconfig
 N:	uniphier
 
-ARM VERSAL NET
-M:	Michal Simek <michal.simek@amd.com>
-S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
-F:	arch/arm/mach-versal-net/
-N:	(?<!uni)versal-net
-
 ARM VERSAL
-M:	Michal Simek <michal.simek@amd.com>
+M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-versal/
 F:	drivers/net/xilinx_axi_mrmac.*
 F:	drivers/soc/soc_xilinx_versal.c
-F:	drivers/spi/cadence_ospi_versal.c
 F:	drivers/watchdog/xilinx_wwdt.c
 N:	(?<!uni)versal
 
@@ -704,7 +638,7 @@ F:	tools/zynqimage.c
 N:	zynq
 
 ARM ZYNQMP
-M:	Michal Simek <michal.simek@amd.com>
+M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-zynqmp/
@@ -741,7 +675,7 @@ N:	ultra96
 N:	zynqmp
 
 ARM ZYNQMP R5
-M:	Michal Simek <michal.simek@amd.com>
+M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-zynqmp-r5/
@@ -753,42 +687,13 @@ S:	Maintained
 F:	drivers/pci/pcie_phytium.c
 F:	arch/arm/dts/phytium-durian.dts
 
-ASPEED FMC SPI DRIVER
-M:	Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
-M:	Cédric Le Goater <clg@kaod.org>
-R:	Aspeed BMC SW team <BMC-SW@aspeedtech.com>
-S:	Maintained
-F:	drivers/spi/spi-aspeed-smc.c
-
 BINMAN
 M:	Simon Glass <sjg@chromium.org>
-M:	Alper Nebi Yasak <alpernebiyasak@gmail.com>
 S:	Maintained
 F:	tools/binman/
 
-BOOTDEVICE
-M:	Simon Glass <sjg@chromium.org>
-S:	Maintained
-F:	boot/bootdev*.c
-F:	boot/bootflow.c
-F:	boot/bootmeth*.c
-F:	boot/bootstd.c
-F:	cmd/bootdev.c
-F:	cmd/bootflow.c
-F:	doc/develop/bootstd.rst
-F:	doc/usage/bootdev.rst
-F:	doc/usage/bootflow.rst
-F:	doc/usage/bootmeth.rst
-F:	drivers/mmc/mmc_bootdev.c
-F:	include/bootdev.h
-F:	include/bootflow.h
-F:	include/bootmeth.h
-F:	include/bootstd.h
-F:	net/eth_bootdevice.c
-F:	test/boot/
-
 BTRFS
-M:	Marek Behún <kabel@kernel.org>
+M:	Marek Behun <marek.behun@nic.cz>
 R:	Qu Wenruo <wqu@suse.com>
 L:	linux-btrfs@vger.kernel.org
 S:	Maintained
@@ -801,11 +706,6 @@ M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	tools/buildman/
 
-CAT
-M:	Roger Knecht <rknecht@pm.me>
-S:	Maintained
-F:	cmd/cat.c
-
 CFI FLASH
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
@@ -829,13 +729,6 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-coldfire.git
 F:	arch/m68k/
 F:	doc/arch/m68k.rst
 
-CYCLIC
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	cmd/cyclic.c
-F:	common/cyclic.c
-F:	include/cyclic.h
-
 DFU
 M:	Lukasz Majewski <lukma@denx.de>
 S:	Maintained
@@ -876,7 +769,6 @@ F:	test/dm/efi_media.c
 
 EFI PAYLOAD
 M:	Heinrich Schuchardt <xypron.glpk@gmx.de>
-M:	Ilias Apalodimas <ilias.apalodimas@linaro.org>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-efi.git
 F:	doc/api/efi.rst
@@ -891,7 +783,6 @@ F:	include/cp437.h
 F:	include/efi*
 F:	include/pe.h
 F:	include/asm-generic/pe.h
-F:	include/mm_communication.h
 F:	lib/charset.c
 F:	lib/efi*/
 F:	test/lib/efi_*
@@ -905,6 +796,12 @@ F:	tools/efivar.py
 F:	tools/file2include.c
 F:	tools/mkeficapsule.c
 
+EFI VARIABLES VIA OP-TEE
+M:	Ilias Apalodimas <ilias.apalodimas@linaro.org>
+S:	Maintained
+F:	lib/efi_loader/efi_variable_tee.c
+F:	include/mm_communication.h
+
 ENVIRONMENT
 M:	Joe Hershberger <joe.hershberger@ni.com>
 R:	Wolfgang Denk <wd@denx.de>
@@ -954,13 +851,12 @@ F:	net/fastboot.c
 F:	test/dm/fastboot.c
 
 FPGA
-M:	Michal Simek <michal.simek@amd.com>
+M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	drivers/fpga/
 F:	cmd/fpga.c
 F:	include/fpga.h
-F:	test/dm/fpga.c
 
 FLATTENED DEVICE TREE
 M:	Simon Glass <sjg@chromium.org>
@@ -986,12 +882,6 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git
 F:	drivers/watchdog/sp805_wdt.c
 F:	drivers/watchdog/sbsa_gwdt.c
 
-GATEWORKS_SC
-M:	Tim Harvey <tharvey@gateworks.com>
-S:	Maintained
-F:	drivers/misc/gsc.c
-F:	include/gsc.h
-
 I2C
 M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
@@ -1000,7 +890,7 @@ F:	drivers/i2c/
 
 KWBIMAGE / KWBOOT TOOLS
 M:	Pali Rohár <pali@kernel.org>
-M:	Marek Behún <kabel@kernel.org>
+M:	Marek Behún <marek.behun@nic.cz>
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
@@ -1008,12 +898,6 @@ F:	doc/README.kwbimage
 F:	doc/kwboot.1
 F:	tools/kwb*
 
-LED
-M:	Ivan Vozvakhov <i.vozvakhov@vk.team>
-S:	Supported
-F:	doc/device-tree-bindings/leds/leds-pwm.txt
-F:	drivers/led/led_pwm.c
-
 LOGGING
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
@@ -1045,7 +929,6 @@ F:	drivers/net/xilinx_emaclite.c
 F:	drivers/serial/serial_xuartlite.c
 F:	drivers/spi/xilinx_spi.c
 F:	drivers/sysreset/sysreset_gpio.c
-F:	drivers/timer/xilinx-timer.c
 F:	drivers/watchdog/xilinx_tb_wdt.c
 N:	xilinx
 
@@ -1077,23 +960,15 @@ R:	GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
 S:	Maintained
 F:	arch/mips/mach-mtmips/
 F:	arch/mips/dts/mt7620.dtsi
-F:	arch/mips/dts/mt7621.dtsi
 F:	arch/mips/dts/mt7620-u-boot.dtsi
-F:	arch/mips/dts/mt7621-u-boot.dtsi
 F:	include/configs/mt7620.h
-F:	include/configs/mt7621.h
 F:	include/dt-bindings/clock/mt7620-clk.h
-F:	include/dt-bindings/clock/mt7621-clk.h
 F:	include/dt-bindings/clock/mt7628-clk.h
 F:	include/dt-bindings/reset/mt7620-reset.h
-F:	include/dt-bindings/reset/mt7621-reset.h
 F:	include/dt-bindings/reset/mt7628-reset.h
 F:	drivers/clk/mtmips/
 F:	drivers/pinctrl/mtmips/
 F:	drivers/gpio/mt7620_gpio.c
-F:	drivers/mtd/nand/raw/mt7621_nand.c
-F:	drivers/mtd/nand/raw/mt7621_nand.h
-F:	drivers/mtd/nand/raw/mt7621_nand_spl.c
 F:	drivers/net/mt7620-eth.c
 F:	drivers/phy/mt7620-usb-phy.c
 F:	drivers/reset/reset-mtmips.c
@@ -1142,12 +1017,17 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-mmc.git
 F:	drivers/mmc/
 
 NAND FLASH
-M:	Dario Binacchi <dario.binacchi@amarulasolutions.com>
-M:	Michael Trimarchi <michael@amarulasolutions.com>
-S:	Maintained
+#M:	Scott Wood <oss@buserror.net>
+S:	Orphaned (Since 2018-07)
 T:	git https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
 F:	drivers/mtd/nand/raw/
 
+NDS32
+M:	Rick Chen <rick@andestech.com>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/custodians/u-boot-nds32.git
+F:	arch/nds32/
+
 NETWORK
 M:	Joe Hershberger <joe.hershberger@ni.com>
 M:	Ramon Fried <rfried.dev@gmail.com>
@@ -1171,13 +1051,6 @@ F:	cmd/nvme.c
 F:	include/nvme.h
 F:	doc/develop/driver-model/nvme.rst
 
-NVMEM
-M:	Sean Anderson <seanga2@gmail.com>
-S:	Maintained
-F:	doc/api/nvmem.rst
-F:	drivers/misc/nvmem.c
-F:	include/nvmem.h
-
 NXP C45 TJA11XX PHY DRIVER
 M:	Radu Pirea <radu-nicolae.pirea@oss.nxp.com>
 S:	Maintained
@@ -1253,7 +1126,7 @@ F:	arch/powerpc/cpu/mpc83xx/
 F:	arch/powerpc/include/asm/arch-mpc83xx/
 
 POWERPC MPC85XX
-M:	Marek Behún <kabel@kernel.org>
+M:	Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git
 F:	arch/powerpc/cpu/mpc85xx/
@@ -1329,11 +1202,6 @@ F:	drivers/gpio/sl28cpld-gpio.c
 F:	drivers/misc/sl28cpld.c
 F:	drivers/watchdog/sl28cpld-wdt.c
 
-SMCCC TRNG
-M:	Etienne Carriere <etienne.carriere@linaro.org>
-S:	Maintained
-F:	drivers/rng/smccc_trng.c
-
 SPI
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
@@ -1357,7 +1225,7 @@ F:	drivers/spmi/
 F:	include/spmi/
 
 SQUASHFS
-M:	Joao Marcos Costa <jmcosta944@gmail.com>
+M:	Joao Marcos Costa <joaomarcos.costa@bootlin.com>
 R:	Thomas Petazzoni <thomas.petazzoni@bootlin.com>
 R:	Miquel Raynal <miquel.raynal@bootlin.com>
 S:	Maintained
@@ -1408,7 +1276,6 @@ F:	arch/arm/mach-k3/config_secure.mk
 F:	configs/am335x_hs_evm_defconfig
 F:	configs/am335x_hs_evm_uart_defconfig
 F:	configs/am43xx_hs_evm_defconfig
-F:	configs/am43xx_hs_evm_qspi_defconfig
 F:	configs/am57xx_hs_evm_defconfig
 F:	configs/am57xx_hs_evm_usb_defconfig
 F:	configs/dra7xx_hs_evm_defconfig
@@ -1419,12 +1286,8 @@ F:	configs/k2g_hs_evm_defconfig
 F:	configs/k2l_hs_evm_defconfig
 F:	configs/am65x_hs_evm_r5_defconfig
 F:	configs/am65x_hs_evm_a53_defconfig
-F:	configs/j7200_hs_evm_a72_defconfig
-F:	configs/j7200_hs_evm_r5_defconfig
-F:	configs/j721e_hs_evm_a72_defconfig
 F:	configs/j721e_hs_evm_r5_defconfig
-F:	configs/j721s2_hs_evm_a72_defconfig
-F:	configs/j721s2_hs_evm_r5_defconfig
+F:	configs/j721e_hs_evm_a72_defconfig
 
 TPM DRIVERS
 M:	Ilias Apalodimas <ilias.apalodimas@linaro.org>
@@ -1481,6 +1344,8 @@ M:	Anatolij Gustschin <agust@denx.de>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-video.git
 F:	drivers/video/
+F:	common/lcd*.c
+F:	include/lcd*.h
 F:	include/video*.h
 
 VirtIO
@@ -1532,13 +1397,6 @@ M:	Max Filippov <jcmvbkbc@gmail.com>
 S:	Maintained
 F:	arch/xtensa/
 
-XXD
-M:	Roger Knecht <rknecht@pm.me>
-S:	Maintained
-F:	cmd/xxd.c
-F:	doc/usage/cmd/xxd.rst
-F:	test/py/tests/test_xxd/
-
 THE REST
 M:	Tom Rini <trini@konsulko.com>
 L:	u-boot@lists.denx.de
@@ -1548,10 +1406,3 @@ T:	git https://source.denx.de/u-boot/u-boot.git
 F:	configs/tools-only_defconfig
 F:	*
 F:	*/
-
-CAAM
-M:	Gaurav Jain <gaurav.jain@nxp.com>
-S:	Maintained
-F:	arch/arm/dts/ls1021a-twr-u-boot.dtsi
-F:	drivers/crypto/fsl/
-F:	include/fsl_sec.h

Makefile

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 VERSION = 2022
-PATCHLEVEL = 10
+PATCHLEVEL = 04
 SUBLEVEL =
 EXTRAVERSION =
 NAME =
@@ -21,7 +21,7 @@ include include/host_arch.h
 ifeq ("", "$(CROSS_COMPILE)")
   MK_ARCH="${shell uname -m}"
 else
-  MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\2/p'}"
+  MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\s*\([^\/]*\/\)*\([^-]*\)-\S*/\2/p'}"
 endif
 unexport HOST_ARCH
 ifeq ("x86_64", $(MK_ARCH))
@@ -30,7 +30,7 @@ else ifneq (,$(findstring $(MK_ARCH), "i386" "i486" "i586" "i686"))
   export HOST_ARCH=$(HOST_ARCH_X86)
 else ifneq (,$(findstring $(MK_ARCH), "aarch64" "armv8l"))
   export HOST_ARCH=$(HOST_ARCH_AARCH64)
-else ifneq (,$(findstring $(MK_ARCH), "arm" "armv7" "armv7a" "armv7l"))
+else ifneq (,$(findstring $(MK_ARCH), "arm" "armv7" "armv7l"))
   export HOST_ARCH=$(HOST_ARCH_ARM)
 else ifeq ("riscv32", $(MK_ARCH))
   export HOST_ARCH=$(HOST_ARCH_RISCV32)
@@ -521,8 +521,8 @@ env_h := include/generated/environment.h
 
 no-dot-config-targets := clean clobber mrproper distclean \
 			 help %docs check% coccicheck \
-			 ubootversion backup tests check pcheck qcheck tcheck \
-			 pylint pylint_err
+			 ubootversion backup tests check qcheck tcheck pylint \
+			 pylint_err
 
 config-targets := 0
 mixed-targets  := 0
@@ -643,13 +643,6 @@ export CFLAGS_EFI	# Compiler flags to add when building EFI app
 export CFLAGS_NON_EFI	# Compiler flags to remove when building EFI app
 export EFI_TARGET	# binutils target if EFI is natively supported
 
-export LTO_ENABLE
-
-# This is y if LTO is enabled for this build. See NO_LTO=1 to disable LTO
-ifeq ($(NO_LTO),)
-LTO_ENABLE=$(if $(CONFIG_LTO),y)
-endif
-
 # If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
 # that (or fail if absent).  Otherwise, search for a linker script in a
 # standard location.
@@ -680,15 +673,6 @@ else
 include/config/auto.conf: ;
 endif # $(dot-config)
 
-ifdef CONFIG_CC_OPTIMIZE_FOR_DEBUG
-KBUILD_HOSTCFLAGS   := -Wall -Wstrict-prototypes -Og -g -fomit-frame-pointer \
-		$(HOST_LFS_CFLAGS) $(HOSTCFLAGS)
-# Avoid false positives -Wmaybe-uninitialized
-# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78394
-KBUILD_HOSTCFLAGS   += -Wno-maybe-uninitialized
-KBUILD_HOSTCXXFLAGS := -Og -g $(HOST_LFS_CFLAGS) $(HOSTCXXFLAGS)
-endif
-
 #
 # Xtensa linker script cannot be preprocessed with -ansi because of
 # preprocessor operations on strings that don't make C identifiers.
@@ -706,25 +690,22 @@ KBUILD_CFLAGS	+= -O2
 endif
 
 ifdef CONFIG_CC_OPTIMIZE_FOR_DEBUG
-KBUILD_CFLAGS	+= -Og -Wno-maybe-uninitialized
-# Avoid false positives -Wmaybe-uninitialized
-# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78394
-KBUILD_CFLAGS	+= -Wno-maybe-uninitialized
+KBUILD_CFLAGS	+= -Og
 endif
 
 LTO_CFLAGS :=
 LTO_FINAL_LDFLAGS :=
 export LTO_CFLAGS LTO_FINAL_LDFLAGS
-ifeq ($(LTO_ENABLE),y)
+ifdef CONFIG_LTO
 	ifeq ($(cc-name),clang)
-		LTO_CFLAGS		+= -DLTO_ENABLE -flto
+		LTO_CFLAGS		+= -flto
 		LTO_FINAL_LDFLAGS	+= -flto
 
 		AR			= $(shell $(CC) -print-prog-name=llvm-ar)
 		NM			= $(shell $(CC) -print-prog-name=llvm-nm)
 	else
 		NPROC			:= $(shell nproc 2>/dev/null || echo 1)
-		LTO_CFLAGS		+= -DLTO_ENABLE -flto=$(NPROC)
+		LTO_CFLAGS		+= -flto=$(NPROC)
 		LTO_FINAL_LDFLAGS	+= -fuse-linker-plugin -flto=$(NPROC)
 
 		# use plugin aware tools
@@ -860,13 +841,12 @@ libs-y += drivers/usb/host/
 libs-y += drivers/usb/mtu3/
 libs-y += drivers/usb/musb/
 libs-y += drivers/usb/musb-new/
-libs-y += drivers/usb/isp1760/
 libs-y += drivers/usb/phy/
 libs-y += drivers/usb/ulpi/
 ifdef CONFIG_POST
 libs-y += post/
 endif
-libs-$(CONFIG_$(SPL_TPL_)UNIT_TEST) += test/
+libs-$(CONFIG_UNIT_TEST) += test/
 libs-$(CONFIG_UT_ENV) += test/env/
 libs-$(CONFIG_UT_OPTEE) += test/optee/
 libs-$(CONFIG_UT_OVERLAY) += test/overlay/
@@ -931,21 +911,17 @@ else
 TPL_SIZE_CHECK =
 endif
 
-ifneq ($(CONFIG_VPL_SIZE_LIMIT),0x0)
-VPL_SIZE_CHECK = @$(call size_check,$@,$(CONFIG_VPL_SIZE_LIMIT))
-else
-VPL_SIZE_CHECK =
-endif
-
 # Statically apply RELA-style relocations (currently arm64 only)
 # This is useful for arm64 where static relocation needs to be performed on
 # the raw binary, but certain simulators only accept an ELF file (but don't
 # do the relocation).
 ifneq ($(CONFIG_STATIC_RELA),)
-# $(2) is u-boot ELF, $(3) is u-boot bin, $(4) is text base
+# $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base
 quiet_cmd_static_rela = RELOC   $@
 cmd_static_rela = \
-	tools/relocate-rela $(3) $(2)
+	start=$$($(NM) $(2) | grep __rel_dyn_start | cut -f 1 -d ' '); \
+	end=$$($(NM) $(2) | grep __rel_dyn_end | cut -f 1 -d ' '); \
+	tools/relocate-rela $(3) $(4) $$start $$end
 else
 quiet_cmd_static_rela =
 cmd_static_rela =
@@ -975,7 +951,6 @@ INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
 endif
 endif
 INPUTS-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
-INPUTS-$(CONFIG_VPL) += vpl/u-boot-vpl.bin
 
 # Allow omitting the .dtb output if it is not normally used
 INPUTS-$(CONFIG_OF_SEPARATE) += $(if $(CONFIG_OF_OMIT_DTB),dts/dt.dtb,u-boot.dtb)
@@ -1004,12 +979,22 @@ ifeq ($(CONFIG_INIT_SP_RELATIVE)$(CONFIG_OF_SEPARATE),yy)
 INPUTS-y += init_sp_bss_offset_check
 endif
 
-ifeq ($(CONFIG_ARCH_ROCKCHIP)$(CONFIG_SPL),yy)
-# Binman image dependencies
+ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
+INPUTS-y += u-boot-with-dtb.bin
+endif
+
+ifeq ($(CONFIG_ARCH_ROCKCHIP),y)
+# On ARM64 this target is produced by binman so we don't need this dep
 ifeq ($(CONFIG_ARM64),y)
-INPUTS-y += u-boot.itb
+ifeq ($(CONFIG_SPL),y)
+# TODO: Get binman to generate this too
+INPUTS-y += u-boot-rockchip.bin
+endif
 else
-INPUTS-y += u-boot.img
+ifeq ($(CONFIG_SPL),y)
+# Generate these inputs for binman which will create the output files
+INPUTS-y += idbloader.img u-boot.img
+endif
 endif
 endif
 
@@ -1040,12 +1025,12 @@ LDFLAGS_u-boot += $(LDFLAGS_FINAL)
 LDFLAGS_u-boot += $(call ld-option, --no-dynamic-linker)
 
 # ld.lld support
-LDFLAGS_u-boot += -z notext $(call ld-option,--apply-dynamic-relocs)
+LDFLAGS_u-boot += -z notext
 
 LDFLAGS_u-boot += --build-id=none
 
 ifeq ($(CONFIG_ARC)$(CONFIG_NIOS2)$(CONFIG_X86)$(CONFIG_XTENSA),)
-LDFLAGS_u-boot += -Ttext $(CONFIG_TEXT_BASE)
+LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
 endif
 
 # insure the checker run with the right endianness
@@ -1145,7 +1130,7 @@ ifeq ($(CONFIG_OF_EMBED)$(CONFIG_EFI_APP),y)
 	@echo >&2 "CONFIG_OF_EMBED is enabled. This option should only"
 	@echo >&2 "be used for debugging purposes. Please use"
 	@echo >&2 "CONFIG_OF_SEPARATE for boards in mainline."
-	@echo >&2 "See doc/develop/devicetree/control.rst for more info."
+	@echo >&2 "See doc/README.fdt-control for more info."
 	@echo >&2 "===================================================="
 endif
 ifneq ($(CONFIG_SPL_FIT_GENERATOR),)
@@ -1154,10 +1139,20 @@ ifneq ($(CONFIG_SPL_FIT_GENERATOR),)
 	@echo >&2 "to binman instead, to avoid the proliferation of"
 	@echo >&2 "arch-specific scripts with no tests."
 	@echo >&2 "===================================================="
+endif
+ifneq ($(CONFIG_DM),y)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board does not use CONFIG_DM. CONFIG_DM will be"
+	@echo >&2 "compulsory starting with the v2020.01 release."
+	@echo >&2 "Failure to update may result in board removal."
+	@echo >&2 "See doc/develop/driver-model/migration.rst for more info."
+	@echo >&2 "===================================================="
 endif
 	$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
 		$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
+	$(call deprecated,CONFIG_DM_ETH,Ethernet drivers,v2020.07,$(CONFIG_NET))
 	$(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY))
+	$(call deprecated,CONFIG_DM_KEYBOARD,Keyboard drivers,v2022.10,$(CONFIG_KEYBOARD))
 	@# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which
 	@# confuses this rule. Use if() to send just a single character which
 	@# is enable to tell 'deprecated' that one of these symbols exists
@@ -1228,12 +1223,9 @@ else ifeq ($(CONFIG_OF_SEPARATE).$(CONFIG_OF_OMIT_DTB),y.)
 u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
 	$(call if_changed,cat)
 
-ifneq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR)$(CONFIG_OF_SEPARATE),yy)
 u-boot.bin: u-boot-dtb.bin FORCE
 	$(call if_changed,copy)
-endif
-
-else ifneq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR)$(CONFIG_OF_SEPARATE),yy)
+else
 u-boot.bin: u-boot-nodtb.bin FORCE
 	$(call if_changed,copy)
 endif
@@ -1281,7 +1273,7 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE
 
 OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
 		$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
-		$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_SEPARATE),-R .bootpg -R .resetvec))
+		$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec)
 
 binary_size_check: u-boot-nodtb.bin FORCE
 	@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
@@ -1328,7 +1320,7 @@ shell_cmd = { $(call echo-cmd,$(1)) $(cmd_$(1)); }
 
 quiet_cmd_objcopy_uboot = OBJCOPY $@
 ifdef cmd_static_rela
-cmd_objcopy_uboot = $(cmd_objcopy) && $(call shell_cmd,static_rela,$<,$@,$(CONFIG_TEXT_BASE)) || { rm -f $@; false; }
+cmd_objcopy_uboot = $(cmd_objcopy) && $(call shell_cmd,static_rela,$<,$@,$(CONFIG_SYS_TEXT_BASE)) || { rm -f $@; false; }
 else
 cmd_objcopy_uboot = $(cmd_objcopy)
 endif
@@ -1382,7 +1374,7 @@ u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
 # from the SPL U-Boot version.
 #
 ifndef CONFIG_SYS_UBOOT_START
-CONFIG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
+CONFIG_SYS_UBOOT_START := $(CONFIG_SYS_TEXT_BASE)
 endif
 
 # Boards with more complex image requirements can provide an .its source file
@@ -1407,7 +1399,7 @@ endif
 
 ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-p $(CONFIG_FIT_EXTERNAL_OFFSET) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \
@@ -1415,10 +1407,10 @@ MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST)))
 else
 MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
 endif
@@ -1437,19 +1429,23 @@ KWD_CONFIG_FILE = $(shell \
 	fi)
 
 MKIMAGEFLAGS_u-boot.kwb = -n $(KWD_CONFIG_FILE) \
-	-T kwbimage -a $(CONFIG_TEXT_BASE) -e $(CONFIG_TEXT_BASE)
+	-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
 
 MKIMAGEFLAGS_u-boot-spl.kwb = -n $(KWD_CONFIG_FILE) \
-	-T kwbimage -a $(CONFIG_TEXT_BASE) -e $(CONFIG_TEXT_BASE) \
+	-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \
 	$(if $(KEYDIR),-k $(KEYDIR))
 
 MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
 		-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -A $(ARCH) -T pblimage
 
+ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
+UBOOT_BIN := u-boot-with-dtb.bin
+else
 UBOOT_BIN := u-boot.bin
+endif
 
 MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 
 u-boot.bin.lzma: u-boot.bin FORCE
@@ -1482,7 +1478,6 @@ endif
 
 u-boot-spl.kwb: u-boot.bin spl/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)
-	$(BOARD_SIZE_CHECK)
 
 u-boot.sha1:	u-boot.bin
 		tools/ubsha1 u-boot.bin
@@ -1503,6 +1498,29 @@ OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \
 u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_PAYLOAD) FORCE
 	$(call if_changed,pad_cat)
 
+ifeq ($(CONFIG_ARCH_ROCKCHIP),y)
+
+# TPL + SPL
+ifeq ($(CONFIG_SPL)$(CONFIG_TPL),yy)
+MKIMAGEFLAGS_u-boot-tpl-rockchip.bin = -n $(CONFIG_SYS_SOC) -T rksd
+tpl/u-boot-tpl-rockchip.bin: tpl/u-boot-tpl.bin FORCE
+	$(call if_changed,mkimage)
+idbloader.img: tpl/u-boot-tpl-rockchip.bin spl/u-boot-spl.bin FORCE
+	$(call if_changed,cat)
+else
+MKIMAGEFLAGS_idbloader.img = -n $(CONFIG_SYS_SOC) -T rksd
+idbloader.img: spl/u-boot-spl.bin FORCE
+	$(call if_changed,mkimage)
+endif
+
+ifeq ($(CONFIG_ARM64),y)
+OBJCOPYFLAGS_u-boot-rockchip.bin = -I binary -O binary \
+	--pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
+u-boot-rockchip.bin: idbloader.img u-boot.itb FORCE
+	$(call if_changed,pad_cat)
+endif # CONFIG_ARM64
+
+endif # CONFIG_ARCH_ROCKCHIP
 
 ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy)
 MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE)
@@ -1533,7 +1551,7 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
 SPL: spl/u-boot-spl.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 
-#ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y)
+ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y)
 ifeq ($(CONFIG_SPL_LOAD_IMX_CONTAINER), y)
 u-boot.cnt: u-boot.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
@@ -1549,7 +1567,7 @@ flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 endif
 endif
-#endif
+endif
 
 u-boot.uim: u-boot.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
@@ -1557,7 +1575,7 @@ u-boot.uim: u-boot.bin FORCE
 u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 
-MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_TEXT_BASE)
+MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE)
 
 u-boot.ubl: u-boot-with-spl.bin FORCE
 	$(call if_changed,mkimage)
@@ -1614,14 +1632,17 @@ u-boot-with-nand-spl.sfp: u-boot-spl-padx4.sfp u-boot.img FORCE
 
 endif
 
-ifeq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR)$(CONFIG_OF_SEPARATE),yy)
-u-boot.bin: u-boot-nodtb.bin u-boot.dtb u-boot-br.bin FORCE
+ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
+u-boot-with-dtb.bin: u-boot.bin u-boot.dtb \
+	$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR), u-boot-br.bin) FORCE
 	$(call if_changed,binman)
 
+ifeq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR),y)
 OBJCOPYFLAGS_u-boot-br.bin := -O binary -j .bootpg -j .resetvec
 u-boot-br.bin: u-boot FORCE
 	$(call if_changed,objcopy)
 endif
+endif
 
 quiet_cmd_ldr = LD      $@
 cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \
@@ -1678,8 +1699,12 @@ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
 ifeq ($(ARCH),arm)
 UBOOT_BINLOAD := u-boot.img
 else
+ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
+UBOOT_BINLOAD := u-boot-with-dtb.bin
+else
 UBOOT_BINLOAD := u-boot.bin
 endif
+endif
 
 OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
 			  --gap-fill=0xff
@@ -1700,9 +1725,8 @@ u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE
 
 quiet_cmd_u-boot-elf ?= LD      $@
 	cmd_u-boot-elf ?= $(LD) u-boot-elf.o -o $@ \
-	$(if $(CONFIG_SYS_BIG_ENDIAN),-EB,-EL) \
-	-T u-boot-elf.lds --defsym=$(CONFIG_PLATFORM_ELFENTRY)=$(CONFIG_TEXT_BASE) \
-	-Ttext=$(CONFIG_TEXT_BASE)
+	-T u-boot-elf.lds --defsym=$(CONFIG_PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \
+	-Ttext=$(CONFIG_SYS_TEXT_BASE)
 u-boot.elf: u-boot.bin u-boot-elf.lds
 	$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
 	$(call if_changed,u-boot-elf)
@@ -1723,7 +1747,7 @@ u-boot-mtk.bin: u-boot-with-spl.bin
 	$(call if_changed,copy)
 else
 MKIMAGEFLAGS_u-boot-mtk.bin = -T mtk_image \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_TEXT_BASE) \
+	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \
 	-n "$(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO))"
 
 u-boot-mtk.bin: u-boot.bin FORCE
@@ -1740,7 +1764,7 @@ ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
 
 # Generate linker list symbols references to force compiler to not optimize
 # them away when compiling with LTO
-ifeq ($(LTO_ENABLE),y)
+ifdef CONFIG_LTO
 u-boot-keep-syms-lto := keep-syms-lto.o
 u-boot-keep-syms-lto_c := $(patsubst %.o,%.c,$(u-boot-keep-syms-lto))
 
@@ -1762,7 +1786,7 @@ endif
 
 # Rule to link u-boot
 # May be overridden by arch/$(ARCH)/config.mk
-ifeq ($(LTO_ENABLE),y)
+ifdef CONFIG_LTO
 quiet_cmd_u-boot__ ?= LTO     $@
       cmd_u-boot__ ?=								\
 		$(CC) -nostdlib -nostartfiles					\
@@ -1777,6 +1801,10 @@ quiet_cmd_u-boot__ ?= LTO     $@
 		-Wl,-Map,u-boot.map;						\
 		$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
 else
+# Note: Linking efi-x86_app64 causes a segfault in the linker at present
+# when using x86_64-linux-gnu-ld.bfd
+# For now, disable --whole-archive which makes things link, although not
+# correctly
 quiet_cmd_u-boot__ ?= LD      $@
       cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@		\
 		-T u-boot.lds $(u-boot-init)					\
@@ -2087,7 +2115,9 @@ spl/u-boot-spl-dtb.bin: spl/u-boot-spl
 spl/u-boot-spl-dtb.hex: spl/u-boot-spl
 	@:
 
-spl/u-boot-spl: tools prepare $(if $(CONFIG_SPL_OF_CONTROL),dts/dt.dtb)
+spl/u-boot-spl: tools prepare \
+		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
+		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
 	$(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all
 
 spl/sunxi-spl.bin: spl/u-boot-spl
@@ -2102,19 +2132,10 @@ spl/u-boot-spl.sfp: spl/u-boot-spl
 spl/boot.bin: spl/u-boot-spl
 	@:
 
-tpl/u-boot-tpl.bin: tpl/u-boot-tpl
-	@:
-	$(TPL_SIZE_CHECK)
-
-tpl/u-boot-tpl: tools prepare $(if $(CONFIG_TPL_OF_CONTROL),dts/dt.dtb)
+tpl/u-boot-tpl.bin: tools prepare \
+		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb)
 	$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all
-
-vpl/u-boot-vpl.bin: vpl/u-boot-vpl
-	@:
-	$(VPL_SIZE_CHECK)
-
-vpl/u-boot-vpl: tools prepare $(if $(CONFIG_TPL_OF_CONTROL),dts/dt.dtb)
-	$(Q)$(MAKE) obj=vpl -f $(srctree)/scripts/Makefile.spl all
+	$(TPL_SIZE_CHECK)
 
 TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include)
 
@@ -2194,15 +2215,13 @@ CLEAN_DIRS  += $(MODVERDIR) \
 			$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
 
 CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
-	       include/generated/env.* drivers/video/u_boot_logo.S \
+	       include/generated/env.in drivers/video/u_boot_logo.S \
 	       tools/version.h u-boot* MLO* SPL System.map fit-dtb.blob* \
 	       u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
 	       lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
 	       idbloader.img flash.bin flash.log defconfig keep-syms-lto.c \
 	       mkimage-out.spl.mkimage mkimage.spl.mkimage imx-boot.map \
-	       itb.fit.fit itb.fit.itb itb.map spl.map mkimage-out.rom.mkimage \
-	       mkimage.rom.mkimage rom.map simple-bin.map simple-bin-spi.map \
-	       idbloader-spi.img
+	       itb.fit.fit itb.fit.itb itb.map spl.map
 
 # Directories & files removed with 'make mrproper'
 MRPROPER_DIRS  += include/config include/generated spl tpl \
@@ -2334,7 +2353,6 @@ help:
 	@echo  'Test targets:'
 	@echo  ''
 	@echo  '  check           - Run all automated tests that use sandbox'
-	@echo  '  pcheck          - Run quick automated tests in parallel'
 	@echo  '  qcheck          - Run quick automated tests that use sandbox'
 	@echo  '  tcheck          - Run quick automated tests on tools'
 	@echo  '  pylint          - Run pylint on all Python files'
@@ -2380,9 +2398,6 @@ help:
 tests check:
 	$(srctree)/test/run
 
-pcheck:
-	$(srctree)/test/run parallel
-
 qcheck:
 	$(srctree)/test/run quick
 
@@ -2460,8 +2475,7 @@ endif
 
 quiet_cmd_genenv = GENENV  $@
 cmd_genenv = $(OBJCOPY) --dump-section .rodata.default_environment=$@ env/common.o; \
-	sed --in-place -e 's/\x00/\x0A/g' $@; sed --in-place -e '/^\s*$$/d' $@; \
-	sort --field-separator== -k1,1 --stable $@ -o $@
+	sed --in-place -e 's/\x00/\x0A/g' $@
 
 u-boot-initial-env: u-boot.bin
 	$(call if_changed,genenv)

README

@@ -134,6 +134,7 @@ Directory Hierarchy:
   /m68k			Files generic to m68k architecture
   /microblaze		Files generic to microblaze architecture
   /mips			Files generic to MIPS architecture
+  /nds32		Files generic to NDS32 architecture
   /nios2		Files generic to Altera NIOS2 architecture
   /powerpc		Files generic to PowerPC architecture
   /riscv		Files generic to RISC-V architecture
@@ -166,6 +167,27 @@ Directory Hierarchy:
 Software Configuration:
 =======================
 
+Configuration is usually done using C preprocessor defines; the
+rationale behind that is to avoid dead code whenever possible.
+
+There are two classes of configuration variables:
+
+* Configuration _OPTIONS_:
+  These are selectable by the user and have names beginning with
+  "CONFIG_".
+
+* Configuration _SETTINGS_:
+  These depend on the hardware etc. and should not be meddled with if
+  you don't know what you're doing; they have names beginning with
+  "CONFIG_SYS_".
+
+Previously, all configuration was done by hand, which involved creating
+symbolic links and editing configuration files manually. More recently,
+U-Boot has added the Kbuild infrastructure used by the Linux kernel,
+allowing you to use the "make menuconfig" command to configure your
+build.
+
+
 Selection of Processor Architecture and Board Type:
 ---------------------------------------------------
 
@@ -272,6 +294,33 @@ board_init_r():
 
 	SPL-specific notes:
 	- stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
+		CONFIG_SPL_STACK_R_ADDR points into SDRAM
+	- preloader_console_init() can be called here - typically this is
+		done by selecting CONFIG_SPL_BOARD_INIT and then supplying a
+		spl_board_init() function containing this call
+	- loads U-Boot or (in falcon mode) Linux
+
+
+Configuration Options:
+----------------------
+
+Configuration depends on the combination of board and CPU type; all
+such information is kept in a configuration file
+"include/configs/<board_name>.h".
+
+Example: For a TQM823L module, all configuration settings are in
+"include/configs/TQM823L.h".
+
+
+Many of the options are named exactly as the corresponding Linux
+kernel configuration options. The intention is to make it easier to
+build a config tool - later.
+
+- ARM Platform Bus Type(CCI):
+		CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
+		provides full cache coherency between two clusters of multi-core
+		CPUs and I/O coherency for devices and I/O masters
+
 		CONFIG_SYS_FSL_HAS_CCI400
 
 		Defined For SoC that has cache coherent interconnect
@@ -294,6 +343,17 @@ The following options need to be configured:
 		the "64" category of the Power ISA). This is necessary for ePAPR
 		compliance, among other possible reasons.
 
+		CONFIG_SYS_FSL_TBCLK_DIV
+
+		Defines the core time base clock divider ratio compared to the
+		system clock.  On most PQ3 devices this is 8, on newer QorIQ
+		devices it can be 16 or 32.  The ratio varies from SoC to Soc.
+
+		CONFIG_SYS_FSL_PCIE_COMPAT
+
+		Defines the string to utilize when trying to match PCIe device
+		tree nodes for the given platform.
+
 		CONFIG_SYS_FSL_ERRATUM_A004510
 
 		Enables a workaround for erratum A004510.  If set,
@@ -319,12 +379,35 @@ The following options need to be configured:
 		This is the value to write into CCSR offset 0x18600
 		according to the A004510 workaround.
 
+		CONFIG_SYS_FSL_DSP_DDR_ADDR
+		This value denotes start offset of DDR memory which is
+		connected exclusively to the DSP cores.
+
+		CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
+		This value denotes start offset of M2 memory
+		which is directly connected to the DSP core.
+
+		CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
+		This value denotes start offset of M3 memory which is directly
+		connected to the DSP core.
+
+		CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+		This value denotes start offset of DSP CCSR space.
+
 		CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 		Single Source Clock is clocking mode present in some of FSL SoC's.
 		In this mode, a single differential clock is used to supply
 		clocks to the sysclock, ddrclock and usbclock.
 
+		CONFIG_SYS_CPC_REINIT_F
+		This CONFIG is defined when the CPC is configured as SRAM at the
+		time of U-Boot entry and is required to be re-initialized.
+
 - Generic CPU options:
+		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
+
+		Defines the endianess of the CPU. Implementation of those
+		values is arch specific.
 
 		CONFIG_SYS_FSL_DDR
 		Freescale DDR driver in use. This type of DDR controller is
@@ -333,18 +416,93 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_DDR_ADDR
 		Freescale DDR memory-mapped register base.
 
+		CONFIG_SYS_FSL_DDR_EMU
+		Specify emulator support for DDR. Some DDR features such as
+		deskew training are not available.
+
+		CONFIG_SYS_FSL_DDRC_GEN1
+		Freescale DDR1 controller.
+
+		CONFIG_SYS_FSL_DDRC_GEN2
+		Freescale DDR2 controller.
+
+		CONFIG_SYS_FSL_DDRC_GEN3
+		Freescale DDR3 controller.
+
+		CONFIG_SYS_FSL_DDRC_GEN4
+		Freescale DDR4 controller.
+
+		CONFIG_SYS_FSL_DDRC_ARM_GEN3
+		Freescale DDR3 controller for ARM-based SoCs.
+
+		CONFIG_SYS_FSL_DDR1
+		Board config to use DDR1. It can be enabled for SoCs with
+		Freescale DDR1 or DDR2 controllers, depending on the board
+		implemetation.
+
+		CONFIG_SYS_FSL_DDR2
+		Board config to use DDR2. It can be enabled for SoCs with
+		Freescale DDR2 or DDR3 controllers, depending on the board
+		implementation.
+
+		CONFIG_SYS_FSL_DDR3
+		Board config to use DDR3. It can be enabled for SoCs with
+		Freescale DDR3 or DDR3L controllers.
+
+		CONFIG_SYS_FSL_DDR3L
+		Board config to use DDR3L. It can be enabled for SoCs with
+		DDR3L controllers.
+
+		CONFIG_SYS_FSL_IFC_BE
+		Defines the IFC controller register space as Big Endian
+
+		CONFIG_SYS_FSL_IFC_LE
+		Defines the IFC controller register space as Little Endian
+
 		CONFIG_SYS_FSL_IFC_CLK_DIV
 		Defines divider of platform clock(clock input to IFC controller).
 
 		CONFIG_SYS_FSL_LBC_CLK_DIV
 		Defines divider of platform clock(clock input to eLBC controller).
 
+		CONFIG_SYS_FSL_DDR_BE
+		Defines the DDR controller register space as Big Endian
+
+		CONFIG_SYS_FSL_DDR_LE
+		Defines the DDR controller register space as Little Endian
+
 		CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
 		Physical address from the view of DDR controllers. It is the
 		same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
 		it could be different for ARM SoCs.
 
+		CONFIG_SYS_FSL_DDR_INTLV_256B
+		DDR controller interleaving on 256-byte. This is a special
+		interleaving mode, handled by Dickens for Freescale layerscape
+		SoCs with ARM core.
+
+		CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
+		Number of controllers used as main memory.
+
+		CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
+		Number of controllers used for other than main memory.
+
+		CONFIG_SYS_FSL_HAS_DP_DDR
+		Defines the SoC has DP-DDR used for DPAA.
+
+		CONFIG_SYS_FSL_SEC_BE
+		Defines the SEC controller register space as Big Endian
+
+		CONFIG_SYS_FSL_SEC_LE
+		Defines the SEC controller register space as Little Endian
+
 - MIPS CPU options:
+		CONFIG_SYS_INIT_SP_OFFSET
+
+		Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack
+		pointer. This is needed for the temporary stack before
+		relocation.
+
 		CONFIG_XWAY_SWAP_BYTES
 
 		Enable compilation of tools/xway-swap-bytes needed for Lantiq
@@ -415,6 +573,8 @@ The following options need to be configured:
 		the defaults discussed just above.
 
 - Cache Configuration for ARM:
+		CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
+				      controller
 		CONFIG_SYS_PL310_BASE - Physical base address of PL310
 					controller register space
 
@@ -541,6 +701,18 @@ The following options need to be configured:
 		CONFIG_SCSI) you must configure support for at
 		least one non-MTD partition type as well.
 
+- LBA48 Support
+		CONFIG_LBA48
+
+		Set this to enable support for disks larger than 137GB
+		Also look at CONFIG_SYS_64BIT_LBA.
+		Whithout these , LBA48 support uses 32bit variables and will 'only'
+		support disks up to 2.1TB.
+
+		CONFIG_SYS_64BIT_LBA:
+			When enabled, makes the IDE subsystem use 64bit sector addresses.
+			Default is 32bit.
+
 - NETWORK Support (PCI):
 		CONFIG_E1000_SPI
 		Utility code for direct access to the SPI bus on Intel 8257x.
@@ -563,6 +735,20 @@ The following options need to be configured:
 			CONFIG_LAN91C96_USE_32_BIT
 			Define this to enable 32 bit addressing
 
+		CONFIG_SMC91111
+		Support for SMSC's LAN91C111 chip
+
+			CONFIG_SMC91111_BASE
+			Define this to hold the physical address
+			of the device (I/O space)
+
+			CONFIG_SMC_USE_32_BIT
+			Define this if data bus is 32 bits
+
+			CONFIG_SMC_USE_IOFUNCS
+			Define this to use i/o functions instead of macros
+			(some hardware wont work with macros)
+
 			CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
 			Define this if you have more then 3 PHYs.
 
@@ -644,6 +830,9 @@ The following options need to be configured:
 		Supported are USB Keyboards and USB Floppy drives
 		(TEAC FD-05PUB).
 
+		CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
+		txfilltuning field in the EHCI controller on reset.
+
 		CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2
 		HW module registers.
 
@@ -717,6 +906,13 @@ The following options need to be configured:
 		the appropriate value in Hz.
 
 - MMC Support:
+		The MMC controller on the Intel PXA is supported. To
+		enable this define CONFIG_MMC. The MMC can be
+		accessed from the boot prompt by mapping the device
+		to physical memory similar to flash. Command line is
+		enabled with CONFIG_CMD_MMC. The MMC driver also works with
+		the FAT fs. This is enabled with CONFIG_CMD_FAT.
+
 		CONFIG_SH_MMCIF
 		Support for Renesas on-chip MMCIF controller
 
@@ -770,6 +966,80 @@ The following options need to be configured:
 - Keyboard Support:
 		See Kconfig help for available keyboard drivers.
 
+- LCD Support:	CONFIG_LCD
+
+		Define this to enable LCD support (for output to LCD
+		display); also select one of the supported displays
+		by defining one of these:
+
+		CONFIG_NEC_NL6448AC33:
+
+			NEC NL6448AC33-18. Active, color, single scan.
+
+		CONFIG_NEC_NL6448BC20
+
+			NEC NL6448BC20-08. 6.5", 640x480.
+			Active, color, single scan.
+
+		CONFIG_NEC_NL6448BC33_54
+
+			NEC NL6448BC33-54. 10.4", 640x480.
+			Active, color, single scan.
+
+		CONFIG_SHARP_16x9
+
+			Sharp 320x240. Active, color, single scan.
+			It isn't 16x9, and I am not sure what it is.
+
+		CONFIG_SHARP_LQ64D341
+
+			Sharp LQ64D341 display, 640x480.
+			Active, color, single scan.
+
+		CONFIG_HLD1045
+
+			HLD1045 display, 640x480.
+			Active, color, single scan.
+
+		CONFIG_OPTREX_BW
+
+			Optrex	 CBL50840-2 NF-FW 99 22 M5
+			or
+			Hitachi	 LMG6912RPFC-00T
+			or
+			Hitachi	 SP14Q002
+
+			320x240. Black & white.
+
+		CONFIG_LCD_ALIGNMENT
+
+		Normally the LCD is page-aligned (typically 4KB). If this is
+		defined then the LCD will be aligned to this value instead.
+		For ARM it is sometimes useful to use MMU_SECTION_SIZE
+		here, since it is cheaper to change data cache settings on
+		a per-section basis.
+
+
+		CONFIG_LCD_ROTATION
+
+		Sometimes, for example if the display is mounted in portrait
+		mode or even if it's mounted landscape but rotated by 180degree,
+		we need to rotate our content of the display relative to the
+		framebuffer, so that user can read the messages which are
+		printed out.
+		Once CONFIG_LCD_ROTATION is defined, the lcd_console will be
+		initialized with a given rotation from "vl_rot" out of
+		"vidinfo_t" which is provided by the board specific code.
+		The value for vl_rot is coded as following (matching to
+		fbcon=rotate:<n> linux-kernel commandline):
+		0 = no rotation respectively 0 degree
+		1 = 90 degree rotation
+		2 = 180 degree rotation
+		3 = 270 degree rotation
+
+		If CONFIG_LCD_ROTATION is not defined, the console will be
+		initialized with 0degree rotation.
+
 - MII/PHY support:
 		CONFIG_PHY_CLOCK_FREQ (ppc4xx)
 
@@ -1088,6 +1358,11 @@ The following options need to be configured:
 
 		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
 
+		CONFIG_SYS_SPD_BUS_NUM
+
+		If defined, then this indicates the I2C bus number for DDR SPD.
+		If not defined, then U-Boot assumes that SPD is on I2C bus 0.
+
 		CONFIG_SYS_RTC_BUS_NUM
 
 		If defined, then this indicates the I2C bus number for the RTC.
@@ -1127,6 +1402,14 @@ The following options need to be configured:
 		Enables support for FPGA family.
 		(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
 
+		CONFIG_FPGA_COUNT
+
+		Specify the number of FPGA devices to support.
+
+		CONFIG_SYS_FPGA_PROG_FEEDBACK
+
+		Enable printing of hash marks during FPGA configuration.
+
 		CONFIG_SYS_FPGA_CHECK_BUSY
 
 		Enable checks on FPGA configuration interface busy
@@ -1139,6 +1422,9 @@ The following options need to be configured:
 		If defined, a function that provides delays in the FPGA
 		configuration driver.
 
+		CONFIG_SYS_FPGA_CHECK_CTRLC
+		Allow Control-C to interrupt FPGA configuration
+
 		CONFIG_SYS_FPGA_CHECK_ERROR
 
 		Check for configuration errors during FPGA bitfile
@@ -1246,6 +1532,14 @@ The following options need to be configured:
 		of the backslashes before semicolons and special
 		symbols.
 
+- Command Line Editing and History:
+		CONFIG_CMDLINE_PS_SUPPORT
+
+		Enable support for changing the command prompt string
+		at run-time. Only static string is supported so far.
+		The string is obtained from environment variables PS1
+		and PS2.
+
 - Default Environment:
 		CONFIG_EXTRA_ENV_SETTINGS
 
@@ -1288,6 +1582,20 @@ The following options need to be configured:
 		overwriting the architecture dependent default
 		settings.
 
+- Frame Buffer Address:
+		CONFIG_FB_ADDR
+
+		Define CONFIG_FB_ADDR if you want to use specific
+		address for frame buffer.  This is typically the case
+		when using a graphics controller has separate video
+		memory.  U-Boot will then place the frame buffer at
+		the given address instead of dynamically reserving it
+		in system RAM by calling lcd_setmem(), which grabs
+		the memory for the frame buffer depending on the
+		configured panel size.
+
+		Please see board_init_f function.
+
 - Automatic software updates via TFTP server
 		CONFIG_UPDATE_TFTP
 		CONFIG_UPDATE_TFTP_CNT_MAX
@@ -1362,6 +1670,36 @@ The following options need to be configured:
 		CONFIG_SPL
 		Enable building of SPL globally.
 
+		CONFIG_SPL_MAX_FOOTPRINT
+		Maximum size in memory allocated to the SPL, BSS included.
+		When defined, the linker checks that the actual memory
+		used by SPL from _start to __bss_end does not exceed it.
+		CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
+		must not be both defined at the same time.
+
+		CONFIG_SPL_MAX_SIZE
+		Maximum size of the SPL image (text, data, rodata, and
+		linker lists sections), BSS excluded.
+		When defined, the linker checks that the actual size does
+		not exceed it.
+
+		CONFIG_SPL_RELOC_TEXT_BASE
+		Address to relocate to.  If unspecified, this is equal to
+		CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
+
+		CONFIG_SPL_BSS_START_ADDR
+		Link address for the BSS within the SPL binary.
+
+		CONFIG_SPL_BSS_MAX_SIZE
+		Maximum size in memory allocated to the SPL BSS.
+		When defined, the linker checks that the actual memory used
+		by SPL from __bss_start to __bss_end does not exceed it.
+		CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
+		must not be both defined at the same time.
+
+		CONFIG_SPL_STACK
+		Adress of the start of the stack SPL will use
+
 		CONFIG_SPL_PANIC_ON_RAW_IMAGE
 		When defined, SPL will panic() if the image it has
 		loaded does not have a signature.
@@ -1372,20 +1710,65 @@ The following options need to be configured:
 		consider that a completely unreadable NAND block is bad,
 		and thus should be skipped silently.
 
+		CONFIG_SPL_RELOC_STACK
+		Adress of the start of the stack SPL will use after
+		relocation.  If unspecified, this is equal to
+		CONFIG_SPL_STACK.
+
+		CONFIG_SYS_SPL_MALLOC_START
+		Starting address of the malloc pool used in SPL.
+		When this option is set the full malloc is used in SPL and
+		it is set up by spl_init() and before that, the simple malloc()
+		can be used if CONFIG_SYS_MALLOC_F is defined.
+
+		CONFIG_SYS_SPL_MALLOC_SIZE
+		The size of the malloc pool used in SPL.
+
 		CONFIG_SPL_DISPLAY_PRINT
 		For ARM, enable an optional function to print more information
 		about the running system.
 
+		CONFIG_SPL_INIT_MINIMAL
+		Arch init code should be built for a very small image
+
+		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
+		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
+		Sector and number of sectors to load kernel argument
+		parameters from when MMC is being used in raw mode
+		(for falcon mode)
+
+		CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
+		Filename to read to load U-Boot when reading from filesystem
+
+		CONFIG_SPL_FS_LOAD_KERNEL_NAME
+		Filename to read to load kernel uImage when reading
+		from filesystem (for Falcon mode)
+
+		CONFIG_SPL_FS_LOAD_ARGS_NAME
+		Filename to read to load kernel argument parameters
+		when reading from filesystem (for Falcon mode)
+
 		CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
 		Set this for NAND SPL on PPC mpc83xx targets, so that
 		start.S waits for the rest of the SPL to load before
 		continuing (the hardware starts execution after just
 		loading the first page rather than the full 4K).
 
+		CONFIG_SPL_SKIP_RELOCATE
+		Avoid SPL relocation
+
 		CONFIG_SPL_UBI
 		Support for a lightweight UBI (fastmap) scanner and
 		loader
 
+		CONFIG_SPL_NAND_RAW_ONLY
+		Support to boot only raw u-boot.bin images. Use this only
+		if you need to save space.
+
+		CONFIG_SPL_COMMON_INIT_DDR
+		Set for common ddr init with serial presence detect in
+		SPL binary.
+
 		CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
 		CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
 		CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
@@ -1410,12 +1793,35 @@ The following options need to be configured:
 		CONFIG_SPL_RAM_DEVICE
 		Support for running image already present in ram, in SPL binary
 
+		CONFIG_SPL_PAD_TO
+		Image offset to which the SPL should be padded before appending
+		the SPL payload. By default, this is defined as
+		CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
+		CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
+		payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
+
+		CONFIG_SPL_TARGET
+		Final target image containing SPL and payload.  Some SPLs
+		use an arch-specific makefile fragment instead, for
+		example if more than one image needs to be produced.
+
 		CONFIG_SPL_FIT_PRINT
 		Printing information about a FIT image adds quite a bit of
 		code to SPL. So this is normally disabled in SPL. Use this
 		option to re-enable it. This will affect the output of the
 		bootm command when booting a FIT image.
 
+- TPL framework
+		CONFIG_TPL
+		Enable building of TPL globally.
+
+		CONFIG_TPL_PAD_TO
+		Image offset to which the TPL should be padded before appending
+		the TPL payload. By default, this is defined as
+		CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
+		CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
+		payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
+
 - Interrupt support (PPC):
 
 		There are common interrupt_init() and timer_interrupt()
@@ -1459,6 +1865,16 @@ Configuration Settings:
 - CONFIG_SYS_PROMPT:	This is what U-Boot prints on the console to
 		prompt for user input.
 
+- CONFIG_SYS_CBSIZE:	Buffer size for input from the Console
+
+- CONFIG_SYS_PBSIZE:	Buffer size for Console output
+
+- CONFIG_SYS_MAXARGS:	max. Number of arguments accepted for monitor commands
+
+- CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to
+		the application (usually a Linux kernel) when it is
+		booted
+
 - CONFIG_SYS_BAUDRATE_TABLE:
 		List of legal baudrate settings for this board.
 
@@ -1471,6 +1887,27 @@ Configuration Settings:
 		the RAM base is not zero, or RAM is divided into banks,
 		this variable needs to be recalcuated to get the address.
 
+- CONFIG_SYS_MEM_TOP_HIDE:
+		If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header,
+		this specified memory area will get subtracted from the top
+		(end) of RAM and won't get "touched" at all by U-Boot. By
+		fixing up gd->ram_size the Linux kernel should gets passed
+		the now "corrected" memory size and won't touch it either.
+		This should work for arch/ppc and arch/powerpc. Only Linux
+		board ports in arch/powerpc with bootwrapper support that
+		recalculate the memory size from the SDRAM controller setup
+		will have to get fixed in Linux additionally.
+
+		This option can be used as a workaround for the 440EPx/GRx
+		CHIP 11 errata where the last 256 bytes in SDRAM shouldn't
+		be touched.
+
+		WARNING: Please make sure that this value is a multiple of
+		the Linux page size (normally 4k). If this is not the case,
+		then the end address of the Linux memory will be located at a
+		non page size aligned address and this could cause major
+		problems.
+
 - CONFIG_SYS_LOADS_BAUD_CHANGE:
 		Enable temporary baudrate change while serial download
 
@@ -1505,7 +1942,7 @@ Configuration Settings:
 - CONFIG_SYS_MALLOC_SIMPLE
 		Provides a simple and small malloc() and calloc() for those
 		boards which do not use the full malloc in SPL (which is
-		enabled with CONFIG_SYS_SPL_MALLOC).
+		enabled with CONFIG_SYS_SPL_MALLOC_START).
 
 - CONFIG_SYS_NONCACHED_MEMORY:
 		Size of non-cached memory area. This area of memory will be
@@ -1526,6 +1963,12 @@ Configuration Settings:
 
 		Non-cached memory is only supported on 32-bit ARM at present.
 
+- CONFIG_SYS_BOOTM_LEN:
+		Normally compressed uImages are limited to an
+		uncompressed size of 8 MBytes. If this is not enough,
+		you can define CONFIG_SYS_BOOTM_LEN in your board config file
+		to adjust this setting to your needs.
+
 - CONFIG_SYS_BOOTMAPSZ:
 		Maximum size of memory mapped by the startup code of
 		the Linux kernel; all data that must be processed by
@@ -1538,6 +1981,11 @@ Configuration Settings:
 		CONFIG_SYS_BOOTMAPSZ.  If CONFIG_SYS_BOOTMAPSZ is undefined,
 		then the value in "bootm_size" will be used instead.
 
+- CONFIG_SYS_BOOT_RAMDISK_HIGH:
+		Enable initrd_high functionality.  If defined then the
+		initrd_high feature is enabled and the bootm ramdisk subcommand
+		is enabled.
+
 - CONFIG_SYS_BOOT_GET_CMDLINE:
 		Enables allocating and saving kernel cmdline in space between
 		"bootm_low" and "bootm_low" + BOOTMAPSZ.
@@ -1546,10 +1994,38 @@ Configuration Settings:
 		Enables allocating and saving a kernel copy of the bd_info in
 		space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
 
+- CONFIG_SYS_MAX_FLASH_SECT:
+		Max number of sectors on a Flash chip
+
+- CONFIG_SYS_FLASH_ERASE_TOUT:
+		Timeout for Flash erase operations (in ms)
+
+- CONFIG_SYS_FLASH_WRITE_TOUT:
+		Timeout for Flash write operations (in ms)
+
+- CONFIG_SYS_FLASH_LOCK_TOUT
+		Timeout for Flash set sector lock bit operation (in ms)
+
+- CONFIG_SYS_FLASH_UNLOCK_TOUT
+		Timeout for Flash clear lock bits operation (in ms)
+
 - CONFIG_SYS_FLASH_PROTECTION
 		If defined, hardware flash sectors protection is used
 		instead of U-Boot software protection.
 
+- CONFIG_SYS_DIRECT_FLASH_TFTP:
+
+		Enable TFTP transfers directly to flash memory;
+		without this option such a download has to be
+		performed in two steps: (1) download to RAM, and (2)
+		copy from RAM to flash.
+
+		The two-step approach is usually more reliable, since
+		you can check if the download worked before you erase
+		the flash, but in some situations (when system RAM is
+		too limited to allow for a temporary copy of the
+		downloaded image) this option may be very useful.
+
 - CONFIG_SYS_FLASH_CFI:
 		Define if the flash driver uses extra elements in the
 		common flash structure for storing flash geometry.
@@ -1570,6 +2046,12 @@ Configuration Settings:
 		s29ws-n MirrorBit flash has non-standard addresses for buffered
 		write commands.
 
+- CONFIG_SYS_FLASH_QUIET_TEST
+		If this option is defined, the common CFI flash doesn't
+		print it's warning upon not recognized FLASH banks. This
+		is useful, if some of the configured banks are only
+		optionally available.
+
 - CONFIG_FLASH_SHOW_PROGRESS
 		If defined (must be an integer), print out countdown
 		digits and dots.  Recommended value: 45 (9..1) for 80
@@ -1584,6 +2066,14 @@ Configuration Settings:
 		while unprotecting/erasing/programming. Please only enable
 		this option if you really know what you are doing.
 
+- CONFIG_ENV_MAX_ENTRIES
+
+	Maximum number of entries in the hash table that is used
+	internally to store the environment settings. The default
+	setting is supposed to be generous and should work in most
+	cases. This setting can be used to tune behaviour; see
+	lib/hashtable.c for details.
+
 - CONFIG_ENV_FLAGS_LIST_DEFAULT
 - CONFIG_ENV_FLAGS_LIST_STATIC
 	Enable validation of the values given to environment variables when
@@ -1693,6 +2183,11 @@ use the "saveenv" command to store a valid environment.
 		later, once stdio is running and output goes to the LCD, if
 		present.
 
+- CONFIG_BOARD_SIZE_LIMIT:
+		Maximum size of the U-Boot image. When defined, the
+		build system checks that the actual size does not
+		exceed it.
+
 Low Level (hardware related) configuration options:
 ---------------------------------------------------
 
@@ -1729,6 +2224,10 @@ Low Level (hardware related) configuration options:
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 
+- CONFIG_SYS_CCSR_DO_NOT_RELOCATE:
+		If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
+		forced to a value that ensures that CCSR is not relocated.
+
 - CONFIG_SYS_IMMR:	Physical address of the Internal Memory.
 		DO NOT CHANGE unless you know exactly what you're
 		doing! (11-4) [MPC8xx systems only]
@@ -1746,6 +2245,24 @@ Low Level (hardware related) configuration options:
 		U-Boot uses the following memory types:
 		- MPC8xx: IMMR (internal memory of the CPU)
 
+- CONFIG_SYS_GBL_DATA_OFFSET:
+
+		Offset of the initial data structure in the memory
+		area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
+		CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
+		data is located at the end of the available space
+		(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
+		GENERATED_GBL_DATA_SIZE), and the initial stack is just
+		below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
+		CONFIG_SYS_GBL_DATA_OFFSET) downward.
+
+	Note:
+		On the MPC824X (or other systems that use the data
+		cache for initial memory) the address chosen for
+		CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
+		point to an otherwise UNUSED address space between
+		the top of RAM and the start of the PCI space.
+
 - CONFIG_SYS_SCCR:	System Clock and reset Control Register (15-27)
 
 - CONFIG_SYS_OR_TIMING_SDRAM:
@@ -1799,6 +2316,12 @@ Low Level (hardware related) configuration options:
 		one, specify here. Note that the value must resolve
 		to something your driver can deal with.
 
+- CONFIG_SYS_DDR_RAW_TIMING
+		Get DDR timing information from other than SPD. Common with
+		soldered DDR chips onboard without SPD. DDR raw timing
+		parameters are extracted from datasheet and hard-coded into
+		header files or board specific files.
+
 - CONFIG_FSL_DDR_INTERACTIVE
 		Enable interactive DDR debugging. See doc/README.fsl-ddr.
 
@@ -1808,6 +2331,10 @@ Low Level (hardware related) configuration options:
 - CONFIG_FSL_DDR_BIST
 		Enable built-in memory test for Freescale DDR controllers.
 
+- CONFIG_SYS_83XX_DDR_USES_CS0
+		Only for 83xx systems. If specified, then DDR should
+		be configured using CS0 and CS1 instead of CS2 and CS3.
+
 - CONFIG_RMII
 		Enable RMII mode for all FECs.
 		Note that this is a global option, we can't
@@ -1853,6 +2380,11 @@ Low Level (hardware related) configuration options:
 		proper). Code that needs stage-specific behavior should check
 		this.
 
+- CONFIG_SYS_MPC85XX_NO_RESETVEC
+		Only for 85xx systems. If this variable is specified, the section
+		.resetvec is not kept and the section .bootpg is placed in the
+		previous 4k of the .text section.
+
 - CONFIG_ARCH_MAP_SYSMEM
 		Generally U-Boot (and in particular the md command) uses
 		effective address. It is therefore not necessary to regard
@@ -2084,7 +2616,6 @@ rarpboot- boot image via network using RARP/TFTP protocol
 diskboot- boot from IDE devicebootd   - boot default, i.e., run 'bootcmd'
 loads	- load S-Record file over serial line
 loadb	- load binary file over serial line (kermit mode)
-loadm   - load binary blob from source address to destination address
 md	- memory display
 mm	- memory modify (auto-incrementing)
 nm	- memory modify (constant address)
@@ -2195,8 +2726,8 @@ details; basically, the header defines the following image properties:
   LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
-  IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: ARM, Intel x86, MIPS, Nios II, PowerPC).
+  IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+  Currently supported: ARM, Intel x86, MIPS, NDS32, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
@@ -2908,6 +3439,23 @@ On Nios II, the ABI is documented here:
     Note: on Nios II, we give "-G0" option to gcc and don't use gp
     to access small data sections, so gp is free.
 
+On NDS32, the following registers are used:
+
+	R0-R1:	argument/return
+	R2-R5:	argument
+	R15:	temporary register for assembler
+	R16:	trampoline register
+	R28:	frame pointer (FP)
+	R29:	global pointer (GP)
+	R30:	link register (LP)
+	R31:	stack pointer (SP)
+	PC:	program counter (PC)
+
+    ==> U-Boot will use R10 to hold a pointer to the global data
+
+NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
+or current versions of GCC may "optimize" the code too much.
+
 On RISC-V, the following registers are used:
 
 	x0: hard-wired zero (zero)

api/api_display.c

@@ -5,7 +5,14 @@
 
 #include <common.h>
 #include <api_public.h>
+#include <lcd.h>
 #include <log.h>
+#include <video_font.h> /* Get font width and height */
+
+/* lcd.h needs BMP_LOGO_HEIGHT to calculate CONSOLE_ROWS */
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
+#include <bmp_logo.h>
+#endif
 
 /* TODO(clchiou): add support of video device */
 
@@ -19,6 +26,14 @@ int display_get_info(int type, struct display_info *di)
 		debug("%s: unsupport display device type: %d\n",
 				__FILE__, type);
 		return API_ENODEV;
+#ifdef CONFIG_LCD
+	case DISPLAY_TYPE_LCD:
+		di->pixel_width  = panel_info.vl_col;
+		di->pixel_height = panel_info.vl_row;
+		di->screen_rows = lcd_get_screen_rows();
+		di->screen_cols = lcd_get_screen_columns();
+		break;
+#endif
 	}
 
 	di->type = type;
@@ -29,9 +44,16 @@ int display_draw_bitmap(ulong bitmap, int x, int y)
 {
 	if (!bitmap)
 		return API_EINVAL;
+#ifdef CONFIG_LCD
+	return lcd_display_bitmap(bitmap, x, y);
+#else
 	return API_ENODEV;
+#endif
 }
 
 void display_clear(void)
 {
+#ifdef CONFIG_LCD
+	lcd_clear();
+#endif
 }

arch/Kconfig

@@ -1,5 +1,5 @@
 config ARCH_MAP_SYSMEM
-	depends on SANDBOX
+	depends on SANDBOX || NDS32
 	def_bool y
 
 config CREATE_ARCH_SYMLINK
@@ -8,6 +8,9 @@ config CREATE_ARCH_SYMLINK
 config HAVE_ARCH_IOREMAP
 	bool
 
+config NEEDS_MANUAL_RELOC
+	bool
+
 config SYS_CACHE_SHIFT_4
 	bool
 
@@ -53,8 +56,6 @@ config ARC
 	select SUPPORT_OF_CONTROL
 	select SYS_CACHE_SHIFT_7
 	select TIMER
-	select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
-	select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
 
 config ARM
 	bool "ARM architecture"
@@ -75,19 +76,19 @@ config M68K
 
 config MICROBLAZE
 	bool "MicroBlaze architecture"
+	select NEEDS_MANUAL_RELOC
 	select SUPPORT_OF_CONTROL
-	imply CMD_TIMER
-	imply SPL_REGMAP if SPL
-	imply SPL_TIMER if SPL
-	imply TIMER
-	imply XILINX_TIMER
+	imply CMD_IRQ
 
 config MIPS
 	bool "MIPS architecture"
 	select HAVE_ARCH_IOREMAP
 	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
-	select SPL_SEPARATE_BSS if SPL
+
+config NDS32
+	bool "NDS32 architecture"
+	select SUPPORT_OF_CONTROL
 
 config NIOS2
 	bool "Nios II architecture"
@@ -111,7 +112,6 @@ config RISCV
 	select SUPPORT_OF_CONTROL
 	select OF_CONTROL
 	select DM
-	select SPL_SEPARATE_BSS if SPL
 	imply DM_SERIAL
 	imply DM_ETH
 	imply DM_EVENT
@@ -137,7 +137,6 @@ config SANDBOX
 	select BZIP2
 	select CMD_POWEROFF
 	select DM
-	select DM_FUZZING_ENGINE
 	select DM_GPIO
 	select DM_I2C
 	select DM_KEYBOARD
@@ -146,6 +145,7 @@ config SANDBOX
 	select DM_SPI
 	select DM_SPI_FLASH
 	select GZIP_COMPRESSED
+	select HAVE_BLOCK_DEVICE
 	select LZO
 	select OF_BOARD_SETUP
 	select PCI_ENDPOINT
@@ -166,12 +166,12 @@ config SANDBOX
 	imply CMD_IO
 	imply CMD_IOTRACE
 	imply CMD_LZMADEC
+	imply CMD_SATA
 	imply CMD_SF
 	imply CMD_SF_TEST
 	imply CRC32_VERIFY
 	imply FAT_WRITE
 	imply FIRMWARE
-	imply FUZZING_ENGINE_SANDBOX
 	imply HASH_VERIFY
 	imply LZMA
 	imply TEE
@@ -251,7 +251,7 @@ config X86
 	imply DM_SPI
 	imply DM_SPI_FLASH
 	imply DM_USB
-	imply VIDEO
+	imply DM_VIDEO
 	imply SYSRESET
 	imply SPL_SYSRESET
 	imply SYSRESET_X86
@@ -373,9 +373,6 @@ config SYS_IMMR
 	default 0xF0000000 if ARCH_MPC8313
 	default 0xE0000000 if MPC83xx && !ARCH_MPC8313
 	default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
-	default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
-			      ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
-			      ARCH_P2020
 	default SYS_CCSRBAR_DEFAULT
 	help
 	  Address for the Internal Memory-Mapped Registers (IMMR) window used
@@ -383,7 +380,7 @@ config SYS_IMMR
 
 config SKIP_LOWLEVEL_INIT
 	bool "Skip the calls to certain low level initialization functions"
-	depends on ARM || MIPS || RISCV
+	depends on ARM || NDS32 || MIPS || RISCV
 	help
 	  If enabled, then certain low level initializations (like setting up
 	  the memory controller) are omitted and/or U-Boot does not relocate
@@ -394,7 +391,7 @@ config SKIP_LOWLEVEL_INIT
 
 config SPL_SKIP_LOWLEVEL_INIT
 	bool "Skip the calls to certain low level initialization functions"
-	depends on SPL && (ARM || MIPS || RISCV)
+	depends on SPL && (ARM || NDS32 || MIPS || RISCV)
 	help
 	  If enabled, then certain low level initializations (like setting up
 	  the memory controller) are omitted and/or U-Boot does not relocate
@@ -443,6 +440,7 @@ source "arch/arm/Kconfig"
 source "arch/m68k/Kconfig"
 source "arch/microblaze/Kconfig"
 source "arch/mips/Kconfig"
+source "arch/nds32/Kconfig"
 source "arch/nios2/Kconfig"
 source "arch/powerpc/Kconfig"
 source "arch/sandbox/Kconfig"
@@ -451,33 +449,4 @@ source "arch/x86/Kconfig"
 source "arch/xtensa/Kconfig"
 source "arch/riscv/Kconfig"
 
-if ARM || M68K || PPC
-
-source "arch/Kconfig.nxp"
-
-endif
-
 source "board/keymile/Kconfig"
-source "board/sunxi/Kconfig"
-
-if MIPS || MICROBLAZE
-
-choice
-	prompt "Endianness selection"
-	help
-	  Some MIPS boards can be configured for either little or big endian
-	  byte order. These modes require different U-Boot images. In general there
-	  is one preferred byteorder for a particular system but some systems are
-	  just as commonly used in the one or the other endianness.
-
-config SYS_BIG_ENDIAN
-	bool "Big endian"
-	depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
-
-config SYS_LITTLE_ENDIAN
-	bool "Little endian"
-	depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE
-
-endchoice
-
-endif

arch/Kconfig.nxp

@@ -1,253 +0,0 @@
-config NXP_ESBC
-	bool "NXP ESBC (secure boot) functionality"
-	help
-	  Enable Freescale Secure Boot feature. Normally selected by defconfig.
-	  If unsure, do not change.
-
-menu "Chain of trust / secure boot options"
-	depends on !FIT_SIGNATURE && NXP_ESBC
-
-config CHAIN_OF_TRUST
-	select FSL_CAAM
-	select ARCH_MISC_INIT
-	select FSL_SEC_MON
-	select SPL_BOARD_INIT if (ARM && SPL)
-	select SPL_HASH if (ARM && SPL)
-	select SHA_HW_ACCEL
-	select SHA_PROG_HW_ACCEL
-	select ENV_IS_NOWHERE
-	select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
-	select CMD_EXT4 if ARM
-	select CMD_EXT4_WRITE if ARM
-	imply CMD_BLOB
-	imply CMD_HASH if ARM
-	def_bool y
-
-config CMD_ESBC_VALIDATE
-	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
-	default y
-	help
-	  This option enables two commands used for secure booting:
-
-	    esbc_validate - validate signature using RSA verification
-	    esbc_halt - put the core in spin loop (Secure Boot Only)
-
-config ESBC_HDR_LS
-	bool
-
-config ESBC_ADDR_64BIT
-	def_bool y
-	depends on ESBC_HDR_LS && FSL_LAYERSCAPE
-	help
-	  For Layerscape based platforms, ESBC image Address in Header is 64bit.
-
-config SYS_FSL_SFP_BE
-	def_bool y
-	depends on PPC || FSL_LSCH2 || ARCH_LS1021A
-
-config SYS_FSL_SFP_LE
-	def_bool y
-	depends on !SYS_FSL_SFP_BE
-
-choice
-	prompt "SFP IP revision"
-	default SYS_FSL_SFP_VER_3_0 if PPC
-	default SYS_FSL_SFP_VER_3_4
-
-config SYS_FSL_SFP_VER_3_0
-	bool "SFP version 3.0"
-
-config SYS_FSL_SFP_VER_3_2
-	bool "SFP version 3.2"
-
-config SYS_FSL_SFP_VER_3_4
-	bool "SFP version 3.4"
-
-endchoice
-
-config SPL_UBOOT_KEY_HASH
-	string "Non-SRK key hash for U-Boot public/private key pair"
-	depends on SPL
-	default ""
-	help
-	  Set the key hash for U-Boot here if public/private key pair used to
-	  sign U-boot are different from the SRK hash put in the fuse.  Example
-	  of a key hash is
-	  41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
-	  Otherwise leave this empty.
-
-if PPC
-
-config BOOTSCRIPT_COPY_RAM
-	bool "Secure boot copies boot script to RAM"
-	help
-	  On systems that support chain of trust booting, a number of addresses
-	  are required to set variables that are used in the copying and then
-	  verification of different parts of the system.  If enabled, the subsequent
-	  options are for what location to use in each step.
-
-config BS_ADDR_DEVICE
-	hex "Address in RAM for bs_device"
-	depends on BOOTSCRIPT_COPY_RAM
-
-config BS_SIZE
-	hex "The size of bs_size which is the amount read from bs_device"
-	depends on BOOTSCRIPT_COPY_RAM
-
-config BS_ADDR_RAM
-	hex "Address in RAM for bs_ram"
-	depends on BOOTSCRIPT_COPY_RAM
-
-config BS_HDR_ADDR_DEVICE
-	hex "Address in RAM for bs_hdr_device"
-	depends on BOOTSCRIPT_COPY_RAM
-
-config BS_HDR_SIZE
-	hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
-	depends on BOOTSCRIPT_COPY_RAM
-
-config BS_HDR_ADDR_RAM
-	hex "Address in RAM for bs_hdr_ram"
-	depends on BOOTSCRIPT_COPY_RAM
-
-config BOOTSCRIPT_HDR_ADDR
-	hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
-	default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
-
-endif
-
-config SYS_FSL_SRK_LE
-	def_bool y
-	depends on ARM
-
-config KEY_REVOCATION
-	def_bool y
-
-endmenu
-
-comment "Other functionality shared between NXP SoCs"
-
-config DEEP_SLEEP
-	bool "Enable SoC deep sleep feature"
-	depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
-	default y
-	help
-	  Indicates this SoC supports deep sleep feature. If deep sleep is
-	  supported, core will start to execute uboot when wakes up.
-
-config LAYERSCAPE_NS_ACCESS
-	bool "Layerscape non-secure access support"
-	depends on ARCH_LS1021A || FSL_LSCH2
-
-config PCIE1
-	bool "PCIe controller #1"
-	depends on LAYERSCAPE_NS_ACCESS || PPC
-
-config PCIE2
-	bool "PCIe controller #2"
-	depends on LAYERSCAPE_NS_ACCESS || PPC
-
-config PCIE3
-	bool "PCIe controller #3"
-	depends on LAYERSCAPE_NS_ACCESS || PPC
-
-config PCIE4
-	bool "PCIe controller #4"
-	depends on LAYERSCAPE_NS_ACCESS || PPC
-
-config FSL_USE_PCA9547_MUX
-	bool "Enable PCA9547 I2C Mux on Freescale boards"
-	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
-	help
-	 This option enables the PCA9547 I2C mux on Freescale boards.
-
-config VID
-	bool "Enable Freescale VID"
-	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
-	help
-	 This option enables setting core voltage based on individual
-	 values saved in SoC fuses.
-
-config SPL_VID
-	bool "Enable Freescale VID in SPL"
-	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
-	help
-	 This option enables setting core voltage based on individual
-	 values saved in SoC fuses, in SPL.
-
-if VID || SPL_VID
-
-config VID_FLS_ENV
-	string "Environment variable for overriding VDD"
-	help
-	  This option allows for specifying the environment variable
-	  to check to override VDD information.
-
-config VOL_MONITOR_INA220
-	bool "Enable the INA220 voltage monitor read"
-	help
-	  This option enables INA220 voltage monitor read
-	  functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_IR36021_READ
-	bool "Enable the IR36021 voltage monitor read"
-	help
-	 This option enables IR36021 voltage monitor read
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_IR36021_SET
-	bool "Enable the IR36021 voltage monitor set"
-	help
-	 This option enables IR36021 voltage monitor set
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_LTC3882_READ
-	bool "Enable the LTC3882 voltage monitor read"
-	help
-	 This option enables LTC3882 voltage monitor read
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_LTC3882_SET
-	bool "Enable the LTC3882 voltage monitor set"
-	help
-	 This option enables LTC3882 voltage monitor set
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_ISL68233_READ
-	bool "Enable the ISL68233 voltage monitor read"
-	help
-	 This option enables ISL68233 voltage monitor read
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_ISL68233_SET
-	bool "Enable the ISL68233 voltage monitor set"
-	help
-	 This option enables ISL68233 voltage monitor set
-	 functionality. It is used by the common VID driver.
-
-endif
-
-config SYS_FSL_NUM_CC_PLLS
-	int "Number of clock control PLLs"
-	depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
-	default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
-	default 6 if FSL_LSCH3 || MPC85xx
-
-config SYS_FSL_ESDHC_BE
-	bool
-
-config SYS_FSL_IFC_BE
-	bool
-
-config FSL_QIXIS
-	bool "Enable QIXIS support"
-	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
-
-config QIXIS_I2C_ACCESS
-	bool "Access to QIXIS is over i2c"
-	depends on FSL_QIXIS
-	default y
-
-config HAS_FSL_DR_USB
-	def_bool y
-	depends on USB_EHCI_HCD && PPC

arch/arc/config.mk

@@ -2,6 +2,12 @@
 #
 # Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
 
+ifndef CONFIG_CPU_BIG_ENDIAN
+CONFIG_SYS_LITTLE_ENDIAN = 1
+else
+CONFIG_SYS_BIG_ENDIAN = 1
+endif
+
 ifdef CONFIG_SYS_LITTLE_ENDIAN
 KBUILD_LDFLAGS += -EL
 PLATFORM_CPPFLAGS += -mlittle-endian

arch/arc/cpu/u-boot.lds

@@ -10,7 +10,7 @@ OUTPUT_ARCH(arc)
 ENTRY(_start)
 SECTIONS
 {
-	. = CONFIG_TEXT_BASE;
+	. = CONFIG_SYS_TEXT_BASE;
 	__image_copy_start = .;
 	. = ALIGN(1024);
 	__ivt_start = .;
@@ -39,8 +39,8 @@ SECTIONS
 	}
 
 	. = ALIGN(4);
-	__u_boot_list : {
-		KEEP(*(SORT(__u_boot_list*)));
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
 	}
 
 	. = ALIGN(4);

arch/arc/include/asm/config.h

@@ -6,4 +6,6 @@
 #ifndef __ASM_ARC_CONFIG_H_
 #define __ASM_ARC_CONFIG_H_
 
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
 #endif /*__ASM_ARC_CONFIG_H_ */

arch/arc/lib/bootm.c

@@ -22,18 +22,16 @@ static int cleanup_before_linux(void)
 	return 0;
 }
 
-__weak int board_prep_linux(struct bootm_headers *images) { return 0; }
+__weak int board_prep_linux(bootm_headers_t *images) { return 0; }
 
 /* Subcommand: PREP */
-static int boot_prep_linux(struct bootm_headers *images)
+static int boot_prep_linux(bootm_headers_t *images)
 {
 	int ret;
 
-	if (CONFIG_IS_ENABLED(LMB)) {
-		ret = image_setup_linux(images);
-		if (ret)
-			return ret;
-	}
+	ret = image_setup_linux(images);
+	if (ret)
+		return ret;
 
 	return board_prep_linux(images);
 }
@@ -49,7 +47,7 @@ __weak void board_jump_and_run(ulong entry, int zero, int arch, uint params)
 }
 
 /* Subcommand: GO */
-static void boot_jump_linux(struct bootm_headers *images, int flag)
+static void boot_jump_linux(bootm_headers_t *images, int flag)
 {
 	ulong kernel_entry;
 	unsigned int r0, r2;
@@ -79,7 +77,7 @@ static void boot_jump_linux(struct bootm_headers *images, int flag)
 		board_jump_and_run(kernel_entry, r0, 0, r2);
 }
 
-int do_bootm_linux(int flag, int argc, char *argv[], struct bootm_headers *images)
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
 {
 	/* No need for those on ARC */
 	if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))

arch/arc/lib/start.S

@@ -7,7 +7,6 @@
 #include <config.h>
 #include <linux/linkage.h>
 #include <asm/arcregs.h>
-#include <system-constants.h>
 
 ENTRY(_start)
 	/* Setup interrupt vector base that matches "__text_start" */
@@ -87,7 +86,7 @@ ENTRY(_start)
 #endif
 
 	/* Establish C runtime stack and frame */
-	mov	%sp, SYS_INIT_SP_ADDR
+	mov	%sp, CONFIG_SYS_INIT_SP_ADDR
 	mov	%fp, %sp
 
 	/* Allocate reserved area from current top of stack */

arch/arm/Kconfig

@@ -8,7 +8,6 @@ config ARM64
 	bool
 	select PHYS_64BIT
 	select SYS_CACHE_SHIFT_6
-	imply SPL_SEPARATE_BSS
 
 config ARM64_CRC32
 	bool "Enable support for CRC32 instruction"
@@ -20,23 +19,6 @@ config ARM64_CRC32
 	  not be present on all ARMv8.0, but is always present on ARMv8.1 and
 	  newer.
 
-config COUNTER_FREQUENCY
-	int "Timer clock frequency"
-	depends on ARM64 || CPU_V7A
-	default 8000000 if IMX8 || MX7 || MX6UL || MX6ULL
-	default 24000000 if ARCH_SUNXI || ARCH_EXYNOS || ROCKCHIP_RK3128 || \
-			ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
-	default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
-	default 100000000 if ARCH_ZYNQMP
-	default 0
-	help
-	  For platforms with ARMv8-A and ARMv7-A which features a system
-	  counter, those platforms needs software to program the counter
-	  frequency. Setup time clock frequency for certain platform.
-	  0 means no need to configure the system counter frequency.
-	  For platforms needs the frequency set in U-Boot with a
-	  pre-defined value, should have the macro defined as a non-zero value.
-
 config POSITION_INDEPENDENT
 	bool "Generate position-independent pre-relocation code"
 	depends on ARM64 || CPU_V7A
@@ -75,10 +57,6 @@ config SYS_INIT_SP_BSS_OFFSET
 	  that the early malloc region, global data (gd), and early stack usage
 	  do not overlap any appended DTB.
 
-config SPL_SYS_NO_VECTOR_TABLE
-	depends on SPL
-	bool
-
 config LINUX_KERNEL_IMAGE_HEADER
 	depends on ARM64
 	bool
@@ -93,7 +71,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE
 	depends on LINUX_KERNEL_IMAGE_HEADER
 	hex
 	help
-	  The value subtracted from CONFIG_TEXT_BASE to calculate the
+	  The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
 	  TEXT_OFFSET value written to the Linux kernel image header.
 
 config GICV2
@@ -289,7 +267,6 @@ config CPU_ARM926EJS
 	bool
 	select SYS_CACHE_SHIFT_5
 	imply SYS_ARM_MMU
-	imply SPL_SEPARATE_BSS
 
 config CPU_ARM946ES
 	bool
@@ -300,7 +277,6 @@ config CPU_ARM1136
 	bool
 	select SYS_CACHE_SHIFT_5
 	imply SYS_ARM_MMU
-	imply SPL_SEPARATE_BSS
 
 config CPU_ARM1176
 	bool
@@ -330,6 +306,20 @@ config CPU_V7R
 	select SYS_ARM_MPU
 	select SYS_CACHE_SHIFT_6
 
+config CPU_PXA
+	bool
+	select SYS_CACHE_SHIFT_5
+	imply SYS_ARM_MMU
+
+config CPU_PXA27X
+	bool
+	select CPU_PXA
+
+config CPU_SA1100
+	bool
+	select SYS_CACHE_SHIFT_5
+	imply SYS_ARM_MMU
+
 config SYS_CPU
 	default "arm720t" if CPU_ARM720T
 	default "arm920t" if CPU_ARM920T
@@ -340,6 +330,8 @@ config SYS_CPU
 	default "armv7" if CPU_V7A
 	default "armv7" if CPU_V7R
 	default "armv7m" if CPU_V7M
+	default "pxa" if CPU_PXA
+	default "sa1100" if CPU_SA1100
 	default "armv8" if ARM64
 
 config SYS_ARM_ARCH
@@ -353,11 +345,14 @@ config SYS_ARM_ARCH
 	default 7 if CPU_V7A
 	default 7 if CPU_V7M
 	default 7 if CPU_V7R
+	default 5 if CPU_PXA
+	default 4 if CPU_SA1100
 	default 8 if ARM64
 
 choice
 	prompt "Select the ARM data write cache policy"
-	default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1
+	default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
+					      CPU_PXA || RZA1
 	default SYS_ARM_CACHE_WRITEBACK
 
 config SYS_ARM_CACHE_WRITEBACK
@@ -382,12 +377,6 @@ config SYS_ARM_CACHE_WRITEALLOC
 	  write is performed.
 endchoice
 
-config ARCH_VERY_EARLY_INIT
-	bool
-
-config SPL_ARCH_VERY_EARLY_INIT
-	bool
-
 config ARCH_CPU_INIT
 	bool "Enable ARCH_CPU_INIT"
 	help
@@ -488,15 +477,6 @@ config TPL_SYS_THUMB_BUILD
 	   density. For ARM architectures that support Thumb2 this flag will
 	   result in Thumb2 code generated by GCC.
 
-config SYS_L2_PL310
-	bool "ARM PL310 L2 cache controller"
-	help
-	  Enable support for ARM PL310 L2 cache controller in U-Boot
-
-config SPL_SYS_L2_PL310
-	bool "ARM PL310 L2 cache controller in SPL"
-	help
-	  Enable support for ARM PL310 L2 cache controller in SPL
 
 config SYS_L2CACHE_OFF
 	bool "L2cache off"
@@ -599,9 +579,6 @@ config ARM64_SUPPORT_AARCH32
 	help
 	  This ARM64 system supports AArch32 execution state.
 
-config S5P
-	def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
-
 choice
 	prompt "Target select"
 	default TARGET_HIKEY
@@ -627,7 +604,6 @@ config ARCH_KIRKWOOD
 	select BOARD_EARLY_INIT_F
 	select CPU_ARM926EJS
 	select GPIO_EXTRA_HEADER
-	select TIMER
 
 config ARCH_MVEBU
 	bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
@@ -639,8 +615,6 @@ config ARCH_MVEBU
 	select GPIO_EXTRA_HEADER
 	select SPL_DM_SPI if SPL
 	select SPL_DM_SPI_FLASH if SPL
-	select SPL_TIMER if SPL
-	select TIMER
 	select OF_CONTROL
 	select OF_SEPARATE
 	select SPI
@@ -650,8 +624,6 @@ config ARCH_ORION5X
 	bool "Marvell Orion"
 	select CPU_ARM926EJS
 	select GPIO_EXTRA_HEADER
-	select SPL_SEPARATE_BSS if SPL
-	select TIMER
 
 config TARGET_STV0991
 	bool "Support stv0991"
@@ -678,6 +650,31 @@ config ARCH_BCM283X
 	imply CMD_DM
 	imply FAT_WRITE
 
+config ARCH_BCM63158
+	bool "Broadcom BCM63158 family"
+	select DM
+	select OF_CONTROL
+	imply CMD_DM
+
+config ARCH_BCM6753
+	bool "Broadcom BCM6753 family"
+	select CPU_V7A
+	select DM
+	select OF_CONTROL
+	imply CMD_DM
+
+config ARCH_BCM68360
+	bool "Broadcom BCM68360 family"
+	select DM
+	select OF_CONTROL
+	imply CMD_DM
+
+config ARCH_BCM6858
+	bool "Broadcom BCM6858 family"
+	select DM
+	select OF_CONTROL
+	imply CMD_DM
+
 config ARCH_BCMSTB
 	bool "Broadcom BCM7XXX family"
 	select CPU_V7A
@@ -690,12 +687,6 @@ config ARCH_BCMSTB
 	  This enables support for Broadcom ARM-based set-top box
 	  chipsets, including the 7445 family of chips.
 
-config ARCH_BCMBCA
-	bool "Broadcom broadband chip family"
-	select DM
-	select OF_CONTROL
-	imply CMD_DM
-
 config TARGET_VEXPRESS_CA9X4
 	bool "Support vexpress_ca9x4"
 	select CPU_V7A
@@ -799,6 +790,7 @@ config ARCH_KEYSTONE
 	select CMD_POWEROFF
 	select CPU_V7A
 	select DDR_SPD
+	select GPIO_EXTRA_HEADER
 	select SUPPORT_SPL
 	select SYS_ARCH_TIMER
 	select SYS_THUMB_BUILD
@@ -822,7 +814,6 @@ config ARCH_OMAP2PLUS
 	imply TI_SYSC if DM && OF_CONTROL
 	imply FIT
 	imply DM_EVENT
-	imply SPL_SEPARATE_BSS
 
 config ARCH_MESON
 	bool "Amlogic Meson"
@@ -862,9 +853,6 @@ config ARCH_LPC32XX
 config ARCH_IMX8
 	bool "NXP i.MX8 platform"
 	select ARM64
-	select SYS_FSL_HAS_SEC
-	select SYS_FSL_SEC_COMPAT_4
-	select SYS_FSL_SEC_LE
 	select DM
 	select GPIO_EXTRA_HEADER
 	select MACH_IMX
@@ -877,7 +865,7 @@ config ARCH_IMX8M
 	select ARM64
 	select GPIO_EXTRA_HEADER
 	select MACH_IMX
-	select SYS_FSL_HAS_SEC
+	select SYS_FSL_HAS_SEC if IMX_HAB
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
 	select SYS_I2C_MXC
@@ -894,20 +882,6 @@ config ARCH_IMX8ULP
 	select OF_CONTROL
 	select SUPPORT_SPL
 	select GPIO_EXTRA_HEADER
-	select MISC
-	select IMX_SENTINEL
-	imply CMD_DM
-	imply DM_EVENT
-
-config ARCH_IMX9
-	bool "NXP i.MX9 platform"
-	select ARM64
-	select DM
-	select MACH_IMX
-	select SUPPORT_SPL
-	select GPIO_EXTRA_HEADER
-	select MISC
-	select IMX_SENTINEL
 	imply CMD_DM
 	imply DM_EVENT
 
@@ -949,7 +923,7 @@ config ARCH_MX7ULP
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
 	select MACH_IMX
-	select SYS_FSL_HAS_SEC
+	select SYS_FSL_HAS_SEC if IMX_HAB
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
 	select ROM_UNIFIED_SECTIONS
@@ -962,7 +936,7 @@ config ARCH_MX7
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
 	select MACH_IMX
-	select SYS_FSL_HAS_SEC
+	select SYS_FSL_HAS_SEC if IMX_HAB
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
 	imply BOARD_EARLY_INIT_F
@@ -978,10 +952,13 @@ config ARCH_MX6
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
-	select SYS_L2_PL310 if !SYS_L2CACHE_OFF
 	imply MXC_GPIO
 	imply SYS_THUMB_BUILD
-	imply SPL_SEPARATE_BSS
+
+if ARCH_MX6
+config SPL_LDSCRIPT
+	default "arch/arm/mach-omap2/u-boot-spl.lds"
+endif
 
 config ARCH_MX5
 	bool "Freescale MX5"
@@ -997,15 +974,10 @@ config ARCH_NEXELL
 	select DM
 	select GPIO_EXTRA_HEADER
 
-config ARCH_NPCM
-	bool "Support Nuvoton SoCs"
-	select DM
-	select OF_CONTROL
-	imply CMD_DM
-
 config ARCH_APPLE
 	bool "Apple SoCs"
 	select ARM64
+	select BLK
 	select CLK
 	select CMD_USB
 	select DM
@@ -1016,10 +988,9 @@ config ARCH_APPLE
 	select DM_SERIAL
 	select DM_SPI
 	select DM_USB
-	select VIDEO
+	select DM_VIDEO
 	select IOMMU
 	select LINUX_KERNEL_IMAGE_HEADER
-	select OF_BOARD_SETUP
 	select OF_CONTROL
 	select PINCTRL
 	select POSITION_INDEPENDENT
@@ -1102,6 +1073,7 @@ config ARCH_SOCFPGA
 	select SPL_DM_SERIAL
 	select SPL_LIBCOMMON_SUPPORT
 	select SPL_LIBGENERIC_SUPPORT
+	select SPL_NAND_SUPPORT if SPL_NAND_DENALI
 	select SPL_OF_CONTROL
 	select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
 	select SPL_SERIAL
@@ -1133,17 +1105,64 @@ config ARCH_SOCFPGA
 
 config ARCH_SUNXI
 	bool "Support sunxi (Allwinner) SoCs"
-	select BOARD_SUNXI
+	select BINMAN
+	select CMD_GPIO
+	select CMD_MMC if MMC
+	select CMD_USB if DISTRO_DEFAULTS && USB_HOST
+	select CLK
+	select DM
+	select DM_ETH
+	select DM_GPIO
+	select DM_I2C if I2C
+	select DM_SPI if SPI
+	select DM_SPI_FLASH if SPI
+	select DM_KEYBOARD
+	select DM_MMC if MMC
+	select DM_SCSI if SCSI
+	select DM_SERIAL
 	select GPIO_EXTRA_HEADER
+	select OF_BOARD_SETUP
 	select OF_CONTROL
 	select OF_SEPARATE
-	select SPECIFY_CONSOLE_INDEX if SERIAL
+	select PINCTRL
+	select SPECIFY_CONSOLE_INDEX
+	select SPL_SEPARATE_BSS if SPL
 	select SPL_STACK_R if SPL
 	select SPL_SYS_MALLOC_SIMPLE if SPL
 	select SPL_SYS_THUMB_BUILD if !ARM64
+	select SUNXI_GPIO
+	select SYS_NS16550
 	select SYS_THUMB_BUILD if !ARM64
+	select USB if DISTRO_DEFAULTS
+	select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
+	select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
 	select SPL_USE_TINY_PRINTF
+	select USE_PREBOOT
+	select SYS_RELOC_GD_ENV_ADDR
+	imply BOARD_LATE_INIT
+	imply CMD_DM
+	imply CMD_GPT
+	imply CMD_UBI if MTD_RAW_NAND
+	imply DISTRO_DEFAULTS
+	imply FAT_WRITE
+	imply FIT
+	imply OF_LIBFDT_OVERLAY
+	imply PRE_CONSOLE_BUFFER
+	imply SPL_GPIO
+	imply SPL_LIBCOMMON_SUPPORT
+	imply SPL_LIBGENERIC_SUPPORT
 	imply SPL_LOAD_FIT
+	imply SPL_MMC if MMC
+	imply SPL_POWER
+	imply SPL_SERIAL
+	imply SYSRESET
+	imply SYSRESET_WATCHDOG
+	imply SYSRESET_WATCHDOG_AUTO
+	imply USB_EHCI_GENERIC
+	imply USB_ETHER if USB_MUSB_GADGET
+	imply USB_GADGET
+	imply USB_OHCI_GENERIC
+	imply WDT
 
 config ARCH_U8500
 	bool "ST-Ericsson U8500 Series"
@@ -1184,18 +1203,6 @@ config ARCH_VERSAL
 	imply BOARD_LATE_INIT
 	imply ENV_VARS_UBOOT_RUNTIME_CONFIG
 
-config ARCH_VERSAL_NET
-	bool "Support Xilinx Keystone Platform"
-	select ARM64
-	select CLK
-	select DM
-	select DM_ETH if NET
-	select DM_MMC if MMC
-	select DM_SERIAL
-	select OF_CONTROL
-	imply BOARD_LATE_INIT
-	imply ENV_VARS_UBOOT_RUNTIME_CONFIG
-
 config ARCH_VF610
 	bool "Freescale Vybrid"
 	select CPU_V7A
@@ -1207,7 +1214,6 @@ config ARCH_VF610
 
 config ARCH_ZYNQ
 	bool "Xilinx Zynq based platform"
-	select ARM_TWD_TIMER
 	select CLK
 	select CLK_ZYNQ
 	select CPU_V7A
@@ -1227,9 +1233,7 @@ config ARCH_ZYNQ
 	select SPL_DM_SPI_FLASH if SPL
 	select SPL_OF_CONTROL if SPL
 	select SPL_SEPARATE_BSS if SPL
-	select SPL_TIMER if SPL
 	select SUPPORT_SPL
-	select TIMER
 	imply ARCH_EARLY_INIT_R
 	imply BOARD_LATE_INIT
 	imply CMD_CLK
@@ -1304,12 +1308,6 @@ config ARCH_VEXPRESS64
 	select ENV_IS_IN_FLASH if MTD
 	imply DISTRO_DEFAULTS
 
-config TARGET_CORSTONE1000
-	bool "Support Corstone1000 Platform"
-	select ARM64
-	select PL01X_SERIAL
-	select DM
-
 config TARGET_TOTAL_COMPUTE
 	bool "Support Total Compute Platform"
 	select ARM64
@@ -1836,6 +1834,11 @@ config TARGET_TEN64
 	  Support for Traverse Technologies Ten64 board, based
 	  on NXP LS1088A.
 
+config TARGET_COLIBRI_PXA270
+	bool "Support colibri_pxa270"
+	select CPU_PXA27X
+	select GPIO_EXTRA_HEADER
+
 config ARCH_UNIPHIER
 	bool "Socionext UniPhier SoCs"
 	select BOARD_LATE_INIT
@@ -1886,7 +1889,7 @@ config ARCH_STM32
 	imply CMD_DM
 
 config ARCH_STI
-	bool "Support STMicroelectronics SoCs"
+	bool "Support STMicrolectronics SoCs"
 	select BLK
 	select CPU_V7A
 	select DM
@@ -1914,6 +1917,7 @@ config ARCH_STM32MP
 	select OF_SYSTEM_SETUP
 	select PINCTRL
 	select REGMAP
+	select SUPPORT_SPL
 	select SYSCON
 	select SYSRESET
 	select SYS_THUMB_BUILD
@@ -1935,7 +1939,7 @@ config ARCH_STM32MP
 config ARCH_ROCKCHIP
 	bool "Support Rockchip SoCs"
 	select BLK
-	select BINMAN if SPL_OPTEE || SPL
+	select BINMAN if SPL_OPTEE || (SPL && !ARM64)
 	select DM
 	select DM_GPIO
 	select DM_I2C
@@ -2047,12 +2051,6 @@ config TARGET_XENGUEST_ARM64
 	select SSCANF
 	imply OF_HAS_PRIOR_STAGE
 
-config ARCH_GXP
-	bool "Support HPE GXP SoCs"
-	select DM
-	select OF_CONTROL
-	imply CMD_DM
-
 endchoice
 
 config SUPPORT_PASSING_ATAGS
@@ -2087,7 +2085,6 @@ config SERIAL_TAG
 
 config STATIC_MACH_TYPE
 	bool "Statically define the Machine ID number"
-	default y if TARGET_DS109 || TARGET_NOKIA_RX51 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
 	help
 	  When booting via ATAGs, enable this option if we know the correct
 	  machine ID number to use at compile time.  Some systems will be
@@ -2096,10 +2093,6 @@ config STATIC_MACH_TYPE
 config MACH_TYPE
 	int "Machine ID number"
 	depends on STATIC_MACH_TYPE
-	default 527 if TARGET_DS109
-	default 1955 if TARGET_NOKIA_RX51
-	default 3036 if TARGET_DS414
-	default 4283 if DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
 	help
 	  When booting via ATAGs, the machine type must be passed as a number.
 	  For the full list see https://www.arm.linux.org.uk/developer/machines
@@ -2129,6 +2122,21 @@ config TI_SECURE_DEVICE
 	  authenticated) and the code. See the doc/README.ti-secure
 	  file for further details.
 
+if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
+config ISW_ENTRY_ADDR
+	hex "Address in memory or XIP address of bootloader entry point"
+	default 0x402F4000 if AM43XX
+	default 0x402F0400 if AM33XX
+	default 0x40301350 if OMAP54XX
+	help
+	  After any reset, the boot ROM searches the boot media for a valid
+	  boot image. For non-XIP devices, the ROM then copies the image into
+	  internal memory. For all boot modes, after the ROM processes the
+	  boot image it eventually computes the entry point address depending
+	  on the device type (secure/non-secure), boot media (xip/non-xip) and
+	  image headers.
+endif
+
 config SYS_KWD_CONFIG
 	string "kwbimage config file path"
 	depends on ARCH_KIRKWOOD || ARCH_MVEBU
@@ -2145,16 +2153,12 @@ source "arch/arm/mach-at91/Kconfig"
 
 source "arch/arm/mach-bcm283x/Kconfig"
 
-source "arch/arm/mach-bcmbca/Kconfig"
-
 source "arch/arm/mach-bcmstb/Kconfig"
 
 source "arch/arm/mach-davinci/Kconfig"
 
 source "arch/arm/mach-exynos/Kconfig"
 
-source "arch/arm/mach-hpe/gxp/Kconfig"
-
 source "arch/arm/mach-highbank/Kconfig"
 
 source "arch/arm/mach-integrator/Kconfig"
@@ -2193,8 +2197,6 @@ source "arch/arm/mach-imx/imx8m/Kconfig"
 
 source "arch/arm/mach-imx/imx8ulp/Kconfig"
 
-source "arch/arm/mach-imx/imx9/Kconfig"
-
 source "arch/arm/mach-imx/imxrt/Kconfig"
 
 source "arch/arm/mach-imx/mxs/Kconfig"
@@ -2245,8 +2247,6 @@ source "arch/arm/mach-zynqmp/Kconfig"
 
 source "arch/arm/mach-versal/Kconfig"
 
-source "arch/arm/mach-versal-net/Kconfig"
-
 source "arch/arm/mach-zynqmp-r5/Kconfig"
 
 source "arch/arm/cpu/armv7/Kconfig"
@@ -2257,10 +2257,8 @@ source "arch/arm/mach-imx/Kconfig"
 
 source "arch/arm/mach-nexell/Kconfig"
 
-source "arch/arm/mach-npcm/Kconfig"
-
 source "board/armltd/total_compute/Kconfig"
-source "board/armltd/corstone1000/Kconfig"
+
 source "board/bosch/shc/Kconfig"
 source "board/bosch/guardian/Kconfig"
 source "board/Marvell/octeontx/Kconfig"
@@ -2268,6 +2266,10 @@ source "board/Marvell/octeontx2/Kconfig"
 source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
 source "board/cortina/presidio-asic/Kconfig"
+source "board/broadcom/bcm963158/Kconfig"
+source "board/broadcom/bcm96753ref/Kconfig"
+source "board/broadcom/bcm968360bg/Kconfig"
+source "board/broadcom/bcm968580xref/Kconfig"
 source "board/broadcom/bcmns3/Kconfig"
 source "board/cavium/thunderx/Kconfig"
 source "board/eets/pdu001/Kconfig"
@@ -2296,11 +2298,11 @@ source "board/hisilicon/poplar/Kconfig"
 source "board/isee/igep003x/Kconfig"
 source "board/kontron/sl28/Kconfig"
 source "board/myir/mys_6ulx/Kconfig"
-source "board/siemens/common/Kconfig"
 source "board/seeed/npi_imx6ull/Kconfig"
 source "board/socionext/developerbox/Kconfig"
 source "board/st/stv0991/Kconfig"
 source "board/tcl/sl50/Kconfig"
+source "board/toradex/colibri_pxa270/Kconfig"
 source "board/traverse/ten64/Kconfig"
 source "board/variscite/dart_6ul/Kconfig"
 source "board/vscom/baltos/Kconfig"
@@ -2311,3 +2313,8 @@ source "board/xen/xenguest_arm64/Kconfig"
 source "arch/arm/Kconfig.debug"
 
 endmenu
+
+config SPL_LDSCRIPT
+	default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
+	default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
+	default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64

arch/arm/Makefile

@@ -10,6 +10,8 @@ arch-$(CONFIG_CPU_ARM720T)	=-march=armv4
 arch-$(CONFIG_CPU_ARM920T)	=-march=armv4t
 arch-$(CONFIG_CPU_ARM926EJS)	=-march=armv5te
 arch-$(CONFIG_CPU_ARM946ES)	=-march=armv5te
+arch-$(CONFIG_CPU_SA1100)	=-march=armv4
+arch-$(CONFIG_CPU_PXA)		=
 arch-$(CONFIG_CPU_ARM1136)	=-march=armv5t
 arch-$(CONFIG_CPU_ARM1176)	=-march=armv5t
 arch-$(CONFIG_CPU_V7A)		=$(call cc-option, -march=armv7-a, \
@@ -38,6 +40,8 @@ tune-$(CONFIG_CPU_ARM720T)	=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM920T)	=
 tune-$(CONFIG_CPU_ARM926EJS)	=
 tune-$(CONFIG_CPU_ARM946ES)	=
+tune-$(CONFIG_CPU_SA1100)	=-mtune=strongarm1100
+tune-$(CONFIG_CPU_PXA)		=-mcpu=xscale
 tune-$(CONFIG_CPU_ARM1136)	=
 tune-$(CONFIG_CPU_ARM1176)	=
 tune-$(CONFIG_CPU_V7A)		=-mtune=generic-armv7-a
@@ -55,11 +59,9 @@ machine-$(CONFIG_ARCH_APPLE)		+= apple
 machine-$(CONFIG_ARCH_ASPEED)		+= aspeed
 machine-$(CONFIG_ARCH_AT91)		+= at91
 machine-$(CONFIG_ARCH_BCM283X)		+= bcm283x
-machine-$(CONFIG_ARCH_BCMBCA)		+= bcmbca
 machine-$(CONFIG_ARCH_BCMSTB)		+= bcmstb
 machine-$(CONFIG_ARCH_DAVINCI)		+= davinci
 machine-$(CONFIG_ARCH_EXYNOS)		+= exynos
-machine-$(CONFIG_ARCH_GXP)		+= hpe
 machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
 machine-$(CONFIG_ARCH_IPQ40XX)		+= ipq40xx
 machine-$(CONFIG_ARCH_K3)		+= k3
@@ -70,7 +72,6 @@ machine-$(CONFIG_ARCH_MEDIATEK)		+= mediatek
 machine-$(CONFIG_ARCH_MESON)		+= meson
 machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
 machine-$(CONFIG_ARCH_NEXELL)		+= nexell
-machine-$(CONFIG_ARCH_NPCM)             += npcm
 machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
 machine-$(CONFIG_ARCH_ORION5X)		+= orion5x
 machine-$(CONFIG_ARCH_OWL)		+= owl
@@ -88,13 +89,10 @@ machine-$(CONFIG_ARCH_OCTEONTX)		+= octeontx
 machine-$(CONFIG_ARCH_OCTEONTX2)	+= octeontx2
 machine-$(CONFIG_ARCH_UNIPHIER)		+= uniphier
 machine-$(CONFIG_ARCH_VERSAL)		+= versal
-machine-$(CONFIG_ARCH_VERSAL_NET)	+= versal-net
 machine-$(CONFIG_ARCH_ZYNQ)		+= zynq
 machine-$(CONFIG_ARCH_ZYNQMP)		+= zynqmp
 machine-$(CONFIG_ARCH_ZYNQMP_R5)	+= zynqmp-r5
 
-machine-$(CONFIG_MACH_IMX)		+= imx
-
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 
 PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
@@ -104,8 +102,8 @@ libs-y += $(machdirs)
 head-y := arch/arm/cpu/$(CPU)/start.o
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifeq ($(CONFIG_SYS_SOC)$(CONFIG_SPL_FRAMEWORK),"mxs")
-head-y := arch/arm/cpu/arm926ejs/mxs/start.o
+ifneq ($(CONFIG_SPL_START_S_PATH),)
+head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
 endif
 endif
 
@@ -113,6 +111,16 @@ libs-y += arch/arm/cpu/$(CPU)/
 libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
+ifeq ($(CONFIG_SPL_BUILD),y)
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
+libs-y += arch/arm/mach-imx/
+endif
+else
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imxrt vf610))
+libs-y += arch/arm/mach-imx/
+endif
+endif
+
 ifneq (,$(filter $(SOC), kirkwood))
 libs-y += arch/arm/mach-mvebu/
 endif

arch/arm/config.mk

@@ -15,11 +15,11 @@ CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
 		  -fstack-protector-strong
 CFLAGS_EFI := -fpic -fshort-wchar
 
-ifneq ($(LTO_ENABLE)$(CONFIG_USE_PRIVATE_LIBGCC),yy)
+ifneq ($(CONFIG_LTO)$(CONFIG_USE_PRIVATE_LIBGCC),yy)
 LDFLAGS_FINAL += --gc-sections
 endif
 
-ifneq ($(LTO_ENABLE),y)
+ifndef CONFIG_LTO
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
 endif
 
@@ -141,11 +141,11 @@ endif
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
-		-j __u_boot_list -j .rela.dyn -j .got -j .got.plt \
+		-j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
 		-j .binman_sym_table -j .text_rest
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-		-j .data -j .got -j .got.plt -j __u_boot_list -j .rel.dyn \
+		-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
 		-j .binman_sym_table -j .text_rest
 endif
 

arch/arm/cpu/arm1176/start.S

@@ -88,7 +88,7 @@ cpu_init_crit:
 
 	/* Prepare to disable the MMU */
 	adr	r2, mmu_disable_phys
-	sub	r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_TEXT_BASE)
+	sub	r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
 	b	mmu_disable
 
 	.align 5

arch/arm/cpu/arm920t/Makefile

@@ -7,6 +7,7 @@ extra-y	= start.o
 
 obj-y	+= cpu.o
 
+obj-$(CONFIG_EP93XX) += ep93xx/
 obj-$(CONFIG_IMX) += imx/
 
 # some files can only build in ARM mode

arch/arm/cpu/arm920t/ep93xx/Makefile

@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Cirrus Logic EP93xx CPU-specific Makefile
+#
+# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+#
+# Copyright (C) 2004, 2005
+# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+#
+# Copyright (C) 2006
+# Dominic Rath <Dominic.Rath@gmx.de>
+#
+# Based on an original Makefile, which is
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y   = cpu.o led.o speed.o timer.o
+obj-y   += lowlevel_init.o

arch/arm/cpu/arm920t/ep93xx/cpu.c

@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Cirrus Logic EP93xx CPU-specific support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
+extern void reset_cpu(void)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+	uint32_t value;
+
+	/* Unlock DeviceCfg and set SWRST */
+	writel(0xAA, &syscon->sysswlock);
+	value = readl(&syscon->devicecfg);
+	value |= SYSCON_DEVICECFG_SWRST;
+	writel(value, &syscon->devicecfg);
+
+	/* Unlock DeviceCfg and clear SWRST */
+	writel(0xAA, &syscon->sysswlock);
+	value = readl(&syscon->devicecfg);
+	value &= ~SYSCON_DEVICECFG_SWRST;
+	writel(value, &syscon->devicecfg);
+
+	/* Dying... */
+	while (1)
+		; /* noop */
+}

arch/arm/cpu/arm920t/ep93xx/led.c

@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ */
+
+#include <asm/io.h>
+#include <asm/arch/ep93xx.h>
+#include <config.h>
+#include <status_led.h>
+
+static uint8_t saved_state[2] = {CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_OFF};
+static uint32_t gpio_pin[2] = {1 << CONFIG_LED_STATUS_GREEN,
+			       1 << CONFIG_LED_STATUS_RED};
+
+static inline void switch_LED_on(uint8_t led)
+{
+	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+	writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
+	saved_state[led] = CONFIG_LED_STATUS_ON;
+}
+
+static inline void switch_LED_off(uint8_t led)
+{
+	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+	writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
+	saved_state[led] = CONFIG_LED_STATUS_OFF;
+}
+
+void red_led_on(void)
+{
+	switch_LED_on(CONFIG_LED_STATUS_RED);
+}
+
+void red_led_off(void)
+{
+	switch_LED_off(CONFIG_LED_STATUS_RED);
+}
+
+void green_led_on(void)
+{
+	switch_LED_on(CONFIG_LED_STATUS_GREEN);
+}
+
+void green_led_off(void)
+{
+	switch_LED_off(CONFIG_LED_STATUS_GREEN);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+	__led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+	if (CONFIG_LED_STATUS_RED == mask) {
+		if (CONFIG_LED_STATUS_ON == saved_state[CONFIG_LED_STATUS_RED])
+			red_led_off();
+		else
+			red_led_on();
+	} else if (CONFIG_LED_STATUS_GREEN == mask) {
+		if (CONFIG_LED_STATUS_ON ==
+		    saved_state[CONFIG_LED_STATUS_GREEN])
+			green_led_off();
+		else
+			green_led_on();
+	}
+}
+
+void __led_set(led_id_t mask, int state)
+{
+	if (CONFIG_LED_STATUS_RED == mask) {
+		if (CONFIG_LED_STATUS_ON == state)
+			red_led_on();
+		else
+			red_led_off();
+	} else if (CONFIG_LED_STATUS_GREEN == mask) {
+		if (CONFIG_LED_STATUS_ON == state)
+			green_led_on();
+		else
+			green_led_off();
+	}
+}

arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S

@@ -0,0 +1,457 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Low-level initialization for EP93xx
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ * Copyright (C) 2013
+ * Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ * Copyright (C) 2006 Cirrus Logic Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ */
+
+#include <config.h>
+#include <asm/arch-ep93xx/ep93xx.h>
+
+/*
+/* Configure the SDRAM based on the supplied settings.
+ *
+ * Input:	r0 - SDRAM DEVCFG register
+ *		r2 - configuration for SDRAM chips
+ * Output:	none
+ * Modifies:	r3, r4
+ */
+ep93xx_sdram_config:
+	/* Program the SDRAM device configuration register. */
+	ldr	r3, =SDRAM_BASE
+#ifdef CONFIG_EDB93XX_SDCS0
+	str	r0, [r3, #SDRAM_OFF_DEVCFG0]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS1
+	str	r0, [r3, #SDRAM_OFF_DEVCFG1]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS2
+	str	r0, [r3, #SDRAM_OFF_DEVCFG2]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS3
+	str	r0, [r3, #SDRAM_OFF_DEVCFG3]
+#endif
+
+	/* Set the Initialize and MRS bits (issue continuous NOP commands
+	 * (INIT & MRS set))
+	 */
+	ldr	r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
+			EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
+			EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
+	str	r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+	/* Delay for 200us. */
+	mov	r4, #0x3000
+delay1:
+	subs	r4, r4, #1
+	bne	delay1
+
+	/* Clear the MRS bit to issue a precharge all. */
+	ldr	r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
+			EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
+	str	r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+	/* Temporarily set the refresh timer to 0x10. Make it really low so
+	 * that refresh cycles are generated.
+	 */
+	ldr	r4, =0x10
+	str	r4, [r3, #SDRAM_OFF_REFRSHTIMR]
+
+	/* Delay for at least 80 SDRAM clock cycles. */
+	mov	r4, #80
+delay2:
+	subs	r4, r4, #1
+	bne	delay2
+
+	/* Set the refresh timer to the fastest required for any device
+	 * that might be used. Set 9.6 ms refresh time.
+	 */
+	ldr	r4, =0x01e0
+	str	r4, [r3, #SDRAM_OFF_REFRSHTIMR]
+
+	/* Select mode register update mode. */
+	ldr	r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
+			EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
+	str	r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+	/* Program the mode register on the SDRAM by performing fake read */
+	ldr	r4, [r2]
+
+	/* Select normal operating mode. */
+	ldr	r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
+	str	r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+	/* Return to the caller. */
+	mov	pc, lr
+
+/*
+ * Test to see if the SDRAM has been configured in a usable mode.
+ *
+ * Input:	r0 - Test address of SDRAM
+ * Output:	r0 - 0 -- Test OK, -1 -- Failed
+ * Modifies:	r0-r5
+ */
+ep93xx_sdram_test:
+	/* Load the test patterns to be written to SDRAM. */
+	ldr	r1, =0xf00dface
+	ldr	r2, =0xdeadbeef
+	ldr	r3, =0x08675309
+	ldr	r4, =0xdeafc0ed
+
+	/* Store the test patterns to SDRAM. */
+	stmia	r0, {r1-r4}
+
+	/* Load the test patterns from SDRAM one at a time and compare them
+	 * to the actual pattern.
+	 */
+	ldr	r5, [r0]
+	cmp	r5, r1
+	ldreq	r5, [r0, #0x0004]
+	cmpeq	r5, r2
+	ldreq	r5, [r0, #0x0008]
+	cmpeq	r5, r3
+	ldreq	r5, [r0, #0x000c]
+	cmpeq	r5, r4
+
+	/* Return -1 if a mismatch was encountered, 0 otherwise. */
+	mvnne	r0, #0xffffffff
+	moveq	r0, #0x00000000
+
+	/* Return to the caller. */
+	mov	pc, lr
+
+/*
+ * Determine the size of the SDRAM. Use data=address for the scan.
+ *
+ * Input:	r0 - Start SDRAM address
+ * Return:	r0 - Single block size
+ *		r1 - Valid block mask
+ *		r2 - Total block count
+ * Modifies:	r0-r5
+ */
+ep93xx_sdram_size:
+	/* Store zero at offset zero. */
+	str	r0, [r0]
+
+	/* Start checking for an alias at 1MB into SDRAM. */
+	ldr	r1, =0x00100000
+
+	/* Store the offset at the current offset. */
+check_block_size:
+	str	r1, [r0, r1]
+
+	/* Read back from zero. */
+	ldr	r2, [r0]
+
+	/* Stop searching of an alias was found. */
+	cmp	r1, r2
+	beq	found_block_size
+
+	/* Advance to the next power of two boundary. */
+	mov	r1, r1, lsl #1
+
+	/* Loop back if the size has not reached 256MB. */
+	cmp	r1, #0x10000000
+	bne	check_block_size
+
+	/* A full 256MB of memory was found, so return it now. */
+	ldr	r0, =0x10000000
+	ldr	r1, =0x00000000
+	ldr	r2, =0x00000001
+	mov	pc, lr
+
+	/* An alias was found. See if the first block is 128MB in size. */
+found_block_size:
+	cmp	r1, #0x08000000
+
+	/* The first block is 128MB, so there is no further memory. Return it
+	 * now.
+	 */
+	ldreq	r0, =0x08000000
+	ldreq	r1, =0x00000000
+	ldreq	r2, =0x00000001
+	moveq	pc, lr
+
+	/* Save the block size, set the block address bits to zero, and
+	 * initialize the block count to one.
+	 */
+	mov	r3, r1
+	ldr	r4, =0x00000000
+	ldr	r5, =0x00000001
+
+	/* Look for additional blocks of memory by searching for non-aliases. */
+find_blocks:
+	/* Store zero back to address zero. It may be overwritten. */
+	str	r0, [r0]
+
+	/* Advance to the next power of two boundary. */
+	mov	r1, r1, lsl #1
+
+	/* Store the offset at the current offset. */
+	str	r1, [r0, r1]
+
+	/* Read back from zero. */
+	ldr	r2, [r0]
+
+	/* See if a non-alias was found. */
+	cmp	r1, r2
+
+	/* If a non-alias was found, then or in the block address bit and
+	 * multiply the block count by two (since there are two unique
+	 * blocks, one with this bit zero and one with it one).
+	 */
+	orrne	r4, r4, r1
+	movne	r5, r5, lsl #1
+
+	/* Continue searching if there are more address bits to check. */
+	cmp	r1, #0x08000000
+	bne	find_blocks
+
+	/* Return the block size, address mask, and count. */
+	mov	r0, r3
+	mov	r1, r4
+	mov	r2, r5
+
+	/* Return to the caller. */
+	mov	pc, lr
+
+
+.globl lowlevel_init
+lowlevel_init:
+
+	mov	r6, lr
+
+	/* Make sure caches are off and invalidated. */
+	ldr	r0, =0x00000000
+	mcr	p15, 0, r0, c1, c0, 0
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* Turn off the green LED and turn on the red LED. If the red LED
+	 * is left on for too long, the external reset circuit described
+	 * by application note AN258 will cause the system to reset.
+	 */
+	ldr	r1, =EP93XX_LED_DATA
+	ldr	r0, [r1]
+	bic	r0, r0, #EP93XX_LED_GREEN_ON
+	orr	r0, r0, #EP93XX_LED_RED_ON
+	str	r0, [r1]
+
+	/* Undo the silly static memory controller programming performed
+	 * by the boot rom.
+	 */
+	ldr	r0, =SMC_BASE
+
+	/* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
+	ldr	r1, =0x0000fbe0
+
+	/* Reset EP93XX_OFF_SMCBCR0 */
+	ldr	r2, [r0]
+	orr	r2, r2, r1
+	str	r2, [r0]
+
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR1]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR1]
+
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR2]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR2]
+
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR3]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR3]
+
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR6]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR6]
+
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR7]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR7]
+
+	/* Set the PLL1 and processor clock. */
+	ldr	r0, =SYSCON_BASE
+#ifdef CONFIG_EDB9301
+	/* 332MHz, giving a 166MHz processor clock. */
+	ldr	r1, = 0x02b49907
+#else
+
+#ifdef CONFIG_EDB93XX_INDUSTRIAL
+	/* 384MHz, giving a 196MHz processor clock. */
+	ldr	r1, =0x02a4bb38
+#else
+	/* 400MHz, giving a 200MHz processor clock. */
+	ldr	r1, =0x02a4e39e
+#endif
+#endif
+	str	r1, [r0, #SYSCON_OFF_CLKSET1]
+
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* Need to make sure that SDRAM is configured correctly before
+	 * coping the code into it.
+	 */
+
+#ifdef CONFIG_EDB93XX_SDCS0
+	mov	r11, #SDRAM_DEVCFG0_BASE
+#endif
+#ifdef CONFIG_EDB93XX_SDCS1
+	mov	r11, #SDRAM_DEVCFG1_BASE
+#endif
+#ifdef CONFIG_EDB93XX_SDCS2
+	mov	r11, #SDRAM_DEVCFG2_BASE
+#endif
+#ifdef CONFIG_EDB93XX_SDCS3
+	ldr	r0, =SYSCON_BASE
+	ldr	r0, [r0, #SYSCON_OFF_SYSCFG]
+	ands	r0, r0, #SYSCON_SYSCFG_LASDO
+	moveq	r11, #SDRAM_DEVCFG3_ASD0_BASE
+	movne	r11, #SDRAM_DEVCFG3_ASD1_BASE
+#endif
+	/* See Table 13-5 in EP93xx datasheet for more info about DRAM
+	 * register mapping */
+
+	/* Try a 32-bit wide configuration of SDRAM. */
+	ldr	r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
+			EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
+			EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
+			EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
+
+	/* Set burst count: 4 and CAS: 2
+	 * Burst mode [A11:A10]; CAS [A16:A14]
+	 */
+	orr	r2, r11, #0x00008800
+	bl	ep93xx_sdram_config
+
+	/* Test the SDRAM. */
+	mov	r0, r11
+	bl	ep93xx_sdram_test
+	cmp	r0, #0x00000000
+	beq	ep93xx_sdram_done
+
+	/* Try a 16-bit wide configuration of SDRAM. */
+	ldr	r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
+			EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
+			EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
+			EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
+			EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
+
+	/* Set burst count: 8, CAS: 2, sequential burst
+	 * Accoring to Table 13-3 for 16bit operations mapping must be shifted.
+	 * Burst mode [A10:A9]; CAS [A15:A13]
+	 */
+	orr	r2, r11, #0x00004600
+	bl	ep93xx_sdram_config
+
+	/* Test the SDRAM. */
+	mov	r0, r11
+	bl	ep93xx_sdram_test
+	cmp	r0, #0x00000000
+	beq	ep93xx_sdram_done
+
+	/* Turn off the red LED. */
+	ldr	r0, =EP93XX_LED_DATA
+	ldr	r1, [r0]
+	bic	r1, r1, #EP93XX_LED_RED_ON
+	str	r1, [r0]
+
+	/* There is no SDRAM so flash the green LED. */
+flash_green:
+	orr	r1, r1, #EP93XX_LED_GREEN_ON
+	str	r1, [r0]
+	ldr	r2, =0x00010000
+flash_green_delay_1:
+	subs	r2, r2, #1
+	bne	flash_green_delay_1
+	bic	r1, r1, #EP93XX_LED_GREEN_ON
+	str	r1, [r0]
+	ldr	r2, =0x00010000
+flash_green_delay_2:
+	subs	r2, r2, #1
+	bne	flash_green_delay_2
+	orr	r1, r1, #EP93XX_LED_GREEN_ON
+	str	r1, [r0]
+	ldr	r2, =0x00010000
+flash_green_delay_3:
+	subs	r2, r2, #1
+	bne	flash_green_delay_3
+	bic	r1, r1, #EP93XX_LED_GREEN_ON
+	str	r1, [r0]
+	ldr	r2, =0x00050000
+flash_green_delay_4:
+	subs	r2, r2, #1
+	bne	flash_green_delay_4
+	b	flash_green
+
+
+ep93xx_sdram_done:
+	ldr	r1, =EP93XX_LED_DATA
+	ldr	r0, [r1]
+	bic	r0, r0, #EP93XX_LED_RED_ON
+	str	r0, [r1]
+
+	/* Determine the size of the SDRAM. */
+	mov	r0, r11
+	bl	ep93xx_sdram_size
+
+	/* Save the SDRAM characteristics. */
+	mov	r8, r0
+	mov	r9, r1
+	mov	r10, r2
+
+	/* Compute total memory size into r1 */
+	mul	r1, r8, r10
+#ifdef CONFIG_EDB93XX_SDCS0
+	ldr	r2, [r0, #SDRAM_OFF_DEVCFG0]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS1
+	ldr	r2, [r0, #SDRAM_OFF_DEVCFG1]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS2
+	ldr	r2, [r0, #SDRAM_OFF_DEVCFG2]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS3
+	ldr	r2, [r0, #SDRAM_OFF_DEVCFG3]
+#endif
+
+	/* Consider small DRAM size as:
+	 * < 32Mb for 32bit bus
+	 * < 64Mb for 16bit bus
+	 */
+	tst	r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
+	moveq	r1, r1, lsr #1
+	cmp	r1, #0x02000000
+
+#if defined(CONFIG_EDB9301)
+	/* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
+	movlt	r1, #0x03f0
+	movge	r1, #0x01e0
+#else
+	/* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
+	movlt	r1, #0x0600
+	movge	r1, #0x2f0
+#endif
+	str	r1, [r0, #SDRAM_OFF_REFRSHTIMR]
+
+	/* Save the memory configuration information. */
+	orr	r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE
+	stmia	r0, {r8-r11}
+
+	mov	lr, r6
+	mov	pc, lr

arch/arm/cpu/arm920t/ep93xx/speed.c

@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Cirrus Logic EP93xx PLL support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <div64.h>
+
+/*
+ * get_board_sys_clk() should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+
+/*
+ * return the PLL output frequency
+ *
+ * PLL rate = get_board_sys_clk() * (X1FBD + 1) * (X2FBD + 1)
+ * / (X2IPD + 1) / 2^PS
+ */
+static ulong get_PLLCLK(uint32_t *pllreg)
+{
+	uint8_t i;
+	const uint32_t clkset = readl(pllreg);
+	uint64_t rate = get_board_sys_clk();
+	rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
+	rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
+	do_div(rate, (clkset  & 0x1f) + 1);			/* X2IPD */
+	for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
+		rate >>= 1;
+
+	return (ulong)rate;
+}
+
+/* return FCLK frequency */
+ulong get_FCLK(void)
+{
+	const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t fclk_div =
+		fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
+	const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
+
+	return fclk_rate;
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+	const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t hclk_div =
+		hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
+	const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
+
+	return hclk_rate;
+}
+
+/* return PCLK frequency */
+ulong get_PCLK(void)
+{
+	const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t pclk_div =
+		pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
+	const ulong pclk_rate = get_HCLK() / pclk_div;
+
+	return pclk_rate;
+}
+
+/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+	ulong uclk_rate;
+
+	const uint32_t value = readl(&syscon->pwrcnt);
+	if (value & SYSCON_PWRCNT_UART_BAUD)
+		uclk_rate = get_board_sys_clk();
+	else
+		uclk_rate = get_board_sys_clk() / 2;
+
+	return uclk_rate;
+}

arch/arm/cpu/arm920t/ep93xx/timer.c

@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Cirrus Logic EP93xx timer support.
+ *
+ * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
+ * author unknown.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <time.h>
+#include <linux/delay.h>
+#include <linux/types.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <div64.h>
+
+#define TIMER_CLKSEL	(1 << 3)
+#define TIMER_ENABLE	(1 << 7)
+
+#define TIMER_FREQ			508469		/* ticks / second */
+#define TIMER_MAX_VAL			0xFFFFFFFF
+
+static struct ep93xx_timer
+{
+	unsigned long long ticks;
+	unsigned long last_read;
+} timer;
+
+static inline unsigned long long usecs_to_ticks(unsigned long usecs)
+{
+	unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
+	do_div(ticks, 1000 * 1000);
+
+	return ticks;
+}
+
+static inline void read_timer(void)
+{
+	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
+	const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
+
+	if (now >= timer.last_read)
+		timer.ticks += now - timer.last_read;
+	else
+		/* an overflow occurred */
+		timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
+
+	timer.last_read = now;
+}
+
+/*
+ * Get the number of ticks (in CONFIG_SYS_HZ resolution)
+ */
+unsigned long long get_ticks(void)
+{
+	unsigned long long sys_ticks;
+
+	read_timer();
+
+	sys_ticks = timer.ticks * CONFIG_SYS_HZ;
+	do_div(sys_ticks, TIMER_FREQ);
+
+	return sys_ticks;
+}
+
+unsigned long get_timer(unsigned long base)
+{
+	return get_ticks() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long target;
+
+	read_timer();
+
+	target = timer.ticks + usecs_to_ticks(usec);
+
+	while (timer.ticks < target)
+		read_timer();
+}
+
+int timer_init(void)
+{
+	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
+
+	/* use timer 3 with 508KHz and free running, not enabled now */
+	writel(TIMER_CLKSEL, &timer_regs->timer3.control);
+
+	/* set initial timer value */
+	writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
+
+	/* Enable the timer */
+	writel(TIMER_ENABLE | TIMER_CLKSEL,
+		&timer_regs->timer3.control);
+
+	/* Reset the timer */
+	read_timer();
+	timer.ticks = 0;
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}

arch/arm/cpu/arm926ejs/mxs/Makefile

@@ -60,14 +60,14 @@ spl/u-boot-spl.ivt: spl/u-boot-spl.bin
 
 u-boot.ivt: u-boot.bin
 	$(call if_changed,mkalign_mxs)
-	$(call if_changed,mkivt_mxs,$(CONFIG_TEXT_BASE),\
+	$(call if_changed,mkivt_mxs,$(CONFIG_SYS_TEXT_BASE),\
 		0x40001000,0x40001040)
 
 spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf
 	$(call if_changed,mkcsfreq_mxs,$(CONFIG_SPL_TEXT_BASE),0x8000)
 
 u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf
-	$(call if_changed,mkcsfreq_mxs,$(CONFIG_TEXT_BASE),0x40001000)
+	$(call if_changed,mkcsfreq_mxs,$(CONFIG_SYS_TEXT_BASE),0x40001000)
 
 %.sig: %.csf
 	$(call if_changed,mkcst_mxs)

arch/arm/cpu/arm926ejs/mxs/start.S

@@ -21,7 +21,6 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <common.h>
-#include <system-constants.h>
 
 /*
  *************************************************************************
@@ -45,7 +44,7 @@ reset:
 	 * it point to the end of OCRAM if the SP is zero.
 	 */
 	cmp	sp, #0x00000000
-	ldreq	sp, =SYS_INIT_SP_ADDR
+	ldreq	sp, =CONFIG_SYS_INIT_SP_ADDR
 
 	/*
 	 * Store all registers on old stack pointer, this will allow us later to

arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds

@@ -29,8 +29,8 @@ SECTIONS
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 
 	. = ALIGN(4);
-	__u_boot_list : {
-		KEEP(*(SORT(__u_boot_list*)));
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
 	} > .sram
 
 	. = ALIGN(4);

arch/arm/cpu/armv7/Kconfig

@@ -75,8 +75,7 @@ config ARMV7_PSCI
 choice
 	prompt "Supported PSCI version"
 	depends on ARMV7_PSCI
-	default ARMV7_PSCI_1_1 if MACH_SUN8I_A33 || MACH_SUN8I_H3
-	default ARMV7_PSCI_0_1 if ARCH_SUNXI
+	default ARMV7_PSCI_1_1 if ARCH_SUNXI
 	default ARMV7_PSCI_1_0
 	help
 	  Select the supported PSCI version.

arch/arm/cpu/armv7/lowlevel_init.S

@@ -13,7 +13,6 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <linux/linkage.h>
-#include <system-constants.h>
 
 .pushsection .text.s_init, "ax"
 WEAK(s_init)
@@ -29,7 +28,7 @@ WEAK(lowlevel_init)
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
 	ldr	sp, =CONFIG_SPL_STACK
 #else
-	ldr	sp, =SYS_INIT_SP_ADDR
+	ldr	sp, =CONFIG_SYS_INIT_SP_ADDR
 #endif
 	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
 #ifdef CONFIG_SPL_DM

arch/arm/cpu/armv7/ls102xa/Kconfig

@@ -3,17 +3,16 @@ config ARCH_LS1021A
 	select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
 	select SYS_FSL_DDR_BE if SYS_FSL_DDR
 	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
-	select SYS_FSL_IFC_BE
 	select SYS_FSL_ERRATUM_A008378
 	select SYS_FSL_ERRATUM_A008407
 	select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
 	select SYS_FSL_ERRATUM_A008997 if USB
+	select SYS_FSL_ERRATUM_A009007 if USB
 	select SYS_FSL_ERRATUM_A009008 if USB
 	select SYS_FSL_ERRATUM_A009663
 	select SYS_FSL_ERRATUM_A009798 if USB
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A010315
-	select SYS_FSL_ESDHC_BE
 	select SYS_FSL_HAS_CCI400
 	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
 	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
@@ -43,6 +42,12 @@ config MAX_CPUS
 	  cores, count the reserved ports. This will allocate enough memory
 	  in spin table to properly handle all cores.
 
+config NXP_ESBC
+	bool	"NXP_ESBC"
+	help
+		Enable Freescale Secure Boot feature. Normally selected
+		by defconfig. If unsure, do not change.
+
 config SYS_CCI400_OFFSET
 	hex "Offset for CCI400 base"
 	depends on SYS_FSL_HAS_CCI400

arch/arm/cpu/armv7/ls102xa/clock.c

@@ -13,6 +13,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS      2
+#endif
+
 void get_sys_info(struct sys_info *sys_info)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);

arch/arm/cpu/armv7/ls102xa/cpu.c

@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -21,7 +20,6 @@
 #include <config.h>
 #include <fsl_wdog.h>
 #include <linux/delay.h>
-#include <dm.h>
 
 #include "fsl_epu.h"
 
@@ -399,19 +397,3 @@ void arch_preboot_os(void)
 	ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
 	asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
 }
-
-#ifdef CONFIG_ARCH_MISC_INIT
-int arch_misc_init(void)
-{
-	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
-		struct udevice *dev;
-		int ret;
-
-		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
-		if (ret)
-			printf("Failed to initialize caam_jr: %d\n", ret);
-	}
-
-	return 0;
-}
-#endif

arch/arm/cpu/armv7/ls102xa/fdt.c

@@ -146,9 +146,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	 * Since second uboot binary has a head, that space need to be
 	 * reserved either(assuming its size is less than 0x1000).
 	 */
-	off = fdt_add_mem_rsv(blob, CONFIG_TEXT_BASE - UBOOT_HEAD_LEN,
-			      CONFIG_SYS_MONITOR_LEN +
-			      CONFIG_SYS_SPL_MALLOC_SIZE + UBOOT_HEAD_LEN);
+	off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
+			CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
+			UBOOT_HEAD_LEN);
 	if (off < 0)
 		printf("Failed to reserve memory for SD boot deep sleep: %s\n",
 		       fdt_strerror(off));

arch/arm/cpu/armv7/ls102xa/psci.S

@@ -36,7 +36,7 @@
 
 	.align	5
 
-#define	ONE_MS		(CONFIG_COUNTER_FREQUENCY / 1000)
+#define	ONE_MS		(COUNTER_FREQUENCY / 1000)
 #define	RESET_WAIT	(30 * ONE_MS)
 
 .globl	psci_version

arch/arm/cpu/armv7/ls102xa/timer.c

@@ -65,7 +65,7 @@ int timer_init(void)
 	/* Enable System Counter */
 	writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);
 
-	freq = CONFIG_COUNTER_FREQUENCY;
+	freq = COUNTER_FREQUENCY;
 	asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
 
 	/* Set PL1 Physical Timer Ctrl */

arch/arm/cpu/armv7/nonsec_virt.S

@@ -189,11 +189,11 @@ ENTRY(_nonsec_init)
  * we do this here instead.
  * But first check if we have the generic timer.
  */
-#if CONFIG_COUNTER_FREQUENCY
+#ifdef COUNTER_FREQUENCY
 	mrc	p15, 0, r0, c0, c1, 1		@ read ID_PFR1
 	and	r0, r0, #CPUID_ARM_GENTIMER_MASK	@ mask arch timer bits
 	cmp	r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
-	ldreq	r1, =CONFIG_COUNTER_FREQUENCY
+	ldreq	r1, =COUNTER_FREQUENCY
 	mcreq	p15, 0, r1, c14, c0, 0		@ write CNTFRQ
 #endif
 

arch/arm/cpu/armv7/s5p-common/Makefile

@@ -3,13 +3,14 @@
 # Copyright (C) 2009 Samsung Electronics
 # Minkyu Kang <mk7.kang@samsung.com>
 
-obj-$(CONFIG_PWM_S5P) += pwm.o
 ifdef CONFIG_ARCH_NEXELL
+obj-$(CONFIG_PWM_NX) += pwm.o
 obj-$(CONFIG_S5P4418_ONEWIRE) += pwm.o
 else
 obj-y += cpu_info.o
 ifndef CONFIG_SPL_BUILD
 obj-y += timer.o
 obj-y += sromc.o
+obj-$(CONFIG_PWM) += pwm.o
 endif
 endif

arch/arm/cpu/armv7/s5p-common/cpu_info.c

@@ -4,7 +4,6 @@
  * Minkyu Kang <mk7.kang@samsung.com>
  */
 #include <common.h>
-#include <display_options.h>
 #include <fdtdec.h>
 #include <init.h>
 #include <asm/global_data.h>

arch/arm/cpu/armv7/start.S

@@ -17,7 +17,6 @@
 #include <asm/system.h>
 #include <linux/linkage.h>
 #include <asm/armv7.h>
-#include <system-constants.h>
 
 /*************************************************************************
  *
@@ -98,10 +97,12 @@ switch_to_hypervisor_ret:
 	orr	r0, r0, #0xc0		@ disable FIQ and IRQ
 	msr	cpsr,r0
 
-#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE)
 /*
  * Setup vector:
+ * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
+ * Continue to use ROM code vector only in OMAP4 spl)
  */
+#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
 	/* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
 	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTLR Register
 	bic	r0, #CR_V		@ V = 0
@@ -255,7 +256,7 @@ ENTRY(cpu_init_cp15)
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
 	ldr	r0, =(CONFIG_SPL_STACK)
 #else
-	ldr	r0, =(SYS_INIT_SP_ADDR)
+	ldr	r0, =(CONFIG_SYS_INIT_SP_ADDR)
 #endif
 	bic	r0, r0, #7	/* 8-byte alignment for ABI compliance */
 	mov	sp, r0

arch/arm/cpu/armv7/stv0991/lowlevel.S

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * (C) Copyright 2014 STMicroelectronics
+ * (C) Copyright 2014 stmicroelectronics
  */
 
 #include <config.h>

arch/arm/cpu/armv7/sunxi/Makefile

@@ -13,7 +13,7 @@ obj-$(CONFIG_MACH_SUN6I)	+= sram.o
 obj-$(CONFIG_MACH_SUN8I)	+= sram.o
 
 ifndef CONFIG_SPL_BUILD
-ifneq ($(CONFIG_MACH_SUN8I_A33)$(CONFIG_MACH_SUN8I_H3),)
+ifdef CONFIG_MACH_SUN8I_H3
 obj-$(CONFIG_ARMV7_PSCI)	+= psci-scpi.o
 else
 obj-$(CONFIG_ARMV7_PSCI)	+= psci.o

arch/arm/cpu/armv7/sunxi/psci-scpi.c

@@ -24,11 +24,7 @@
 #define MPIDR_AFFLVL0(mpidr)	(mpidr & 0xf)
 #define MPIDR_AFFLVL1(mpidr)	(mpidr >> 8 & 0xf)
 
-#if defined(CONFIG_MACH_SUN8I_H3)
 #define SCPI_SHMEM_BASE		0x0004be00
-#else
-#define SCPI_SHMEM_BASE		0x00053e00
-#endif
 #define SCPI_SHMEM		((struct scpi_shmem *)SCPI_SHMEM_BASE)
 
 #define SCPI_RX_CHANNEL		1
@@ -402,12 +398,12 @@ static void __secure sunxi_set_entry_address(void *entry)
 
 	writel((u32)entry, &cpucfg->priv0);
 
-#ifdef CONFIG_MACH_SUN8I_H3
-	/* Redirect CPU 0 to the secure monitor via the resume shim. */
-	writel(0x16aaefe8, &cpucfg->super_standy_flag);
-	writel(0xaa16efe8, &cpucfg->super_standy_flag);
-	writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
-#endif
+	if (IS_ENABLED(CONFIG_MACH_SUN8I_H3)) {
+		/* Redirect CPU 0 to the secure monitor via the resume shim. */
+		writel(0x16aaefe8, &cpucfg->super_standy_flag);
+		writel(0xaa16efe8, &cpucfg->super_standy_flag);
+		writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
+	}
 }
 #endif
 

arch/arm/cpu/armv7/sunxi/psci.c

@@ -67,7 +67,7 @@ static u32 __secure cp15_read_cntp_ctl(void)
 	return val;
 }
 
-#define ONE_MS (CONFIG_COUNTER_FREQUENCY / 1000)
+#define ONE_MS (COUNTER_FREQUENCY / 1000)
 
 static void __secure __mdelay(u32 ms)
 {
@@ -170,7 +170,7 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)
 
 	sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu),
 			   (void *)cpucfg + SUN8I_R40_PWROFF,
-			   on, cpu);
+			   on, 0);
 }
 #else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
 static void __secure sunxi_cpu_set_power(int cpu, bool on)

arch/arm/cpu/armv7/sunxi/u-boot-spl.lds

@@ -38,8 +38,8 @@ SECTIONS
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 
 	. = ALIGN(4);
-	__u_boot_list : {
-		KEEP(*(SORT(__u_boot_list*)));
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
 	} > .sram
 
 	. = ALIGN(4);

arch/arm/cpu/armv8/Kconfig

@@ -76,7 +76,6 @@ config ARMV8_SEC_FIRMWARE_SUPPORT
 
 config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
 	bool "Enable ARMv8 secure monitor firmware framework support for SPL"
-	depends on SPL
 	select SPL_FIT
 	select SPL_OF_LIBFDT
 	help
@@ -84,7 +83,6 @@ config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
 
 config SPL_RECOVER_DATA_SECTION
 	bool "save/restore SPL data section"
-	depends on SPL
 	help
 	  Say Y here to save SPL data section for cold boot, and restore
 	  at warm boot in SPL phase.
@@ -92,7 +90,6 @@ config SPL_RECOVER_DATA_SECTION
 config SEC_FIRMWARE_ARMV8_PSCI
 	bool "PSCI implementation in secure monitor firmware"
 	depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
-	depends on ARMV8_PSCI=n
 	help
 	  This config enables the ARMv8 PSCI implementation in secure monitor
 	  firmware. This is a private PSCI implementation and different from
@@ -134,9 +131,6 @@ config PSCI_RESET
 
 	  Select Y here to make use of PSCI calls for system reset
 
-config SYS_HAS_ARMV8_SECURE_BASE
-	bool
-
 config ARMV8_PSCI
 	bool "Enable PSCI support" if EXPERT
 	help
@@ -164,41 +158,22 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER
 	  A value 0 or no definition of it works for single cluster system.
 	  System with multi-cluster should difine their own exact value.
 
-config ARMV8_PSCI_RELOCATE
-	bool "Relocate PSCI code"
-	depends on ARMV8_PSCI
-	depends on SYS_HAS_ARMV8_SECURE_BASE
-	help
-	  Relocate PSCI code, for example to a secure memory on the SoC. If not
-	  set, the PSCI sections are placed together with the u-boot and the
-	  regions will be marked as reserved before linux is started.
-
-config ARMV8_SECURE_BASE
-	hex "Secure address for PSCI image"
-	depends on ARMV8_PSCI_RELOCATE
-	default 0x18000000 if ARCH_LS1028A
-	help
-	  Address for placing the PSCI text, data and stack sections.
-
-
 config ARMV8_EA_EL3_FIRST
 	bool "External aborts and SError interrupt exception are taken in EL3"
 	help
 	  Exception handling at all exception levels for External Abort and
 	  SError interrupt exception are taken in EL3.
 
-menuconfig ARMV8_CRYPTO
-	bool "ARM64 Accelerated Cryptographic Algorithms"
+if SYS_HAS_ARMV8_SECURE_BASE
 
-if ARMV8_CRYPTO
-
-config ARMV8_CE_SHA1
-	bool "SHA-1 digest algorithm (ARMv8 Crypto Extensions)"
-	default y if SHA1
-
-config ARMV8_CE_SHA256
-	bool "SHA-256 digest algorithm (ARMv8 Crypto Extensions)"
-	default y if SHA256
+config ARMV8_SECURE_BASE
+	hex "Secure address for PSCI image"
+	depends on ARMV8_PSCI
+	help
+	  Address for placing the PSCI text, data and stack sections.
+	  If not defined, the PSCI sections are placed together with the u-boot
+	  but platform can choose to place PSCI code image separately in other
+	  places such as some secure RAM built-in SOC etc.
 
 endif
 

arch/arm/cpu/armv8/Makefile

@@ -44,5 +44,3 @@ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
 obj-$(CONFIG_ARMV8_PSCI) += psci.o
 obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
 obj-$(CONFIG_XEN) += xen/
-obj-$(CONFIG_ARMV8_CE_SHA1) += sha1_ce_glue.o sha1_ce_core.o
-obj-$(CONFIG_ARMV8_CE_SHA256) += sha256_ce_glue.o sha256_ce_core.o

arch/arm/cpu/armv8/cache_v8.c

@@ -39,28 +39,8 @@ DECLARE_GLOBAL_DATA_PTR;
  *    off:          FFF
  */
 
-static int get_effective_el(void)
+u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
 {
-	int el = current_el();
-
-	if (el == 2) {
-		u64 hcr_el2;
-
-		/*
-		 * If we are using the EL2&0 translation regime, the TCR_EL2
-		 * looks like the EL1 version, even though we are in EL2.
-		 */
-		__asm__ ("mrs %0, HCR_EL2\n" : "=r" (hcr_el2));
-		if (hcr_el2 & BIT(HCR_EL2_E2H_BIT))
-			return 1;
-	}
-
-	return el;
-}
-
-u64 get_tcr(u64 *pips, u64 *pva_bits)
-{
-	int el = get_effective_el();
 	u64 max_addr = 0;
 	u64 ips, va_bits;
 	u64 tcr;
@@ -135,7 +115,7 @@ static u64 *find_pte(u64 addr, int level)
 
 	debug("addr=%llx level=%d\n", addr, level);
 
-	get_tcr(NULL, &va_bits);
+	get_tcr(0, NULL, &va_bits);
 	if (va_bits < 39)
 		start_level = 1;
 
@@ -363,7 +343,7 @@ __weak u64 get_page_table_size(void)
 	u64 va_bits;
 	int start_level = 0;
 
-	get_tcr(NULL, &va_bits);
+	get_tcr(0, NULL, &va_bits);
 	if (va_bits < 39)
 		start_level = 1;
 
@@ -435,7 +415,7 @@ __weak void mmu_setup(void)
 		setup_all_pgtables();
 
 	el = current_el();
-	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
+	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 			  MEMORY_ATTRIBUTES);
 
 	/* enable the mmu */
@@ -503,10 +483,6 @@ void dcache_enable(void)
 		mmu_setup();
 	}
 
-	/* Set up page tables only once (it is done also by mmu_setup()) */
-	if (!gd->arch.tlb_fillptr)
-		setup_all_pgtables();
-
 	set_sctlr(get_sctlr() | CR_C);
 }
 

arch/arm/cpu/armv8/config.mk

@@ -3,7 +3,6 @@
 # (C) Copyright 2002
 # Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
 PLATFORM_RELFLAGS += -fno-common -ffixed-x18
-PLATFORM_RELFLAGS += $(call cc-option,-mbranch-protection=none)
 
 PF_NO_UNALIGNED := $(call cc-option, -mstrict-align)
 PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED)

arch/arm/cpu/armv8/cpu-dt.c

@@ -8,9 +8,9 @@
 #include <asm/psci.h>
 #include <asm/system.h>
 #include <asm/armv8/sec_firmware.h>
-#include <linux/libfdt.h>
 
-__weak int psci_update_dt(void *fdt)
+#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT)
+int psci_update_dt(void *fdt)
 {
 	/*
 	 * If the PSCI in SEC Firmware didn't work, avoid to update the
@@ -18,10 +18,8 @@ __weak int psci_update_dt(void *fdt)
 	 * number to support detecting PSCI dynamically and then switching
 	 * the SMP boot method between PSCI and spin-table.
 	 */
-	if (CONFIG_IS_ENABLED(SEC_FIRMWARE_ARMV8_PSCI) &&
-	    sec_firmware_support_psci_version() == PSCI_INVALID_VER)
+	if (sec_firmware_support_psci_version() == PSCI_INVALID_VER)
 		return 0;
-
 	fdt_psci(fdt);
 
 #if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE)
@@ -32,3 +30,4 @@ __weak int psci_update_dt(void *fdt)
 
 	return 0;
 }
+#endif

arch/arm/cpu/armv8/cpu.c

@@ -79,9 +79,6 @@ static void relocate_secure_section(void)
 
 void armv8_setup_psci(void)
 {
-	if (current_el() != 3)
-		return;
-
 	relocate_secure_section();
 	secure_ram_addr(psci_setup_vectors)();
 	secure_ram_addr(psci_arch_init)();

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -26,7 +26,6 @@ config ARCH_LS1012A
 config ARCH_LS1028A
 	bool
 	select ARMV8_SET_SMPEN
-	select ESBC_HDR_LS if CHAIN_OF_TRUST
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
 	select GICV3
@@ -56,14 +55,13 @@ config ARCH_LS1028A
 	select SYS_FSL_ERRATUM_A011334
 	select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
 	select RESV_RAM if GIC_V3_ITS
-	select SYS_HAS_ARMV8_SECURE_BASE
 	imply PANIC_HANG
 
 config ARCH_LS1043A
 	bool
 	select ARMV8_SET_SMPEN
 	select ARM_ERRATA_855873 if !TFABOOT
-	select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI && !SD_BOOT)
+	select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
 	select FSL_LAYERSCAPE
 	select FSL_LSCH2
 	select GICV2
@@ -76,6 +74,7 @@ config ARCH_LS1043A
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008850 if !TFABOOT
 	select SYS_FSL_ERRATUM_A008997
+	select SYS_FSL_ERRATUM_A009007
 	select SYS_FSL_ERRATUM_A009008
 	select SYS_FSL_ERRATUM_A009660 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009663 if !TFABOOT
@@ -85,7 +84,6 @@ config ARCH_LS1043A
 	select SYS_FSL_ERRATUM_A010539
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_DDR4
-	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
@@ -93,14 +91,13 @@ config ARCH_LS1043A
 	select SYS_I2C_MXC_I2C2 if !DM_I2C
 	select SYS_I2C_MXC_I2C3 if !DM_I2C
 	select SYS_I2C_MXC_I2C4 if !DM_I2C
-	select SYS_HAS_ARMV8_SECURE_BASE
 	imply CMD_PCI
 	imply ID_EEPROM
 
 config ARCH_LS1046A
 	bool
 	select ARMV8_SET_SMPEN
-	select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI && !SD_BOOT)
+	select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
 	select FSL_LAYERSCAPE
 	select FSL_LSCH2
 	select GICV2
@@ -115,6 +112,7 @@ config ARCH_LS1046A
 	select SYS_FSL_ERRATUM_A008511 if !TFABOOT
 	select SYS_FSL_ERRATUM_A008850 if !TFABOOT
 	select SYS_FSL_ERRATUM_A008997
+	select SYS_FSL_ERRATUM_A009007
 	select SYS_FSL_ERRATUM_A009008
 	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A009801
@@ -124,7 +122,6 @@ config ARCH_LS1046A
 	select SYS_FSL_ERRATUM_A010539
 	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_SRDS_2
-	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
@@ -141,7 +138,6 @@ config ARCH_LS1088A
 	bool
 	select ARMV8_SET_SMPEN
 	select ARM_ERRATA_855873 if !TFABOOT
-	select ESBC_HDR_LS if CHAIN_OF_TRUST
 	select FSL_IFC
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
@@ -191,11 +187,9 @@ config ARCH_LS2080A
 	select ARM_ERRATA_828024
 	select ARM_ERRATA_829520
 	select ARM_ERRATA_833471
-	select ESBC_HDR_LS if CHAIN_OF_TRUST
 	select FSL_IFC
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
-	select SYS_FSL_OTHER_DDR_NUM_CTRLS
 	select GICV3
 	select SKIP_LOWLEVEL_INIT
 	select SYS_FSL_SRDS_1
@@ -245,7 +239,6 @@ config ARCH_LS2080A
 config ARCH_LX2162A
 	bool
 	select ARMV8_SET_SMPEN
-	select ESBC_HDR_LS if CHAIN_OF_TRUST
 	select FSL_DDR_BIST
 	select FSL_DDR_INTERACTIVE
 	select FSL_LAYERSCAPE
@@ -284,7 +277,6 @@ config ARCH_LX2162A
 config ARCH_LX2160A
 	bool
 	select ARMV8_SET_SMPEN
-	select ESBC_HDR_LS if CHAIN_OF_TRUST
 	select FSL_DDR_BIST
 	select FSL_DDR_INTERACTIVE
 	select FSL_LAYERSCAPE
@@ -326,11 +318,6 @@ config ARCH_LX2160A
 config FSL_LSCH2
 	bool
 	select SKIP_LOWLEVEL_INIT
-	select SYS_FSL_CCSR_GUR_BE
-	select SYS_FSL_CCSR_SCFG_BE
-	select SYS_FSL_ESDHC_BE
-	select SYS_FSL_IFC_BE
-	select SYS_FSL_PEX_LUT_BE
 	select SYS_FSL_HAS_CCI400
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_5
@@ -338,46 +325,16 @@ config FSL_LSCH2
 
 config FSL_LSCH3
 	select ARCH_MISC_INIT
-	select SYS_FSL_CCSR_GUR_LE
-	select SYS_FSL_CCSR_SCFG_LE
-	select SYS_FSL_ESDHC_LE
-	select SYS_FSL_IFC_LE
-	select SYS_FSL_PEX_LUT_LE
 	bool
 
 config NXP_LSCH3_2
 	bool
 
-config SYS_FSL_CCSR_GUR_BE
-	bool
-
-config SYS_FSL_CCSR_SCFG_BE
-	bool
-
-config SYS_FSL_PEX_LUT_BE
-	bool
-
-config SYS_FSL_CCSR_GUR_LE
-	bool
-
-config SYS_FSL_CCSR_SCFG_LE
-	bool
-
-config SYS_FSL_ESDHC_LE
-	bool
-
-config SYS_FSL_IFC_LE
-	bool
-
-config SYS_FSL_PEX_LUT_LE
-	bool
-
 menu "Layerscape architecture"
 	depends on FSL_LSCH2 || FSL_LSCH3
 
 config FSL_LAYERSCAPE
 	bool
-	select ARM_SMCCC
 
 config HAS_FEATURE_GIC64K_ALIGN
 	bool
@@ -498,6 +455,11 @@ config EMC2305
 	 Enable the EMC2305 fan controller for configuration of fan
 	 speed.
 
+config NXP_ESBC
+	bool "NXP_ESBC"
+	help
+		Enable Freescale Secure Boot feature
+
 config QSPI_AHB_INIT
 	bool "Init the QSPI AHB bus"
 	help
@@ -540,36 +502,6 @@ config SYS_FSL_HAS_CCN508
 
 config SYS_FSL_HAS_DP_DDR
 	bool
-	help
-	  Defines the SoC has DP-DDR used for DPAA.
-
-config DP_DDR_CTRL
-	int
-	depends on SYS_FSL_HAS_DP_DDR
-	default 2 if ARCH_LS2080A
-
-config DP_DDR_DIMM_SLOTS_PER_CTLR
-	int
-	depends on SYS_FSL_HAS_DP_DDR
-	default 1 if ARCH_LS2080A
-
-config DP_DDR_NUM_CTRLS
-	int
-	depends on SYS_FSL_HAS_DP_DDR
-	default 1 if ARCH_LS2080A
-
-config SYS_DP_DDR_BASE
-	hex
-	depends on SYS_FSL_HAS_DP_DDR
-	default 0x6000000000 if ARCH_LS2080A
-
-config SYS_DP_DDR_BASE_PHY
-	int
-	depends on SYS_FSL_HAS_DP_DDR
-	default 0 if ARCH_LS2080A
-	help
-	  DDR controller uses this value as the base address for binding.
-	  It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
 
 config SYS_FSL_SRDS_1
 	bool
@@ -743,6 +675,9 @@ config SYS_FSL_HAS_RGMII
 	bool
 	depends on SYS_FSL_EC1 || SYS_FSL_EC2
 
+config SPL_LDSCRIPT
+	default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+
 config HAS_FSL_XHCI_USB
 	bool
 	help

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017-2021 NXP
+ * Copyright 2017-2020 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  */
 
@@ -17,7 +17,6 @@
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/ptrace.h>
-#include <linux/arm-smccc.h>
 #include <linux/errno.h>
 #include <asm/system.h>
 #include <fm_eth.h>
@@ -50,7 +49,6 @@
 #endif
 #endif
 #include <linux/mii.h>
-#include <dm.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -454,7 +452,7 @@ static inline void early_mmu_setup(void)
 
 	/* point TTBR to the new table */
 	set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
-			  get_tcr(NULL, NULL) &
+			  get_tcr(el, NULL, NULL) &
 			  ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 			  MEMORY_ATTRIBUTES);
 
@@ -609,7 +607,7 @@ static inline void final_mmu_setup(void)
 	invalidate_icache_all();
 
 	/* point TTBR to the new table */
-	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
+	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 			  MEMORY_ATTRIBUTES);
 
 	set_sctlr(get_sctlr() | CR_M);
@@ -769,7 +767,7 @@ enum boot_src __get_boot_src(u32 porsr1)
 
 enum boot_src get_boot_src(void)
 {
-	struct arm_smccc_res res;
+	struct pt_regs regs;
 	u32 porsr1 = 0;
 
 #if defined(CONFIG_FSL_LSCH3)
@@ -779,9 +777,11 @@ enum boot_src get_boot_src(void)
 #endif
 
 	if (current_el() == 2) {
-		arm_smccc_smc(SIP_SVC_RCW, 0, 0, 0, 0, 0, 0, 0, &res);
-		if (!res.a0)
-			porsr1 = res.a1;
+		regs.regs[0] = SIP_SVC_RCW;
+
+		smc_call(&regs);
+		if (!regs.regs[0])
+			porsr1 = regs.regs[1];
 	}
 
 	if (current_el() == 3 || !porsr1) {
@@ -818,7 +818,7 @@ int mmc_get_env_dev(void)
 }
 #endif
 
-enum env_location arch_env_get_location(enum env_operation op, int prio)
+enum env_location env_get_location(enum env_operation op, int prio)
 {
 	enum boot_src src = get_boot_src();
 	enum env_location env_loc = ENVL_NOWHERE;
@@ -1080,9 +1080,9 @@ static void config_core_prefetch(void)
 	char *buf = NULL;
 	char buffer[HWCONFIG_BUFFER_SIZE];
 	const char *prefetch_arg = NULL;
-	struct arm_smccc_res res;
 	size_t arglen;
 	unsigned int mask;
+	struct pt_regs regs;
 
 	if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
 		buf = buffer;
@@ -1100,10 +1100,11 @@ static void config_core_prefetch(void)
 		}
 
 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
-		arm_smccc_smc(SIP_PREFETCH_DISABLE_64, mask, 0, 0, 0, 0, 0, 0,
-			      &res);
+		regs.regs[0] = SIP_PREFETCH_DISABLE_64;
+		regs.regs[1] = mask;
+		smc_call(&regs);
 
-		if (res.a0)
+		if (regs.regs[0])
 			printf("Prefetch disable config failed for mask ");
 		else
 			printf("Prefetch disable config passed for mask ");
@@ -1229,7 +1230,6 @@ int timer_init(void)
 	return 0;
 }
 
-#if !CONFIG_IS_ENABLED(SYSRESET)
 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
 
 void __efi_runtime reset_cpu(void)
@@ -1249,7 +1249,6 @@ void __efi_runtime reset_cpu(void)
 	scfg_out32(rstcr, val);
 #endif
 }
-#endif
 
 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
 
@@ -1345,20 +1344,25 @@ phys_size_t get_effective_memsize(void)
 #ifdef CONFIG_TFABOOT
 phys_size_t tfa_get_dram_size(void)
 {
-	struct arm_smccc_res res;
+	struct pt_regs regs;
+	phys_size_t dram_size = 0;
 
-	arm_smccc_smc(SMC_DRAM_BANK_INFO, -1, 0, 0, 0, 0, 0, 0, &res);
-	if (res.a0)
+	regs.regs[0] = SMC_DRAM_BANK_INFO;
+	regs.regs[1] = -1;
+
+	smc_call(&regs);
+	if (regs.regs[0])
 		return 0;
 
-	return res.a1;
+	dram_size = regs.regs[1];
+	return dram_size;
 }
 
 static int tfa_dram_init_banksize(void)
 {
 	int i = 0, ret = 0;
+	struct pt_regs regs;
 	phys_size_t dram_size = tfa_get_dram_size();
-	struct arm_smccc_res res;
 
 	debug("dram_size %llx\n", dram_size);
 
@@ -1366,15 +1370,19 @@ static int tfa_dram_init_banksize(void)
 		return -EINVAL;
 
 	do {
-		arm_smccc_smc(SMC_DRAM_BANK_INFO, i, 0, 0, 0, 0, 0, 0, &res);
-		if (res.a0) {
+		regs.regs[0] = SMC_DRAM_BANK_INFO;
+		regs.regs[1] = i;
+
+		smc_call(&regs);
+		if (regs.regs[0]) {
 			ret = -EINVAL;
 			break;
 		}
 
-		debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2);
-		gd->bd->bi_dram[i].start = res.a1;
-		gd->bd->bi_dram[i].size = res.a2;
+		debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
+		      regs.regs[2]);
+		gd->bd->bi_dram[i].start = regs.regs[1];
+		gd->bd->bi_dram[i].size = regs.regs[2];
 
 		dram_size -= gd->bd->bi_dram[i].size;
 
@@ -1644,14 +1652,6 @@ __weak int serdes_misc_init(void)
 
 int arch_misc_init(void)
 {
-	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
-		struct udevice *dev;
-		int ret;
-
-		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
-		if (ret)
-			printf("Failed to initialize caam_jr: %d\n", ret);
-	}
 	serdes_misc_init();
 
 	return 0;

arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -671,7 +671,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 			       "clock-frequency", get_qman_freq(), 1);
 #endif
 
-#ifdef CONFIG_FMAN_ENET
+#ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_firmware(blob);
 #endif
 #ifdef CONFIG_FSL_PFE

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

@@ -18,6 +18,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS      2
+#endif
+
 void get_sys_info(struct sys_info *sys_info)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -25,8 +29,8 @@ void get_sys_info(struct sys_info *sys_info)
  * mux 2 clock for LS1043A/LS1046A.
  */
 #if defined(CONFIG_SYS_DPAA_FMAN) || \
-	    defined(CONFIG_ARCH_LS1046A) || \
-	    defined(CONFIG_ARCH_LS1043A)
+	    defined(CONFIG_TARGET_LS1046ARDB) || \
+	    defined(CONFIG_TARGET_LS1043ARDB)
 	u32 rcw_tmp;
 #endif
 	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@@ -125,13 +129,13 @@ void get_sys_info(struct sys_info *sys_info)
 
 #define HWA_CGA_M2_CLK_SEL	0x00000007
 #define HWA_CGA_M2_CLK_SHIFT	0
-#if defined(CONFIG_ARCH_LS1046A) || defined(CONFIG_ARCH_LS1043A)
+#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB)
 	rcw_tmp = in_be32(&gur->rcwsr[15]);
 	switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
 	case 1:
 		sys_info->freq_cga_m2 = freq_c_pll[1];
 		break;
-#if defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_TARGET_LS1046ARDB)
 	case 2:
 		sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
 		break;
@@ -139,7 +143,7 @@ void get_sys_info(struct sys_info *sys_info)
 	case 3:
 		sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
 		break;
-#if defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_TARGET_LS1046ARDB)
 	case 6:
 		sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
 		break;

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c

@@ -147,14 +147,10 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
 	cfg >>= sd_prctl_shift;
 
 	cfg = serdes_get_number(sd, cfg);
-	if (cfg == 0) {
-		printf("SERDES%d is disabled\n", sd + 1);
-	} else {
-		printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
+	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 
-		if (!is_serdes_prtcl_valid(sd, cfg))
-			printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
-	}
+	if (!is_serdes_prtcl_valid(sd, cfg))
+		printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
 
 	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 		enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c

@@ -21,6 +21,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	6
+#endif
+
+
 void get_sys_info(struct sys_info *sys_info)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);

arch/arm/cpu/armv8/fsl-layerscape/icid.c

@@ -46,7 +46,6 @@ void set_icids(void)
 #endif
 }
 
-#ifndef CONFIG_SPL_BUILD
 int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids)
 {
 	int i, ret;
@@ -191,4 +190,3 @@ void fdt_fixup_icid(void *blob)
 	fdt_fixup_fman_icids(blob, smmu_ph);
 #endif
 }
-#endif

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2014-2015 Freescale Semiconductor
- * Copyright 2019-2022 NXP
+ * Copyright 2019 NXP
  *
  * Extracted from armv8/start.S
  */
@@ -344,7 +344,7 @@ ENTRY(fsl_ocram_clear_ecc_err)
 	ldr	x0, =DCSR_DCFG_MBEESR2
 	str	w1, [x0]
 	ret
-ENDPROC(fsl_ocram_clear_ecc_err)
+ENDPROC(fsl_ocram_init)
 #endif
 
 #ifdef CONFIG_FSL_LSCH3

arch/arm/cpu/armv8/fsl-layerscape/mp.c

@@ -302,7 +302,6 @@ int cpu_release(u32 nr, int argc, char *const argv[])
 	u64 boot_addr;
 	u64 *table = get_spin_tbl_addr();
 	int pos;
-	int ret;
 
 	boot_addr = simple_strtoull(argv[0], NULL, 16);
 
@@ -327,10 +326,16 @@ int cpu_release(u32 nr, int argc, char *const argv[])
 		asm volatile("sev");
 	} else {
 		/* Use PSCI to kick the core */
+		struct pt_regs regs;
+
 		printf("begin to kick cpu core #%d to address %llx\n",
 		       nr, boot_addr);
-		ret = invoke_psci_fn(PSCI_0_2_FN64_CPU_ON, nr, boot_addr, 0);
-		if (ret)
+		regs.regs[0] = PSCI_0_2_FN64_CPU_ON;
+		regs.regs[1] = nr;
+		regs.regs[2] = boot_addr;
+		regs.regs[3] = 0;
+		smc_call(&regs);
+		if (regs.regs[0])
 			return -1;
 	}
 

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -206,9 +206,6 @@ static void erratum_a008997(void)
 
 static void erratum_a009007(void)
 {
-	if (!IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A009007))
-		return;
-
 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
 	defined(CONFIG_ARCH_LS1012A)
 	void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
@@ -682,7 +679,7 @@ void fsl_lsch2_early_init_f(void)
 			SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
 			SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
 			SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
-			SCFG_SNPCNFGCR_SATAWRSNP | SCFG_SNPCNFGCR_EDMASNP);
+			SCFG_SNPCNFGCR_SATAWRSNP);
 #elif defined(CONFIG_ARCH_LS1012A)
 	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
 			SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |

arch/arm/cpu/armv8/fsl-layerscape/spintable.S

@@ -113,6 +113,6 @@ _dead_loop:
 	.align 3
 	.global __real_cntfrq
 __real_cntfrq:
-	.quad CONFIG_COUNTER_FREQUENCY
+	.quad COUNTER_FREQUENCY
 	/* Secondary Boot Code ends here */
 __secondary_boot_code_end:

arch/arm/cpu/armv8/fsl-layerscape/spl.c

@@ -67,24 +67,11 @@ void spl_board_init(void)
 #endif
 }
 
-void tzpc_init(void)
-{
-	/*
-	 * Mark the whole OCRAM as non-secure, otherwise DMA devices cannot
-	 * access it. This is for example necessary for MMC boot.
-	 */
-#ifdef TZPCR0SIZE_BASE
-	out_le32(TZPCR0SIZE_BASE, 0);
-#endif
-}
-
 void board_init_f(ulong dummy)
 {
 	int ret;
 
 	icache_enable();
-	tzpc_init();
-
 	/* Clear global data */
 	memset((void *)gd, 0, sizeof(gd_t));
 	if (IS_ENABLED(CONFIG_DEBUG_UART))

arch/arm/cpu/armv8/linux-kernel-image-header-vars.h

@@ -69,7 +69,7 @@
 				 (__HEAD_FLAG_PAGE_SIZE << 1) |	\
 				 (__HEAD_FLAG_PHYS_BASE << 3))
 
-#define TEXT_OFFSET (CONFIG_TEXT_BASE - \
+#define TEXT_OFFSET (CONFIG_SYS_TEXT_BASE - \
 			CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE)
 
 /*

arch/arm/cpu/armv8/sec_firmware.c

@@ -13,7 +13,6 @@
 #include <asm/global_data.h>
 #include <asm/ptrace.h>
 #include <linux/kernel.h>
-#include <linux/arm-smccc.h>
 #include <asm/io.h>
 #include <asm/system.h>
 #include <asm/types.h>
@@ -36,6 +35,9 @@ phys_addr_t sec_firmware_addr;
 #ifndef SEC_FIRMWARE_FIT_IMAGE
 #define SEC_FIRMWARE_FIT_IMAGE		"firmware"
 #endif
+#ifndef SEC_FIRMWARE_FIT_CNF_NAME
+#define SEC_FIRMWARE_FIT_CNF_NAME	"config-1"
+#endif
 #ifndef SEC_FIRMWARE_TARGET_EL
 #define SEC_FIRMWARE_TARGET_EL		2
 #endif
@@ -43,8 +45,46 @@ phys_addr_t sec_firmware_addr;
 static int sec_firmware_get_data(const void *sec_firmware_img,
 				const void **data, size_t *size)
 {
-	return fit_get_data_conf_prop(sec_firmware_img, SEC_FIRMWARE_FIT_IMAGE,
-				      data, size);
+	int conf_node_off, fw_node_off;
+	char *conf_node_name = NULL;
+	char *desc;
+	int ret;
+
+	conf_node_name = SEC_FIRMWARE_FIT_CNF_NAME;
+
+	conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
+	if (conf_node_off < 0) {
+		printf("SEC Firmware: %s: no such config\n", conf_node_name);
+		return -ENOENT;
+	}
+
+	fw_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off,
+			SEC_FIRMWARE_FIT_IMAGE);
+	if (fw_node_off < 0) {
+		printf("SEC Firmware: No '%s' in config\n",
+		       SEC_FIRMWARE_FIT_IMAGE);
+		return -ENOLINK;
+	}
+
+	/* Verify secure firmware image */
+	if (!(fit_image_verify(sec_firmware_img, fw_node_off))) {
+		printf("SEC Firmware: Bad firmware image (bad CRC)\n");
+		return -EINVAL;
+	}
+
+	if (fit_image_get_data(sec_firmware_img, fw_node_off, data, size)) {
+		printf("SEC Firmware: Can't get %s subimage data/size",
+		       SEC_FIRMWARE_FIT_IMAGE);
+		return -ENOENT;
+	}
+
+	ret = fit_get_desc(sec_firmware_img, fw_node_off, &desc);
+	if (ret)
+		printf("SEC Firmware: Can't get description\n");
+	else
+		printf("%s\n", desc);
+
+	return ret;
 }
 
 /*
@@ -83,15 +123,18 @@ static int sec_firmware_check_copy_loadable(const void *sec_firmware_img,
 {
 	phys_addr_t sec_firmware_loadable_addr = 0;
 	int conf_node_off, ld_node_off, images;
+	char *conf_node_name = NULL;
 	const void *data;
 	size_t size;
 	ulong load;
 	const char *name, *str, *type;
 	int len;
 
-	conf_node_off = fit_conf_get_node(sec_firmware_img, NULL);
+	conf_node_name = SEC_FIRMWARE_FIT_CNF_NAME;
+
+	conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
 	if (conf_node_off < 0) {
-		puts("SEC Firmware: no config\n");
+		printf("SEC Firmware: %s: no such config\n", conf_node_name);
 		return -ENOENT;
 	}
 
@@ -331,25 +374,29 @@ bool sec_firmware_support_hwrng(void)
  */
 int sec_firmware_get_random(uint8_t *rand, int bytes)
 {
-	struct arm_smccc_res res;
 	unsigned long long num;
+	struct pt_regs regs;
 	int param1;
 
 	if (!bytes || bytes > 8) {
 		printf("Max Random bytes genration supported is 8\n");
 		return -1;
 	}
+#define SIP_RNG_64 0xC200FF11
+	regs.regs[0] = SIP_RNG_64;
+
 	if (bytes <= 4)
 		param1 = 0;
 	else
 		param1 = 1;
+	regs.regs[1] = param1;
 
-#define SIP_RNG_64 0xC200FF11
-	arm_smccc_smc(SIP_RNG_64, param1, 0, 0, 0, 0, 0, 0, &res);
-	if (res.a0)
+	smc_call(&regs);
+
+	if (regs.regs[0])
 		return -1;
 
-	num = res.a1;
+	num = regs.regs[1];
 	memcpy(rand, &num, bytes);
 
 	return 0;
@@ -426,8 +473,8 @@ int fdt_fixup_kaslr(void *fdt)
 		return 0;
 	}
 
-	err = sec_firmware_get_random(rand, 8);
-	if (err < 0) {
+	ret = sec_firmware_get_random(rand, 8);
+	if (ret < 0) {
 		printf("WARNING: No random number to set kaslr-seed\n");
 		return 0;
 	}

arch/arm/cpu/armv8/sha1_ce_core.S

@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * sha1_ce_core.S - SHA-1 secure hash using ARMv8 Crypto Extensions
- *
- * Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org>
- * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-#include <asm/system.h>
-#include <asm/macro.h>
-
-	.text
-	.arch		armv8-a+crypto
-
-	k0		.req	v0
-	k1		.req	v1
-	k2		.req	v2
-	k3		.req	v3
-
-	t0		.req	v4
-	t1		.req	v5
-
-	dga		.req	q6
-	dgav		.req	v6
-	dgb		.req	s7
-	dgbv		.req	v7
-
-	dg0q		.req	q12
-	dg0s		.req	s12
-	dg0v		.req	v12
-	dg1s		.req	s13
-	dg1v		.req	v13
-	dg2s		.req	s14
-
-	.macro		add_only, op, ev, rc, s0, dg1
-	.ifc		\ev, ev
-	add		t1.4s, v\s0\().4s, \rc\().4s
-	sha1h		dg2s, dg0s
-	.ifnb		\dg1
-	sha1\op		dg0q, \dg1, t0.4s
-	.else
-	sha1\op		dg0q, dg1s, t0.4s
-	.endif
-	.else
-	.ifnb		\s0
-	add		t0.4s, v\s0\().4s, \rc\().4s
-	.endif
-	sha1h		dg1s, dg0s
-	sha1\op		dg0q, dg2s, t1.4s
-	.endif
-	.endm
-
-	.macro		add_update, op, ev, rc, s0, s1, s2, s3, dg1
-	sha1su0		v\s0\().4s, v\s1\().4s, v\s2\().4s
-	add_only	\op, \ev, \rc, \s1, \dg1
-	sha1su1		v\s0\().4s, v\s3\().4s
-	.endm
-
-	.macro		loadrc, k, val, tmp
-	movz		\tmp, :abs_g0_nc:\val
-	movk		\tmp, :abs_g1:\val
-	dup		\k, \tmp
-	.endm
-
-	/*
-	 * void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src,
-	 * 			      uint32_t blocks)
-	 */
-ENTRY(sha1_armv8_ce_process)
-	/* load round constants */
-	loadrc		k0.4s, 0x5a827999, w6
-	loadrc		k1.4s, 0x6ed9eba1, w6
-	loadrc		k2.4s, 0x8f1bbcdc, w6
-	loadrc		k3.4s, 0xca62c1d6, w6
-
-	/* load state (4+1 digest states) */
-	ld1		{dgav.4s}, [x0]
-	ldr		dgb, [x0, #16]
-
-	/* load input (64 bytes into v8->v11 16B vectors) */
-0:	ld1		{v8.4s-v11.4s}, [x1], #64
-	sub		w2, w2, #1
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-	rev32		v8.16b, v8.16b
-	rev32		v9.16b, v9.16b
-	rev32		v10.16b, v10.16b
-	rev32		v11.16b, v11.16b
-#endif
-
-1:	add		t0.4s, v8.4s, k0.4s
-	mov		dg0v.16b, dgav.16b
-
-	add_update	c, ev, k0,  8,  9, 10, 11, dgb
-	add_update	c, od, k0,  9, 10, 11,  8
-	add_update	c, ev, k0, 10, 11,  8,  9
-	add_update	c, od, k0, 11,  8,  9, 10
-	add_update	c, ev, k1,  8,  9, 10, 11
-
-	add_update	p, od, k1,  9, 10, 11,  8
-	add_update	p, ev, k1, 10, 11,  8,  9
-	add_update	p, od, k1, 11,  8,  9, 10
-	add_update	p, ev, k1,  8,  9, 10, 11
-	add_update	p, od, k2,  9, 10, 11,  8
-
-	add_update	m, ev, k2, 10, 11,  8,  9
-	add_update	m, od, k2, 11,  8,  9, 10
-	add_update	m, ev, k2,  8,  9, 10, 11
-	add_update	m, od, k2,  9, 10, 11,  8
-	add_update	m, ev, k3, 10, 11,  8,  9
-
-	add_update	p, od, k3, 11,  8,  9, 10
-	add_only	p, ev, k3,  9
-	add_only	p, od, k3, 10
-	add_only	p, ev, k3, 11
-	add_only	p, od
-
-	/* update state */
-	add		dgbv.2s, dgbv.2s, dg1v.2s
-	add		dgav.4s, dgav.4s, dg0v.4s
-
-	/* loop on next block? */
-	cbz		w2, 2f
-	b		0b
-
-	/* store new state */
-2:	st1		{dgav.4s}, [x0]
-	str		dgb, [x0, #16]
-	mov		w0, w2
-	ret
-ENDPROC(sha1_armv8_ce_process)

arch/arm/cpu/armv8/sha1_ce_glue.c

@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * sha1_ce_glue.c - SHA-1 secure hash using ARMv8 Crypto Extensions
- *
- * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
- */
-
-#include <common.h>
-#include <u-boot/sha1.h>
-
-extern void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src,
-				  uint32_t blocks);
-
-void sha1_process(sha1_context *ctx, const unsigned char *data,
-		  unsigned int blocks)
-{
-	if (!blocks)
-		return;
-
-	sha1_armv8_ce_process(ctx->state, data, blocks);
-}

arch/arm/cpu/armv8/sha256_ce_core.S

@@ -1,134 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * sha256-ce-core.S - core SHA-256 transform using v8 Crypto Extensions
- *
- * Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org>
- * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
- */
-
- #include <config.h>
- #include <linux/linkage.h>
- #include <asm/system.h>
- #include <asm/macro.h>
-
-	.text
-	.arch		armv8-a+crypto
-
-	dga		.req	q20
-	dgav		.req	v20
-	dgb		.req	q21
-	dgbv		.req	v21
-
-	t0		.req	v22
-	t1		.req	v23
-
-	dg0q		.req	q24
-	dg0v		.req	v24
-	dg1q		.req	q25
-	dg1v		.req	v25
-	dg2q		.req	q26
-	dg2v		.req	v26
-
-	.macro		add_only, ev, rc, s0
-	mov		dg2v.16b, dg0v.16b
-	.ifeq		\ev
-	add		t1.4s, v\s0\().4s, \rc\().4s
-	sha256h		dg0q, dg1q, t0.4s
-	sha256h2	dg1q, dg2q, t0.4s
-	.else
-	.ifnb		\s0
-	add		t0.4s, v\s0\().4s, \rc\().4s
-	.endif
-	sha256h		dg0q, dg1q, t1.4s
-	sha256h2	dg1q, dg2q, t1.4s
-	.endif
-	.endm
-
-	.macro		add_update, ev, rc, s0, s1, s2, s3
-	sha256su0	v\s0\().4s, v\s1\().4s
-	add_only	\ev, \rc, \s1
-	sha256su1	v\s0\().4s, v\s2\().4s, v\s3\().4s
-	.endm
-
-	/*
-	 * The SHA-256 round constants
-	 */
-	.align		4
-.Lsha2_rcon:
-	.word		0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5
-	.word		0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5
-	.word		0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3
-	.word		0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174
-	.word		0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc
-	.word		0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da
-	.word		0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7
-	.word		0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967
-	.word		0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13
-	.word		0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85
-	.word		0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3
-	.word		0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070
-	.word		0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5
-	.word		0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3
-	.word		0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208
-	.word		0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
-
-	/*
-	 * void sha256_armv8_ce_process(struct sha256_ce_state *sst,
-	 * 				uint8_t const *src, uint32_t blocks)
-	 */
-ENTRY(sha256_armv8_ce_process)
-	/* load round constants */
-	adr		x8, .Lsha2_rcon
-	ld1		{ v0.4s- v3.4s}, [x8], #64
-	ld1		{ v4.4s- v7.4s}, [x8], #64
-	ld1		{ v8.4s-v11.4s}, [x8], #64
-	ld1		{v12.4s-v15.4s}, [x8]
-
-	/* load state */
-	ldp		dga, dgb, [x0]
-
-	/* load input */
-0:	ld1		{v16.4s-v19.4s}, [x1], #64
-	sub		w2, w2, #1
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-	rev32		v16.16b, v16.16b
-	rev32		v17.16b, v17.16b
-	rev32		v18.16b, v18.16b
-	rev32		v19.16b, v19.16b
-#endif
-
-1:	add		t0.4s, v16.4s, v0.4s
-	mov		dg0v.16b, dgav.16b
-	mov		dg1v.16b, dgbv.16b
-
-	add_update	0,  v1, 16, 17, 18, 19
-	add_update	1,  v2, 17, 18, 19, 16
-	add_update	0,  v3, 18, 19, 16, 17
-	add_update	1,  v4, 19, 16, 17, 18
-
-	add_update	0,  v5, 16, 17, 18, 19
-	add_update	1,  v6, 17, 18, 19, 16
-	add_update	0,  v7, 18, 19, 16, 17
-	add_update	1,  v8, 19, 16, 17, 18
-
-	add_update	0,  v9, 16, 17, 18, 19
-	add_update	1, v10, 17, 18, 19, 16
-	add_update	0, v11, 18, 19, 16, 17
-	add_update	1, v12, 19, 16, 17, 18
-
-	add_only	0, v13, 17
-	add_only	1, v14, 18
-	add_only	0, v15, 19
-	add_only	1
-
-	/* update state */
-	add		dgav.4s, dgav.4s, dg0v.4s
-	add		dgbv.4s, dgbv.4s, dg1v.4s
-
-	/* handled all input blocks? */
-	cbnz		w2, 0b
-
-	/* store new state */
-3:	stp		dga, dgb, [x0]
-	ret
-ENDPROC(sha256_armv8_ce_process)

arch/arm/cpu/armv8/sha256_ce_glue.c

@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * sha256_ce_glue.c - SHA-256 secure hash using ARMv8 Crypto Extensions
- *
- * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
- */
-
-#include <common.h>
-#include <u-boot/sha256.h>
-
-extern void sha256_armv8_ce_process(uint32_t state[8], uint8_t const *src,
-				    uint32_t blocks);
-
-void sha256_process(sha256_context *ctx, const unsigned char *data,
-		    unsigned int blocks)
-{
-	if (!blocks)
-		return;
-
-	sha256_armv8_ce_process(ctx->state, data, blocks);
-}

arch/arm/cpu/armv8/start.S

@@ -35,7 +35,7 @@ _start:
 
 .globl	_TEXT_BASE
 _TEXT_BASE:
-	.quad	CONFIG_TEXT_BASE
+	.quad	CONFIG_SYS_TEXT_BASE
 
 /*
  * These are defined in the linker script.
@@ -125,7 +125,7 @@ pie_fixup_done:
 	msr	cptr_el3, xzr			/* Enable FP/SIMD */
 	b	0f
 2:	mrs	x1, hcr_el2
-	tbnz	x1, #HCR_EL2_E2H_BIT, 1f	/* HCR_EL2.E2H */
+	tbnz	x1, #34, 1f			/* HCR_EL2.E2H */
 	orr	x1, x1, #HCR_EL2_AMO_EL2	/* Route SErrors to EL2 */
 	msr	hcr_el2, x1
 	set_vbar vbar_el2, x0
@@ -138,9 +138,9 @@ pie_fixup_done:
 0:
 	msr	daifclr, #0x4			/* Unmask SError interrupts */
 
-#if CONFIG_COUNTER_FREQUENCY
+#ifdef COUNTER_FREQUENCY
 	branch_if_not_highest_el x0, 4f
-	ldr	x0, =CONFIG_COUNTER_FREQUENCY
+	ldr	x0, =COUNTER_FREQUENCY
 	msr	cntfrq_el0, x0			/* Initialize CNTFRQ */
 #endif
 

arch/arm/cpu/armv8/u-boot-spl.lds

@@ -23,7 +23,7 @@ SECTIONS
 {
 	.text : {
 		. = ALIGN(8);
-		__image_copy_start = .;
+		*(.__image_copy_start)
 		CPUDIR/start.o (.text*)
 		*(.text*)
 	} >.sram
@@ -46,9 +46,9 @@ SECTIONS
 	} >.sram
 #endif
 
-	__u_boot_list : {
+	.u_boot_list : {
 		. = ALIGN(8);
-		KEEP(*(SORT(__u_boot_list*)));
+		KEEP(*(SORT(.u_boot_list*)));
 	} >.sram
 
 	.image_copy_end : {

arch/arm/cpu/armv8/u-boot.lds

@@ -109,8 +109,8 @@ SECTIONS
 	. = .;
 
 	. = ALIGN(8);
-	__u_boot_list : {
-		KEEP(*(SORT(__u_boot_list*)));
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
 	}
 
 	. = ALIGN(8);

arch/arm/cpu/pxa/Makefile

@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+extra-y	= start.o
+
+obj-$(CONFIG_CPU_PXA25X)	+= pxa2xx.o
+obj-$(CONFIG_CPU_PXA27X)	+= pxa2xx.o
+
+obj-y	+= cpuinfo.o
+obj-y	+= timer.o
+obj-y	+= usb.o
+obj-y	+= relocate.o
+obj-y	+= cache.o

arch/arm/cpu/pxa/cache.c

@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Vasily Khoruzhick <anarsoul@gmail.com>
+ */
+
+#include <cpu_func.h>
+#include <asm/cache.h>
+#include <linux/types.h>
+#include <common.h>
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+void invalidate_dcache_all(void)
+{
+	/* Flush/Invalidate I cache */
+	asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0));
+	/* Flush/Invalidate D cache */
+	asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
+}
+
+void flush_dcache_all(void)
+{
+	return invalidate_dcache_all();
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+	stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+
+	while (start <= stop) {
+		asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	return invalidate_dcache_range(start, stop);
+}
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
+
+/*
+ * Stub implementations for l2 cache operations
+ */
+
+__weak void l2_cache_disable(void) {}
+
+#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+__weak void invalidate_l2_cache(void) {}
+#endif

arch/arm/cpu/pxa/config.mk

@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+
+#
+# !WARNING!
+# The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from
+# really small OneNAND memories where the mmap'd window is only 1KiB big. The
+# .text.0 contains only the bare minimum needed to load the real SPL into SRAM.
+# Add .text.0 and .text.1 into OBJFLAGS, so when the SPL is being objcopy'd,
+# they are not discarded.
+#
+
+#ifdef CONFIG_SPL_BUILD
+OBJCOPYFLAGS += -j .text.0 -j .text.1
+#endif

arch/arm/cpu/pxa/cpuinfo.c

@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PXA CPU information display
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <linux/compiler.h>
+
+#ifdef CONFIG_CPU_PXA25X
+#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
+#error "Init SP address must be set to 0xfffff800 for PXA250"
+#endif
+#endif
+
+#define	CPU_MASK_PXA_PRODID	0x000003f0
+#define	CPU_MASK_PXA_REVID	0x0000000f
+
+#define	CPU_MASK_PRODREV	(CPU_MASK_PXA_PRODID | CPU_MASK_PXA_REVID)
+
+#define	CPU_VALUE_PXA25X	0x100
+#define	CPU_VALUE_PXA27X	0x110
+
+static uint32_t pxa_get_cpuid(void)
+{
+	uint32_t cpuid;
+	asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid));
+	return cpuid;
+}
+
+int cpu_is_pxa25x(void)
+{
+	uint32_t id = pxa_get_cpuid();
+	id &= CPU_MASK_PXA_PRODID;
+	return id == CPU_VALUE_PXA25X;
+}
+
+int cpu_is_pxa27x(void)
+{
+	uint32_t id = pxa_get_cpuid();
+	id &= CPU_MASK_PXA_PRODID;
+	return id == CPU_VALUE_PXA27X;
+}
+
+int cpu_is_pxa27xm(void)
+{
+	uint32_t id = pxa_get_cpuid();
+	return ((id & CPU_MASK_PXA_PRODID) == CPU_VALUE_PXA27X) &&
+			((id & CPU_MASK_PXA_REVID) == 8);
+}
+
+uint32_t pxa_get_cpu_revision(void)
+{
+	return pxa_get_cpuid() & CPU_MASK_PRODREV;
+}
+
+#ifdef	CONFIG_DISPLAY_CPUINFO
+static const char *pxa25x_get_revision(void)
+{
+	static __maybe_unused const char * const revs_25x[] = { "A0" };
+	static __maybe_unused const char * const revs_26x[] = {
+								"A0", "B0", "B1"
+								};
+	static const char *unknown = "Unknown";
+	uint32_t id;
+
+	if (!cpu_is_pxa25x())
+		return unknown;
+
+	id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
+
+/* PXA26x is a sick special case as it can't be told apart from PXA25x :-( */
+#ifdef	CONFIG_CPU_PXA26X
+	switch (id) {
+	case 3: return revs_26x[0];
+	case 5: return revs_26x[1];
+	case 6: return revs_26x[2];
+	}
+#else
+	if (id == 6)
+		return revs_25x[0];
+#endif
+	return unknown;
+}
+
+static const char *pxa27x_get_revision(void)
+{
+	static const char *const rev[] = { "A0", "A1", "B0", "B1", "C0", "C5" };
+	static const char *unknown = "Unknown";
+	uint32_t id;
+
+	if (!cpu_is_pxa27x())
+		return unknown;
+
+	id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
+
+	if ((id == 5) || (id == 6) || (id > 8))
+		return unknown;
+
+	/* Cap the special PXA270 C5 case. */
+	if (id == 7)
+		id = 5;
+
+	/* Cap the special PXA270M A1 case. */
+	if (id == 8)
+		id = 1;
+
+	return rev[id];
+}
+
+static int print_cpuinfo_pxa2xx(void)
+{
+	if (cpu_is_pxa25x()) {
+		puts("Marvell PXA25x rev. ");
+		puts(pxa25x_get_revision());
+	} else if (cpu_is_pxa27x()) {
+		puts("Marvell PXA27x");
+		if (cpu_is_pxa27xm()) puts("M");
+		puts(" rev. ");
+		puts(pxa27x_get_revision());
+	} else
+		return -EINVAL;
+
+	puts("\n");
+
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	int ret;
+
+	puts("CPU: ");
+
+	ret = print_cpuinfo_pxa2xx();
+	if (!ret)
+		return ret;
+
+	return ret;
+}
+#endif

arch/arm/cpu/pxa/pxa2xx.c

@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <irq_func.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <command.h>
+
+/* Flush I/D-cache */
+static void cache_flush(void)
+{
+	unsigned long i = 0;
+
+	asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
+}
+
+int cleanup_before_linux(void)
+{
+	/*
+	 * This function is called just before we call Linux. It prepares
+	 * the processor for Linux by just disabling everything that can
+	 * disturb booting Linux.
+	 */
+
+	disable_interrupts();
+	icache_disable();
+	dcache_disable();
+	cache_flush();
+
+	return 0;
+}
+
+inline void writelrb(uint32_t val, uint32_t addr)
+{
+	writel(val, addr);
+	asm volatile("" : : : "memory");
+	readl(addr);
+	asm volatile("" : : : "memory");
+}
+
+void pxa2xx_dram_init(void)
+{
+	uint32_t tmp;
+	int i;
+	/*
+	 * 1) Initialize Asynchronous static memory controller
+	 */
+
+	writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
+	writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
+	writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
+	/*
+	 * 2) Initialize Card Interface
+	 */
+
+	/* MECR: Memory Expansion Card Register */
+	writelrb(CONFIG_SYS_MECR_VAL, MECR);
+	/* MCMEM0: Card Interface slot 0 timing */
+	writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
+	/* MCMEM1: Card Interface slot 1 timing */
+	writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+	writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+	writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
+	/* MCIO0: Card Interface I/O Space Timing, slot 0 */
+	writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
+	/* MCIO1: Card Interface I/O Space Timing, slot 1 */
+	writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
+
+	/*
+	 * 3) Configure Fly-By DMA register
+	 */
+
+	writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
+
+	/*
+	 * 4) Initialize Timing for Sync Memory (SDCLK0)
+	 */
+
+	/*
+	 * Before accessing MDREFR we need a valid DRI field, so we set
+	 * this to power on defaults + DRI field.
+	 */
+
+	/* Read current MDREFR config and zero out DRI */
+	tmp = readl(MDREFR) & ~0xfff;
+	/* Add user-specified DRI */
+	tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
+	/* Configure important bits */
+	tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
+	tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
+
+	/* Write MDREFR back */
+	writelrb(tmp, MDREFR);
+
+	/*
+	 * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
+	 */
+
+	/* Initialize SXCNFG register. Assert the enable bits.
+	 *
+	 * Write SXMRS to cause an MRS command to all enabled banks of
+	 * synchronous static memory. Note that SXLCR need not be written
+	 * at this time.
+	 */
+	writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
+
+	/*
+	 * 6) Initialize SDRAM
+	 */
+
+	writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
+	writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
+
+	/*
+	 * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
+	 *    but not enable each SDRAM partition pair.
+	 */
+
+	writelrb(CONFIG_SYS_MDCNFG_VAL &
+		~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
+
+	/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
+	writel(0, OSCR);
+	while (readl(OSCR) < 0x300)
+		asm volatile("" : : : "memory");
+
+	/*
+	 * 8) Trigger a number (usually 8) refresh cycles by attempting
+	 *    non-burst read or write accesses to disabled SDRAM, as commonly
+	 *    specified in the power up sequence documented in SDRAM data
+	 *    sheets. The address(es) used for this purpose must not be
+	 *    cacheable.
+	 */
+	for (i = 9; i >= 0; i--) {
+		writel(i, 0xa0000000);
+		asm volatile("" : : : "memory");
+	}
+	/*
+	 * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
+	 */
+
+	tmp = CONFIG_SYS_MDCNFG_VAL &
+		(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
+	tmp |= readl(MDCNFG);
+	writelrb(tmp, MDCNFG);
+
+	/*
+	 * 10) Write MDMRS.
+	 */
+
+	writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
+
+	/*
+	 * 11) Enable APD
+	 */
+
+	if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
+		tmp = readl(MDREFR);
+		tmp |= MDREFR_APD;
+		writelrb(tmp, MDREFR);
+	}
+}
+
+void pxa_gpio_setup(void)
+{
+	writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
+	writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
+	writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
+#if defined(CONFIG_CPU_PXA27X)
+	writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
+#endif
+
+	writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
+	writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
+	writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
+#if defined(CONFIG_CPU_PXA27X)
+	writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
+#endif
+
+	writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
+	writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
+	writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
+#if defined(CONFIG_CPU_PXA27X)
+	writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
+#endif
+
+	writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
+	writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
+	writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
+	writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
+	writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
+	writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
+#if defined(CONFIG_CPU_PXA27X)
+	writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
+	writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
+#endif
+
+	writel(CONFIG_SYS_PSSR_VAL, PSSR);
+}
+
+void pxa_interrupt_setup(void)
+{
+	writel(0, ICLR);
+	writel(0, ICMR);
+#if defined(CONFIG_CPU_PXA27X)
+	writel(0, ICLR2);
+	writel(0, ICMR2);
+#endif
+}
+
+void pxa_clock_setup(void)
+{
+	writel(CONFIG_SYS_CKEN, CKEN);
+	writel(CONFIG_SYS_CCCR, CCCR);
+	asm volatile("mcr	p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
+
+	/* enable the 32Khz oscillator for RTC and PowerManager */
+	writel(OSCC_OON, OSCC);
+	while (!(readl(OSCC) & OSCC_OOK))
+		asm volatile("" : : : "memory");
+}
+
+void pxa_wakeup(void)
+{
+	uint32_t rcsr;
+
+	rcsr = readl(RCSR);
+	writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
+
+	/* Wakeup */
+	if (rcsr & RCSR_SMR) {
+		writel(PSSR_PH, PSSR);
+		pxa2xx_dram_init();
+		icache_disable();
+		dcache_disable();
+		asm volatile("mov	pc, %0" : : "r"(readl(PSPR)));
+	}
+}
+
+int arch_cpu_init(void)
+{
+	pxa_gpio_setup();
+	pxa_wakeup();
+	pxa_interrupt_setup();
+	pxa_clock_setup();
+	return 0;
+}
+
+void i2c_clk_enable(void)
+{
+	/* Set the global I2C clock on */
+	writel(readl(CKEN) | CKEN14_I2C, CKEN);
+}
+
+void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn));
+
+void reset_cpu(void)
+{
+	uint32_t tmp;
+
+	setbits_le32(OWER, OWER_WME);
+
+	tmp = readl(OSCR);
+	tmp += 0x1000;
+	writel(tmp, OSMR3);
+	writel(MDREFR_SLFRSH, MDREFR);
+
+	for (;;)
+		;
+}
+
+void enable_caches(void)
+{
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
+	icache_enable();
+#endif
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+	dcache_enable();
+#endif
+}

arch/arm/cpu/pxa/relocate.S

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  relocate - PXA270 vector relocation
+ *
+ *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The PXA SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+	.section	.text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+	bx	lr
+
+ENDPROC(relocate_vectors)

arch/arm/cpu/pxa/start.S

@@ -0,0 +1,205 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  armboot - Startup Code for XScale CPU-core
+ *
+ *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
+ *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ *  Copyright (C) 2000	Wolfgang Denk <wd@denx.de>
+ *  Copyright (C) 2001	Alex Zuepke <azu@sysgo.de>
+ *  Copyright (C) 2001	Marius Groger <mag@sysgo.de>
+ *  Copyright (C) 2002	Alex Zupke <azu@sysgo.de>
+ *  Copyright (C) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (C) 2002	Kyle Harris <kharris@nexus-tech.net>
+ *  Copyright (C) 2003	Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
+ *  Copyright (C) 2003	Kshitij <kshitij@ti.com>
+ *  Copyright (C) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (C) 2003	Robert Schwebel <r.schwebel@pengutronix.de>
+ *  Copyright (C) 2004	Texas Instruments <r-woodruff2@ti.com>
+ *  Copyright (C) 2010	Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+	.globl	reset
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+	bl  cpu_init_crit
+#endif
+
+#ifdef	CONFIG_CPU_PXA25X
+	bl	lock_cache_for_stack
+#endif
+#ifdef	CONFIG_CPU_PXA27X
+	/*
+	 * enable clock for SRAM
+	 */
+	ldr	r0,=CKEN
+	ldr	r1,[r0]
+	orr	r1,r1,#(1 << 20)
+	str	r1,[r0]
+#endif
+	bl	_main
+
+/*------------------------------------------------------------------------------*/
+
+	.globl	c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+#ifdef CONFIG_CPU_PXA25X
+	/*
+	 * Unlock (actually, disable) the cache now that board_init_f
+	 * is done. We could do this earlier but we would need to add
+	 * a new C runtime hook, whereas c_runtime_cpu_setup already
+	 * exists.
+	 * As this routine is just a call to cpu_init_crit, let us
+	 * tail-optimize and do a simple branch here.
+	 */
+	b	cpu_init_crit
+#else
+	bx	lr
+#endif
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
+	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00003300	@ clear bits 13:12, 9:8 (--VI --RS)
+	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+	orr	r0, r0, #0x00000002	@ set bit 1 (A) Align
+	mcr	p15, 0, r0, c1, c0, 0
+
+	mov	pc, lr		/* back to my caller */
+#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */
+
+/*
+ * Enable MMU to use DCache as DRAM.
+ *
+ * This is useful on PXA25x and PXA26x in early bootstages, where there is no
+ * other possible memory available to hold stack.
+ */
+#ifdef CONFIG_CPU_PXA25X
+.macro CPWAIT reg
+	mrc	p15, 0, \reg, c2, c0, 0
+	mov	\reg, \reg
+	sub	pc, pc, #4
+.endm
+lock_cache_for_stack:
+	/* Domain access -- enable for all CPs */
+	ldr	r0, =0x0000ffff
+	mcr	p15, 0, r0, c3, c0, 0
+
+	/* Point TTBR to MMU table */
+	ldr	r0, =mmutable
+	mcr	p15, 0, r0, c2, c0, 0
+
+	/* Kick in MMU, ICache, DCache, BTB */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, #0x1b00
+	bic	r0, #0x0087
+	orr	r0, #0x1800
+	orr	r0, #0x0005
+	mcr	p15, 0, r0, c1, c0, 0
+	CPWAIT	r0
+
+	/* Unlock Icache, Dcache */
+	mcr	p15, 0, r0, c9, c1, 1
+	mcr	p15, 0, r0, c9, c2, 1
+
+	/* Flush Icache, Dcache, BTB */
+	mcr	p15, 0, r0, c7, c7, 0
+
+	/* Unlock I-TLB, D-TLB */
+	mcr	p15, 0, r0, c10, c4, 1
+	mcr	p15, 0, r0, c10, c8, 1
+
+	/* Flush TLB */
+	mcr	p15, 0, r0, c8, c7, 0
+
+	/* Allocate 4096 bytes of Dcache as RAM */
+
+	/* Drain pending loads and stores */
+	mcr	p15, 0, r0, c7, c10, 4
+
+	mov	r4, #0x00
+	mov	r5, #0x00
+	mov	r2, #0x01
+	mcr	p15, 0, r0, c9, c2, 0
+	CPWAIT	r0
+
+	/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
+	mov	r0, #128
+	ldr	r1, =0xfffff000
+
+alloc:
+	mcr	p15, 0, r1, c7, c2, 5
+	/* Drain pending loads and stores */
+	mcr	p15, 0, r0, c7, c10, 4
+	strd	r4, [r1], #8
+	strd	r4, [r1], #8
+	strd	r4, [r1], #8
+	strd	r4, [r1], #8
+	subs	r0, #0x01
+	bne	alloc
+	/* Drain pending loads and stores */
+	mcr	p15, 0, r0, c7, c10, 4
+	mov	r2, #0x00
+	mcr	p15, 0, r2, c9, c2, 0
+	CPWAIT	r0
+
+	mov	pc, lr
+
+.section .mmutable, "a"
+mmutable:
+	.align	14
+	/* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
+	.set	__base, 0
+	.rept	0xfff
+	.word	(__base << 20) | 0xc12
+	.set	__base, __base + 1
+	.endr
+
+	/* 0xfff00000 : 1:1, cached mapping */
+	.word	(0xfff << 20) | 0x1c1e
+#endif	/* CONFIG_CPU_PXA25X */

arch/arm/cpu/pxa/timer.c

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Marvell PXA2xx/3xx timer driver
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+
+int timer_init(void)
+{
+	writel(0, CONFIG_SYS_TIMER_COUNTER);
+	return 0;
+}

arch/arm/cpu/pxa/usb.c

@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2006
+ * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
+ */
+
+#include <common.h>
+#include <linux/delay.h>
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
+# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
+
+#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+#include <usb.h>
+
+int usb_cpu_init(void)
+{
+#if defined(CONFIG_CPU_MONAHANS)
+	/* Enable USB host clock. */
+	writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
+	udelay(100);
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+	/* Enable USB host clock. */
+	writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
+#endif
+
+#if defined(CONFIG_CPU_MONAHANS)
+	/* Configure Port 2 for Host (USB Client Registers) */
+	writel(0x3000c, UP2OCR);
+#endif
+
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+	mdelay(11);
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+	while (readl(UHCHR) & UHCHR_FSBIR)
+		udelay(1);
+
+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
+	writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+	writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
+#endif
+	writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
+
+	return 0;
+}
+
+int usb_cpu_stop(void)
+{
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+	udelay(11);
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+	writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
+	udelay(10);
+
+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
+	writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+	writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
+#endif
+	writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
+
+#if defined(CONFIG_CPU_MONAHANS)
+	/* Disable USB host clock. */
+	writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
+	udelay(100);
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+	/* Disable USB host clock. */
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+#endif
+
+	return 0;
+}
+
+int usb_cpu_init_fail(void)
+{
+	return usb_cpu_stop();
+}
+
+# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */

arch/arm/cpu/sa1100/Makefile

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+extra-y	= start.o
+
+obj-y	+= cpu.o
+obj-y	+= timer.o

arch/arm/cpu/sa1100/cpu.c

@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <irq_func.h>
+#include <asm/system.h>
+#include <asm/io.h>
+
+static void cache_flush(void);
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * just disable everything that can disturb booting linux
+	 */
+
+	disable_interrupts();
+
+	/* turn off I-cache */
+	icache_disable();
+	dcache_disable();
+
+	/* flush I-cache */
+	cache_flush();
+
+	return (0);
+}
+
+/* flush I/D-cache */
+static void cache_flush (void)
+{
+	unsigned long i = 0;
+
+	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+}
+
+#define RST_BASE 0x90030000
+#define RSRR	0x00
+#define RCSR	0x04
+
+__attribute__((noreturn)) void reset_cpu(void)
+{
+	/* repeat endlessly */
+	while (1) {
+		writel(0, RST_BASE + RCSR);
+		writel(1, RST_BASE + RSRR);
+	}
+}

arch/arm/cpu/sa1100/start.S

@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  armboot - Startup Code for SA1100 CPU
+ *
+ *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
+ *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ *  Copyright (C) 2000	Wolfgang Denk <wd@denx.de>
+ *  Copyright (c) 2001	Alex Züpke <azu@sysgo.de>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * relocate armboot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+
+	.globl	reset
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+	bl	cpu_init_crit
+#endif
+
+	bl	_main
+
+/*------------------------------------------------------------------------------*/
+
+	.globl	c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+	mov	pc, lr
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+
+/* Interrupt-Controller base address */
+IC_BASE:	.word	0x90050000
+#define ICMR	0x04
+
+
+/* Reset-Controller */
+RST_BASE:		.word   0x90030000
+#define RSRR	0x00
+#define RCSR	0x04
+
+
+/* PWR */
+PWR_BASE:		.word   0x90020000
+#define PSPR    0x08
+#define PPCR    0x14
+cpuspeed:		.word   CONFIG_SYS_CPUSPEED
+
+
+cpu_init_crit:
+	/*
+	 * mask all IRQs
+	 */
+	ldr	r0, IC_BASE
+	mov	r1, #0x00
+	str	r1, [r0, #ICMR]
+
+	/* set clock speed */
+	ldr	r0, PWR_BASE
+	ldr	r1, cpuspeed
+	str	r1, [r0, #PPCR]
+
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
+	/*
+	 * before relocating, we have to setup RAM timing
+	 * because memory timing is board-dependend, you will
+	 * find a lowlevel_init.S in your board directory.
+	 */
+	mov	ip,	lr
+	bl	lowlevel_init
+	mov	lr,	ip
+#endif
+
+	/*
+	 * disable MMU stuff and enable I-cache
+	 */
+	mrc	p15,0,r0,c1,c0
+	bic	r0, r0, #0x00002000	@ clear bit 13 (X)
+	bic	r0, r0, #0x0000000f	@ clear bits 3-0 (WCAM)
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) Icache
+	orr	r0, r0, #0x00000002	@ set bit 1 (A) Align
+	mcr	p15,0,r0,c1,c0
+
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	mov	pc, lr

arch/arm/cpu/sa1100/timer.c

@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ */
+
+#include <common.h>
+#include <SA-1100.h>
+#include <time.h>
+#include <linux/delay.h>
+
+static ulong get_timer_masked (void)
+{
+	return OSCR;
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked ();
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	if (usec >= 1000) {
+		tmo = usec / 1000;
+		tmo *= CONFIG_SYS_HZ;
+		tmo /= 1000;
+	} else {
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*1000);
+	}
+
+	endtime = get_timer_masked () + tmo;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}

arch/arm/cpu/u-boot-spl.lds

@@ -32,8 +32,8 @@ SECTIONS
 	}
 
 	. = ALIGN(4);
-	__u_boot_list : {
-		KEEP(*(SORT(__u_boot_list*)));
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
 	}
 
 	. = ALIGN(4);

arch/arm/cpu/u-boot.lds

@@ -15,7 +15,7 @@ ENTRY(_start)
 SECTIONS
 {
 #ifndef CONFIG_CMDLINE
-	/DISCARD/ : { *(__u_boot_list_2_cmd_*) }
+	/DISCARD/ : { *(.u_boot_list_2_cmd_*) }
 #endif
 #if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
 	/*
@@ -149,8 +149,8 @@ SECTIONS
 	. = .;
 
 	. = ALIGN(4);
-	__u_boot_list : {
-		KEEP(*(SORT(__u_boot_list*)));
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
 	}
 
 	. = ALIGN(4);

arch/arm/dts/Makefile

@@ -5,9 +5,9 @@ dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb
 dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb
 dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb
 
-dtb-$(CONFIG_TARGET_SMDKC100) += s5pc1xx-smdkc100.dtb
-dtb-$(CONFIG_TARGET_S5P_GONI) += s5pc1xx-goni.dtb
-dtb-$(CONFIG_ARCH_EXYNOS4) += exynos4210-origen.dtb \
+dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
+dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
+dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
 	exynos4210-smdkv310.dtb \
 	exynos4210-universal_c210.dtb \
 	exynos4210-trats.dtb \
@@ -19,7 +19,7 @@ dtb-$(CONFIG_TARGET_HIKEY960) += hi3660-hikey960.dtb
 
 dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb
 
-dtb-$(CONFIG_ARCH_EXYNOS5) += exynos5250-arndale.dtb \
+dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 	exynos5250-snow.dtb \
 	exynos5250-spring.dtb \
 	exynos5250-smdk5250.dtb \
@@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += \
 	kirkwood-ib62x0.dtb \
 	kirkwood-iconnect.dtb \
 	kirkwood-is2.dtb \
+	kirkwood-km_kirkwood.dtb \
 	kirkwood-lsxhl.dtb \
 	kirkwood-lschlv2.dtb \
 	kirkwood-net2big.dtb \
@@ -89,9 +90,6 @@ dtb-$(CONFIG_ROCKCHIP_PX30) += \
 dtb-$(CONFIG_ROCKCHIP_RK3036) += \
 	rk3036-sdk.dtb
 
-dtb-$(CONFIG_ROCKCHIP_RK3066) += \
-	rk3066a-mk808.dtb
-
 dtb-$(CONFIG_ROCKCHIP_RK3128) += \
 	rk3128-evb.dtb
 
@@ -136,7 +134,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
 
 dtb-$(CONFIG_ROCKCHIP_RK3399) += \
 	rk3399-evb.dtb \
-	rk3399-eaidk-610.dtb \
 	rk3399-ficus.dtb \
 	rk3399-firefly.dtb \
 	rk3399-gru-bob.dtb \
@@ -232,12 +229,12 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 	tegra210-p2571.dtb \
 	tegra210-p3450-0000.dtb
 
-ifdef CONFIG_ARMADA_32BIT
-ifdef CONFIG_ARMADA_375
-dtb-$(CONFIG_ARCH_MVEBU) +=			\
-	armada-375-db.dtb
-else
 dtb-$(CONFIG_ARCH_MVEBU) +=			\
+	armada-3720-db.dtb			\
+	armada-3720-espressobin.dtb		\
+	armada-3720-turris-mox.dtb		\
+	armada-3720-uDPU.dtb			\
+	armada-375-db.dtb			\
 	armada-385-atl-x530.dtb			\
 	armada-385-atl-x530DP.dtb		\
 	armada-385-db-88f6820-amc.dtb		\
@@ -246,6 +243,12 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-388-gp.dtb			\
 	armada-388-helios4.dtb			\
 	armada-38x-controlcenterdc.dtb		\
+	armada-7040-db-nand.dtb			\
+	armada-7040-db.dtb			\
+	armada-8040-clearfog-gt-8k.dtb		\
+	armada-8040-db.dtb			\
+	armada-8040-mcbin.dtb			\
+	armada-8040-puzzle-m801.dtb		\
 	armada-xp-crs305-1g-4s.dtb		\
 	armada-xp-crs305-1g-4s-bit.dtb		\
 	armada-xp-crs326-24g-2s.dtb		\
@@ -256,21 +259,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-xp-gp.dtb			\
 	armada-xp-maxbcm.dtb			\
 	armada-xp-synology-ds414.dtb		\
-	armada-xp-theadorable.dtb
-endif
-else
-dtb-$(CONFIG_ARCH_MVEBU) +=			\
-	armada-3720-db.dtb			\
-	armada-3720-espressobin.dtb		\
-	armada-3720-turris-mox.dtb		\
-	armada-3720-eDPU.dtb			\
-	armada-3720-uDPU.dtb			\
-	armada-7040-db-nand.dtb			\
-	armada-7040-db.dtb			\
-	armada-8040-clearfog-gt-8k.dtb		\
-	armada-8040-db.dtb			\
-	armada-8040-mcbin.dtb			\
-	armada-8040-puzzle-m801.dtb		\
+	armada-xp-theadorable.dtb		\
 	cn9130-db-A.dtb				\
 	cn9130-db-B.dtb				\
 	cn9131-db-A.dtb				\
@@ -279,7 +268,6 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	cn9132-db-B.dtb				\
 	cn9130-crb-A.dtb			\
 	cn9130-crb-B.dtb
-endif
 
 dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
 dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
@@ -351,8 +339,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-mini-qspi.dtb			\
 	zynqmp-sm-k26-revA.dtb			\
 	zynqmp-smk-k26-revA.dtb			\
-	zynqmp-sck-kr-g-revA.dtbo		\
-	zynqmp-sck-kr-g-revB.dtbo		\
 	zynqmp-sck-kv-g-revA.dtbo		\
 	zynqmp-sck-kv-g-revB.dtbo		\
 	zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb	\
@@ -383,32 +369,26 @@ dtb-$(CONFIG_ARCH_VERSAL) += \
 	versal-mini-emmc0.dtb \
 	versal-mini-emmc1.dtb \
 	xilinx-versal-virt.dtb
-dtb-$(CONFIG_ARCH_VERSAL_NET) += \
-	versal-net-mini.dtb \
-	xilinx-versal-net-virt.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
 	zynqmp-r5.dtb
 dtb-$(CONFIG_AM33XX) += \
 	am335x-baltos.dtb \
 	am335x-bone.dtb \
 	am335x-boneblack.dtb \
-	am335x-boneblack-wireless.dtb \
-	am335x-boneblue.dtb \
 	am335x-brppt1-mmc.dtb \
+	am335x-brppt1-nand.dtb \
+	am335x-brppt1-spi.dtb \
 	am335x-brxre1.dtb \
 	am335x-brsmarc1.dtb \
 	am335x-draco.dtb \
 	am335x-evm.dtb \
 	am335x-evmsk.dtb \
 	am335x-bonegreen.dtb \
-	am335x-bonegreen-wireless.dtb \
 	am335x-icev2.dtb \
 	am335x-pocketbeagle.dtb \
 	am335x-pxm50.dtb \
 	am335x-rut.dtb \
 	am335x-sancloud-bbe.dtb \
-	am335x-sancloud-bbe-lite.dtb \
-	am335x-sancloud-bbe-extended-wifi.dtb \
 	am335x-shc.dtb \
 	am335x-pdu001.dtb \
 	am335x-chiliboard.dtb \
@@ -424,14 +404,12 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
 	am437x-cm-t43.dtb
 dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb
 dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
-dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
+dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_agilex_socdk.dtb			\
 	socfpga_arria5_secu1.dtb			\
 	socfpga_arria5_socdk.dtb			\
-	socfpga_arria10_chameleonv3_270_3.dtb		\
-	socfpga_arria10_chameleonv3_480_2.dtb		\
 	socfpga_arria10_socdk_sdmmc.dtb			\
 	socfpga_cyclone5_mcvevk.dtb			\
 	socfpga_cyclone5_is1.dtb			\
@@ -514,7 +492,6 @@ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
 dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
 dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
 dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
-dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb
 
 dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
 
@@ -641,7 +618,6 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
 	sun8i-a33-et-q8-v1.6.dtb \
 	sun8i-a33-ga10h-v1.1.dtb \
 	sun8i-a33-inet-d978-rev2.dtb \
-	sun8i-a33-inet-u70b-rev1.dtb \
 	sun8i-a33-ippo-q8h-v1.2.dtb \
 	sun8i-a33-olinuxino.dtb \
 	sun8i-a33-q8-tablet.dtb \
@@ -715,8 +691,7 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
 	sun50i-h6-tanix-tx6.dtb \
 	sun50i-h6-tanix-tx6-mini.dtb
 dtb-$(CONFIG_MACH_SUN50I_H616) += \
-	sun50i-h616-orangepi-zero2.dtb \
-	sun50i-h616-x96-mate.dtb
+	sun50i-h616-orangepi-zero2.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
 	sun50i-a64-amarula-relic.dtb \
 	sun50i-a64-bananapi-m64.dtb \
@@ -740,7 +715,8 @@ dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-cubieboard4.dtb \
 	sun9i-a80-cx-a99.dtb
 
-dtb-$(CONFIG_VF610) += vf610-colibri-eval-v3.dtb \
+dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
+	vf610-colibri.dtb \
 	vf610-twr.dtb \
 	vf610-pcm052.dtb \
 	vf610-bk4r1.dtb
@@ -773,7 +749,6 @@ dtb-y += \
 	imx6dl-cubox-i-emmc-som-v15.dtb \
 	imx6dl-cubox-i-som-v15.dtb \
 	imx6dl-dhcom-pdk2.dtb \
-	imx6dl-dhcom-picoitx.dts \
 	imx6dl-gw51xx.dtb \
 	imx6dl-gw52xx.dtb \
 	imx6dl-gw53xx.dtb \
@@ -807,14 +782,12 @@ dtb-y += \
 	imx6dl-sabreauto.dtb \
 	imx6dl-sabresd.dtb \
 	imx6dl-wandboard-revd1.dtb \
-	imx6s-dhcom-drc02.dtb
 
 endif
 
 ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),)
 dtb-y += \
-	imx6q-apalis-eval.dtb \
-	imx6q-bosch-acc.dtb \
+	imx6-apalis.dtb \
 	imx6q-cm-fx6.dtb \
 	imx6q-cubox-i.dtb \
 	imx6q-cubox-i-emmc-som-v15.dtb \
@@ -890,24 +863,23 @@ dtb-$(CONFIG_MX6UL) += \
 	imx6ul-phytec-segin-ff-rdk-nand.dtb \
 	imx6ul-pico-hobbit.dtb \
 	imx6ul-pico-pi.dtb \
-	imx6ul-kontron-bl.dtb \
-	imx6ull-kontron-bl.dtb
+	imx6ul-kontron-n631x-s.dtb \
+	imx6ull-kontron-n641x-s.dtb
 
 dtb-$(CONFIG_MX6ULL) += \
 	imx6ull-14x14-evk.dtb \
-	imx6ull-colibri-emmc-eval-v3.dtb \
-	imx6ull-colibri-eval-v3.dtb \
+	imx6ull-colibri.dtb \
+	imx6ull-colibri-emmc.dtb \
 	imx6ull-myir-mys-6ulx-eval.dtb \
 	imx6ull-seeed-npi-imx6ull-dev-board.dtb \
 	imx6ull-phytec-segin-ff-rdk-emmc.dtb \
 	imx6ull-dart-6ul.dtb \
 	imx6ull-somlabs-visionsom.dtb \
-	imx6ulz-bsh-smm-m2.dtb \
 	imx6ulz-14x14-evk.dtb
 
 dtb-$(CONFIG_ARCH_MX6) += \
-	imx6q-apalis-eval.dtb \
-	imx6dl-colibri-eval-v3.dtb
+	imx6-apalis.dtb \
+	imx6-colibri.dtb
 
 dtb-$(CONFIG_O4_IMX_NANO) += \
 	o4-imx-nano.dtb
@@ -918,8 +890,8 @@ dtb-$(CONFIG_EV_IMX280_NANO_X_MB) += \
 dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
 	imx7d-sdb-qspi.dtb \
 	imx7-cm.dtb \
-	imx7d-colibri-emmc-eval-v3.dtb \
-	imx7d-colibri-eval-v3.dtb \
+	imx7-colibri-emmc.dtb \
+	imx7-colibri-rawnand.dtb \
 	imx7s-warp.dtb \
 	imx7d-meerkat96.dtb \
 	imx7d-pico-pi.dtb \
@@ -938,6 +910,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
 	imx8qm-rom7720-a1.dtb \
 	fsl-imx8qxp-ai_ml.dtb \
 	fsl-imx8qxp-colibri.dtb \
+	fsl-imx8qxp-apalis.dtb \
 	fsl-imx8qxp-mek.dtb \
 	imx8-deneb.dtb \
 	imx8-giedi.dtb
@@ -946,25 +919,19 @@ dtb-$(CONFIG_ARCH_IMX8ULP) += \
 	imx8ulp-evk.dtb
 
 dtb-$(CONFIG_ARCH_IMX8M) += \
-	imx8mm-data-modul-edm-sbc.dtb \
 	imx8mm-evk.dtb \
 	imx8mm-icore-mx8mm-ctouch2.dtb \
 	imx8mm-icore-mx8mm-edimm2.2.dtb \
-	imx8mm-kontron-bl.dtb \
-	imx8mm-kontron-bl-osm-s.dtb \
-	imx8mm-mx8menlo.dtb \
+	imx8mm-kontron-n801x-s.dtb \
+	imx8mm-kontron-n801x-s-lvds.dtb \
 	imx8mm-venice.dtb \
 	imx8mm-venice-gw71xx-0x.dtb \
 	imx8mm-venice-gw72xx-0x.dtb \
 	imx8mm-venice-gw73xx-0x.dtb \
 	imx8mm-venice-gw7901.dtb \
 	imx8mm-venice-gw7902.dtb \
-	imx8mm-venice-gw7903.dtb \
-	imx8mm-venice-gw7904.dtb \
-	imx8mm-verdin-wifi-dev.dtb \
+	imx8mm-verdin.dtb \
 	phycore-imx8mm.dtb \
-	imx8mn-bsh-smm-s2.dtb \
-	imx8mn-bsh-smm-s2pro.dtb \
 	imx8mn-ddr4-evk.dtb \
 	imx8mq-cm.dtb \
 	imx8mn-evk.dtb \
@@ -976,23 +943,14 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mn-beacon-kit.dtb \
 	imx8mq-mnt-reform2.dtb \
 	imx8mq-phanbell.dtb \
-	imx8mp-dhcom-pdk2.dtb \
 	imx8mp-evk.dtb \
-	imx8mp-icore-mx8mp-edimm2.2.dtb \
 	imx8mp-phyboard-pollux-rdk.dtb \
-	imx8mp-venice.dtb \
-	imx8mp-venice-gw74xx.dtb \
-	imx8mp-verdin-wifi-dev.dtb \
+	imx8mp-verdin.dtb \
 	imx8mq-pico-pi.dtb \
-	imx8mq-kontron-pitx-imx8m.dtb \
-	imx8mq-librem5-r4.dtb
-
-dtb-$(CONFIG_ARCH_IMX9) += \
-	imx93-11x11-evk.dtb
+	imx8mq-kontron-pitx-imx8m.dtb
 
 dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
-	imxrt1020-evk.dtb \
-	imxrt1170-evk.dtb \
+	imxrt1020-evk.dtb
 
 dtb-$(CONFIG_RCAR_GEN2) += \
 	r8a7790-lager-u-boot.dtb \
@@ -1068,8 +1026,6 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
 
 dtb-$(CONFIG_TARGET_SAM9X60EK) += sam9x60ek.dtb
 
-dtb-$(CONFIG_TARGET_SAM9X60_CURIOSITY) += at91-sam9x60_curiosity.dtb
-
 dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
 
 dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \
@@ -1094,8 +1050,6 @@ dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \
 	omap3-beagle-xm.dtb \
 	omap3-beagle.dtb
 
-dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb
-
 dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \
 	omap3-igep0020.dtb
 
@@ -1165,74 +1119,43 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
 	bcm2837-rpi-cm3-io3.dtb \
 	bcm2711-rpi-4-b.dtb
 
+dtb-$(CONFIG_ARCH_BCM63158) += \
+	bcm963158.dtb
+
+dtb-$(CONFIG_ARCH_BCM68360) += \
+	bcm968360bg.dtb
+
+dtb-$(CONFIG_ARCH_BCM6753) += \
+	bcm96753ref.dtb
+
+dtb-$(CONFIG_ARCH_BCM6858) += \
+	bcm968580xref.dtb
+
 dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
 
 dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
 
-dtb-$(CONFIG_BCM47622) += \
-	bcm947622.dtb
-dtb-$(CONFIG_BCM4908) += \
-	bcm94908.dtb
-dtb-$(CONFIG_BCM4912) += \
-	bcm94912.dtb
-dtb-$(CONFIG_BCM63138) += \
-	bcm963138.dtb
-dtb-$(CONFIG_BCM63146) += \
-	bcm963146.dtb
-dtb-$(CONFIG_BCM63148) += \
-	bcm963148.dtb
-dtb-$(CONFIG_BCM63158) += \
-	bcm963158.dtb
-dtb-$(CONFIG_BCM63178) += \
-	bcm963178.dtb
-dtb-$(CONFIG_BCM6756) += \
-	bcm96756.dtb
-dtb-$(CONFIG_BCM6813) += \
-	bcm96813.dtb
-dtb-$(CONFIG_BCM6846) += \
-	bcm96846.dtb
-dtb-$(CONFIG_BCM6855) += \
-	bcm96855.dtb \
-	bcm96753ref.dtb
-dtb-$(CONFIG_BCM6856) += \
-	bcm96856.dtb \
-	bcm968360bg.dtb
-dtb-$(CONFIG_BCM6858) += \
-	bcm96858.dtb \
-	bcm968580xref.dtb
-dtb-$(CONFIG_BCM6878) += \
-	bcm96878.dtb
-
 dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
 dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
 
 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
 
-dtb-$(CONFIG_STM32MP13x) += \
-	stm32mp135f-dk.dtb
-
 dtb-$(CONFIG_STM32MP15x) += \
 	stm32mp157a-dk1.dtb \
-	stm32mp157a-dk1-scmi.dtb \
 	stm32mp157a-icore-stm32mp1-ctouch2.dtb \
 	stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
 	stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
 	stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
 	stm32mp157c-dk2.dtb \
-	stm32mp157c-dk2-scmi.dtb \
 	stm32mp157c-ed1.dtb \
-	stm32mp157c-ed1-scmi.dtb \
 	stm32mp157c-ev1.dtb \
-	stm32mp157c-ev1-scmi.dtb \
 	stm32mp157c-odyssey.dtb \
 	stm32mp15xx-dhcom-drc02.dtb \
 	stm32mp15xx-dhcom-pdk2.dtb \
 	stm32mp15xx-dhcom-picoitx.dtb \
-	stm32mp15xx-dhcor-avenger96.dtb \
-	stm32mp15xx-dhcor-drc-compact.dtb \
-	stm32mp15xx-dhcor-testbench.dtb
+	stm32mp15xx-dhcor-avenger96.dtb
 
-dtb-$(CONFIG_SOC_K3_AM654) += \
+dtb-$(CONFIG_SOC_K3_AM6) += \
 	k3-am654-base-board.dtb \
 	k3-am654-r5-base-board.dtb \
 	k3-am65-iot2050-spl.dtb \
@@ -1253,31 +1176,17 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
 			      k3-am642-sk.dtb \
 			      k3-am642-r5-sk.dtb
 
-dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
-			      k3-am625-r5-sk.dtb
-
 dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7622-rfb.dtb \
 	mt7623a-unielec-u7623-02-emmc.dtb \
 	mt7622-bananapi-bpi-r64.dtb \
 	mt7623n-bananapi-bpi-r2.dtb \
 	mt7629-rfb.dtb \
-	mt7981-rfb.dtb \
-	mt7981-emmc-rfb.dtb \
-	mt7981-sd-rfb.dtb \
-	mt7986a-rfb.dtb \
-	mt7986b-rfb.dtb \
-	mt7986a-sd-rfb.dtb \
-	mt7986b-sd-rfb.dtb \
-	mt7986a-emmc-rfb.dtb \
-	mt7986b-emmc-rfb.dtb \
 	mt8183-pumpkin.dtb \
 	mt8512-bm1-emmc.dtb \
 	mt8516-pumpkin.dtb \
 	mt8518-ap1-emmc.dtb
 
-dtb-$(CONFIG_ARCH_NPCM7xx) += nuvoton-npcm750-evb.dtb
-dtb-$(CONFIG_ARCH_NPCM8XX) += nuvoton-npcm845-evb.dtb
 dtb-$(CONFIG_XEN) += xenguest-arm64.dtb
 
 dtb-$(CONFIG_ARCH_OCTEONTX) += octeontx.dtb
@@ -1306,8 +1215,6 @@ dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
 
 dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
 
-dtb-$(CONFIG_TARGET_GXP) += hpe-bmc-dl360gen10.dts
-
 dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb \
 					imx8mm-cl-iot-gate-ied.dtbo \
 					imx8mm-cl-iot-gate-ied-adc0.dtbo \
@@ -1334,9 +1241,6 @@ dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
 
 dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
 
-dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \
-				corstone1000-fvp.dtb
-
 include $(srctree)/scripts/Makefile.dts
 
 targets += $(dtb-y)

arch/arm/dts/am335x-bone-common.dtsi

@@ -397,9 +397,4 @@
 &rtc {
 	clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 	clock-names = "ext-clk", "int-clk";
-	system-power-controller;
-};
-
-&pruss_tm {
-	status = "okay";
 };

arch/arm/dts/am335x-boneblack-common.dtsi

@@ -3,6 +3,9 @@
  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include <dt-bindings/display/tda998x.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
 &ldo3_reg {
 	regulator-min-microvolt = <1800000>;
 	regulator-max-microvolt = <1800000>;
@@ -22,9 +25,145 @@
 	non-removable;
 };
 
+&am33xx_pinmux {
+	nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
+		pinctrl-single,pins = <
+			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+		>;
+	};
+
+	nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
+		pinctrl-single,pins = <
+			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
+		>;
+	};
+
+	mcasp0_pins: mcasp0_pins {
+		pinctrl-single,pins = <
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */
+		>;
+	};
+};
+
+&lcdc {
+	status = "okay";
+
+	/* If you want to get 24 bit RGB and 16 BGR mode instead of
+	 * current 16 bit RGB and 24 BGR modes, set the propety
+	 * below to "crossed" and uncomment the video-ports -property
+	 * in tda19988 node.
+	 */
+	blue-and-red-wiring = "straight";
+
+	port {
+		lcdc_0: endpoint@0 {
+			remote-endpoint = <&hdmi_0>;
+		};
+	};
+};
+
+&i2c0 {
+	tda19988: tda19988@70 {
+		compatible = "nxp,tda998x";
+		reg = <0x70>;
+		nxp,calib-gpios = <&gpio1 25 0>;
+		interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>;
+
+		pinctrl-names = "default", "off";
+		pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
+		pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
+
+		/* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */
+		/* video-ports = <0x234501>; */
+
+		#sound-dai-cells = <0>;
+		audio-ports = <	TDA998x_I2S	0x03>;
+
+		ports {
+			port@0 {
+				hdmi_0: endpoint@0 {
+					remote-endpoint = <&lcdc_0>;
+				};
+			};
+		};
+	};
+};
+
+&rtc {
+	system-power-controller;
+};
+
+&mcasp0	{
+	#sound-dai-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcasp0_pins>;
+	status = "okay";
+	op-mode = <0>;	/* MCASP_IIS_MODE */
+	tdm-slots = <2>;
+	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
+			0 0 1 0
+		>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
+};
+
 / {
 	memory@80000000 {
 		device_type = "memory";
 		reg = <0x80000000 0x20000000>; /* 512 MB */
 	};
+
+	clk_mcasp0_fixed: clk_mcasp0_fixed {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <24576000>;
+	};
+
+	clk_mcasp0: clk_mcasp0 {
+		#clock-cells = <0>;
+		compatible = "gpio-gate-clock";
+		clocks = <&clk_mcasp0_fixed>;
+		enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "TI BeagleBone Black";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&dailink0_master>;
+		simple-audio-card,frame-master = <&dailink0_master>;
+
+		dailink0_master: simple-audio-card,cpu {
+			sound-dai = <&mcasp0>;
+			clocks = <&clk_mcasp0>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&tda19988>;
+		};
+	};
 };

arch/arm/dts/am335x-boneblack-hdmi.dtsi

@@ -1,141 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/display/tda998x.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-&am33xx_pinmux {
-	nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-		>;
-	};
-
-	nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
-		>;
-	};
-
-	mcasp0_pins: mcasp0_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */
-		>;
-	};
-};
-
-&lcdc {
-	status = "okay";
-
-	/* If you want to get 24 bit RGB and 16 BGR mode instead of
-	 * current 16 bit RGB and 24 BGR modes, set the propety
-	 * below to "crossed" and uncomment the video-ports -property
-	 * in tda19988 node.
-	 */
-	blue-and-red-wiring = "straight";
-
-	port {
-		lcdc_0: endpoint@0 {
-			remote-endpoint = <&hdmi_0>;
-		};
-	};
-};
-
-&i2c0 {
-	tda19988: tda19988@70 {
-		compatible = "nxp,tda998x";
-		reg = <0x70>;
-		nxp,calib-gpios = <&gpio1 25 0>;
-		interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>;
-
-		pinctrl-names = "default", "off";
-		pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
-		pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
-
-		/* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */
-		/* video-ports = <0x234501>; */
-
-		#sound-dai-cells = <0>;
-		audio-ports = <	TDA998x_I2S	0x03>;
-
-		ports {
-			port@0 {
-				hdmi_0: endpoint@0 {
-					remote-endpoint = <&lcdc_0>;
-				};
-			};
-		};
-	};
-};
-
-&mcasp0	{
-	#sound-dai-cells = <0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcasp0_pins>;
-	status = "okay";
-	op-mode = <0>;	/* MCASP_IIS_MODE */
-	tdm-slots = <2>;
-	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
-			0 0 1 0
-		>;
-	tx-num-evt = <32>;
-	rx-num-evt = <32>;
-};
-
-/ {
-	clk_mcasp0_fixed: clk_mcasp0_fixed {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <24576000>;
-	};
-
-	clk_mcasp0: clk_mcasp0 {
-		#clock-cells = <0>;
-		compatible = "gpio-gate-clock";
-		clocks = <&clk_mcasp0_fixed>;
-		enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */
-	};
-
-	sound {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "TI BeagleBone Black";
-		simple-audio-card,format = "i2s";
-		simple-audio-card,bitclock-master = <&dailink0_master>;
-		simple-audio-card,frame-master = <&dailink0_master>;
-
-		dailink0_master: simple-audio-card,cpu {
-			sound-dai = <&mcasp0>;
-			clocks = <&clk_mcasp0>;
-		};
-
-		simple-audio-card,codec {
-			sound-dai = <&tda19988>;
-		};
-	};
-};

arch/arm/dts/am335x-boneblack-wireless.dts

@@ -1,111 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include "am335x-bone-common.dtsi"
-#include "am335x-boneblack-common.dtsi"
-#include "am335x-boneblack-hdmi.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "TI AM335x BeagleBone Black Wireless";
-	compatible = "ti,am335x-bone-black-wireless", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
-
-	wlan_en_reg: fixedregulator@2 {
-		compatible = "regulator-fixed";
-		regulator-name = "wlan-en-regulator";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		startup-delay-us= <70000>;
-
-		/* WL_EN */
-		gpio = <&gpio3 9 0>;
-		enable-active-high;
-	};
-};
-
-&am33xx_pinmux {
-	bt_pins: pinmux_bt_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* gmii1_txd0.gpio0_28 - BT_EN */
-		>;
-	};
-
-	mmc3_pins: pinmux_mmc3_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */
-		>;
-	};
-
-	uart3_pins: pinmux_uart3_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1)	/* gmii1_rxd3.uart3_rxd */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* gmii1_rxd2.uart3_txd */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3)		/* mdio_data.uart3_ctsn */
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* mdio_clk.uart3_rtsn */
-		>;
-	};
-
-	wl18xx_pins: pinmux_wl18xx_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gmii1_txclk.gpio3_9 WL_EN */
-			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* rmii1_refclk.gpio0_29 WL_IRQ */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* gmii1_rxclk.gpio3_10 LS_BUF_EN */
-		>;
-	};
-};
-
-&mac {
-	status = "disabled";
-};
-
-&mmc3 {
-	dmas = <&edma_xbar 12 0 1
-		&edma_xbar 13 0 2>;
-	dma-names = "tx", "rx";
-	status = "okay";
-	vmmc-supply = <&wlan_en_reg>;
-	bus-width = <4>;
-	non-removable;
-	cap-power-off-card;
-	keep-power-in-suspend;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-	wlcore: wlcore@2 {
-		compatible = "ti,wl1835";
-		reg = <2>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <29 IRQ_TYPE_EDGE_RISING>;
-	};
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins &bt_pins>;
-	status = "okay";
-
-	bluetooth {
-		compatible = "ti,wl1835-st";
-		enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&gpio3 {
-	ls-buf-en-hog {
-		gpio-hog;
-		gpios = <10 GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "LS_BUF_EN";
-	};
-};

arch/arm/dts/am335x-boneblack.dts

@@ -7,7 +7,6 @@
 #include "am33xx.dtsi"
 #include "am335x-bone-common.dtsi"
 #include "am335x-boneblack-common.dtsi"
-#include "am335x-boneblack-hdmi.dtsi"
 
 / {
 	model = "TI AM335x BeagleBone Black";

arch/arm/dts/am335x-boneblue.dts

@@ -1,617 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include "am335x-osd335x-common.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "TI AM335x BeagleBone Blue";
-	compatible = "ti,am335x-bone-blue", "ti,am33xx";
-
-	chosen {
-		stdout-path = &uart0;
-		tick-timer = &timer2;
-	};
-
-	leds {
-		pinctrl-names = "default";
-		pinctrl-0 = <&user_leds_s0>;
-
-		compatible = "gpio-leds";
-
-		usr_0_led {
-			label = "beaglebone:green:usr0";
-			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-			default-state = "off";
-		};
-
-		usr_1_led {
-			label = "beaglebone:green:usr1";
-			gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "mmc0";
-			default-state = "off";
-		};
-
-		usr_2_led {
-			label = "beaglebone:green:usr2";
-			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "cpu0";
-			default-state = "off";
-		};
-
-		usr_3_led {
-			label = "beaglebone:green:usr3";
-			gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "mmc1";
-			default-state = "off";
-		};
-
-		wifi_led {
-			label = "wifi";
-			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-			linux,default-trigger = "phy0assoc";
-		};
-
-		red_led {
-			label = "red";
-			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		green_led {
-			label = "green";
-			gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		batt_1_led {
-			label = "bat25";
-			gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		batt_2_led {
-			label = "bat50";
-			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		batt_3_led {
-			label = "bat75";
-			gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		batt_4_led {
-			label = "bat100";
-			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-
-	vmmcsd_fixed: fixedregulator0 {
-		compatible = "regulator-fixed";
-		regulator-name = "vmmcsd_fixed";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-
-	wlan_en_reg: fixedregulator@2 {
-		compatible = "regulator-fixed";
-		regulator-name = "wlan-en-regulator";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		startup-delay-us= <70000>;
-
-		/* WL_EN */
-		gpio = <&gpio3 9 0>;
-		enable-active-high;
-	};
-};
-
-&am33xx_pinmux {
-	user_leds_s0: user_leds_s0 {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */
-			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */
-
-		>;
-	};
-
-	i2c2_pins: pinmux_i2c2_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* (D18) uart1_ctsn.I2C2_SDA */
-			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* (D17) uart1_rtsn.I2C2_SCL */
-		>;
-	};
-
-	/* UT0 */
-	uart0_pins: pinmux_uart0_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-		>;
-	};
-
-	/* UT1 */
-	uart1_pins: pinmux_uart1_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-		>;
-	};
-
-	/* GPS */
-	uart2_pins: pinmux_uart2_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE1)	/* (A17) spi0_sclk.uart2_rxd */
-			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* (B17) spi0_d0.uart2_txd */
-		>;
-	};
-
-	/* DSM2 */
-	uart4_pins: pinmux_uart4_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)	/* (T17) gpmc_wait0.uart4_rxd */
-		>;
-	};
-
-	/* UT5 */
-	uart5_pins: pinmux_uart5_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4)	/* (U2) lcd_data9.uart5_rxd */
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT_PULLDOWN, MUX_MODE4)	/* (U1) lcd_data8.uart5_txd */
-		>;
-	};
-
-	mmc1_pins: pinmux_mmc1_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)		/* (C15) spi0_cs1.gpio0[6] */
-		>;
-	};
-
-	mmc2_pins: pinmux_mmc2_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)	/* (U9) gpmc_csn1.mmc1_clk */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)	/* (V9) gpmc_csn2.mmc1_cmd */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)	/* (U7) gpmc_ad0.mmc1_dat0 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)	/* (V7) gpmc_ad1.mmc1_dat1 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)	/* (R8) gpmc_ad2.mmc1_dat2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)	/* (T8) gpmc_ad3.mmc1_dat3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)	/* (U8) gpmc_ad4.mmc1_dat4 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)	/* (V8) gpmc_ad5.mmc1_dat5 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)	/* (R9) gpmc_ad6.mmc1_dat6 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)	/* (T9) gpmc_ad7.mmc1_dat7 */
-		>;
-	};
-
-	mmc3_pins: pinmux_mmc3_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6)	/* (L15) gmii1_rxd1.mmc2_clk */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6)	/* (J16) gmii1_txen.mmc2_cmd */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5)	/* (J17) gmii1_rxdv.mmc2_dat0 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5)	/* (J18) gmii1_txd3.mmc2_dat1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5)	/* (K15) gmii1_txd2.mmc2_dat2 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5)	/* (H16) gmii1_col.mmc2_dat3 */
-		>;
-	};
-
-	bt_pins: pinmux_bt_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* (K17) gmii1_txd0.gpio0[28] - BT_EN */
-		>;
-	};
-
-	uart3_pins: pinmux_uart3_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1)	/* (L17) gmii1_rxd3.uart3_rxd */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* (L16) gmii1_rxd2.uart3_txd */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3)		/* (M17) mdio_data.uart3_ctsn */
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* (M18) mdio_clk.uart3_rtsn */
-		>;
-	};
-
-	wl18xx_pins: pinmux_wl18xx_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* (K18) gmii1_txclk.gpio3[9] - WL_EN */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */
-		>;
-	};
-
-	/* DCAN */
-	dcan1_pins: pinmux_dcan1_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2)		/* (E17) uart0_rtsn.dcan1_rx */
-			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2)		/* (E18) uart0_ctsn.dcan1_tx */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7)		/* (M16) gmii1_rxd0.gpio2[21] */
-		>;
-	};
-
-	/* E1 */
-	eqep0_pins: pinmux_eqep0_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT, MUX_MODE1)		/* (B12) mcasp0_aclkr.eQEP0A_in */
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT, MUX_MODE1)		/* (C13) mcasp0_fsr.eQEP0B_in */
-		>;
-	};
-
-	/* E2 */
-	eqep1_pins: pinmux_eqep1_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT, MUX_MODE2)		/* (V2) lcd_data12.eQEP1A_in */
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_INPUT, MUX_MODE2)		/* (V3) lcd_data13.eQEP1B_in */
-		>;
-	};
-
-	/* E3 */
-	eqep2_pins: pinmux_eqep2_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE4)		/* (T12) gpmc_ad12.eQEP2A_in */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE4)		/* (R12) gpmc_ad13.eQEP2B_in */
-		>;
-	};
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
-
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-
-	status = "okay";
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins>;
-
-	status = "okay";
-};
-
-&uart5 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart5_pins>;
-
-	status = "okay";
-};
-
-&usb0 {
-	dr_mode = "peripheral";
-	interrupts-extended = <&intc 18 &tps 0>;
-	interrupt-names = "mc", "vbus";
-};
-
-&usb1 {
-	dr_mode = "host";
-};
-
-&i2c0 {
-	baseboard_eeprom: baseboard_eeprom@50 {
-		compatible = "atmel,24c256";
-		reg = <0x50>;
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-		baseboard_data: baseboard_data@0 {
-			reg = <0 0x100>;
-		};
-	};
-};
-
-&i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins>;
-
-	status = "okay";
-	clock-frequency = <400000>;
-
-	mpu9250@68 {
-		compatible = "invensense,mpu9250";
-		reg = <0x68>;
-		interrupt-parent = <&gpio3>;
-		interrupts = <21 IRQ_TYPE_EDGE_RISING>;
-		i2c-gate {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			ax8975@c {
-				compatible = "asahi-kasei,ak8975";
-				reg = <0x0c>;
-			};
-		};
-	};
-
-	pressure@76 {
-		compatible = "bosch,bmp280";
-		reg = <0x76>;
-	};
-};
-
-/include/ "tps65217.dtsi"
-
-&tps {
-	/delete-property/ ti,pmic-shutdown-controller;
-
-	charger {
-		interrupts = <0>, <1>;
-		interrupt-names = "USB", "AC";
-		status = "okay";
-	};
-};
-
-&mmc1 {
-	status = "okay";
-	vmmc-supply = <&vmmcsd_fixed>;
-	bus-width = <4>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc1_pins>;
-	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
-};
-
-&mmc2 {
-	status = "okay";
-	vmmc-supply = <&vmmcsd_fixed>;
-	bus-width = <8>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins>;
-};
-
-&mmc3 {
-	dmas = <&edma_xbar 12 0 1
-		&edma_xbar 13 0 2>;
-	dma-names = "tx", "rx";
-	status = "okay";
-	vmmc-supply = <&wlan_en_reg>;
-	bus-width = <4>;
-	non-removable;
-	cap-power-off-card;
-	keep-power-in-suspend;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-	wlcore: wlcore@2 {
-		compatible = "ti,wl1835";
-		reg = <2>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <21 IRQ_TYPE_EDGE_RISING>;
-	};
-};
-
-&tscadc {
-	status = "okay";
-	adc {
-		ti,adc-channels = <0 1 2 3 4 5 6 7>;
-	};
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins &bt_pins>;
-	status = "okay";
-
-	bluetooth {
-		compatible = "ti,wl1835-st";
-		enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&rtc {
-	system-power-controller;
-	clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
-	clock-names = "ext-clk", "int-clk";
-};
-
-&dcan1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&dcan1_pins>;
-	status = "okay";
-};
-
-&gpio0 {
-	gpio-line-names =
-		"UART3_CTS", /* M17 */
-		"UART3_RTS", /* M18 */
-		"UART2_RX", /* A17 */
-		"UART2_TX", /* B17 */
-		"I2C1_SDA", /* B16 */
-		"I2C1_SCL", /* A16 */
-		"MMC0_CD", /* C15 */
-		"SPI1_SS2", /* C18 */
-		"EQEP_1A", /* V2 */
-		"EQEP_1B", /* V3 */
-		"MDIR_2B", /* V4 */
-		"BATT_LED_2", /* T5 */
-		"I2C2_SDA", /* D18 */
-		"I2C2_SCL", /* D17 */
-		"UART1_RX", /* D16 */
-		"UART1_TX", /* D15 */
-		"MMC2_DAT1", /* J18 */
-		"MMC2_DAT2", /* K15 */
-		"NC", /* F16 */
-		"WIFI_LED", /* A15 */
-		"MOT_STBY", /* D14 */
-		"WLAN_IRQ", /* K16 */
-		"PWM_2A", /* U10 */
-		"PWM_2B", /* T10 */
-		"",
-		"",
-		"BATT_LED_4", /* T11 */
-		"BATT_LED_1", /* U12 */
-		"BT_EN", /* K17 */
-		"SPI1_SS1", /* H18 */
-		"UART4_RX", /* T17 */
-		"MDIR_1B"; /* U17 */
-};
-
-&gpio1 {
-	gpio-line-names =
-		"MMC1_DAT0", /* U7 */
-		"MMC1_DAT1", /* V7 */
-		"MMC1_DAT2", /* R8 */
-		"MMC1_DAT3", /* T8 */
-		"MMC1_DAT4", /* U8 */
-		"MMC1_DAT5", /* V8 */
-		"MMC1_DAT6", /* R9 */
-		"MMC1_DAT7", /* T9 */
-		"DCAN1_TX", /* E18 */
-		"DCAN1_RX", /* E17 */
-		"UART0_RX", /* E15 */
-		"UART0_TX", /* E16 */
-		"EQEP_2A", /* T12 */
-		"EQEP_2B", /* R12 */
-		"PRU_E_A", /* V13 */
-		"PRU_E_B", /* U13 */
-		"MDIR_2A", /* R13 */
-		"GPIO1_17", /* V14 */
-		"PWM_1A", /* U14 */
-		"PWM_1B", /* T14 */
-		"EMMC_RST", /* R14 */
-		"USR_LED_0", /* V15 */
-		"USR_LED_1", /* U15 */
-		"USR_LED_2", /* T15 */
-		"USR_LED_3", /* V16 */
-		"GPIO1_25", /* U16 */
-		"MCASP0_AXR0", /* T16 */
-		"MCASP0_AXR1", /* V17 */
-		"MCASP0_ACLKR", /* U18 */
-		"BATT_LED_3", /* V6 */
-		"MMC1_CLK", /* U9 */
-		"MMC1_CMD"; /* V9 */
-};
-
-&gpio2 {
-	gpio-line-names =
-		"MDIR_1A", /* T13 */
-		"MCASP0_FSR", /* V12 */
-		"LED_RED", /* R7 */
-		"LED_GREEN", /* T7 */
-		"MODE_BTN", /* U6 */
-		"PAUSE_BTN", /* T6 */
-		"MDIR_4A", /* R1 */
-		"MDIR_4B", /* R2 */
-		"MDIR_3B", /* R3 */
-		"MDIR_3A", /* R4 */
-		"SVO7", /* T1 */
-		"SVO8", /* T2 */
-		"SVO5", /* T3 */
-		"SVO6", /* T4 */
-		"UART5_TX", /* U1 */
-		"UART5_RX", /* U2 */
-		"SERVO_EN", /* U3 */
-		"NC", /* U4 */
-		"UART3_RX", /* L17 */
-		"UART3_TX", /* L16 */
-		"MMC2_CLK", /* L15 */
-		"DCAN1_SILENT", /* M16 */
-		"SVO1", /* U5 */
-		"SVO3", /* R5 */
-		"SVO2", /* V5 */
-		"SVO4", /* R6 */
-		"MMC0_DAT3", /* F17 */
-		"MMC0_DAT2", /* F18 */
-		"MMC0_DAT1", /* G15 */
-		"MMC0_DAT0", /* G16 */
-		"MMC0_CLK", /* G17 */
-		"MMC0_CMD"; /* G18 */
-};
-
-&gpio3 {
-	gpio-line-names =
-		"MMC2_DAT3", /* H16 */
-		"GPIO3_1", /* H17 */
-		"GPIO3_2", /* J15 */
-		"MMC2_CMD", /* J16 */
-		"MMC2_DAT0", /* J17 */
-		"I2C0_SDA", /* C17 */
-		"I2C0_SCL", /* C16 */
-		"EMU1", /* C14 */
-		"EMU0", /* B14 */
-		"WL_EN", /* K18 */
-		"WL_BT_OE", /* L18 */
-		"",
-		"",
-		"NC", /* F15 */
-		"SPI1_SCK", /* A13 */
-		"SPI1_MISO", /* B13 */
-		"SPI1_MOSI", /* D12 */
-		"GPIO3_17", /* C12 */
-		"EQEP_0A", /* B12 */
-		"EQEP_0B", /* C13 */
-		"GPIO3_20", /* D13 */
-		"IMU_INT", /* A14 */
-		"",
-		"",
-		"",
-		"",
-		"",
-		"",
-		"",
-		"",
-		"",
-		"";
-
-	ls-buf-en-hog {
-		gpio-hog;
-		gpios = <10 GPIO_ACTIVE_HIGH>;
-		output-high;
-	};
-};
-
-&epwmss0 {
-	status = "okay";
-};
-
-&eqep0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&eqep0_pins>;
-	status = "okay";
-};
-
-&epwmss1 {
-	status = "okay";
-};
-
-&eqep1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&eqep1_pins>;
-	status = "okay";
-};
-
-&epwmss2 {
-	status = "okay";
-};
-
-&eqep2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&eqep2_pins>;
-	status = "okay";
-};