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e110ca11b3
BL808 contains clocks and resets controlled by registers in several MMIO regions, mostly because each MMIO region is in a separate power domain. Add the descriptions for the known clocks and resets. Signed-off-by: Samuel Holland <samuel@sholland.org>
25 lines
589 B
C
25 lines
589 B
C
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
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#ifndef _DT_BINDINGS_CLOCK_BL808_MM_GLB_H_
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#define _DT_BINDINGS_CLOCK_BL808_MM_GLB_H_
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#define CLK_MM_UART 0
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#define CLK_MM_I2C 1
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#define CLK_MM_SPI 2
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#define CLK_MM_MUXPLL 3
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#define CLK_MM_XCLK 4
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#define CLK_MM_CPU 5
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#define CLK_MM_BCLK1X 6
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#define CLK_MM_BCLK2X 7
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#define CLK_MM_CNN 8
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#define CLK_MM_DSP 9
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#define CLK_MM_DSP_DP 10
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#define CLK_MM_H264 11
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#define CLK_MM_IC20 12
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#define CLK_MM_UART0 13
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#define CLK_MM_SPI0 14
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#define CLK_MM_I2C1 15
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#define CLK_MM_UART1 16
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#endif /* _DT_BINDINGS_CLOCK_BL808_MM_GLB_H_ */
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