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a2615b3b16
Use the vendor CSRs for enabling/disabling the caches, and the ISA extension for cache maintenance. Signed-off-by: Samuel Holland <samuel@sholland.org>
97 lines
2.0 KiB
C
97 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <cpu_func.h>
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#include <asm/cache.h>
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#include <asm/csr.h>
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#include <linux/bitops.h>
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#include "thead_csr.h"
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#define THEAD_SYNC_I ".long 0x01a0000b"
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#define THEAD_DCACHE_CIALL ".long 0x0030000b"
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#define THEAD_DCACHE_CIPA_A0 ".long 0x02b5000b"
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#define THEAD_DCACHE_IALL ".long 0x0020000b"
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#define THEAD_DCACHE_IPA_A0 ".long 0x02a5000b"
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#define THEAD_ICACHE_IPA_A0 ".long 0x0385000b"
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static inline void sync_i(void)
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{
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asm volatile (THEAD_SYNC_I ::: "memory");
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}
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void flush_dcache_all(void)
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{
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asm volatile (THEAD_DCACHE_CIALL ::: "memory");
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sync_i();
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}
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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register ulong addr asm ("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
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for (; addr < end; addr += CONFIG_SYS_CACHELINE_SIZE)
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asm volatile (THEAD_DCACHE_CIPA_A0 :: "r" (addr) : "memory");
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sync_i();
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}
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void invalidate_dcache_all(void)
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{
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asm volatile (THEAD_DCACHE_IALL ::: "memory");
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sync_i();
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}
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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register ulong addr asm ("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
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for (; addr < end; addr += CONFIG_SYS_CACHELINE_SIZE)
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asm volatile (THEAD_DCACHE_IPA_A0 :: "r" (addr) : "memory");
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sync_i();
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}
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void invalidate_icache_range(unsigned long start, unsigned long end)
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{
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register ulong addr asm ("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
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for (; addr < end; addr += CONFIG_SYS_CACHELINE_SIZE)
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asm volatile (THEAD_ICACHE_IPA_A0 :: "r" (addr) : "memory");
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sync_i();
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}
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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void icache_enable(void)
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{
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invalidate_icache_all();
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csr_set(CSR_MHCR, MHCR_IE);
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}
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void icache_disable(void)
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{
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csr_clear(CSR_MHCR, MHCR_IE);
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}
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int icache_status(void)
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{
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return csr_read(CSR_MHCR) & MHCR_IE;
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}
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void dcache_enable(void)
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{
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invalidate_dcache_all();
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csr_set(CSR_MHCR, MHCR_DE);
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}
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void dcache_disable(void)
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{
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flush_dcache_all();
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csr_clear(CSR_MHCR, MHCR_DE);
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}
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int dcache_status(void)
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{
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return csr_read(CSR_MHCR) & MHCR_DE;
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}
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#endif
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