random-mirrors/smaeul-u-boot
1
0
Fork 0
mirror of https://github.com/smaeul/u-boot.git synced 2025-09-13 13:36:02 +01:00
Code Issues Packages Projects Releases Wiki Activity
smaeul-u-boot/arch/riscv/cpu/thead
History
Samuel Holland a2615b3b16 riscv: cpu: thead: Add CPU-specific cache operations 
Use the vendor CSRs for enabling/disabling the caches, and the ISA
extension for cache maintenance.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-07-28 16:13:28 -05:00
..
cache.c
riscv: cpu: thead: Add CPU-specific cache operations
2023-07-28 16:13:28 -05:00
cpu.c
riscv: cpu: thead: Initialize extension CSRs
2023-07-28 16:13:28 -05:00
dram.c
riscv: cpu: Add skeleton for T-HEAD CPUs
2023-07-28 16:13:28 -05:00
Kconfig
riscv: cpu: thead: Add CPU-specific cache operations
2023-07-28 16:13:28 -05:00
Makefile
riscv: cpu: thead: Add CPU-specific cache operations
2023-07-28 16:13:28 -05:00
thead_csr.h
riscv: cpu: thead: Add extension CSR definitions
2023-07-28 16:13:28 -05:00