Samuel Holland a2615b3b16 riscv: cpu: thead: Add CPU-specific cache operations
Use the vendor CSRs for enabling/disabling the caches, and the ISA
extension for cache maintenance.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-07-28 16:13:28 -05:00

6 lines
85 B
Makefile

# SPDX-License-Identifier: GPL-2.0+
obj-y += cache.o
obj-y += cpu.o
obj-y += dram.o