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5159250118
Enable the T-HEAD ISA extensions, as these are required to use the cache maintenance instructions. Enable the branch predictor and BTB to improve performance. Some bits are only available on specific CPU models, so provide Kconfig symbols for selecting the right model. Signed-off-by: Samuel Holland <samuel@sholland.org>
44 lines
878 B
C
44 lines
878 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <irq_func.h>
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#include <asm/cache.h>
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#include <asm/csr.h>
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#include <linux/bitops.h>
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#include "thead_csr.h"
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/*
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* cleanup_before_linux() is called just before we call linux
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* it prepares the processor for linux
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*
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* we disable interrupt and caches.
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*/
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int cleanup_before_linux(void)
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{
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disable_interrupts();
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cache_flush();
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return 0;
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}
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void harts_early_init(void)
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{
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if (!CONFIG_IS_ENABLED(RISCV_MMODE))
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return;
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csr_set(CSR_MXSTATUS, MXSTATUS_THEADISAEE | MXSTATUS_MM);
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if (IS_ENABLED(THEAD_C906)) {
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csr_set(CSR_MHCR,
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MHCR_BTB_C906 | MHCR_BPE | MHCR_RS | MHCR_WB | MHCR_WA);
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csr_set(CSR_MHINT, MHINT_IWPE | MHINT_IPLD | MHINT_IPLD);
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}
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if (IS_ENABLED(THEAD_E906)) {
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csr_set(CSR_MHCR,
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MHCR_BTB_E906 | MHCR_BPE | MHCR_RS | MHCR_WB | MHCR_WA);
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}
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}
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