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T-HEAD C9xx and E9xx CPUs contain some extra CSRs which control the branch predictor and cache-related functionality. Signed-off-by: Samuel Holland <samuel@sholland.org>
37 lines
1.3 KiB
C
37 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _THEAD_CSR_H_
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#define _THEAD_CSR_H_
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#define CSR_MXSTATUS 0x7c0
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#define CSR_MHCR 0x7c1
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#define CSR_MHINT 0x7c5
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#define MXSTATUS_THEADISAEE BIT(22) /* T-HEAD ISA extensions enable */
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#define MXSTATUS_MM BIT(15) /* misaligned access enable */
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#define MHCR_IE BIT(0) /* icache enable */
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#define MHCR_DE BIT(1) /* dcache enable */
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#define MHCR_WA BIT(2) /* dcache write allocate */
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#define MHCR_WB BIT(3) /* dcache write back */
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#define MHCR_RS BIT(4) /* return stack enable */
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#define MHCR_BPE BIT(5) /* branch prediction enable */
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#define MHCR_BTB_C906 BIT(6) /* branch target prediction enable */
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#define MHCR_WBR BIT(8) /* write burst enable */
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#define MHCR_BTB_E906 BIT(12) /* branch target prediction enable */
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#define MHINT_DPLD BIT(2) /* dcache prefetch enable */
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#define MHINT_AMR_PAGE (0x0 << 3)
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#define MHINT_AMR_LIMIT_3 (0x1 << 3)
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#define MHINT_AMR_LIMIT_64 (0x2 << 3)
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#define MHINT_AMR_LIMIT_128 (0x3 << 3)
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#define MHINT_IPLD BIT(8) /* icache prefetch enable */
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#define MHINT_IWPE BIT(9) /* icache way prediction enable */
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#define MHINT_D_DIS_PREFETCH_2 (0x0 << 13)
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#define MHINT_D_DIS_PREFETCH_4 (0x1 << 13)
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#define MHINT_D_DIS_PREFETCH_8 (0x2 << 13)
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#define MHINT_D_DIS_PREFETCH_16 (0x3 << 13)
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#define MHINT_AEE BIT(20) /* accurate exception enable */
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#endif /* _THEAD_CSR_H_ */
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